WO2021083107A1 - 摄像模组及电子设备 - Google Patents

摄像模组及电子设备 Download PDF

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Publication number
WO2021083107A1
WO2021083107A1 PCT/CN2020/123880 CN2020123880W WO2021083107A1 WO 2021083107 A1 WO2021083107 A1 WO 2021083107A1 CN 2020123880 W CN2020123880 W CN 2020123880W WO 2021083107 A1 WO2021083107 A1 WO 2021083107A1
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WIPO (PCT)
Prior art keywords
camera
signal terminal
signal
mipi
line
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PCT/CN2020/123880
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English (en)
French (fr)
Inventor
吕宗安
Original Assignee
维沃移动通信有限公司
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Application filed by 维沃移动通信有限公司 filed Critical 维沃移动通信有限公司
Publication of WO2021083107A1 publication Critical patent/WO2021083107A1/zh
Priority to US17/733,992 priority Critical patent/US12022177B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1613—Constructional details or arrangements for portable computers
    • G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
    • G06F1/1684—Constructional details or arrangements related to integrated I/O peripherals not covered by groups G06F1/1635 - G06F1/1675
    • G06F1/1686—Constructional details or arrangements related to integrated I/O peripherals not covered by groups G06F1/1635 - G06F1/1675 the I/O peripheral being an integrated camera
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1613—Constructional details or arrangements for portable computers
    • G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
    • G06F1/1684—Constructional details or arrangements related to integrated I/O peripherals not covered by groups G06F1/1635 - G06F1/1675
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/45—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/61—Control of cameras or camera modules based on recognised objects
    • H04N23/611—Control of cameras or camera modules based on recognised objects where the recognised objects include parts of the human body
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/667—Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/90—Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0264—Details of the structure or mounting of specific components for a camera module assembly

Definitions

  • the present invention relates to the field of electronic technology, in particular to a camera module and electronic equipment.
  • electronic devices such as smart phones and tablet computers have become more and more popular, and have gradually become an indispensable part of people's daily lives.
  • electronic devices are usually equipped with multiple cameras.
  • one or more cameras are set on the front and back sides of the electronic device to meet the shooting needs in different scenarios and Effectively improve the quality of shooting.
  • each camera when the electronic device is equipped with multiple cameras, each camera usually transmits the image signal to the image processor connection through the Mobile Industry Processor Interface (MIPI), and through the MIPI sending port of the camera
  • MIPI Mobile Industry Processor Interface
  • a switch unit (such as a single-pole multi-throw switch) is set between the MIPI receiving port of the processor to realize the time-sharing shooting of each camera in different scenes.
  • the switch unit due to the large size of the switch unit, it occupies a large installation space on the circuit board of the electronic device. In the case of limited circuit board area, the components carried on the circuit board are too compact, which is not conducive to The heat dissipation between the components of the electronic equipment can easily cause damage to the electronic equipment.
  • the embodiments of the present invention provide a camera module and an electronic device to solve the problem of low reliability of the current electronic device provided with multiple cameras.
  • an embodiment of the present invention provides a camera module, which is applied to an electronic device including a processor, the camera module includes a first camera and a second camera, and the first camera is provided with M first signals At the end, the second camera is provided with N second signal ends, the M and the N are positive integers, and the M is greater than or equal to the N:
  • the M first signal terminals are connected with the processor to form M connection lines;
  • the N second signal terminals are connected to the N connection lines of the M connection lines in a one-to-one correspondence, and at least one second signal terminal is connected to its corresponding connection line through a resistor.
  • an embodiment of the present invention also provides an electronic device including the above-mentioned camera module.
  • the camera module of the embodiment of the present invention includes a first camera and a second camera, the first camera is provided with M first signal ends, the second camera is provided with N second signal ends, M and N are positive integers, and M is greater than or equal to N: M first signal terminals are connected to the processor to form M connection lines; N second signal terminals are connected to N of the M connection lines in a one-to-one correspondence, and at least one second signal The terminal is connected to its corresponding connection line through a resistor. In this way, the time-sharing shooting of the first camera and the second camera can be realized, and the signal reflection during shooting of the first camera can be reduced, and the shooting quality of the camera module can be improved.
  • FIG. 1 is one of the schematic structural diagrams of a camera module provided by an embodiment of the present invention
  • FIG. 2 is a second structural diagram of a camera module provided by an embodiment of the present invention.
  • Figure 3a is one of the signal eye diagrams of the first camera provided by an embodiment of the present invention.
  • Figure 3b is the second signal eye diagram of the first camera provided by the embodiment of the present invention.
  • Fig. 3c is a signal eye diagram of a second camera provided by an embodiment of the present invention.
  • FIG. 4 is a third structural diagram of a camera module provided by an embodiment of the present invention.
  • FIG. 5 is the fourth structural diagram of the camera module provided by the embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a camera module provided by an embodiment of the present invention.
  • the camera module is applied to an electronic device including a processor.
  • the camera module includes a first camera 21 and The second camera 22, the first camera 21 is provided with M first signal terminals 211, the second camera 22 is provided with N second signal terminals 221, M and N are positive integers, and M is greater than or equal to N:
  • the M first signal terminals 211 are connected with the processor 10 to form M connection lines 23;
  • the N second signal terminals 221 are connected to the N connection lines 23 of the M connection lines 23 in a one-to-one correspondence, and at least one second signal terminal 221 is connected to its corresponding connection line 23 through a resistor 24.
  • the camera module connects the signal end of the second camera 22 to the corresponding connection line 23 formed by the first camera 21 and the processor 10, so that when the first camera 21 and the second camera 22 capture images at different times,
  • the processor 10 can respectively receive the signals transmitted by the first signal terminal 211 of the first camera 21 and the second signal terminal 221 of the second camera 22, so that the first camera 21 and the second camera 22 can be connected without a switch unit. Time-sharing shooting.
  • the second signal terminal 221 is connected to the connection line 23 between the first signal terminal 211 and the processor 10, when the first signal terminal 211 transmits a signal, the transmission signal will pass through the connection line 23 to the second signal terminal 221 When the line reaches the second signal terminal 221, the second camera 22 as a load will cause signal reflection, and the longer the line from the first signal terminal 211 to the second signal terminal 221, the more serious the signal reflection, and the reflected signal will affect the processor 10
  • the received transmission signal causes the signal eye pattern of the first camera 21 to deteriorate; and by setting the resistor 24 between the second signal terminal 221 and the corresponding connection line 23, when the transmission signal of the first signal terminal 211 reaches the resistor 24
  • the reflection compared to the reflection at the second signal terminal 221, can shorten the length of the transmission signal transmission line between the connection line 23 and the second signal terminal 221, thereby reducing the reflection of the transmission signal of the first signal terminal 211 and improving the first signal terminal 211.
  • the shooting quality of a camera 21 can further improve the shooting quality
  • each first signal terminal 211 are signal terminals of the MIPI transmission interface of the first camera 21, and each first signal terminal 211 may be a clock signal terminal for transmitting a clock signal or for transmitting data.
  • the at least one second signal terminal 221 may be a part or all of the second signal terminals 221 of the N second signal terminals 221.
  • the N second signal terminals 221 include clock signal terminals, it may be Only the clock signal terminal is connected to the resistor 24; or, in some embodiments, among the N second signal terminals 221, each second signal terminal 221 is connected to its corresponding connection line through a resistor, that is, at least one of the above-mentioned at least one
  • the second signal terminals 221 are the aforementioned N second signal terminals 221, so that the signal reflection of the first camera 21 can be further reduced, and the shooting quality of the first camera 21 can be further improved.
  • the line length between the connection point of the first connection line 23 and the first signal terminal 211 connected to the first connection line 23 is smaller than the second signal connection point between the connection point and the first connection line 23.
  • the first connection line 23 is any one of the N connection lines 23.
  • the line length from the first signal terminal 211 to the connection point is less than the line length from the corresponding second signal terminal 221 to the connection point, if the transmission signal of the first signal terminal 211 reaches the corresponding second signal terminal 221, it may be generated Severe reflection, and by arranging the resistor 24 between the corresponding second signal terminal 221 and the connection point, the effect of reducing signal reflection can be more significant.
  • the line length between the connection point of the first connection line 23 and the first signal terminal 211 connected to the first connection line 23 may also be equal to or greater than the second signal connection point connected to the first connection line 23.
  • the length of the line between the ends 221 is not limited here.
  • the above-mentioned target second signal terminal 221 is connected to the second connection line 23 through the first resistor 24, and the first line length between the first resistor 24 and the target second signal terminal 221 is greater than the second line length ,among them:
  • the second line length is: the line length between the first resistor 24 and the second connection line 23;
  • the target second signal terminal 221 is any second signal terminal 221 of the at least one second signal terminal 221.
  • the transmission signal of the first signal terminal 211 corresponding to the target second signal terminal 221 can be further shortened, between the second connection line 23 and the target second signal terminal 221 The length of the transmission line, thereby further reducing the reflection of the transmission signal of the first signal terminal 211.
  • the length of the first line may also be less than or equal to the length of the second line, which is not limited here.
  • the transmitted signal will also reach the first camera 21 to generate a reflected signal, which causes the signal eye diagram of the second camera 22 to deteriorate.
  • the shooting quality of the camera 22 is affected by the reflected signal.
  • the first camera 21 and the second camera 22 satisfy at least one of the following:
  • the pixels of the second camera 22 are lower than the pixels of the first camera 21;
  • the signal frequency of the second camera 22 is lower than the signal frequency of the first camera 21;
  • the transmission rate of the second camera 22 is lower than the transmission rate of the first camera 21.
  • the number of the first signal terminal 211 and the second signal terminal 221 may be the same, that is, the above M is equal to the above N.
  • the camera module includes a camera A (equivalent to the first camera 21), a camera B (equivalent to the second camera 22), and a resistance module, and the camera B is a low-pixel camera, and the camera A It can be a high-pixel camera or a low-pixel camera with higher pixels than camera B;
  • the resistance module includes resistance R1, resistance R2 and resistance R3, and the resistance range of resistance R1, resistance R2 and resistance R3 can be 5 ⁇ to 200 ⁇ ;
  • D1B is connected to the connection line 23 between D1A and D1 through a resistor R2
  • D2B is connected to the connection line 23 between D2A and D2 through a resistor R3 (that is, the above-mentioned at least one second signal terminal 221 includes CLKB , D1B and D2B), and the resistance module is set close to camera A;
  • the electrical signals containing image information collected by camera A and camera B are transmitted to the processor 10 through the MIPI interface, MIPI transmitting interface A and MIPI transmitting interface B are output, MIPI receiving interface is input, MIPI transmitting interface A and MIPI transmitting interface B
  • the above traces are electrically connected.
  • CLKA, D1A, D2A, CLK, D1, D2, CLKB, D1B, D2B are the network names of MIPI differential pair traces.
  • a differential pair contains two MIPI traces, P and N, all connected to the same
  • the MIPI wiring of a common node is electrically connected; one end of the resistance module is connected to MIPI transmission interface B, and the other end is connected to the public node;
  • the function of the resistance module 14 is to reduce the reflection size of the branch wiring and improve the eye diagram of the MIPI receiving interface position. As shown in Figure 3b, it is the camera A when the resistance module is set Signal eye diagram. When the MIPI rate of the camera A is high and the MIPI branch line is long, under the action of the resistance module 14, the signal eye diagram of the MIPI receiving interface position can still meet the standard requirements.
  • the camera A and camera B may also include other numbers of signal terminals.
  • the following methods 1 and 2 are listed here for description:
  • the resistance module includes three resistors 24, and the MIPI receiving port of the processor 10 includes a clock signal terminal and a data signal terminal;
  • the resistance module includes 5 resistors 24, and the MIPI receiving port of the processor 10 includes a clock signal terminal and 4 data signal terminals, as shown in FIG. 4.
  • the numbers of the first signal terminals 211 and the second signal terminals 221 may be different, that is, the above M is greater than the above N.
  • the following manners 3 to 5 are listed here for description:
  • the resistance module includes two resistors 24, and the MIPI receiving port of the processor 10 includes a clock signal terminal and two data signal terminals;
  • the resistance module includes two resistors 24, and the MIPI receiving port of the processor 10 includes a clock signal terminal and 4 data signal terminals;
  • the resistance module includes three resistors 24, and the MIPI receiving port of the processor 10 includes a clock signal terminal and four data signal terminals.
  • the camera module can also be provided with other cameras.
  • a camera that works simultaneously with the first camera 21 can also be provided.
  • the M first signal terminals 211 include a first clock signal terminal
  • the N connection lines 23 include a third connection line 23 connected to the first clock signal terminal
  • the N second signal terminals 221 include a second clock signal terminal.
  • Signal terminal, and the second clock signal terminal is connected to the third connection line 23 through the second resistor 24
  • the camera module further includes a third camera provided with K third signal terminals, and the third of the K third signal terminals
  • the clock signal is connected to the third connection line 23
  • the K-1 third signal terminals except the third clock signal are respectively connected to the connection line 23 between the first signal terminal 211 and the processor 10, and at least one third signal
  • the terminals are respectively connected to the corresponding connection line 23 through the resistor 24, and K is a positive integer, so that when the camera module is provided with more than two cameras, the reflection of the first camera 21 during signal transmission can be reduced, and the first camera can be improved. 21 shooting quality.
  • connection line 23 connected to the third signal terminal and the connection line 23 connected to the second signal terminal 221 may be the same or different; in addition, the connection between the third camera and the first camera 21 and the second camera 22
  • the working principle is similar to the working principle between the first camera 21 and the second camera 22, which will not be repeated here.
  • the sixth to the fifteenth manners are provided here to describe the case where the camera module is provided with a first camera 21, a second camera 22, and a third camera, and the details are as follows:
  • the resistance module includes 4 resistors 24, and the MIPI receiving port of the processor 10 includes Clock signal terminal and 1 data signal terminal, as shown in Figure 5;
  • the resistance module includes 5 resistors 24, and the MIPI receiving port of the processor 10 includes Clock signal terminal and 2 data signal terminals;
  • the resistance module includes 7 resistors 24, and the MIPI receiving port of the processor 10 includes Clock signal terminal and 4 data signal terminals;
  • the resistance module includes 5 resistors 24 and the MIPI receiving port of the processor 10 Including clock signal terminal and 2 data signal terminals;
  • the resistance module includes 6 resistors 24, and the MIPI receiving port of the processor 10 includes Clock signal terminal and 2 data signal terminals;
  • the resistance module includes 8 resistors 24, and the MIPI receiver of the processor 10
  • the port includes a clock signal terminal and 4 data signal terminals;
  • the resistance module includes 7 resistors 24 and the MIPI receiving port of the processor 10 Including clock signal terminal and 4 data signal terminals;
  • the resistance module includes 8 resistors 24 and the MIPI receiving port of the processor 10 Including clock signal terminal and 4 data signal terminals;
  • the resistance module includes 10 resistors 24, and the MIPI receiving port of the processor 10 includes Clock signal terminal and 4 data signal terminals.
  • the camera module includes a first camera 21 and a second camera 22.
  • the first camera 21 is provided with M first signal terminals 211
  • the second camera 22 is provided with N second signal terminals 221, M and N is a positive integer, and M is greater than or equal to N:
  • M first signal terminals 211 are connected to the processor 10 to form M connection lines 23;
  • N second signal terminals 221 are connected to N of the M connection lines 23 23 are connected in a one-to-one correspondence, and at least one second signal terminal 221 is connected to its corresponding connection line 23 through a resistor 24.
  • an embodiment of the present invention also provides an electronic device including the above-mentioned camera module.

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Abstract

本发明提供一种摄像模组及电子设备，摄像模组包括第一摄像头和第二摄像头，第一摄像头设置有M个第一信号端，第二摄像头设置有N个第二信号端，M和N为正整数，且M大于或者等于N：M个第一信号端与处理器连接形成M条连接线路；N个第二信号端与M条连接线路中的N条连接线路一一对应连接，且至少一个第二信号端通过电阻连接至其所对应的连接线路。

Description

摄像模组及电子设备
相关申请的交叉引用
本申请主张在2019年10月30日在中国提交的中国专利申请号No.201911044545.1的优先权，其全部内容通过引用包含于此。
技术领域
本发明涉及电子技术领域，尤其涉及一种摄像模组及电子设备。
背景技术
随着电子技术的飞速发展，智能手机以及平板电脑等电子设备已越来越普及，并逐渐成为人们日常生活不可缺少的一部分。为满足人们对于电子设备的摄像功能越来越高的要求，目前电子设备通常设置多个摄像头，例如，电子设备的前后两侧各设置一个或者多个摄像头，从而满足不同场景下的拍摄需求以及有效提升拍摄质量。
其中，在电子设备设置有多个摄像头的情况下，每一摄像头通常是通过移动产业处理器接口(Mobile Industry Processor Interface，MIPI)将图像信号传输至图像处理器连，且通过摄像头的MIPI发送端口与处理器的MIPI接收端口之间设置开关单元(如单刀多掷开关)，实现控制各摄像头在不同场景下的分时拍摄。但是，由于开关单元的体积通常较大，在电子设备的电路板上占用较大的安装空间，在电路板面积有限的情况下，使得电路板上承载的各元器件之间过于紧凑，不利于电子设备元器件之间的散热，从而容易造成电子设备的损坏。
可见，目前设置有多个摄像头的电子设备存在可靠性低的问题。
发明内容
本发明实施例提供一种摄像模组及电子设备，以解决目前设置有多个摄像头的电子设备存在可靠性低的问题。
为解决上述问题，本发明实施例是这样实现的：
第一方面，本发明实施例提供一种摄像模组，应用于包括处理器的电子设备，所述摄像模组包括第一摄像头和第二摄像头，所述第一摄像头设置有M个第一信号端，所述第二摄像头设置有N个第二信号端，所述M和所述N为正整数，且所述M大于或者等于所述N：
所述M个第一信号端与所述处理器连接形成M条连接线路；
所述N个第二信号端与所述M条连接线路中的N条连接线路一一对应连接，且至少一个第二信号端通过电阻连接至其所对应的连接线路。
第二方面，本发明实施例还提供一种电子设备，包括上述摄像模组。
本发明实施例的摄像模组，包括第一摄像头和第二摄像头，第一摄像头设置有M个第一信号端，第二摄像头设置有N个第二信号端，M和N为正整数，且M大于或者等于N：M个第一信号端与处理器连接形成M条连接线路；N个第二信号端与M条连接线路中的N条连接线路一一对应连接，且至少一个第二信号端通过电阻连接至其所对应的连接线路。这样，既可以实现第一摄像头和第二摄像头的分时拍摄，又可以降低第一摄像头拍摄时的信号反射，提升摄像模组的拍摄质量。
附图说明
图1是本发明实施例提供的摄像模组的结构示意图之一；
图2是本发明实施例提供的摄像模组的结构示意图之二；
图3a是本发明实施例提供的第一摄像头的信号眼图之一
图3b是本发明实施例提供的第一摄像头的信号眼图之二；
图3c是本发明实施例提供的第二摄像头的信号眼图；
图4是本发明实施例提供的摄像模组的结构示意图之三；
图5是本发明实施例提供的摄像模组的结构示意图之四。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造 性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图1，图1是本发明实施例提供的一种摄像模组的结构示意图，该摄像模组应用于包括处理器的电子设备，如图1所示，摄像模组包括第一摄像头21和第二摄像头22，第一摄像头21设置有M个第一信号端211，第二摄像头22设置有N个第二信号端221，M和N为正整数，且M大于或者等于N：
M个第一信号端211与处理器10连接形成M条连接线路23；
N个第二信号端221与M条连接线路23中的N条连接线路23一一对应连接，且至少一个第二信号端221通过电阻24连接至其所对应的连接线路23。
这里，摄像模组通过将第二摄像头22的信号端，连接至对应的第一摄像头21与处理器10形成的连接线路23，从而在第一摄像头21和第二摄像头22不同时间拍摄图像时，处理器10可以分别接收到第一摄像头21的第一信号端211和第二摄像头22的第二信号端221传输的信号，从而无需设置开关单元即可实现第一摄像头21和第二摄像头22的分时拍摄。
另外，由于第二信号端221连接在第一信号端211与处理器10之间的连接线路23上，在第一信号端211传输信号时，传输信号会通过连接线路23至第二信号端221的线路到达第二信号端221，第二摄像头22作为负载会造成信号反射，且第一信号端211至第二信号端221的线路越长，信号反射越严重，反射信号会影响到处理器10接收到的传输信号，导致第一摄像头21的信号眼图变差；而通过在第二信号端221与其对应的连接线路23之间设置电阻24，第一信号端211的传输信号到达电阻24时反射，相比于到达第二信号端221再反射，可以缩短传输信号在连接线路23与第二信号端221之间传输的线路长度，从而降低第一信号端211的传输信号的反射，提升第一摄像头21的拍摄质量，进而提升摄像模组的拍摄质量。
需要说明的是，上述M个第一信号端211是第一摄像头21的MIPI发送接口的信号端，且每一第一信号端211可以是用于传输时钟信号的时钟信号端或者用于传输数据信号的数据信号端等；同样地，上述N个第二信号端221可以是第二摄像头22的MIPI发送接口的信号端，且每一第一信号端211也 可以是时钟信号端或者数据信号端等，在此并不进行限定。
另外，上述至少一个第二信号端221可以是N个第二信号端221中的部分或者全部第二信号端221，例如，在上述N个第二信号端221包括时钟信号端的情况下，可以是仅时钟信号端连接有电阻24；或者，在一些实施方式中，所述N个第二信号端221中，每一第二信号端221通过电阻连接至其所对应的连接线路，即上述至少一个第二信号端221为上述N个第二信号端221，从而可以进一步降低第一摄像头21的信号反射，进一步提升第一摄像头21的拍摄质量。
在一些实施方式中，上述第一连接线路23的连接点与第一连接线路23所连接的第一信号端211之间的线路长度，小于连接点与第一连接线路23所连接的第二信号端221之间的线路长度；
第一连接线路23为N条连接线路23中的任一条连接线路23。
这里，由于第一信号端211至连接点的线路长度小于对应的第二信号端221至连接点的线路长度，若第一信号端211的传输信号达到对应的第二信号端221，则可能产生严重的反射，而通过在对应的第二信号端221至连接点之间设置电阻24，则可以使降低信号反射的效果更显著。
当然，上述第一连接线路23的连接点与第一连接线路23所连接的第一信号端211之间的线路长度，也可以等于或者大于连接点与第一连接线路23所连接的第二信号端221之间的线路长度，在此并不进行限定。
在一些实施方式中，上述目标第二信号端221通过第一电阻24连接至第二连接线路23，且第一电阻24与目标第二信号端221之间的第一线路长度大于第二线路长度，其中：
第二线路长度为：第一电阻24与第二连接线路23之间的线路长度；
目标第二信号端221为至少一个第二信号端221中的任一第二信号端221。
同样地，由于第一线路长度大于第二线路长度，从而可以进一步缩短目标第二信号端221对应的第一信号端211的传输信号，在第二连接线路23至目标第二信号端221之间传输的线路长度，从而进一步降低第一信号端211的传输信号的反射。
当然，第一线路长度也可以小于或者等于第二线路长度，在此也不作限定。
需要说明的是，由于第二摄像头22的第二信号端221在传输信号时，传输信号也会到达第一摄像头21产生反射信号，导致第二摄像头22的信号眼图变差，为降低第二摄像头22的拍摄质量受反射信号的影响，在一些实施方式中，第一摄像头21和第二摄像头22满足以下至少一项：
第二摄像头22的像素低于第一摄像头21的像素；
第二摄像头22的信号频率低于第一摄像头21的信号频率；
第二摄像头22的传输速率低于第一摄像头21的传输速率。
本发明实施例中，上述第一信号端211和第二信号端221的数量可以相同，即上述M等于上述N。
示例性地，如图2中所示，摄像模组包括摄像头A(相当于第一摄像头21)、摄像头B(相当于第二摄像头22)以及电阻模块，且摄像头B为低像素摄像头，摄像头A可以为高像素摄像头，也可以像素高于摄像头B的低像素摄像头；
其中，摄像头A的MIPI发送接口A包括时钟信号端CLKA、数据信号端D1A和D2A(相当于M个第一信号端211，且M＝3)，CLKA、D1A和D2A与处理器10的MIPI接收接口连接，且CLKA与MIPI接收端口的CLK连接、D1A与MIPI接收端口的D1连接以及D2A与MIPI接收端口的D2连接，形成3条连接线路23；
电阻模块包括电阻R1、电阻R2和电阻R3，且电阻R1、电阻R2和电阻R3的阻值范围可以为5Ω至200Ω；
摄像头B的MIPI发送接口B包括时钟信号端CLKB、数据信号端D1B和D2B(相当于N个第二信号端221，且N＝3)，且CLKB通过电阻R1连接于CLK1与CLK之间的连接线路23上，D1B通过电阻R2连接于D1A与D1之间的连接线路23上，以及D2B通过电阻R3连接于D2A与D2之间的连接线路23上(即上述至少一个第二信号端221包括CLKB、D1B和D2B)，且电阻模块靠近摄像头A设置；
摄像头A和摄像头B采集到的包含图像信息的电信号通过MIPI接口传 输到处理器10，MIPI发送接口A和MIPI发送接口B为输出，MIPI接收接口为输入，MIPI发送接口A和MIPI发送接口B上述走线电气连接，CLKA、D1A、D2A、CLK、D1、D2、CLKB、D1B、D2B为MIPI差分对走线的网络名，一个差分对包含P和N两条MIPI走线，所有连接到同一个公共节点的MIPI走线实现电气连接；电阻模块的一端连接到MIPI发送接口B，另一端连接到公共节点处；
当摄像头A工作时，摄像头B处于待机或断电状态，此时CLKA、D1A、D2A、CLK、D1和D2为MIPI信号主路，CLKB、D1B和D2B为MIPI信号支路，MIPI发送接口A通过MIPI信号主路发送至MIPI接收接口，此时MIPI主路信号上会叠加MIPI支路走线反射的信号，导致MIPI接收接口的信号眼图变差(例如，如图3a所示，为未设置电阻模块时摄像头A的信号眼图)，电阻模块14的作用是减小支路走线的反射大小，改善MIPI接收接口位置的眼图，如图3b所示，为设置电阻模块时摄像头A的信号眼图。当摄像头A的MIPI速率较高，MIPI支路走线较长时，在电阻模块14的作用下，MIPI接收接口位置的信号眼图仍可以满足标准要求。
当摄像头B工作时，摄像头A处于待机或断电状态，此时CLKB、D1B、D2B、CLK、D1和D2为MIPI信号主路，CLKA、D1A和D2A为MIPI信号支路，MIPI发送接口B通过MIPI信号主路发送至MIPI接收接口，此时MIPI主路信号上会叠加MIPI支路走线反射回来的信号，导致MIPI接收接口的信号眼图变差。其中，摄像头B可采用低像素摄像头，MIPI速率低，支路走线较短，信号反射较小，由如图3c所示的为摄像头B的信号眼图可知，在MIPI主路上串联电阻24后MIPI接收接口位置的信号眼图仍可以满足标准要求；
需要说明的是，在上述M等于N的情况下，上述摄像头A和摄像头B还可以包括其他数量的信号端，例如，在此列举如下方式一和方式二进行说明：
方式一中，摄像头A的MIPI发送接口A包括时钟信号端和1个数据信号端(M＝2)，且摄像头B的MIPI发送接口B包括时钟信号端和1个数据信号端(N＝2)，此时，电阻模块包括3个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和1个数据信号端；
方式二中，摄像头A的MIPI发送接口A包括时钟信号端和4个数据信号端(M＝5)，且摄像头B的MIPI发送接口B包括时钟信号端和4个数据信号端(N＝5)，此时，电阻模块包括5个电阻24，，以及处理器10的MIPI接收端口包括时钟信号端和4个数据信号端，即如图4所示。
当然，上述第一信号端211和第二信号端221的数量可以不相同，即上述M大于上述N，例如，在此列举如下方式三至方式五进行说明：
方式三中，摄像头A的MIPI发送接口A包括时钟信号端和2个数据信号端(M＝3)，且摄像头B的MIPI发送接口B包括时钟信号端和1个数据信号端(N＝2)，此时，电阻模块包括2个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和2个数据信号端；
方式四中，摄像头A的MIPI发送接口A包括时钟信号端和4个数据信号端(M＝5)，且摄像头B的MIPI发送接口B包括时钟信号端和1个数据信号端(N＝2)，此时，电阻模块包括2个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和4个数据信号端；
方式五中，摄像头A的MIPI发送接口A包括时钟信号端和4个数据信号端(M＝5)，且摄像头B的MIPI发送接口B包括时钟信号端和2个数据信号端(N＝3)，此时，电阻模块包括3个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和4个数据信号端。
需要说明的是，上述摄像模组除设置有上述第一摄像头21和第二摄像头22之外，还可以设置其他摄像头，例如，还可以设置一与第一摄像头21同时工作的摄像头，等等。
在一些实施方式中，M个第一信号端211包括第一时钟信号端，且N条连接线路23包括连接第一时钟信号端的第三连接线路23；N个第二信号端221包括第二时钟信号端，且第二时钟信号端通过第二电阻24与第三连接线路23连接；摄像模组还包括设置有K个第三信号端的第三摄像头，且K个第三信号端中的第三时钟信号与第三连接线路23连接；除第三时钟信号之外的K-1个第三信号端分别连接第一信号端211与处理器10之间的连接线路23，且至少一个第三信号端分别通过电阻24与对应的连接线路23连接，K为正整数，从而在摄像模组设置有两个以上的摄像头的情况下，可以降低第 一摄像头21传输信号时的反射，提升第一摄像头21的拍摄质量。
需要说明的是，第三信号端连接的连接线路23与第二信号端221连接的连接线路23可以相同，也可以不同；另外，第三摄像头与第一摄像头21、第二摄像头22之间的工作原理，类似于第一摄像头21与第二摄像头22之间的工作原理，对此不再进行赘述。
示例性地，在此提供方式六至方式十五，对摄像模组设置有第一摄像头21、第二摄像头22以及第三摄像头的情况进行说明，具体如下：
方式六中，摄像头A的MIPI发送接口A包括时钟信号端和1个数据信号端(M＝2)，且摄像头B的MIPI发送接口B包括时钟信号端和1个数据信号端(N＝2)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和1个数据信号端(N＝2)，此时，电阻模块包括4个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和1个数据信号端，如图5所示；
方式七中，摄像头A的MIPI发送接口A包括时钟信号端和2个数据信号端(M＝3)，且摄像头B的MIPI发送接口B包括时钟信号端和2个数据信号端(N＝3)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和1个数据信号端(N＝2)，此时，电阻模块包括5个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和2个数据信号端；
方式八中，摄像头A的MIPI发送接口A包括时钟信号端和4个数据信号端(M＝5)，且摄像头B的MIPI发送接口B包括时钟信号端和4个数据信号端(N＝5)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和1个数据信号端(N＝2)，此时，电阻模块包括7个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和4个数据信号端；
方式九中，摄像头A的MIPI发送接口A包括时钟信号端和2个数据信号端(M＝3)，且摄像头B的MIPI发送接口B包括时钟信号端和1个数据信号端(N＝2)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和2个数据信号端(N＝3)，此时电，阻模块包括5个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和2个数据信号端；
方式十中，摄像头A的MIPI发送接口A包括时钟信号端和2个数据信号端(M＝3)，且摄像头B的MIPI发送接口B包括时钟信号端和2个数据信 号端(N＝3)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和2个数据信号端(N＝3)，此时，电阻模块包括6个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和2个数据信号端；
方式十一中，摄像头A的MIPI发送接口A包括时钟信号端和4个数据信号端(M＝5)，且摄像头B的MIPI发送接口B包括时钟信号端和4个数据信号端(N＝5)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和2个数据信号端(N＝3)，此时电，阻模块包括8个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和4个数据信号端；
方式十二中，摄像头A的MIPI发送接口A包括时钟信号端和4个数据信号端(M＝5)，且摄像头B的MIPI发送接口B包括时钟信号端和1个数据信号端(N＝2)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和4个数据信号端(N＝5)，此时，电阻模块包括7个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和4个数据信号端；
方式十三中，摄像头A的MIPI发送接口A包括时钟信号端和4个数据信号端(M＝5)，且摄像头B的MIPI发送接口B包括时钟信号端和2个数据信号端(N＝3)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和4个数据信号端(N＝5)，此时，电阻模块包括8个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和4个数据信号端；
方式十中，摄像头A的MIPI发送接口A包括时钟信号端和4个数据信号端(M＝5)，且摄像头B的MIPI发送接口B包括时钟信号端和4个数据信号端(N＝5)，摄像头C(即第三摄像头)的MIPI发送接口C包括时钟信号端和4个数据信号端(N＝5)，此时，电阻模块包括10个电阻24，以及处理器10的MIPI接收端口包括时钟信号端和4个数据信号端。
本发明实施例中，摄像模组包括第一摄像头21和第二摄像头22，第一摄像头21设置有M个第一信号端211，第二摄像头22设置有N个第二信号端221，M和N为正整数，且M大于或者等于N：M个第一信号端211与处理器10连接形成M条连接线路23；N个第二信号端221与M条连接线路23中的N条连接线路23一一对应连接，且至少一个第二信号端221通过电阻24连接至其所对应的连接线路23。这样，既可以实现第一摄像头21和第二 摄像头22的分时拍摄，又可以降低第一摄像头21拍摄时的信号反射，提升摄像模组的拍摄质量。
基于上述摄像模组，本发明实施例还提供一种电子设备，包括上述摄像模组。
由于电子设备本体的结构是现有技术，摄像模组在上述实施例中已进行详细说明，因此，本实施例中对于具体的电子设备的结构不再赘述。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (7)

  1. 一种摄像模组，应用于包括处理器的电子设备，所述摄像模组包括第一摄像头和第二摄像头，所述第一摄像头设置有M个第一信号端，所述第二摄像头设置有N个第二信号端，所述M和所述N为正整数，且所述M大于或者等于所述N，其特征在于：
    所述M个第一信号端与所述处理器连接形成M条连接线路；
    所述N个第二信号端与所述M条连接线路中的N条连接线路一一对应连接，且至少一个第二信号端通过电阻连接至其所对应的连接线路。
  2. 根据权利要求1所述的摄像模组，其特征在于，第一连接线路的连接点与所述第一连接线路所连接的第一信号端之间的线路长度，小于所述连接点与所述第一连接线路所连接的第二信号端之间的线路长度；
    所述第一连接线路为所述N条连接线路中的任一条连接线路。
  3. 根据权利要求2所述的摄像模组，其特征在于，目标第二信号端通过第一电阻连接至第二连接线路，且所述第一电阻与所述目标第二信号端之间的第一线路长度大于第二线路长度，其中：
    所述第二线路长度为：所述第一电阻与所述第二连接线路之间的线路长度；
    所述目标第二信号端为所述至少一个第二信号端中的任一第二信号端。
  4. 根据权利要求1至3中任一项所述的摄像模组，其特征在于，所述第一摄像头和所述第二摄像头满足以下至少一项：
    所述第二摄像头的像素低于所述第一摄像头的像素；
    所述第二摄像头的信号频率低于所述第一摄像头的信号频率；
    所述第二摄像头的传输速率低于所述第一摄像头的传输速率。
  5. 根据权利要求1至3中任一项所述的摄像模组，其特征在于，所述M个第一信号端包括第一时钟信号端，且所述N条连接线路包括连接所述第一时钟信号端的第三连接线路；
    所述N个第二信号端包括第二时钟信号端，且所述第二时钟信号端通过第二电阻与所述第三连接线路连接；
    所述摄像模组还包括设置有K个第三信号端的第三摄像头，且所述K个第三信号端中的第三时钟信号与所述第三连接线路连接；
    除第三时钟信号之外的K-1个第三信号端分别连接所述第一信号端与所述处理器之间的连接线路，且至少一个所述第三信号端分别通过电阻与对应的连接线路连接，所述K为正整数。
  6. 根据权利要求1至3中任一项所述的摄像模组，其特征在于，所述N个第二信号端中，每一第二信号端通过电阻连接至其所对应的连接线路。
  7. 一种电子设备，包括处理器，其特征在于，所述电子设备还包括如权利要求1至6中任一项所述的摄像模组。
PCT/CN2020/123880 2019-10-30 2020-10-27 摄像模组及电子设备 WO2021083107A1 (zh)

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