WO2021082417A1 - Procédé et système pour commander l'accès à un port série interne d'un dispositif à nœuds multiples - Google Patents

Procédé et système pour commander l'accès à un port série interne d'un dispositif à nœuds multiples Download PDF

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Publication number
WO2021082417A1
WO2021082417A1 PCT/CN2020/092816 CN2020092816W WO2021082417A1 WO 2021082417 A1 WO2021082417 A1 WO 2021082417A1 CN 2020092816 W CN2020092816 W CN 2020092816W WO 2021082417 A1 WO2021082417 A1 WO 2021082417A1
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serial port
cpld
path
node
serial
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PCT/CN2020/092816
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English (en)
Chinese (zh)
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史文举
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苏州浪潮智能科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C

Definitions

  • the present invention relates to the technical field of cloud computing, and more specifically, to a method and system for controlling internal serial port access of a multi-node device.
  • the current storage multi-control system or server blade system has multiple nodes in the device.
  • a baseboard management controller (Baseboard Management Controller, BMC for short) is used to externally output serial signals of the BMC and operating system.
  • BMC Baseboard Management Controller
  • the commonly used method is to aggregate the serial port signals of each node through the Complex Programmable Logic Device (CPLD) of the management board, and then output them to the outside in a unified manner.
  • the outside world can switch the external serial port to a different serial port through the serial port switch command of the CPLD.
  • this method only provides BMC and operating system strings. Adding other device serial ports will increase the demand for backplane signal pins, occupying expensive backplane connectors and causing waste of resources.
  • the purpose of the embodiments of the present invention is to provide a method and system for controlling internal serial port access of a multi-node device.
  • 3-level switching the access requirements of all equipment serial ports in the machine can be realized on any management board, the cost of the backplane is saved, and the R&D, production and debugging, and after-sales fault location are convenient.
  • one aspect of the embodiments of the present invention provides a method for controlling access to the internal serial port of a multi-node device, which includes the following steps:
  • the first CPLD controlling each of the several nodes selects one of the serial ports of the several serial devices connected to it;
  • the first CPLD transmits the serial device information corresponding to the selected serial port path to the multiplexer (MUX) chip in the node;
  • Control the MUX chip to select the output path according to the control instructions of the external serial port, and transmit the serial device information to the second CPLD in the corresponding management board through the node serial port path corresponding to the output path;
  • the management board controls the second CPLD to select the node serial port path of one of several nodes according to the switching instruction of the external serial port;
  • the second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.
  • the first CPLD that controls each node of the plurality of nodes selects one of the serial port channels of the serial port devices connected to it.
  • One also includes:
  • the first CPLD provides the path where the first BMC serial port is located as the default path of the first CPLD.
  • the output path of the MUX chip is connected to the backplane to transmit serial device information to the second CPLD in the management board through the backplane.
  • the MUX chip includes two output channels, and the two output channels are respectively connected to the first management board and the second management board.
  • the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the corresponding management board through the node serial port path corresponding to the output path
  • the second CPLD in also includes:
  • the output path selection of the MUX chip is controlled by the output level of the GPIO of the first BMC in the node.
  • the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the corresponding management board through the node serial port path corresponding to the output path
  • the second CPLD in also includes:
  • the MUX chip output strobes the first management board
  • the MUX chip output strobes the second management board.
  • the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the corresponding management board through the node serial port path corresponding to the output path
  • the second CPLD in also includes:
  • the MUX chip provides the path where the first management board is located as the default output path of the MUX chip.
  • the management board controls the second CPLD to select one of the node serial port channels of one of the several nodes according to the switching instruction of the external serial port further includes:
  • the second CPLD provides the path of the second BMC serial port as the default path of the second CPLD.
  • the present invention also provides a control system for access to the internal serial port of a multi-node device, which is characterized in that it includes:
  • At least one memory stores program instructions that can be run on the processor, and the program instructions execute the following steps when run by the processor:
  • the first CPLD controlling each of the several nodes selects one of the serial ports of the several serial devices connected to it;
  • the first CPLD transmits the serial device information corresponding to the selected serial port path to the MUX chip in the node;
  • Control the MUX chip to select the output path according to the control instruction of the external serial port, and transmit the serial device information to the second CPLD in the corresponding management board through the node serial path corresponding to the output path;
  • the management board controls the second CPLD to select the node serial port path of one of several nodes according to the switching instruction of the external serial port;
  • the second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.
  • the output path of the MUX chip is connected to the backplane to transmit the serial device information to the second CPLD in the management board through the backplane, and the backplane is used for Interaction of transit information.
  • the present invention has the following beneficial technical effects: the present invention adopts 3-level switching control, and all serial ports in the control node are collected into the first-level CPLD, which can meet the access of the serial ports of the internal equipment of the node; the MUX chip divides the serial ports collected by the CPLD in the node into 2 When the serial port is connected to two management boards, the output of MUX is controlled by the network, and the corresponding management board is selected according to the control, which reduces the signal demand and at the same time satisfies the reliability that both management boards can access the serial port; the serial port signal output by each node passes through The backplane is gathered to the CPLD on the management board, and output to the external serial port through the second-level CPLD switch, so that the access requirements of all the device serial ports in the machine can be realized on any management board, saving the cost of the backplane, and facilitating R&D, production and debugging, and after-sales failure Positioning.
  • FIG. 1 is a schematic diagram of an embodiment of a method for controlling internal serial port access of a multi-node device provided by the present invention
  • FIG. 2 is a schematic diagram of a first embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention
  • FIG. 3 is a schematic diagram of a second embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention
  • Fig. 4 is a schematic diagram of a third embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention.
  • Fig. 1 shows a schematic diagram of an embodiment of a method for controlling internal serial port access of a multi-node device provided by the present invention.
  • the embodiment of the present invention includes the following steps:
  • the first CPLD1 transmits the serial device information corresponding to the selected serial port path to the MUX chip in the node;
  • the management board controls the second CPLD to select the node serial port path of one of several nodes according to the switching instruction of the external serial port;
  • the second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.
  • Fig. 2 shows a schematic diagram of a first embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention.
  • the first CPLD1 that is, all serial devices that need to be accessed are connected to the first CPLD.
  • step S100 according to the selection instruction of the external serial port, the first CPLD controlling each of the several nodes selects one of the serial ports of the several serial devices connected to it.
  • a multiplexer is made by encoding, and the first CPLD selects the serial port channel according to the received selection instruction.
  • the first CPLD defines the switching special character command of the selection instruction as: @# ⁇ %0-f, where @# ⁇ % remains unchanged, 0 to f change, and 16 devices are supported
  • the selection of the serial port path, @#$%0 selects the serial port of the first BMC of the node, @#$%1 selects the serial port of the first device, @#$%2 selects the serial port of the second device, and so on.
  • step S200 the first CPLD transmits the serial device information corresponding to the selected serial port path to the MUX chip in the node.
  • step S300 the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the second CPLD in the corresponding management board through the node serial port path corresponding to the output path.
  • the MUX chip is a 2 out of 1 chip, and the MUX chip is respectively connected to two management boards through a Universal Asynchronous Receiver/Transmitter (UART).
  • UART Universal Asynchronous Receiver/Transmitter
  • step S400 the management board controls the second CPLD to select the node serial port path of one of several nodes according to the switching instruction of the external serial port.
  • the serial port signals output by each node are collected in the second CPLD on the management board.
  • the second CPLD is encoded as a multiplexer.
  • the second CPLD selects the serial port channel according to the received switching command. Because the first CPLD and the second CPLD The CPLD is on one path, so the instructions for switching the respective paths need to be differentiated.
  • the second CPLD defines the switching instruction as: &*%$0-g, where &*%$ remains unchanged Change from 0 to g.
  • the second BMC serial port can support 16 controller node channel strobes, &*%$0 strobes the second BMC serial port of the management board, &*%$1 strobes the first node serial port , &*%$2 strobes the serial port of the second node, and so on.
  • the second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.
  • the first CPLD that controls each of the several nodes selects the serial ports of the serial devices connected to it
  • One also includes:
  • the first CPLD provides the path where the first BMC serial port is located as the default path of the first CPLD.
  • the BMC is used to externally output the serial port signals of the BMC and the operating system.
  • the output path of the MUX chip is connected to the backplane to transmit the serial device information to the second CPLD in the management board through the backplane.
  • the board is used for the exchange of relay information.
  • the serial port signals output by each node are collected through the backplane to the second CPLD on the management board, because through the method of controlling access to the internal serial ports of the multi-node device of the present invention, all nodes pass through the first CPLD. , The collection function of the second CPLD can greatly save the cost of the backplane.
  • the MUX chip includes two output channels, and the two output channels are respectively connected to the first management board and the second management board.
  • the MUX chip corresponds to two management boards.
  • the system reliability is low.
  • the existence of two management boards not only increases the reliability of the system, but also does not increase the cost as much as more management boards.
  • the two management boards can also access the serial ports on different nodes at the same time, which is convenient for multiple people to debug, develop and locate problems at the same time.
  • the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the corresponding management through the node serial port path corresponding to the output path
  • the second CPLD in the board also includes:
  • the output path selection of the MUX chip is controlled by the output level of the GPIO of the first BMC in the node.
  • the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the corresponding management through the node serial port path corresponding to the output path
  • the second CPLD in the board also includes:
  • the MUX chip output strobes the first management board
  • the MUX chip output strobes the second management board.
  • the high and low levels are manually set.
  • the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the corresponding management through the node serial port path corresponding to the output path
  • the second CPLD in the board also includes:
  • the MUX chip provides the path where the first management board is located as the default output path of the MUX chip.
  • Fig. 3 shows a schematic diagram of a second embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention.
  • the first CPLD is to select the first BMC by default
  • the MUX is also to select the first management board by default.
  • the serial port strobe connection is shown in Figure 3.
  • the management board controls the second CPLD to select one of the node serial ports of several nodes according to the switching instruction of the external serial port further includes:
  • the second CPLD provides the path of the second BMC serial port as the default path of the second CPLD.
  • Fig. 4 shows a schematic diagram of a third embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention.
  • a control system for accessing internal serial ports of a multi-node device provided by the present invention.
  • you want to access the serial port of the first device on the second node through the second management board you first need to inform the first BMC of the second node to control the GPIO through the network through the network port of the second management board.
  • the present invention also provides a control system for access to the internal serial port of a multi-node device, which is characterized in that it includes:
  • At least one memory stores program instructions that can be run on the processor, and the program instructions execute the following steps when run by the processor:
  • the first CPLD controlling each of the several nodes selects one of the serial ports of the several serial devices connected to it;
  • the first CPLD transmits the serial device information corresponding to the selected serial port path to the MUX chip in the node;
  • Control the MUX chip to select the output path according to the control instructions of the external serial port, and transmit the serial device information to the second CPLD in the corresponding management board through the node serial port path corresponding to the output path;
  • the management board controls the second CPLD to select the node serial port path of one of several nodes according to the switching instruction of the external serial port;
  • the second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.
  • the output path of the MUX chip is connected to the backplane to transmit the serial device information to the second CPLD in the management board through the backplane, and the backplane is used for Interaction of transit information.
  • the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, and the computer program may be stored in a computer-readable storage medium.
  • the computer program executes the above-mentioned functions defined in the method disclosed in the embodiment of the present invention.
  • the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.
  • non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory Memory.
  • Volatile memory can include random access memory (RAM), which can act as external cache memory.
  • RAM can be obtained in many forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchronous link DRAM (SLDRAM) and direct Rambus RAM (DRRAM).
  • DRAM synchronous RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM Synchronous link DRAM
  • DRRAM direct Rambus RAM
  • the storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FPGA Field Programmable Gate Array
  • a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP, and/or any other such configuration.
  • the steps of the method or algorithm described in combination with the disclosure herein may be directly included in hardware, a software module executed by a processor, or a combination of the two.
  • the software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from or write information to the storage medium.
  • the storage medium may be integrated with the processor.
  • the processor and the storage medium may reside in the ASIC.
  • the ASIC can reside in the user terminal.
  • the processor and the storage medium may reside as discrete components in the user terminal.
  • functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted through the computer-readable medium.
  • Computer-readable media include computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another location.
  • a storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or may be used to carry or store instructions in the form of Or any other medium that can be accessed by a general-purpose or special-purpose computer or general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
  • coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to send software from a website, server, or other remote source
  • coaxial cable Cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media.
  • magnetic disks and optical disks include compact disks (CDs), laser disks, optical disks, digital versatile disks (DVD), floppy disks, and Blu-ray disks. Disks usually reproduce data magnetically, while optical disks use lasers to optically reproduce data. . Combinations of the above content should also be included in the scope of computer-readable media.
  • the program can be stored in a computer-readable storage medium.
  • the storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

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Abstract

L'invention concerne un procédé pour commander l'accès à un port série interne d'un dispositif à nœuds multiples, comprenant les étapes suivantes : selon une instruction de sélection d'un port série externe, un premier CPLD qui commande chaque nœud parmi plusieurs nœuds sélectionne un chemin de port série de plusieurs dispositifs série qui lui sont connectés ; le premier CPLD transmet des informations de dispositif série correspondant au chemin de port série sélectionné à une puce MUX dans le nœud ; selon une instruction de commande du port série externe, la puce MUX est commandée pour sélectionner un chemin de sortie, et transmettre les informations de dispositif série à un second CPLD dans une carte de gestion correspondante au moyen d'un chemin de port série de nœud correspondant au chemin de sortie ; selon une instruction de commutation du port série externe, la carte de gestion commande le second CPLD pour sélectionner un chemin de port série de nœud d'un nœud parmi plusieurs nœuds ; et le second CPLD transmet les informations de dispositif série correspondant au chemin de port série de nœud sélectionné au port série externe. La solution de la présente invention peut réaliser la demande d'accès à des ports série de tous les dispositifs dans le système entier sur n'importe quelle carte de gestion, réduire les coûts de fond de panier et faciliter la recherche et le développement, le débogage et la localisation de défauts.
PCT/CN2020/092816 2019-10-30 2020-05-28 Procédé et système pour commander l'accès à un port série interne d'un dispositif à nœuds multiples WO2021082417A1 (fr)

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