WO2021082417A1

WO2021082417A1 - Method and system for controlling internal serial port access of multi-node device

Info

Publication number: WO2021082417A1
Application number: PCT/CN2020/092816
Authority: WO
Inventors: 史文举
Original assignee: 苏州浪潮智能科技有限公司
Priority date: 2019-10-30
Filing date: 2020-05-28
Publication date: 2021-05-06
Also published as: CN111078603A; CN111078603B

Abstract

A method for controlling internal serial port access of a multi-node device, comprising the following steps: according to a selection instruction of an external serial port, a first CPLD that controls each node of several nodes selects one serial port path of several serial devices connected thereto; the first CPLD transmits serial device information corresponding to the selected serial port path to an MUX chip in the node; according to a control instruction of the external serial port, the MUX chip is controlled to select an output path, and transmit the serial device information to a second CPLD in a corresponding management board by means of a node serial port path corresponding to the output path; according to a switching instruction of the external serial port, the management board controls the second CPLD to select a node serial port path of one of several nodes; and the second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port. The solution of the present invention may achieve the access demand of serial ports of all devices in the entire system on any management board, save on back plate costs, and facilitate research and development, debugging and fault location.

Description

Method and system for controlling internal serial port access of multi-node equipment

This application claims the priority of the Chinese patent application filed to the Chinese Patent Office on October 30, 2019, with the application number 201911044684.4 and the invention title "A method and system for controlling internal serial port access of multi-node devices", and its entire contents Incorporated in this application by reference.

Technical field

The present invention relates to the technical field of cloud computing, and more specifically, to a method and system for controlling internal serial port access of a multi-node device.

Background technique

The current storage multi-control system or server blade system has multiple nodes in the device. Generally, a baseboard management controller (Baseboard Management Controller, BMC for short) is used to externally output serial signals of the BMC and operating system. With the increase of various complex applications, more and more devices need serial access. At present, the commonly used method is to aggregate the serial port signals of each node through the Complex Programmable Logic Device (CPLD) of the management board, and then output them to the outside in a unified manner. The outside world can switch the external serial port to a different serial port through the serial port switch command of the CPLD. . However, this method only provides BMC and operating system strings. Adding other device serial ports will increase the demand for backplane signal pins, occupying expensive backplane connectors and causing waste of resources.

Summary of the invention

In view of this, the purpose of the embodiments of the present invention is to provide a method and system for controlling internal serial port access of a multi-node device. Through the use of 3-level switching, the access requirements of all equipment serial ports in the machine can be realized on any management board, the cost of the backplane is saved, and the R&D, production and debugging, and after-sales fault location are convenient.

Based on the foregoing objectives, one aspect of the embodiments of the present invention provides a method for controlling access to the internal serial port of a multi-node device, which includes the following steps:

According to the selection instruction of the external serial port, the first CPLD controlling each of the several nodes selects one of the serial ports of the several serial devices connected to it;

The first CPLD transmits the serial device information corresponding to the selected serial port path to the multiplexer (MUX) chip in the node;

Control the MUX chip to select the output path according to the control instructions of the external serial port, and transmit the serial device information to the second CPLD in the corresponding management board through the node serial port path corresponding to the output path;

The management board controls the second CPLD to select the node serial port path of one of several nodes according to the switching instruction of the external serial port;

The second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.

According to the embodiment of the method for controlling access to the internal serial port of a multi-node device of the present invention, according to the selection instruction of the external serial port, the first CPLD that controls each node of the plurality of nodes selects one of the serial port channels of the serial port devices connected to it. One also includes:

The first CPLD provides the path where the first BMC serial port is located as the default path of the first CPLD.

According to the embodiment of the method for controlling internal serial port access of a multi-node device of the present invention, the output path of the MUX chip is connected to the backplane to transmit serial device information to the second CPLD in the management board through the backplane.

According to the embodiment of the method for controlling internal serial port access of a multi-node device of the present invention, the MUX chip includes two output channels, and the two output channels are respectively connected to the first management board and the second management board.

According to the embodiment of the method for controlling access to the internal serial port of a multi-node device of the present invention, the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the corresponding management board through the node serial port path corresponding to the output path The second CPLD in also includes:

The output path selection of the MUX chip is controlled by the output level of the GPIO of the first BMC in the node.

In response to the GPIO output being low, the MUX chip output strobes the first management board;

In response to the GPIO output being at a high level, the MUX chip output strobes the second management board.

The MUX chip provides the path where the first management board is located as the default output path of the MUX chip.

According to the embodiment of the method for controlling access to the internal serial port of a multi-node device of the present invention, wherein the management board controls the second CPLD to select one of the node serial port channels of one of the several nodes according to the switching instruction of the external serial port further includes:

The second CPLD provides the path of the second BMC serial port as the default path of the second CPLD.

On the other hand, the present invention also provides a control system for access to the internal serial port of a multi-node device, which is characterized in that it includes:

processor;

At least one memory, the memory stores program instructions that can be run on the processor, and the program instructions execute the following steps when run by the processor:

The first CPLD transmits the serial device information corresponding to the selected serial port path to the MUX chip in the node;

Control the MUX chip to select the output path according to the control instruction of the external serial port, and transmit the serial device information to the second CPLD in the corresponding management board through the node serial path corresponding to the output path;

According to the embodiment of the control system for accessing the internal serial port of the multi-node device of the present invention, the output path of the MUX chip is connected to the backplane to transmit the serial device information to the second CPLD in the management board through the backplane, and the backplane is used for Interaction of transit information.

The present invention has the following beneficial technical effects: the present invention adopts 3-level switching control, and all serial ports in the control node are collected into the first-level CPLD, which can meet the access of the serial ports of the internal equipment of the node; the MUX chip divides the serial ports collected by the CPLD in the node into 2 When the serial port is connected to two management boards, the output of MUX is controlled by the network, and the corresponding management board is selected according to the control, which reduces the signal demand and at the same time satisfies the reliability that both management boards can access the serial port; the serial port signal output by each node passes through The backplane is gathered to the CPLD on the management board, and output to the external serial port through the second-level CPLD switch, so that the access requirements of all the device serial ports in the machine can be realized on any management board, saving the cost of the backplane, and facilitating R&D, production and debugging, and after-sales failure Positioning.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained according to the drawings without creative work.

FIG. 1 is a schematic diagram of an embodiment of a method for controlling internal serial port access of a multi-node device provided by the present invention;

2 is a schematic diagram of a first embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention;

FIG. 3 is a schematic diagram of a second embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention;

Fig. 4 is a schematic diagram of a third embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following describes the embodiments of the present invention in detail in conjunction with specific embodiments and with reference to the accompanying drawings.

It should be noted that all the expressions "first" and "second" in the embodiments of the present invention are used to distinguish two entities with the same name but not the same or parameters that are not the same, as shown in "first" and "second" Only for the convenience of presentation, it should not be construed as a limitation to the embodiments of the present invention, and subsequent embodiments will not describe this one by one.

Based on the foregoing objective, the first aspect of the embodiments of the present invention proposes an embodiment of a method for controlling access to the internal serial port of a multi-node device. Fig. 1 shows a schematic diagram of an embodiment of a method for controlling internal serial port access of a multi-node device provided by the present invention. As shown in Figure 1, the embodiment of the present invention includes the following steps:

S100. According to the selection instruction of the external serial port, control the first CPLD1 of each of the several nodes to select one of the serial ports of several serial devices connected to it;

S200. The first CPLD1 transmits the serial device information corresponding to the selected serial port path to the MUX chip in the node;

S300. Control the MUX chip to select the output path according to the control instruction of the external serial port, and transmit the serial port device information to the second CPLD in the corresponding management board through the node serial port path corresponding to the output path;

S400. The management board controls the second CPLD to select the node serial port path of one of several nodes according to the switching instruction of the external serial port;

S500. The second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.

Fig. 2 shows a schematic diagram of a first embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention. As shown in FIG. 2, in some embodiments of the present invention, before step S100, all the serial ports in the node are first collected on the first CPLD1, that is, all serial devices that need to be accessed are connected to the first CPLD. Then, in step S100, according to the selection instruction of the external serial port, the first CPLD controlling each of the several nodes selects one of the serial ports of the several serial devices connected to it. Inside the first CPLD, a multiplexer is made by encoding, and the first CPLD selects the serial port channel according to the received selection instruction. In some embodiments of the present invention, the first CPLD defines the switching special character command of the selection instruction as: @#￥%0-f, where @#￥% remains unchanged, 0 to f change, and 16 devices are supported The selection of the serial port path, @#$％0 selects the serial port of the first BMC of the node, @#$%1 selects the serial port of the first device, @#$％2 selects the serial port of the second device, and so on.

In step S200, the first CPLD transmits the serial device information corresponding to the selected serial port path to the MUX chip in the node.

In step S300, the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the second CPLD in the corresponding management board through the node serial port path corresponding to the output path. In some embodiments of the present invention, the MUX chip is a 2 out of 1 chip, and the MUX chip is respectively connected to two management boards through a Universal Asynchronous Receiver/Transmitter (UART).

In step S400, the management board controls the second CPLD to select the node serial port path of one of several nodes according to the switching instruction of the external serial port. The serial port signals output by each node are collected in the second CPLD on the management board. The second CPLD is encoded as a multiplexer. The second CPLD selects the serial port channel according to the received switching command. Because the first CPLD and the second CPLD The CPLD is on one path, so the instructions for switching the respective paths need to be differentiated. In some embodiments of the present invention, the second CPLD defines the switching instruction as: &*%$0-g, where &*%$ remains unchanged Change from 0 to g. In addition to the second BMC serial port, it can support 16 controller node channel strobes, &*%$0 strobes the second BMC serial port of the management board, &*%$1 strobes the first node serial port , &*%$2 strobes the serial port of the second node, and so on.

Finally, according to step S500, the second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.

According to some embodiments of the method for controlling access to the internal serial port of a multi-node device of the present invention, according to an external serial port selection instruction, the first CPLD that controls each of the several nodes selects the serial ports of the serial devices connected to it One also includes:

In some embodiments of the present invention, there are multiple nodes in the device, and the BMC is used to externally output the serial port signals of the BMC and the operating system.

According to some embodiments of the method for controlling access to the internal serial port of the multi-node device of the present invention, the output path of the MUX chip is connected to the backplane to transmit the serial device information to the second CPLD in the management board through the backplane. The board is used for the exchange of relay information.

In some embodiments of the present invention, the serial port signals output by each node are collected through the backplane to the second CPLD on the management board, because through the method of controlling access to the internal serial ports of the multi-node device of the present invention, all nodes pass through the first CPLD. , The collection function of the second CPLD can greatly save the cost of the backplane.

According to some embodiments of the method for controlling internal serial port access of a multi-node device according to the present invention, the MUX chip includes two output channels, and the two output channels are respectively connected to the first management board and the second management board.

In some embodiments of the present invention, it is preferable that the MUX chip corresponds to two management boards. When the MUX chip corresponds to a management board, the system reliability is low. The existence of two management boards not only increases the reliability of the system, but also does not increase the cost as much as more management boards. Moreover, the two management boards can also access the serial ports on different nodes at the same time, which is convenient for multiple people to debug, develop and locate problems at the same time.

According to some embodiments of the method for controlling internal serial port access of a multi-node device according to the present invention, the MUX chip is controlled to select the output path according to the control instruction of the external serial port, and the serial device information is transmitted to the corresponding management through the node serial port path corresponding to the output path The second CPLD in the board also includes:

Among them, the high and low levels are manually set.

Fig. 3 shows a schematic diagram of a second embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention. In some embodiments of the present invention, if you want to access the serial port of the BMC on the first node through the first management board, the first CPLD is to select the first BMC by default, and the MUX is also to select the first management board by default. Enter the command &*%$1 from the external serial port of the management board, and the second CPLD will be strobed to the serial port of the first node, and the first management board can access the serial port of the first BMC on the first node. The serial port strobe connection is shown in Figure 3.

According to some embodiments of the method for controlling access to the internal serial port of a multi-node device according to the present invention, wherein the management board controls the second CPLD to select one of the node serial ports of several nodes according to the switching instruction of the external serial port further includes:

Fig. 4 shows a schematic diagram of a third embodiment of a control system for accessing internal serial ports of a multi-node device provided by the present invention. In some embodiments of the present invention, if you want to access the serial port of the first device on the second node through the second management board, you first need to inform the first BMC of the second node to control the GPIO through the network through the network port of the second management board. Pull up the strobe of MUX; then enter the switching command &*%$2 on the external serial port of the second management board, and the second CPLD will be strobed to the serial port of the second node; then enter @#$%1, and the first CPLD will be It will be selected to the serial port of the first device; that is, the second management board can access the serial port of the first device on the second node. The serial port strobe connection mode is shown in 4.

processor;

Similarly, those skilled in the art should understand that all the embodiments, features and advantages described above for the method for controlling access to the internal serial port of a multi-node device according to the present invention are equally applicable to the control of access to the internal serial port of a multi-node device according to the present invention. system. For the sake of brevity of the present disclosure, the description will not be repeated here.

It should be particularly pointed out that the steps in each embodiment of the method and system for controlling access to the internal serial port of the multi-node device can be crossed, replaced, added, and deleted. Therefore, these reasonable permutation and combination transformations should also belong to the original The protection scope of the invention should not be limited to the embodiments.

Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be realized by instructing relevant hardware through computer programs. Programs based on the method of controlling internal serial port access of multi-node devices can be stored. In a computer readable storage medium, when the program is executed, it may include the processes of the above-mentioned method embodiments. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc. The foregoing computer program embodiment can achieve the same or similar effects as any of the foregoing corresponding method embodiments.

In addition, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, and the computer program may be stored in a computer-readable storage medium. When the computer program is executed by the processor, it executes the above-mentioned functions defined in the method disclosed in the embodiment of the present invention.

In addition, the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.

In addition, it should be understood that the computer-readable storage medium (eg, memory) herein may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory Memory. Volatile memory can include random access memory (RAM), which can act as external cache memory. As an example and not limitation, RAM can be obtained in many forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchronous link DRAM (SLDRAM) and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and functions have been described in general terms. Whether this function is implemented as software or hardware depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art can implement the functions in various ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of the disclosure of the embodiments of the present invention.

The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein can be implemented or executed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSP), and application-specific integrated circuits (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP, and/or any other such configuration.

The steps of the method or algorithm described in combination with the disclosure herein may be directly included in hardware, a software module executed by a processor, or a combination of the two. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from or write information to the storage medium. In an alternative, the storage medium may be integrated with the processor. The processor and the storage medium may reside in the ASIC. The ASIC can reside in the user terminal. In an alternative, the processor and the storage medium may reside as discrete components in the user terminal.

In one or more exemplary designs, functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted through the computer-readable medium. Computer-readable media include computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another location. A storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or may be used to carry or store instructions in the form of Or any other medium that can be accessed by a general-purpose or special-purpose computer or general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if you use coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to send software from a website, server, or other remote source, the above-mentioned coaxial cable Cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media. As used herein, magnetic disks and optical disks include compact disks (CDs), laser disks, optical disks, digital versatile disks (DVD), floppy disks, and Blu-ray disks. Disks usually reproduce data magnetically, while optical disks use lasers to optically reproduce data. . Combinations of the above content should also be included in the scope of computer-readable media.

The above are exemplary embodiments disclosed by the present invention, but it should be noted that various changes and modifications can be made without departing from the scope of the disclosure of the embodiments of the present invention as defined by the claims. The functions, steps and/or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any specific order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual forms, they may also be understood as plural unless explicitly limited to a singular number.

It should be understood that as used herein, unless the context clearly supports an exception, the singular form "a" is intended to also include the plural form. It should also be understood that "and/or" as used herein refers to any and all possible combinations including one or more items listed in association.

The serial numbers of the disclosed embodiments of the foregoing embodiments of the present invention are only for description, and do not represent the superiority of the embodiments.

Those of ordinary skill in the art can understand that all or part of the steps in the above-mentioned embodiments can be completed by hardware, or by a program instructing related hardware to be completed. The program can be stored in a computer-readable storage medium. The storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope of disclosure (including the claims) of the embodiments of the present invention is limited to these examples; under the idea of the embodiments of the present invention The above embodiments or the technical features in different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

A method for controlling internal serial port access of a multi-node device is characterized in that it comprises the following steps:

According to the selection instruction of the external serial port, the first CPLD controlling each of the several nodes selects one of the serial ports of the several serial devices connected to it;

The first CPLD transmits the serial device information corresponding to the selected serial port path to the multiplexer chip in the node;

Control the multiplexer chip to select an output path according to the control instruction of the external serial port, and transmit the serial port device information to the second CPLD in the corresponding management board through the node serial port path corresponding to the output path;

The management board controls the second CPLD to select the node serial port path of one of the several nodes according to the switching instruction of the external serial port;

The second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.
The method according to claim 1, wherein, according to the selection instruction of the external serial port, controlling the first CPLD of each of the plurality of nodes to select one of the serial ports of the serial devices connected to it further comprises:

The first CPLD provides the path where the first BMC serial port is located as the default path of the first CPLD.
The method according to claim 1, wherein the output path of the multiplexer chip is connected to a backplane to transmit the serial device information to the management board through the backplane. In the second CPLD.
The method according to claim 1, wherein the multiplexer chip includes two output paths, and the two output paths are respectively connected to a first management board and a second management board.
The method according to claim 4, wherein the multiplexer chip is controlled to select an output path according to a control instruction of the external serial port, and the serial device information is passed through a node corresponding to the output path The second CPLD transmitted through the serial port path to the corresponding management board also includes:

The multiplexer chip is controlled by the output level of the GPIO of the first BMC in the node to select the output path.
The method according to claim 5, wherein the multiplexer chip is controlled to select an output path according to a control instruction of the external serial port, and the serial port device information is passed through a node corresponding to the output path The second CPLD transmitted through the serial port path to the corresponding management board also includes:

In response to the GPIO output being low, the multiplexer chip output strobes the first management board;

In response to the GPIO output being at a high level, the multiplexer chip output strobes the second management board.
The method according to claim 6, wherein the multiplexer chip is controlled to select an output path according to a control instruction of the external serial port, and the serial port device information is passed through a node corresponding to the output path The second CPLD transmitted through the serial port path to the corresponding management board also includes:

The multiplexer chip provides the path where the first management board is located as the default output path of the multiplexer chip.
The method according to claim 4, wherein the management board controlling the second CPLD to select the node serial port path of one of the several nodes according to the switching instruction of the external serial port further comprises:

The second CPLD provides the path where the second BMC serial port is located as the default path of the second CPLD.
A control system for accessing internal serial ports of a multi-node device, which is characterized in that it comprises:

processor;

At least one memory, the memory stores program instructions that can be run on the processor, and the program instructions perform the following steps when run by the processor:

According to the selection instruction of the external serial port, the first CPLD controlling each of the several nodes selects one of the serial ports of the several serial devices connected to it;

The first CPLD transmits the serial device information corresponding to the selected serial port path to the multiplexer chip in the node;

Controlling the multiplexer chip selection output path according to the control instruction of the external serial port, and transmitting the serial port device information to the second CPLD in the corresponding management board through the node serial port path corresponding to the output path;

The management board controls the second CPLD to select the node serial port path of one of the several nodes according to the switching instruction of the external serial port;

The second CPLD transmits the serial device information corresponding to the selected node serial port path to the external serial port.
The system according to claim 9, wherein the output path of the multiplexer chip is connected to a backplane, so as to transmit the serial device information to the second in the management board through the backplane. CPLD.