WO2021081787A1 - 运算放大器及运算放大器的启动电路 - Google Patents

运算放大器及运算放大器的启动电路 Download PDF

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WO2021081787A1
WO2021081787A1 PCT/CN2019/114257 CN2019114257W WO2021081787A1 WO 2021081787 A1 WO2021081787 A1 WO 2021081787A1 CN 2019114257 W CN2019114257 W CN 2019114257W WO 2021081787 A1 WO2021081787 A1 WO 2021081787A1
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Prior art keywords
operational amplifier
transistor
amplifier
terminal
stage
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PCT/CN2019/114257
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English (en)
French (fr)
Inventor
余永长
易岷
李伟男
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19950556.1A priority Critical patent/EP4044428A4/en
Priority to PCT/CN2019/114257 priority patent/WO2021081787A1/zh
Priority to CN201980101650.6A priority patent/CN114616754A/zh
Publication of WO2021081787A1 publication Critical patent/WO2021081787A1/zh
Priority to US17/733,359 priority patent/US20220263470A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45269—Complementary non-cross coupled types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H03F3/45641—Measuring at the loading circuit of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45008—Indexing scheme relating to differential amplifiers the addition of two signals being made by a resistor addition circuit for producing the common mode signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45082—Indexing scheme relating to differential amplifiers the common mode signal being taken or deducted from the one or more outputs of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45358—Indexing scheme relating to differential amplifiers the AAC comprising multiple transistors parallel coupled at their sources and drains only, e.g. in a cascode dif amp, only those forming the composite common source transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45396—Indexing scheme relating to differential amplifiers the AAC comprising one or more switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45404—Indexing scheme relating to differential amplifiers the CMCL comprising capacitors containing, not in parallel with the resistors, an addition circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45418—Indexing scheme relating to differential amplifiers the CMCL comprising a resistor addition circuit

Definitions

  • This application relates to the field of electronic technology, and in particular to operational amplifiers and operational amplifier startup circuits.
  • Operational amplifier as one of the most basic modules in analog integrated circuits, is widely used in various analog circuits and digital-analog hybrid circuits. Take the RF transceiver system as an example. Operational amplifiers are usually used in trans-impedance amplifiers (TIA), low-pass filters (LPF), variable gain amplifiers (VGA), and analog amplifiers. Digital converter (analog to digital converter, ADC), digital to analog converter (digital to analog converter, DAC) and other key modules. In the link cascade system, if the pre-stage or post-stage circuits of these key modules cannot provide an effective start signal, the operational amplifier may not be able to start smoothly, thus working in a normal amplifying working state.
  • TIA trans-impedance amplifiers
  • LPF low-pass filters
  • VGA variable gain amplifiers
  • ADC analog to digital converter
  • DAC digital to analog converter
  • the operational amplifier may not be able to start smoothly, thus working in a normal amplifying working state.
  • the operational amplifier usually needs a start-up circuit to ensure the self-starting of the operational amplifier.
  • the start-up circuit can provide a start-up current during the start-up process of the operational amplifier to ensure that the transistors in the operational amplifier work in the normal amplifying working state.
  • the application provides an operational amplifier and a startup circuit of the operational amplifier, which has the advantages of simple structure and low power consumption.
  • an operational amplifier including: a multi-stage series amplifier; and a start-up circuit.
  • the start-up circuit includes: a first start-up transistor M16 and a second start-up transistor M17, the source of the first start-up transistor M16 and the source of the second start-up transistor M17 and the first stage of the multi-stage series amplifier
  • the tail bias node of the amplifier is connected, the gate of the first start transistor M16 and the gate of the second start transistor M17 are used to connect the first bias voltage V b , and the drain of the first start transistor M16
  • the drain of the second start transistor M17 is connected to the input terminal of the amplifier of the second stage or above.
  • the embodiment of the present application provides an operational amplifier, which includes a startup circuit capable of quickly starting the operational amplifier.
  • the start-up circuit has a simple structure and no additional poles and zeros are introduced, so there is no need for bandwidth compensation of an operational amplifier, which is conducive to high-speed and high-gain design.
  • the operating current of the startup circuit after the operational amplifier is started is small, which has the advantage of low power consumption.
  • the first bias voltage V b is set such that: when the input transistor pair of the first-stage amplifier is not turned on,
  • the gate-source voltage, V th represents the threshold voltage of the first start transistor M16 and the second start transistor M17.
  • the first bias voltage V b can be configured so that after the operational amplifier startup circuit is started,
  • the tail bias node is the drain of the tail bias transistor M5 of the first-stage amplifier.
  • the tail bias node is one end of a bias resistor of the first-stage amplifier.
  • the operational amplifier includes a three-stage series amplifier, and the drain of the first startup transistor M16 is connected to the third input transistor of the second-stage amplifier.
  • the gate of M7 is connected, and the drain of the second start transistor M17 is connected to the gate of the fourth input transistor M9 of the second stage amplifier.
  • the operational amplifier further includes: a stability compensation circuit, including a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2 ,
  • a stability compensation circuit including a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2 ,
  • the first end of the first capacitor C1 is connected to the drain of the third input transistor M7 of the second stage amplifier, the second end of the first capacitor C1 is connected to the first end of the first resistor R1, and the The second end of the first resistor R1 is connected to the drain of the first input transistor M1 of the first stage amplifier;
  • the first end of the second capacitor C2 is connected to the drain of the fourth input transistor M9 of the second stage amplifier,
  • the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the drain of the second input transistor M2 of the first stage amplifier.
  • the operational amplifier further includes a common-mode detection circuit
  • the common-mode detection circuit includes: a first input terminal for receiving the output of the operational amplifier The first differential output voltage Voutp; the second input terminal is used to receive the second differential output voltage Voutn output by the operational amplifier; the output terminal is used to output the common-mode output voltage V CM , the common-mode output voltage V CM Is the average value of the first differential output voltage Voutp and the second differential output voltage Voutn.
  • the common mode detection circuit includes: a third resistor R3 and a fourth resistor R4, and the first end of the third resistor R3 is connected to the operation
  • the first differential output end of the amplifier is connected
  • the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the second end of the operational amplifier.
  • the differential output ends are connected, and the second end of the third resistor R3 is the output end of the common mode detection circuit.
  • the operational amplifier further includes: a common mode loop compensation circuit, including a third capacitor C3 and a fourth capacitor C4.
  • the first terminal is connected to the first differential output terminal of the operational amplifier
  • the second terminal of the third capacitor C3 is connected to the first terminal of the fourth capacitor C4
  • the second terminal of the fourth capacitor C4 is connected to The second differential output terminal of the operational amplifier is connected.
  • the operational amplifier further includes a common-mode negative feedback circuit
  • the common-mode negative feedback circuit includes an error amplifier
  • the first input terminal of the error amplifier Is used to receive the common mode reference voltage V CMREF of the operational amplifier
  • the second input terminal of the error amplifier is used to receive the common mode output voltage V CM output by the common mode detection circuit
  • the output terminal of the error amplifier is connected to The bias circuit of the operational amplifier is connected.
  • a startup circuit of an operational amplifier includes a multi-stage series amplifier.
  • the startup circuit includes a first startup transistor M16 and a second startup transistor M17.
  • the source and the source of the second start transistor M17 are connected to the tail bias node of the first stage amplifier in the multi-stage series amplifier, and the gate of the first start transistor M16 and the second start transistor
  • the gate of M17 is used to connect the first bias voltage V b , the drain of the first start transistor M16 and the drain of the second start transistor M17, and the input terminal of the second stage or higher amplifier Connected.
  • the embodiment of the present application provides a start-up circuit, which can quickly start the operational amplifier.
  • the start-up circuit has a simple structure and no additional poles and zeros are introduced, so there is no need for bandwidth compensation of an operational amplifier, which is conducive to high-speed and high-gain design. And after starting the operational amplifier, the operating current is small, which has the advantage of low power consumption.
  • the first bias voltage V b is set such that: when the input transistor pair of the first-stage amplifier is not conducting,
  • V GS represents the gate-source voltage of the first start transistor M16 and the second start transistor M17
  • V th represents the first The threshold voltages of the startup transistor M16 and the second startup transistor M17.
  • the tail bias node is the drain of the tail bias transistor M5 of the first-stage amplifier.
  • the tail bias node is one end of a bias resistor of the first-stage amplifier.
  • the operational amplifier includes a three-stage series amplifier, and the drain of the first startup transistor M16 is connected to the third input transistor of the second-stage amplifier.
  • the gate of M7 is connected, and the drain of the second start transistor M17 is connected to the gate of the fourth input transistor M9 of the second stage amplifier.
  • the operational amplifier further includes:
  • the stability compensation circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2.
  • the first end of the second capacitor C2 is connected to the drain of the fourth input transistor M9 of the second stage amplifier, the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second capacitor C2 is connected to the first end of the second resistor R2.
  • the second end of the resistor R2 is connected to the drain of the second input transistor M2 of the first stage amplifier.
  • the operational amplifier further includes a common-mode detection circuit
  • the common-mode detection circuit includes: a first input terminal for receiving an output of the operational amplifier The first differential output voltage Voutp; the second input terminal is used to receive the second differential output voltage Voutn output by the operational amplifier; the output terminal is used to output the common-mode output voltage V CM , the common-mode output voltage V CM Is the average value of the first differential output voltage Voutp and the second differential output voltage Voutn.
  • the common mode detection circuit includes: a third resistor R3 and a fourth resistor R4, and the first end of the third resistor R3 is connected to the operation
  • the first differential output end of the amplifier is connected
  • the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the second end of the operational amplifier.
  • the differential output ends are connected, and the second end of the third resistor R3 is the output end of the common mode detection circuit.
  • the operational amplifier further includes: a common mode loop compensation circuit, including a third capacitor C3 and a fourth capacitor C4.
  • the first terminal is connected to the first differential output terminal of the operational amplifier
  • the second terminal of the third capacitor C3 is connected to the first terminal of the fourth capacitor C4
  • the second terminal of the fourth capacitor C4 is connected to The second differential output terminal of the operational amplifier is connected.
  • the operational amplifier further includes a common-mode negative feedback circuit
  • the common-mode negative feedback circuit includes an error amplifier
  • the first input of the error amplifier The terminal is used to receive the common-mode reference voltage V CMREF of the operational amplifier
  • the second input terminal of the error amplifier is used to receive the common-mode output voltage V CM output by the common-mode detection circuit
  • the output terminal of the error amplifier It is connected with the bias circuit of the operational amplifier.
  • a chip in a third aspect, includes the operational amplifier described in the first aspect or any one of the possible implementation manners of the first aspect.
  • an electronic device in a fourth aspect, includes the operational amplifier described in the first aspect or any one of the possible implementation manners of the first aspect.
  • Fig. 1 is a schematic diagram of an application environment of an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an operational amplifier according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an operational amplifier according to another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an operational amplifier according to another embodiment of the present application.
  • FIG. 5 is a schematic diagram of the circuit structure of an operational amplifier according to an embodiment of the present application.
  • the embodiments of the present application provide an operational amplifier and a startup circuit of the operational amplifier.
  • the startup circuit has the advantages of simple circuit structure and low power consumption, and can realize the rapid startup of the operational amplifier.
  • Fig. 1 is a schematic diagram of an application environment of an embodiment of the present application.
  • Figure 1 shows a schematic diagram of the link cascade in a radio frequency system.
  • the radio frequency system is a receiver system, including a low noise amplifier (LNA), a mixer, and a trans-impedance amplifier (TIA) , Low-pass filter (low-pass filter, LPF) and analog to digital converter (analog to digital converter, ADC).
  • LNA low noise amplifier
  • TIA trans-impedance amplifier
  • LPF Low-pass filter
  • ADC analog to digital converter
  • the operational amplifier in the embodiment of the present application can be set in the TIA, LPF, VGA, ADC and other modules in FIG. 1. It should be noted that FIG.
  • the operational amplifier can be widely used in various analog integrated circuits or digital-to-analog integrated circuits.
  • filter circuits for example, filter circuits, amplifying circuits, arithmetic circuits, signal generating circuits, signal conversion circuits, or power supplies.
  • the abnormal amplification working state may mean that the input voltage of the operational amplifier exceeds its normal input voltage range.
  • Abnormal amplification working state includes input low bias and input high bias. Input low bias means that the input voltage of the operational amplifier is lower than the lower limit of its normal input voltage range, and input high bias means that the input voltage of the operational amplifier is higher than the upper limit of its normal input voltage range.
  • the input transistor pair of the operational amplifier may be in the sub-threshold region, and the operating current is much lower than the expected value, thereby affecting various characteristic parameters of the circuit and causing it to deviate from the design index.
  • the operational amplifier cannot work in the normal amplifying working state, but in the abnormal amplifying working state.
  • the operational amplifier usually needs a startup circuit to ensure the self-starting of the operational amplifier.
  • the start-up circuit can provide a start-up current during the start-up process of the operational amplifier to ensure that the transistors in the operational amplifier work in the normal amplifying working state.
  • the embodiment of the present application provides a start-up circuit, which can quickly start the operational amplifier.
  • the starting circuit has a simple structure and does not affect the performance of the main signal path. And after starting the operational amplifier, the operating current is small, which has the advantage of low power consumption.
  • FIG. 2 is a schematic structural diagram of an operational amplifier 200 according to an embodiment of the present application.
  • the operational amplifier 200 may include a multi-stage series amplifier.
  • the operational amplifier 200 may be a two-stage amplifier, a three-stage amplifier, or an amplifier with more than three stages.
  • the operational amplifier 200 is a two-stage amplifier as an example for description.
  • the operational amplifier 200 includes a first-stage amplifier, a second-stage amplifier, and a startup circuit.
  • the input terminal of the operational amplifier 200 may be a differential input terminal.
  • the output terminal of the operational amplifier 200 may be a differential output terminal or a single output terminal, which is not limited in the embodiment of the present application. If the operational amplifier 200 is a differential output terminal, the differential input terminal may be referred to as a first differential input terminal Vinp and a second differential input terminal Vinn, respectively.
  • the differential output terminals of the above operational amplifier may be referred to as the first differential output terminal Voutp and the second differential output terminal Voutn, respectively.
  • the first stage amplifier includes a bias circuit, a tail bias circuit, and an input transistor pair (M1, M2).
  • the transistor M1 and the transistor M2 may be referred to as the first input transistor M1 and the second input transistor M2, or collectively referred to as the input transistor pair of the first-stage amplifier.
  • the gates (g) of the input transistor pair (M1, M2) are the differential input terminals (Vinp, Vinn) of the operational amplifier 200, respectively.
  • the source (s) of the input transistor pair (M1, M2) is connected to the tail bias circuit, and the drain (d) of the input transistor pair (M1, M2) is connected to the bias circuit.
  • the drain (d) of the input transistor pair (M1, M2) is the output terminal of the first stage amplifier, which is connected to the input terminal of the second stage amplifier.
  • the tail bias circuit and the bias circuit are used to provide bias current for the input transistor pair (M1, M2).
  • the startup circuit includes a first startup transistor M16 and a second startup transistor M17, wherein the first startup transistor M16 and the second startup transistor M17 form a differential transistor pair.
  • the transistor M16 and the transistor M17 may be collectively referred to as a start transistor pair.
  • the source (s) of the start transistor pair (M16, M17) is connected to the tail bias node P of the first stage amplifier, and the gate (g) of the start transistor pair (M16, M17) is used to connect the first bias voltage V b .
  • the drain (d) of the start-up transistor pair (M16, M17) can be connected to the input of the second stage or above the amplifier. Among them, as an example, the drain (d) of the startup transistor pair (M16, M17) shown in FIG. 2 is connected to the input terminal of the second-stage amplifier.
  • the tail bias node P of the first-stage amplifier may refer to the node where the tail-bias circuit of the first-stage amplifier is connected to the source (s) of the input transistor pair (M1, M2).
  • the tail bias circuit may include a tail bias transistor, and the tail bias node P may be the drain of the tail bias transistor of the first stage amplifier.
  • the tail bias circuit may include a bias resistor, and the tail bias node P is one end of the bias resistor of the first-stage amplifier.
  • the tail bias node P may be the source (s) of the input transistor pair (M1, M2).
  • the voltage at the tail bias node P can be represented by V p .
  • the input terminal of the amplifier of the second stage or above may be a differential input terminal.
  • the differential input terminal of the second stage amplifier may include a first differential input terminal Vinp2 and a second differential input terminal Vinn2.
  • the drains (d) of the startup transistors M16 and M17 may be connected to the two differential input terminals of the second stage or higher amplifiers, respectively. As shown in Figure 2, the drain (d) of the first start transistor M16 is connected to the first differential input terminal Vinp2 of the second stage amplifier, and the drain (d) of the second start transistor M17 is connected to the second stage amplifier's second The differential input terminal Vinn2 is connected.
  • connection of the source (s) and drain (d) of the startup transistor pair (M16, M17) is the same as the source (s) and drain of the input transistor pair (M1, M2) of the first-stage amplifier.
  • the connection method of pole (d) is the same. That is, the source (s) of the startup transistor pair (M16, M17) and the source (s) of the input transistor pair (M1, M2) are connected to the same node, and the drain (d) of the startup transistor pair (M16, M17) is connected to the input The drains (d) of the transistor pair (M1, M2) are connected to the same node.
  • each bias voltage in the circuit is first established, for example, the first bias voltage V b , the tail bias circuit, and the bias voltage in the bias circuit.
  • the start-up transistors (M16, M17) are turned on first to generate working current and drive the second stage amplifier of the operational amplifier to work.
  • the input transistor pair (M1, M2) is driven to work through the external loop feedback, so that the operational amplifier 200 enters a normal working state, thereby completing the startup of the operational amplifier 200.
  • the first bias voltage V b is set such that: before the operational amplifier 200 starts,
  • the startup transistor pair (M16, M17) is in a conducting state. Therefore, after the operational amplifier 200 is powered on, the start transistor pair (M16, M17) is first turned on and generates an operating current to start the operational amplifier.
  • V p represents the voltage at the tail bias node P.
  • the setting of the first bias voltage V b is such that after the operational amplifier 200 is started,
  • the startup circuit of the operational amplifier in the embodiment of the present application has a simple structure and can be implemented with only two transistors. After the start of the operational amplifier 200, since the enable transistor (M16, M17) the gate-source voltage V GS is reduced, and therefore, current I D starting circuit after start of the operational amplifier is small, it is conducive to low-power circuits.
  • formula (1) shows the formula of the operating current when the transistor is operating in the saturation region
  • I D represents the operating current
  • ⁇ represents the mobility of carriers
  • C ox represents the capacitance per unit area of the gate oxide layer of the transistor
  • W represents the channel width of the transistor
  • L represents the channel length of the transistor
  • V GS represents The gate-source voltage of the transistor
  • V th represents the threshold voltage of the transistor.
  • V GS decreases, the operating current I D is also decreased. If V GS is less than V th, the operating state of the MOS transistor into the cut-off region, ideally, the operating current I D is zero.
  • the first bias voltage V b may be set to be equal to the common mode reference voltage V CMREF of the operational amplifier 200.
  • the loop of the startup circuit in the embodiment of the present application is simple, and no additional poles and zeros are introduced, so there is no need for bandwidth compensation of the operational amplifier, which is beneficial to high-speed and high-gain design.
  • the startup circuit of the embodiment of the application adopts a differential structure, and the differential characteristic is better.
  • the operating current of the start-up circuit is reduced or even zero, so that no additional direct current offset (DC offset) is introduced, which is conducive to the low-voltage design of advanced technology.
  • the above-mentioned startup transistor pair (M16, M17) can be N-metal-oxide-semiconductor (NMOS) tubes, or P-metal-oxide-semiconductor (P-metal-oxide-semiconductor). semiconductor, PMOS) tube.
  • the type of the start transistor pair (M16, M17) can be the same as the input transistor pair (M1, M2) of the first-stage amplifier. If the input transistor pair (M1, M2) is an NMOS tube, the start transistor (M16 , M17) is an NMOS tube. If the input transistor pair (M1, M2) is a PMOS tube, the startup transistor pair (M16, M17) is a PMOS tube.
  • the operational amplifier in the embodiments of the present application may use a complementary metal oxide semiconductor (CMOS) process, or may use other integrated circuit processes.
  • CMOS complementary metal oxide semiconductor
  • BJT bipolar junction transistor
  • SOI silicon-on-insulator
  • FIG. 3 is a schematic structural diagram of an operational amplifier 300 according to another embodiment of the present application.
  • the operational amplifier 300 in FIG. 3 has a similar structure to the operational amplifier 200 in FIG. 2, and the difference is that the drains of the startup transistor pair (M16, M17) are respectively connected to the two differential input terminals of the third-stage amplifier. That is, the drain of the first startup transistor M16 is connected to the first differential input terminal of the third stage amplifier, and the drain (d) of the second startup transistor M17 is connected to the second differential input terminal of the third stage amplifier.
  • FIG. 4 is a schematic structural diagram of an operational amplifier 400 according to another embodiment of the present application.
  • the start-up circuit may only include the first start-up transistor M16, the source of the first start-up transistor M16 is used to connect to the tail bias node P, and the gate of the first start-up transistor M16 is used to connect to the first bias voltage V b , the drain of the first startup transistor M16 is used to connect to the input terminal of the amplifier of the second stage or above.
  • the drain of the first startup transistor M16 in FIG. 4 is used to connect to any one of the two differential input terminals of the second-stage amplifier.
  • the drain of the first startup transistor M16 may also be used to connect to any one of the two differential input terminals of the amplifier above the second stage.
  • FIG. 5 is a schematic diagram of a circuit structure of an operational amplifier 500 according to another embodiment of the present application.
  • the operational amplifier 500 in FIG. 5 is a two-stage amplifier. It should be understood that after limited modifications, the structure of the operational amplifier 500 is also suitable for three-stage amplifiers or amplifiers with more than three stages.
  • the first stage amplifier circuit of the operational amplifier includes transistors M1, M2, M3, M4, and M5.
  • the bias circuit of the first-stage amplifier in FIG. 2 to FIG. 4 may include the transistors M3 and M4 in FIG. 5.
  • the tail bias circuit of the first stage amplifier in FIGS. 2 to 4 may include the transistor M5 in FIG. 5.
  • the transistors M3 and M4 may be referred to as bias transistors
  • the transistor M5 may be referred to as a tail bias transistor.
  • the second stage amplifier circuit of the operational amplifier includes transistors M6, M7, M8, and M9.
  • the sources of the bias transistors M3 and M4 are connected to the power supply V DD , and the drains of the bias transistors M3 and M4 are connected to the drains of the input transistor pair (M1, M2).
  • the transistor M7 and the transistor M9 are the input transistor pair of the second-stage amplifier.
  • the transistor M7 and the transistor M9 may be referred to as the third input transistor M7 and the fourth input transistor M9 of the second-stage amplifier.
  • the gate of the third input transistor M7 is the first differential input terminal of the second stage amplifier
  • the gate of the fourth input transistor M9 is the second differential input terminal of the second stage amplifier.
  • the drain of the third input transistor M7 is the first differential output terminal of the second stage amplifier
  • the drain of the fourth input transistor M9 is the second differential output terminal of the second stage amplifier
  • the third input transistor M7 and the fourth input transistor M9 The drain is also the differential output of the operational amplifier.
  • the startup circuit includes a first startup transistor M16 and a second startup transistor M17.
  • the gates of the first start transistor M16 and the second start transistor M17 are used to connect the first bias voltage V b .
  • the sources of the first start transistor M16 and the second start transistor M17 are connected, and connected to the drain of the tail bias transistor M5.
  • the drain of the first start transistor M16 is connected to the gate of the third input transistor M7 of the second stage amplifier, and the drain of the second start transistor M17 is connected to the gate of the fourth input transistor M9 of the second stage amplifier.
  • the drain of the third input transistor M7 is the differential output terminal V outp of the operational amplifier
  • the drain of the fourth input transistor M9 is the differential output terminal V outn of the operational amplifier.
  • the operational amplifier further includes a stability compensation circuit, which can be used for frequency compensation of the fully differential amplifier.
  • the stability compensation circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2.
  • the drain of the third input transistor M7 is connected to the first terminal of the first capacitor C1, the second terminal of the first capacitor C1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the first terminal.
  • the drain of the first input transistor M1 of the amplifier is connected.
  • the drain of the fourth input transistor M9 is connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the first end
  • the drain of the second input transistor M2 of the amplifier is connected.
  • the transistor M15 is a current mirror bias circuit of the operational amplifier, which is used to receive the bias current and generate a bias voltage for the operational amplifier.
  • the transistor M12 and the transistor M13 adopt a diode connection, which constitutes the load of the error amplifier in the common-mode negative feedback circuit.
  • the operational amplifier further includes a common-mode detection circuit, and the common-mode detection circuit is used to generate a common-mode output voltage V CM of the operational amplifier.
  • the common mode detection circuit includes a third resistor R3 and a fourth resistor R4.
  • the first end of the third resistor R3 is connected to the first differential output terminal Voutp of the operational amplifier.
  • the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the second differential output terminal Voutn of the operational amplifier, and the third resistor
  • the second terminal of R3 is the output terminal of the common mode detection circuit.
  • the operational amplifier further includes a common mode loop compensation circuit, and the common mode loop compensation circuit is used for frequency compensation of the common mode loop.
  • the common mode loop compensation circuit includes a third capacitor C3 and a fourth capacitor C4, the first end of the third capacitor C3 is connected to the first differential output terminal Voutp of the operational amplifier, The second terminal of the third capacitor C3 is connected to the first terminal of the fourth capacitor, and the second terminal of the fourth capacitor is connected to the second differential output terminal Voutn of the operational amplifier.
  • the second end of the third capacitor C3 is connected to the output end of the common mode detection circuit, that is, the second end of the third capacitor C3 is connected to the second end of the third resistor R3.
  • the operational amplifier further includes a common-mode negative feedback circuit.
  • the common-mode negative feedback circuit is used to compare the common-mode output voltage V CM and the common-mode reference voltage V CMREF , and adjust the bias circuit of the operational amplifier according to the comparison result to make the common mode negative feedback circuit.
  • the mode output voltage V CM is equal to the common mode reference voltage V CMREF.
  • the common-mode negative feedback circuit includes an error amplifier. The first input terminal of the error amplifier is used to connect to the common-mode reference voltage V CMREF of the operational amplifier, and the second input terminal of the error amplifier is used for The common mode output voltage V CM connected to the operational amplifier is connected to the second end of the third resistor R3. The output terminal of the error amplifier is connected with the bias circuit of the operational amplifier, so as to adjust the bias circuit of the operational amplifier.
  • the error amplifier includes transistors M10, M11, M12, M13, and M14.
  • the transistor M10 and the transistor M11 are amplifier tubes, and the transistors M12, M13, and M14 are bias transistors.
  • the gates of the transistor M10 and the transistor M11 are the differential input terminals of the error amplifier, and the drain of the transistor M10 is the output terminal of the error amplifier.
  • the gate of the transistor M10 in the common-mode negative feedback circuit is connected to the second end of the third resistor R3 in the common-mode detection circuit.
  • the gate of the transistor M11 in the common mode feedback circuit is used to connect to the common mode reference voltage V CMREF.
  • FIG. 5 is only used as an example of the specific circuit structure of the operational amplifier in the embodiment of the present application, and is not a limitation.
  • the feedback circuit may also adopt other implementation manners, which is not limited in the embodiment of the present application.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

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Abstract

本申请提供了一种运算放大器以及运算放大器的启动电路，具有结构简单，功耗低的优点。该运算放大器包括：多级串联放大器和启动电路，该启动电路包括第一启动晶体管M16和第二启动晶体管M17，第一启动晶体管M16的源极和第二启动晶体管M17的源极与多级串联放大器中的第一级放大器的尾偏置节点相连，第一启动晶体管M16的栅极和第二启动晶体管M17的栅极用于连接第一偏置电压V b，第一启动晶体管M16的漏极和第二启动晶体管M17的漏极与第二级或第二级以上的放大器的输入端相连。

Description

运算放大器及运算放大器的启动电路 技术领域
本申请涉及电子技术领域，尤其涉及运算放大器及运算放大器的启动电路。
背景技术
运算放大器(operational amplifier,OPA)作为模拟集成电路中最基本的模块之一，广泛应用于各种模拟电路和数模混合电路中。以射频收发系统为例，运算放大器通常应用于跨阻放大器(trans-impedance amplifier,TIA)、低通滤波器(low-pass filter,LPF)、可变增益放大器(variable gain amplifier，VGA)、模数转换器(analog to digital converter，ADC)、数模转换器(digital to analog converter，DAC)等关键模块中。在链路级联系统中，如果这些关键模块的前级或后级电路不能提供有效的启动信号，则运算放大器不一定能够顺利启动，从而工作在正常放大工作状态。因此，运算放大器通常需要启动电路以保证运算放大器的自启动。启动电路可以在运算放大器启动过程中提供启动电流，以保证运算放大器中的各晶体管工作在正常放大工作态。虽然现有的电路设计中存在多种拓扑的启动电路，但业界一直在研究功耗更低，设计更简单的启动电路。
发明内容
本申请提供了一种运算放大器和运算放大器的启动电路，具有结构简单、功耗低的优点。
第一方面，提供了一种运算放大器，包括：多级串联放大器；启动电路。该启动电路包括：第一启动晶体管M16和第二启动晶体管M17，所述第一启动晶体管M16的源极和所述第二启动晶体管M17的源极与所述多级串联放大器中的第一级放大器的尾偏置节点相连，所述第一启动晶体管M16的栅极和所述第二启动晶体管M17的栅极用于连接第一偏置电压V b，所述第一启动晶体管M16的漏极和所述第二启动晶体管M17的漏极与第二级或第二级以上的放大器的输入端相连。
本申请实施例提供了一种运算放大器，其包括的启动电路能够快速启动运算放大器。该启动电路结构简单，没有引入额外的零极点，所以无需运算放大器的进行带宽补偿，有利于高速高增益设计。并且启动电路在运算放大器启动之后的工作电流小，具有功耗低的优点。
结合第一方面，在第一方面的某些可能的实现方式中，所述第一偏置电压V b的设置使得：在所述第一级放大器的输入晶体管对未导通的情况下，|V GS|＞|V th|；以及，在所述运算放大器启动之后，|V GS|＜|V th|，其中，V GS表示所述第一启动晶体管M16和所述第二启动晶体管M17的栅源电压，V th表示所述第一启动晶体管M16和所述第二启动晶体管M17的阈值电压。
本申请实施例中，可以通过配置第一偏置电压V b，使得运算放大器启动电路在启动 之后，|V GS|＜|V th|，因而理想状态下启动电路的工作电流为零，从而不会引入额外的直流失调，提高了运算放大器的性能，并减少了功耗。
结合第一方面，在第一方面的某些可能的实现方式中，所述尾偏置节点为所述第一级放大器的尾偏置晶体管M5的漏极。
结合第一方面，在第一方面的某些可能的实现方式中，所述尾偏置节点为所述第一级放大器的偏置电阻的一端。
结合第一方面，在第一方面的某些可能的实现方式中，所述运算放大器包括三级串联放大器，所述第一启动晶体管M16的漏极与所述第二级放大器的第三输入晶体管M7的栅极相连，所述第二启动晶体管M17的漏极与所述第二级放大器的第四输入晶体管M9的栅极相连。
结合第一方面，在第一方面的某些可能的实现方式中，所述运算放大器还包括：稳定性补偿电路，包括第一电阻R1、第二电阻R2、第一电容C1和第二电容C2，所述第一电容C1的第一端与第二级放大器的第三输入晶体管M7的漏极相连，所述第一电容C1的第二端与第一电阻R1的第一端相连，所述第一电阻R1的第二端与第一级放大器的第一输入晶体管M1的漏极相连；所述第二电容C2的第一端与第二级放大器的第四输入晶体管M9的漏极相连，所述第二电容C2的第二端与第二电阻R2的第一端相连，所述第二电阻R2的第二端与第一级放大器的第二输入晶体管M2的漏极相连。
结合第一方面，在第一方面的某些可能的实现方式中，所述运算放大器还包括共模检测电路，所述共模检测电路包括：第一输入端，用于接收所述运算放大器输出的第一差分输出电压Voutp；第二输入端，用于接收所述运算放大器输出的第二差分输出电压Voutn；输出端，用于输出共模输出电压V CM，所述共模输出电压V CM为所述第一差分输出电压Voutp和第二差分输出电压Voutn的平均值。
结合第一方面，在第一方面的某些可能的实现方式中，所述共模检测电路包括：第三电阻R3和第四电阻R4，所述第三电阻R3的第一端与所述运算放大器的第一差分输出端相连，所述第三电阻R3的第二端与所述第四电阻R4的第一端相连，所述第四电阻R4的第二端与所述运算放大器的第二差分输出端相连，所述第三电阻R3的第二端为所述共模检测电路的输出端。
结合第一方面，在第一方面的某些可能的实现方式中，所述运算放大器还包括：共模环路补偿电路，包括第三电容C3和第四电容C4，所述第三电容C3的第一端与所述运算放大器的第一差分输出端相连，所述第三电容C3的第二端与所述第四电容C4的第一端相连，所述第四电容C4的第二端与所述运算放大器的第二差分输出端相连。
结合第一方面，在第一方面的某些可能的实现方式中，所述运算放大器还包括共模负反馈电路，所述共模负反馈电路包括误差放大器，所述误差放大器的第一输入端用于接收所述运算放大器的共模参考电压V CMREF，所述误差放大器的第二输入端用于接收所述共模检测电路输出的共模输出电压V CM，所述误差放大器的输出端与所述运算放大器的偏置电路相连。
第二方面，提供了一种运算放大器的启动电路，所述运算放大器包括多级串联放大器，所述启动电路包括：第一启动晶体管M16和第二启动晶体管M17，所述第一启动晶体管M16的源极和所述第二启动晶体管M17的源极与所述多级串联放大器中的第一级放大器 的尾偏置节点相连，所述第一启动晶体管M16的栅极和所述第二启动晶体管M17的栅极用于连接第一偏置电压V b，所述第一启动晶体管M16的漏极和所述第二启动晶体管M17的漏极与第二级或第二级以上的放大器的输入端相连。
本申请实施例提供了一种启动电路，能够快速启动运算放大器。该启动电路结构简单，没有引入额外的零极点，所以无需运算放大器的进行带宽补偿，有利于高速高增益设计。并且在启动运算放大器之后的工作电流小，具有功耗低的优点。
结合第二方面，在第二方面的某些可能的实现方式中，所述第一偏置电压V b的设置使得：在所述第一级放大器的输入晶体管对处于未导通的情况下，|V GS|＞|V th|；以及，
在所述运算放大器启动之后，|V GS|＜|V th|，其中，V GS表示所述第一启动晶体管M16和所述第二启动晶体管M17的栅源电压，V th表示所述第一启动晶体管M16和所述第二启动晶体管M17的阈值电压。
结合第二方面，在第二方面的某些可能的实现方式中，所述尾偏置节点为所述第一级放大器的尾偏置晶体管M5的漏极。
结合第二方面，在第二方面的某些可能的实现方式中，所述尾偏置节点为所述第一级放大器的偏置电阻的一端。
结合第二方面，在第二方面的某些可能的实现方式中，所述运算放大器包括三级串联放大器，所述第一启动晶体管M16的漏极与所述第二级放大器的第三输入晶体管M7的栅极相连，所述第二启动晶体管M17的漏极与所述第二级放大器的第四输入晶体管M9的栅极相连。
结合第二方面，在第二方面的某些可能的实现方式中，所述运算放大器还包括：
稳定性补偿电路，包括第一电阻R1、第二电阻R2、第一电容C1和第二电容C2，所述第一电容C1的第一端与第二级放大器的第三输入晶体管M7的漏极相连，所述第一电容C1的第二端与第一电阻R1的第一端相连，所述第一电阻R1的第二端与第一级放大器的第一输入晶体管M1的漏极相连；所述第二电容C2的第一端与第二级放大器的第四输入晶体管M9的漏极相连，所述第二电容C2的第二端与第二电阻R2的第一端相连，所述第二电阻R2的第二端与第一级放大器的第二输入晶体管M2的漏极相连。
结合第二方面，在第二方面的某些可能的实现方式中，所述运算放大器还包括共模检测电路，所述共模检测电路包括：第一输入端，用于接收所述运算放大器输出的第一差分输出电压Voutp；第二输入端，用于接收所述运算放大器输出的第二差分输出电压Voutn；输出端，用于输出共模输出电压V CM，所述共模输出电压V CM为所述第一差分输出电压Voutp和第二差分输出电压Voutn的平均值。
结合第二方面，在第二方面的某些可能的实现方式中，所述共模检测电路包括：第三电阻R3和第四电阻R4，所述第三电阻R3的第一端与所述运算放大器的第一差分输出端相连，所述第三电阻R3的第二端与所述第四电阻R4的第一端相连，所述第四电阻R4的第二端与所述运算放大器的第二差分输出端相连，所述第三电阻R3的第二端为所述共模检测电路的输出端。
结合第二方面，在第二方面的某些可能的实现方式中，所述运算放大器还包括：共模环路补偿电路，包括第三电容C3和第四电容C4，所述第三电容C3的第一端与所述运算放大器的第一差分输出端相连，所述第三电容C3的第二端与所述第四电容C4的第一端 相连，所述第四电容C4的第二端与所述运算放大器的第二差分输出端相连。
结合第二方面，在第二方面的某些可能的实现方式中，所述运算放大器还包括：共模负反馈电路，所述共模负反馈电路包括误差放大器，所述误差放大器的第一输入端用于接收所述运算放大器的共模参考电压V CMREF，所述误差放大器的第二输入端用于接收所述共模检测电路输出的共模输出电压V CM，所述误差放大器的输出端与所述运算放大器的偏置电路相连。
第三方面，提供了一种芯片，所述芯片包括第一方面或第一方面中的任意一种可能的实现方式中所述的运算放大器。
第四方面，提供了一种电子设备，所述电子设备包括第一方面或第一方面中的任意一种可能的实现方式中所述的运算放大器。
附图说明
图1是本申请一实施例的应用环境的示意图。
图2是本申请一实施例的运算放大器的结构示意图。
图3是本申请又一实施例的运算放大器的结构示意图。
图4是本申请又一实施例的运算放大器的结构示意图。
图5是本申请一实施例的运算放大器的电路结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例提供了一种运算放大器以及运算放大器的启动电路，该启动电路具有电路结构简单，功耗低的优点，能够实现运算放大器的快速启动。
图1是本申请一实施例的应用环境的示意图。图1示出的为射频系统中的链路级联示意图，该射频系统为接收机系统，包括低噪声放大器(LNA)、混频器(mixer)、跨阻放大器(trans-impedance amplifier,TIA)、低通滤波器(low-pass filter,LPF)和模数转换器(analog to digital converter,ADC)。本申请实施例中的运算放大器可以设置于图1中的TIA、LPF、VGA、ADC等模块中。需要说明的是，图1仅作为示例以说明本申请实施例的运算放大器的应用环境，运算放大器可以广泛地应用在各种模拟集成电路或数模集成电路中。例如，滤波电路、放大电路、运算电路、信号发生电路、信号转换电路或电源等。
运算放大器在启动之后，通常存在两种稳定态，一个是正常放大工作态，另一个是非正常放大工作态。其中，非正常放大工作态可以指运算放大器的输入电压超出其正常输入电压范围。非正常放大工作态包括输入低偏置和输入高偏置的情况。输入低偏置是指运算放大器的输入电压低于其正常输入电压范围的下限，输入高偏置是指运算放大器的输入电压高于其正常输入电压范围的上限。运算放大器处于非正常工作状态时将影响其所在的电路模块或电路系统的工作性能。例如，在非正常放大状态下，运算放大器的输入晶体管对可能会处于亚阈值区域，工作电流远低于期望值，从而影响电路的各种特性参数，使其偏离设计指标。
如果运算放大器所在模块的前级或后级不能提供有效的启动信号，则运算放大器不能工作在正常放大工作状态，而是工作在非正常放大工作态。为了保证运算放大器在启动之 后工作在正常放大工作态，运算放大器通常需要启动电路以保证运算放大器的自启动。启动电路可以在运算放大器启动过程中提供启动电流，以保证运算放大器中的各晶体管工作在正常放大工作态。
现有技术中已存在各种原理和拓扑结构不同的启动电路，但是现有的启动电路中存在不足之处。例如，启动电路的启动过程中经过的启动环路级数多，需要额外的稳定性补偿设计。或者启动电路在启动之后还在工作，因此消耗了额外的功耗。并且启动电路设计复杂，占用了较多的芯片面积。
因此，本申请实施例提供了一种启动电路，能够快速启动运算放大器。该启动电路结构简单，不影响主信号通路性能。并且在启动运算放大器之后的工作电流小，具有功耗低的优点。接下来结合图2-图5，详细介绍本申请实施例提供的运算放大器以及运算放大器的启动电路。
图2是本申请一实施例的运算放大器200的结构示意图。运算放大器200可包括多级串联放大器，例如，运算放大器200可以是二级放大器、三级放大器或者三级以上的放大器。其中，图2中以运算放大器200为二级放大器为例进行说明。
如图2所示，运算放大器200包括第一级放大器、第二级放大器以及启动电路。运算放大器200的输入端可以为差分输入端。运算放大器200的输出端可以为差分输出端，也可以为单输出端，本申请实施例对此不作限定。若运算放大器200为差分输出端，则差分输入端可以分别称为第一差分输入端Vinp，和第二差分输入端Vinn。上述运算放大器的差分输出端可以分别称为第一差分输出端Voutp和第二差分输出端Voutn。
第一级放大器包括偏置电路、尾偏置电路以及输入晶体管对(M1，M2)。为了便于说明，可以将晶体管M1和晶体管M2称为第一输入晶体管M1和第二输入晶体管M2，或者合称为第一级放大器的输入晶体管对。输入晶体管对(M1，M2)的栅极(g)分别为运算放大器200的差分输入端(Vinp,Vinn)。输入晶体管对(M1,M2)的源极(s)与尾偏置电路相连，输入晶体管对(M1,M2)的漏极(d)与偏置电路相连。输入晶体管对(M1，M2)的漏极(d)为第一级放大器的输出端，其与第二级放大器的输入端相连。尾偏置电路和偏置电路用于为输入晶体管对(M1,M2)提供偏置电流。
继续参见图2，启动电路包括第一启动晶体管M16和第二启动晶体管M17，其中第一启动晶体管M16和第二启动晶体管M17形成差分晶体管对。为了便于说明，可以将晶体管M16和晶体管M17合称为启动晶体管对。启动晶体管对(M16,M17)的源极(s)与第一级放大器的尾偏置节点P相连，启动晶体管对(M16,M17)的栅极(g)用于连接第一偏置电压V b，启动晶体管对(M16,M17)的漏极(d)可以与第二级或第二级以上的放大器的输入端相连。其中，作为示例，图2所示的启动晶体管对(M16,M17)的漏极(d)与第二级放大器的输入端相连。
第一级放大器的尾偏置节点P可以指第一级放大器的尾偏置电路与输入晶体管对(M1,M2)的源极(s)相连处的节点。例如，尾偏置电路可以包括尾偏置晶体管，所述尾偏置节点P可以为第一级放大器的尾偏置晶体管的漏极。或者，尾偏置电路中可以包括偏置电阻，则所述尾偏置节点P为第一级放大器的偏置电阻的一端。或者，所述尾偏置节点P可以为输入晶体管对(M1,M2)的源极(s)。在本申请实施例中，尾偏置节点P处的电压可以用V p表示。
第二级或第二级以上的放大器的输入端可以为差分输入端。例如，第二级放大器的差分输入端可以包括第一差分输入端Vinp2和第二差分输入端Vinn2。在一些示例中，启动晶体管M16和M17的漏极(d)可以分别与第二级或第二级以上放大器的两个差分输入端相连。如图2所示，第一启动晶体管M16的漏极(d)与第二级放大器的第一差分输入端Vinp2相连，第二启动晶体管M17的漏极(d)与第二级放大器的第二差分输入端Vinn2相连。
在一些示例中，启动晶体管对(M16,M17)的源极(s)和漏极(d)的连接方式与第一级放大器的输入晶体管对(M1,M2)的源极(s)和漏极(d)的连接方式相同。即启动晶体管对(M16，M17)的源极(s)与输入晶体管对(M1,M2)的源极(s)连接同一节点，启动晶体管对(M16,M17)的漏极(d)与输入晶体管对(M1,M2)的漏极(d)连接同一节点。
在运算放大器200上电之后，电路中的各偏置电压首先建立，例如，第一偏置电压V b、尾偏置电路和偏置电路中的偏置电压。偏置电压建立之后，启动晶体管(M16，M17)首先导通，产生工作电流，并带动运算放大器的第二级放大器工作。第二级放大器启动之后，通过外部环路反馈带动输入晶体管对(M1，M2)工作，使得运算放大器200进入正常工作状态，从而完成运算放大器200的启动。
在一些示例中，为了使启动晶体管(M16,M17)在运算放大器200上电之后能够顺利导通，所述第一偏置电压V b的设置使得：在运算放大器200启动之前，|V GS|＞|V th|，其中，V GS表示启动晶体管对(M16,M17)的栅源电压，V th表示启动晶体管对(M16,M17)的阈值电压。在|V GS|＞|V th|时，启动晶体管对(M16,M17)处于导通状态。因而在运算放大器200上电之后，启动晶体管对(M16,M17)首先导通，并产生工作电流，以启动运算放大器。启动晶体管对(M16,M17)的栅源电压V GS可以表示为V GS＝V b-V p,其中，V p表示尾偏置节点P处的电压。在启动电路启动之后，第一级差分放大器正常工作，尾偏置电路为输入晶体管对(M1，M2)提供偏置电流，此时尾偏置节点P的电压V p升高，而偏置电压V b的大小不变。因此启动晶体管对(M16,M17)的栅源电压V GS＝V b-V p减小，从而启动晶体管对(M16,M17)的工作电流开始减小，也减少了启动电路的功耗。
在一些示例中，为了减少运算放大器200启动之后启动晶体管(M16,M17)的工作电流。所述第一偏置电压V b的设置使得：在运算放大器200启动之后，|V GS|＜|V th|。如果合理地设置第一偏置电压V b，可以使得运算放大器200启动之后(即处于正常放大工作态之后)，|V GS|＜|V th|。在这种情况下启动晶体管对(M16,M17)处于关断状态，理想状态下，启动晶体管对(M16,M17)的工作电流为零，从而减少启动电路的功耗。
本申请实施例中的运算放大器的启动电路结构简单，只需两个晶体管便可以实现。在运算放大器200启动之后，由于启动晶体管(M16,M17)的栅源电压V GS减小，因此，启动电路在运算放大器启动之后的工作电流I D较小，有利于实现低功耗电路。为了便于说明，公式(1)示出了晶体管在饱和区工作时的工作电流公式，
Figure PCTCN2019114257-appb-000001
其中，I D表示工作电流， μ表示载流子的迁移率，C ox表示晶体管的栅氧化层的单位面积电容大小，W表示晶体管的沟道宽度、L表示晶体管的沟道长度，V GS表示晶体管的 栅源电压，V th表示晶体管的阈值电压。
从公式(1)可以看出，随着V GS的减小，工作电流I D也随之减小。若V GS小于V th，则MOS管的工作状态进入截止区，理想状态下，工作电流I D为零。
在一些示例中，第一偏置电压V b可以设置为与运算放大器200的共模参考电压V CMREF的大小相等。
本申请实施例中的启动电路的环路简单，没有引入额外的零极点，所以无需运算放大器的进行带宽补偿，有利于高速高增益设计。
本申请实施例的启动电路采用了差分结构，差分特性较好。另外在运算放大器启动之后，启动电路的工作电流减少，甚至为零，从而不会引入额外的直流失调(direct current offset,DC offset)，有利于先进工艺低压设计。
可选地，上述启动晶体管对(M16,M17)可以是N型金属氧化层半导体(N-metal-oxide-semiconductor,NMOS)管，也可以是P型金属氧化层半导体(P-metal-oxide-semiconductor,PMOS)管。例如，启动晶体管对(M16,M17)的类型可以与第一级放大器的输入晶体管对(M1，M2)的类型相同，若输入晶体对管(M1,M2)为NMOS管，则启动晶体管(M16,M17)为NMOS管。若输入晶体对管(M1,M2)为PMOS管，则启动晶体管对(M16,M17)为PMOS管。
可选地，本申请实施例中的运算放大器可以使用互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺，也可以使用其它集成电路工艺。例如双极结型晶体管(bipolar junction transistor,BJT)工艺、绝缘体上硅(silicon-on-insulator,SOI)工艺等。
图3是本申请又一实施例的运算放大器300的结构示意图。图3的运算放大器300与图2中的运算放大器200的结构类似，其区别在于启动晶体管对(M16,M17)的漏极分别与第三级放大器的两个差分输入端相连。即第一启动晶体管M16的漏极与第三级放大器的第一差分输入端相连，第二启动晶体管M17的漏极(d)与第三级放大器的第二差分输入端相连。
可选地，本申请实施例中的启动晶体管对(M16,M17)也可以被单个晶体管替代。例如，图4是本申请又一实施例的运算放大器400的结构示意图。如图4所示，启动电路可以只包括第一启动晶体管M16，第一启动晶体管M16的源极用于连接尾偏置节点P，第一启动晶体管M16的栅极用于接第一偏置电压V b，第一启动晶体管M16的漏极用于连接第二级或第二级以上的放大器的输入端。其中，图4中的第一启动晶体管M16的漏极用于连接第二级放大器的两个差分输入端中的任意一个差分输入端。在一些示例中，第一启动晶体管M16的漏极也可以用于连接第二级以上的放大器的两个差分输入端中的任意一个差分输入端。
图5是本申请又一实施例的运算放大器500的电路结构示意图。图5中的运算放大器500为二级放大器，应理解，经过有限的变形，该运算放大器500的结构也适用于三级放大器或三级以上的放大器。如图5所示，运算放大器的第一级放大器电路包括晶体管M1，M2，M3，M4，M5。其中，图2-图4中的第一级放大器的偏置电路可以包括图5中的晶体管M3和M4。图2-图4中的第一级放大器的尾偏置电路可以包括图5中的晶体管M5。为了便于说明，晶体管M3和M4可称为偏置晶体管，晶体管M5可称为尾偏置晶体管。 运算放大器的第二级放大器电路包括晶体管M6、M7、M8、M9。
在第一级放大器电路中，偏置晶体管M3和M4的源极与电源V DD相连，偏置晶体管M3和M4的漏极与输入晶体管对(M1，M2)的漏极相连。晶体管M7和晶体管M9为第二级放大器的输入晶体管对，为了便于说明，晶体管M7和晶体管M9可以称为第二级放大器的第三输入晶体管M7和第四输入晶体管M9。第三输入晶体管M7的栅极为第二级放大器的第一差分输入端，第四输入晶体管M9的栅极为第二级放大器的第二差分输入端。第三输入晶体管M7的漏极为第二级放大器的第一差分输出端，第四输入晶体管M9的漏极为第二级放大器的第二差分输出端，同时第三输入晶体管M7和第四输入晶体管M9的漏极也是运算放大器的差分输出端。
如图5所示，启动电路包括第一启动晶体管M16和第二启动晶体管M17。其中，第一启动晶体管M16和第二启动晶体管M17的栅极用于连接第一偏置电压V b。第一启动晶体管M16和第二启动晶体管M17的源极相连，并连接到尾偏置晶体管M5的漏极。第一启动晶体管M16的漏极与第二级放大器的第三输入晶体管M7的栅极相连，第二启动晶体管M17的漏极与第二级放大器的第四输入晶体管M9的栅极相连。第三输入晶体管M7的漏极为运算放大器的差分输出端V outp，第四输入晶体管M9的漏极为运算放大器的差分输出端V outn。
可选地，运算放大器还包括稳定性补偿电路，稳定性补偿电路可用于全差分放大器的频率补偿。如图5所示，作为示例，稳定性补偿电路包括第一电阻R1、第二电阻R2，第一电容C1和第二电容C2。第三输入晶体管M7的漏极与第一电容C1的第一端相连，第一电容C1的第二端与第一电阻R1的第一端相连，第一电阻R1的第二端与第一级放大器的第一输入晶体管M1的漏极相连。第四输入晶体管M9的漏极与第二电容C2的第一端相连，第二电容C2的第二端与第二电阻R2的第一端相连，第二电阻R2的第二端与第一级放大器的第二输入晶体管M2的漏极相连。晶体管M15为运算放大器的电流镜偏置电路，用于接收偏置电流，并为运算放大器产生偏置电压。晶体管M12与晶体管M13采用二极管连接方式，其构成了共模负反馈电路中的误差放大器的负载。
可选地，运算放大器还包括共模检测电路，共模检测电路用于产生运算放大器的共模输出电压V CM。所述共模检测电路包括：第一输入端，用于接收所述运算放大器输出的第一差分输出电压Voutp；第二输入端，用于接收所述运算放大器输出的第二差分输出电压Voutn；输出端，用于输出共模输出电压V CM，所述共模输出电压V CM为所述第一差分输出电压Voutp和第二差分输出电压Voutn的平均值，即V CM＝(Voutp+Voutn)/2。
如图5所示，作为示例，共模检测电路包括第三电阻R3和第四电阻R4，所述第三电阻R3的第一端与所述运算放大器的第一差分输出端Voutp相连，所述第三电阻R3的第二端与所述第四电阻R4的第一端相连，所述第四电阻R4的第二端与所述运算放大器的第二差分输出端Voutn相连，所述第三电阻R3的第二端为所述共模检测电路的输出端。
可选地，运算放大器还包括共模环路补偿电路，共模环路补偿电路用于共模环路的频率补偿。如图5所示，作为示例，共模环路补偿电路包括第三电容C3和第四电容C4，所述第三电容C3的第一端与所述运算放大器的第一差分输出端Voutp相连，所述第三电容C3的第二端与所述第四电容的第一端相连，所述第四电容的第二端与所述运算放大器的第二差分输出端Voutn相连。所述第三电容C3的第二端与共模检测电路的输出端相连， 即第三电容C3的第二端与所述第三电阻R3的第二端相连。
可选地，运算放大器还包括共模负反馈电路，共模负反馈电路用于比较共模输出电压V CM和共模参考电压V CMREF，并根据比较结果调节运算放大器的偏置电路，使得共模输出电压V CM与共模参考电压V CMREF相等。如图5所示，共模负反馈电路包括误差放大器，所述误差放大器的第一输入端用于与所述运算放大器的共模参考电压V CMREF相连，所述误差放大器的第二输入端用于连接运算放大器的共模输出电压V CM，即与所述第三电阻R3的第二端相连。所述误差放大器的输出端与所述运算放大器的偏置电路相连，以便于调节所述运算放大器的偏置电路。
如图5所示，作为示例，所述误差放大器包括晶体管M10、M11、M12、M13、M14。其中，晶体管M10和晶体管M11为放大管，晶体管M12、M13和M14为偏置晶体管。晶体管M10和晶体管M11的栅极为误差放大器的差分输入端，晶体管M10的漏极为误差放大器的输出端。共模负反馈电路中的晶体管M10的栅极与共模检测电路中的第三电阻R3的第二端相连。共模反馈电路中的晶体管M11的栅极用于与共模参考电压V CMREF相连。
应理解，图5仅作为本申请实施例的运算放大器的具体电路结构的示例而非限定，例如，图5中的稳定性补偿电路、共模检测电路、共模环路补偿电路或共模负反馈电路也可以采取其它的实现方式，本申请实施例对此不作限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种运算放大器，其特征在于，包括：
    多级串联放大器；
    启动电路，包括：第一启动晶体管M16和第二启动晶体管M17，所述第一启动晶体管M16的源极和所述第二启动晶体管M17的源极与所述多级串联放大器中的第一级放大器的尾偏置节点相连，所述第一启动晶体管M16的栅极和所述第二启动晶体管M17的栅极用于连接第一偏置电压V b，所述第一启动晶体管M16的漏极和所述第二启动晶体管M17的漏极与第二级或第二级以上的放大器的输入端相连。
  2. 如权利要求1所述的运算放大器，其特征在于，所述第一偏置电压V b的设置使得：
    在所述第一级放大器的输入晶体管对未导通的情况下，|V GS|＞|V th|；以及，
    在所述运算放大器启动之后，|V GS|＜|V th|，其中，V GS表示所述第一启动晶体管M16和所述第二启动晶体管M17的栅源电压，V th表示所述第一启动晶体管M16和所述第二启动晶体管M17的阈值电压。
  3. 如权利要求1或2所述的运算放大器，其特征在于，所述尾偏置节点为所述第一级放大器的尾偏置晶体管M5的漏极。
  4. 如权利要求1或2所述的运算放大器，其特征在于，所述尾偏置节点为所述第一级放大器的偏置电阻的一端。
  5. 如权利要求1至4中任一项所述的运算放大器，其特征在于，所述运算放大器包括三级串联放大器，所述第一启动晶体管M16的漏极与所述第二级放大器的第三输入晶体管M7的栅极相连，所述第二启动晶体管M17的漏极与所述第二级放大器的第四输入晶体管M9的栅极相连。
  6. 如权利要求1至5中任一项所述的运算放大器，其特征在于，所述运算放大器还包括：
    稳定性补偿电路，包括第一电阻R1、第二电阻R2、第一电容C1和第二电容C2，所述第一电容C1的第一端与第二级放大器的第三输入晶体管M7的漏极相连，所述第一电容C1的第二端与第一电阻R1的第一端相连，所述第一电阻R1的第二端与第一级放大器的第一输入晶体管M1的漏极相连；
    所述第二电容C2的第一端与第二级放大器的第四输入晶体管M9的漏极相连，所述第二电容C2的第二端与第二电阻R2的第一端相连，所述第二电阻R2的第二端与第一级放大器的第二输入晶体管M2的漏极相连。
  7. 如权利要求1至6中任一项所述的运算放大器，其特征在于，所述运算放大器还包括共模检测电路，所述共模检测电路包括：
    第一输入端，用于接收所述运算放大器输出的第一差分输出电压Voutp；
    第二输入端，用于接收所述运算放大器输出的第二差分输出电压Voutn；
    输出端，用于输出共模输出电压V CM，所述共模输出电压V CM为所述第一差分输出电压Voutp和第二差分输出电压Voutn的平均值。
  8. 如权利要求7所述的运算放大器，其特征在于，所述共模检测电路包括：第三电 阻R3和第四电阻R4，所述第三电阻R3的第一端与所述运算放大器的第一差分输出端相连，所述第三电阻R3的第二端与所述第四电阻R4的第一端相连，所述第四电阻R4的第二端与所述运算放大器的第二差分输出端相连，所述第三电阻R3的第二端为所述共模检测电路的输出端。
  9. 如权利要求7或8所述的运算放大器，其特征在于，所述运算放大器还包括：
    共模环路补偿电路，包括第三电容C3和第四电容C4，所述第三电容C3的第一端与所述运算放大器的第一差分输出端相连，所述第三电容C3的第二端与所述第四电容C4的第一端相连，所述第四电容C4的第二端与所述运算放大器的第二差分输出端相连。
  10. 如权利要求7至9中任一项所述的运算放大器，其特征在于，所述运算放大器还包括共模负反馈电路，所述共模负反馈电路包括误差放大器，所述误差放大器的第一输入端用于接收所述运算放大器的共模参考电压V CMREF，所述误差放大器的第二输入端用于接收所述共模检测电路输出的共模输出电压V CM，所述误差放大器的输出端与所述运算放大器的偏置电路相连。
  11. 一种芯片，其特征在于，所述芯片包括如权利要求1至10中任一项所述的运算放大器。
  12. 一种电子设备，其特征在于，所述电子设备包括如权利要求1至10中任一项所述的运算放大器。
PCT/CN2019/114257 2019-10-30 2019-10-30 运算放大器及运算放大器的启动电路 WO2021081787A1 (zh)

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