WO2021073419A1 - 浪涌防护方法及装置、防护电路、存储介质 - Google Patents

浪涌防护方法及装置、防护电路、存储介质 Download PDF

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Publication number
WO2021073419A1
WO2021073419A1 PCT/CN2020/118506 CN2020118506W WO2021073419A1 WO 2021073419 A1 WO2021073419 A1 WO 2021073419A1 CN 2020118506 W CN2020118506 W CN 2020118506W WO 2021073419 A1 WO2021073419 A1 WO 2021073419A1
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Prior art keywords
unit
energy storage
voltage
protection
conducted
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PCT/CN2020/118506
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English (en)
French (fr)
Inventor
谢长江
赵晶
周先驰
黄国强
李新
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中兴通讯股份有限公司
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Publication of WO2021073419A1 publication Critical patent/WO2021073419A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/06—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage using spark-gap arresters

Definitions

  • the embodiments of the present disclosure relate to the field of communication power supply equipment, and in particular, to a surge protection method and device, a protection circuit, and a storage medium.
  • the system equipment is powered by a DC power supply, and the DC power supply is generally turned off and on using a Metal Oxide Semiconductor Field Effect Transistor (MOSFET for short), which can also be referred to as MOS for short.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the DC power supply must realize the anti-reverse connection, the MOS tube should realize the anti-reverse function.
  • the DC power supply generally has an external capacitor, so the MOS tube needs to realize a slow start, and the MOS tube slowly turns on the MOS tube through the slow start to charge the capacitor, so as to realize the reliable turn-on of the MOS.
  • Solution 1 As shown in Figure 1, single-stage protection is added to the input end of the DC power supply and a protection scheme is added to the MOS tube:
  • the surge energy is high and the spike voltage is high, which exceeds the operating voltage of the protective device Transient Voltage Suppresser (TVS) (that is, VD1, VD2 in the figure).
  • the protection devices VD1 and VD2 clamp and absorb the lightning surge energy, reduce the spike voltage at both ends of the anti-reverse MOS tube (that is, VT1 in Figure 1) and the slow-start MOS tube (that is, VT2 in Figure 1), so that the peak voltage is reduced to Within the safe working range of MOS tube.
  • the protective devices VD1 and VD2 play a protective role when lightning surges occur, ensuring that the MOS tube works normally when lightning surges occur.
  • the general input range of DC power supply is -36V ⁇ -72V. In this range, the DC power supply must work normally, but the protection devices VD1 and VD2 cannot work. In this case, VD1 and VD2 can only choose TVS above 72V. However, with a TVS above 72V, when a lightning surge occurs in the DC power supply, the clamping voltage of the TVS is high, and the residual voltage at both ends of the TVS is high, which makes the anti-reverse MOS tube (that is, VT1 in Figure 1) and the slow start MOS tube (that is, in Figure 1) VT2) can only choose MOS transistors above 200V, but MOS transistors above 200V have problems such as large volume, large internal resistance, high heat consumption, high withstand voltage, and high cost.
  • Solution 2 As shown in Figure 2, double-level protection and MOS protection are added to the input end of the DC power supply:
  • the lightning surge energy is high and the peak voltage is high, which exceeds the protective device TVS (ie VD1, VD2 in Figure 2), the operating voltage of the varistor RV1, VD1, RV1, and VD2 pair
  • the lightning surge energy is clamped and absorbed to reduce the spike voltage at both ends of the anti-reverse MOS tube (ie VT1 in Figure 2) and the slow-start MOS tube (ie VT2 in Figure 2), so that the peak voltage falls within the safe working range of the MOS tube .
  • VD1, RV1, VD2 play a protective role when lightning surge occurs, ensuring that the MOS tube works normally when lightning surge occurs.
  • the general input range of DC power supply is -36V ⁇ -72V. In this range, the DC power supply must work normally, but the protection devices VD1, RV1, VD2 cannot work, so VD1, VD2 and RV1 can only choose TVS and varistors above 72V. .
  • the clamping voltage of the TVS and varistor is high, so that the anti-reverse MOS tube VT1 and slow-start MOS tube VT2 can only choose MOS tubes above 200V, but above 200V MOS tubes have the problems of large volume, large internal resistance, high heat consumption, high withstand voltage, and high cost.
  • the embodiments of the present disclosure provide a surge protection method and device, a protection circuit, and a storage medium to at least solve the problem of high residual voltage of anti-reverse MOS tubes and slow-start MOS tubes in the case of lightning surges in related technologies. You can only choose the anti-reverse MOS tube with high withstand voltage and the slow-start MOS tube.
  • a protection circuit including a first fuse unit, a protection unit, a unidirectional conduction unit, an energy storage unit, and an energy storage discharge unit, wherein,
  • the first fuse unit and the unidirectional conduction unit are respectively connected to the positive pole of the power supply, the protection unit and the energy storage unit are respectively connected to the negative pole of the power supply, and the first fuse unit and the protection unit are connected in series ,
  • the unidirectional conduction unit is connected in series with the energy storage unit, the energy storage and discharge unit is connected in parallel at the energy storage unit, and the power supply is connected in series with the MOS tube;
  • the first fuse unit and the protection unit are not conductive; the unidirectional conduction unit and the energy storage unit are not conductive; the MOS The tube works under the normal voltage;
  • the first fuse unit is conductive with the protection unit; the unidirectional conductive unit is not conductive with the energy storage unit;
  • the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the energy storage unit are conducted.
  • a surge protection method is provided, which is applied to any of the protection circuits described above, and the method includes:
  • the voltage input to the protection circuit from the power source is the normal voltage of the power source
  • the first fuse unit and the protection unit are not conducted;
  • the unidirectional conduction unit and the energy storage unit are not conducted ;
  • the MOS tube works under the normal voltage
  • the first fuse unit and the protection unit are conducted; the unidirectional conduction unit and the energy storage unit are not conducted;
  • the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the energy storage unit are conducted.
  • a surge protection device applied to the protection circuit, and the device includes:
  • the first processing module is configured to: when the voltage input to the protection circuit from the power source is the normal voltage of the power source, the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the protection unit The energy storage unit is not turned on; the MOS tube works under the normal voltage;
  • the second processing module is configured to conduct the first fuse unit and the protection unit when the voltage input to the protection circuit from the power source is a forward surge voltage; the unidirectional conduction unit and the storage The energy unit is not conducting;
  • the third processing module is configured to: when the voltage input to the protection circuit from the power source is a negative surge voltage, the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the The energy storage unit is turned on.
  • a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the foregoing method embodiments when running.
  • an electronic device including a memory and a processor, the memory is stored with a computer program, and the processor is configured to run the computer program to execute any of the above Steps in the method embodiment.
  • the first fuse unit and the unidirectional conduction unit are respectively connected to the positive pole of the power supply, the protection unit and the energy storage unit are respectively connected to the negative pole of the power supply, and the first fuse unit and The protection unit is connected in series, the unidirectional conduction unit is connected in series with the energy storage unit, the energy storage and discharge unit is connected in parallel at the energy storage unit, and the power supply is connected in series with the MOS tube;
  • the voltage is the normal voltage of the power supply
  • the first fuse unit and the protection unit are not conductive
  • the unidirectional conduction unit and the energy storage unit are not conductive
  • the MOS tube is in the Working under normal voltage
  • the input voltage of the power supply is a forward surge voltage
  • the first fuse unit and the protection unit are conducted
  • the unidirectional conduction unit and the energy storage unit are not conducted
  • the unidirectional conduction unit and the energy storage unit are conducted.
  • Figure 1 is a schematic circuit diagram of a lightning surge protection scheme in the prior art
  • FIG. 2 is a schematic diagram of another lightning surge protection scheme in the prior art
  • Fig. 3 is a schematic circuit diagram of a protection circuit according to an alternative embodiment of the present disclosure.
  • FIG. 4 is a schematic circuit diagram of another protection circuit according to an optional embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a surge protection method according to an optional embodiment of the present disclosure.
  • Fig. 6 is a structural block diagram of a surge protection device according to an optional embodiment of the present disclosure.
  • FIG. 7 is a schematic circuit diagram of another protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 8 is a circuit diagram (1) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 9 is a circuit diagram (2) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 10 is a circuit diagram (3) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 11 is a circuit diagram (4) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 12 is a circuit diagram (5) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 13 is a circuit diagram (6) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 14 is a circuit diagram (7) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 15 is a circuit diagram (8) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 16 is a circuit diagram (9) of a protection circuit according to an optional embodiment of the present disclosure.
  • Fig. 17 is a circuit diagram (10) of a protection circuit according to an alternative embodiment of the present disclosure.
  • Fig. 18 is a circuit diagram (11) of a protection circuit according to an alternative embodiment of the present disclosure.
  • FIG. 3 is a schematic circuit diagram of a protection circuit according to an optional embodiment of the present disclosure.
  • the protection circuit includes the following units: a first fuse unit, a protection unit, One-way conduction unit, energy storage unit and energy storage discharge unit, of which,
  • the first fuse unit and the unidirectional conduction unit are respectively connected to the positive pole of the power supply, the protection unit and the energy storage unit are respectively connected to the negative pole of the power supply, and the first fuse unit and the protection unit are connected in series ,
  • the unidirectional conduction unit is connected in series with the energy storage unit, the energy storage and discharge unit is connected in parallel at the energy storage unit, and the power supply is connected in series with the MOS tube;
  • the first fuse unit and the protection unit are not conductive; the unidirectional conduction unit and the energy storage unit are not conductive; the MOS The tube works under the normal voltage;
  • the first fuse unit and the protection unit are conducted; the unidirectional conduction unit and the energy storage unit are not conducted;
  • the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the energy storage unit are conducted.
  • the first fuse unit and the unidirectional conduction unit are respectively connected to the positive pole of the power supply, the protection unit and the energy storage unit are respectively connected to the negative pole of the power supply, and the first fuse unit and The protection unit is connected in series, the unidirectional conduction unit is connected in series with the energy storage unit, the energy storage and discharge unit is connected in parallel at the energy storage unit, and the power supply is connected in series with the MOS tube;
  • the voltage is the normal voltage of the power supply
  • the first fuse unit and the protection unit are not conductive
  • the unidirectional conduction unit and the energy storage unit are not conductive
  • the MOS tube is in the Working under normal voltage
  • the input voltage of the power supply is a forward surge voltage
  • the first fuse unit and the protection unit are conducted
  • the unidirectional conduction unit and the energy storage unit are not conducted
  • the unidirectional conduction unit and the energy storage unit are conducted.
  • the first fuse unit is conductive with the protection unit and the unidirectional conductive unit is not conductive with the energy storage unit, so that the forward surge voltage is clamped to a specified voltage,
  • the MOS tube works under the specified voltage.
  • the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the energy storage unit are conducted; so that the energy storage unit obtains the negative surge voltage Part or all of the voltage.
  • the energy storage and discharge unit is further configured to discharge part or all of the negative surge voltage in the energy storage unit after a predetermined time.
  • FIG. 4 is a schematic circuit diagram of another protection circuit according to an optional embodiment of the present disclosure. As shown in FIG. 4, the protection circuit further includes:
  • the second fuse unit is respectively connected to the negative pole of the power supply, the protection unit, and the energy storage unit, and is configured to disconnect the second fuse unit when an abnormality occurs in any of the following units: the unidirectional conduction Unit, the energy storage unit, the energy storage discharge unit.
  • the normal voltage when the power supply is input with a normal voltage, the normal voltage may be -36V ⁇ -72V, the first fuse unit series protection unit is not turned on, and the unidirectional conduction unit series energy storage unit is not turned on either .
  • the second fuse unit works under normal voltage, that is, when the subsequent circuit (ie, anti-reverse MOS transistor and slow-start MOS transistor) is connected behind the second fuse unit, the subsequent circuit can also be under normal voltage jobs.
  • the first fuse unit series protection unit when a forward surge is applied between the positive pole of the power supply and the negative pole of the power supply, the first fuse unit series protection unit is turned on, and the unidirectional conduction unit series energy storage unit is not turned on.
  • the input forward surge forms a surge relief circuit through the first fuse unit and the protection unit that are turned on.
  • the protection unit clamps the input forward surge to a certain voltage (that is, reduces the forward surge to a certain voltage). Bottom), so that the subsequent circuits (ie, the anti-reverse MOS transistor and the slow-start MOS transistor connected subsequently) work under a normal safe voltage.
  • the first fuse unit series protection unit when a negative surge is applied between the positive pole of the power supply and the negative pole of the power supply, the first fuse unit series protection unit is not turned on, and the unidirectional conduction unit series energy storage unit is turned on. Negative surges are connected through the unidirectional conduction unit in series with the energy storage unit to form a surge relief circuit.
  • the energy storage unit starts to store energy, and part or all of the negative surge energy is stored in the energy storage unit, so that the subsequent circuit (ie The subsequent connected anti-reverse MOS transistors and slow-start MOS transistors) work under a normal safe voltage.
  • the energy storage discharge unit discharges energy to the energy storage unit after the negative surge ends, and the energy storage unit continues to store energy when the next negative surge is input.
  • the second fuse unit also plays a protective role. When any of the conduction unit, the energy storage unit, and the energy storage discharge unit is abnormal, the second fuse unit is disconnected to protect the subsequent circuit (that is, the subsequent connected anti-reverse MOS tube and slow down Start the MOS tube).
  • FIG. 5 is a flowchart of a surge protection method according to an optional embodiment of the present disclosure. As shown in FIG. 5, the process includes the following steps :
  • Step S402 in the case that the voltage of the power supply input to the protection circuit is the normal voltage of the power supply, the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the energy storage unit No conduction; the MOS tube works under the normal voltage;
  • Step S404 in the case that the voltage input to the protection circuit from the power source is a forward surge voltage, the first fuse unit and the protection unit are conducted; the unidirectional conduction unit and the energy storage unit are not conducted through;
  • Step S406 when the voltage input to the protection circuit from the power source is a negative surge voltage, the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the energy storage unit are conducted through.
  • the first fuse unit and the unidirectional conduction unit are respectively connected to the positive pole of the power supply, the protection unit and the energy storage unit are respectively connected to the negative pole of the power supply, and the first fuse unit and The protection unit is connected in series, the unidirectional conduction unit is connected in series with the energy storage unit, the energy storage and discharge unit is connected in parallel at the energy storage unit, and the power supply is connected in series with the MOS tube;
  • the voltage is the normal voltage of the power supply
  • the first fuse unit and the protection unit are not conductive
  • the unidirectional conduction unit and the energy storage unit are not conductive
  • the MOS tube is in the Working under normal voltage
  • the input voltage of the power supply is a forward surge voltage
  • the first fuse unit and the protection unit are conducted
  • the unidirectional conduction unit and the energy storage unit are not conducted
  • the unidirectional conduction unit and the energy storage unit are conducted.
  • the forward surge voltage is clamped to a specified value Voltage, wherein the MOS tube works under the specified voltage.
  • the negative wave is obtained through the energy storage unit.
  • part or all of the surge voltage is discharged through the energy storage and discharge unit to discharge part or all of the negative surge voltage to make the MOS tube work normally.
  • a surge protection device is also provided, which is applied to the above-mentioned protection circuit.
  • the device is used to implement the above-mentioned embodiments and preferred implementations, and what has been described will not be repeated.
  • the term "module" can implement a combination of software and/or hardware with predetermined functions.
  • Fig. 6 is a structural block diagram of a surge protection device according to an optional embodiment of the present disclosure. As shown in Fig. 6, the device includes:
  • the first processing module 52 is configured to: when the voltage input to the protection circuit from the power source is the normal voltage of the power source, the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and The energy storage unit is not turned on; the MOS tube works under the normal voltage;
  • the second processing module 54 is configured to conduct the first fuse unit and the protection unit when the voltage input to the protection circuit from the power source is a forward surge voltage; the unidirectional conduction unit is connected to the protection unit.
  • the energy storage unit is not conducting;
  • the third processing module 56 is configured to: when the voltage input to the protection circuit from the power source is a negative surge voltage, the first fuse unit and the protection unit are not conducted; the unidirectional conduction unit and the protection unit are not conducted; The energy storage unit is turned on.
  • the first fuse unit and the unidirectional conduction unit are respectively connected to the positive pole of the power supply, the protection unit and the energy storage unit are respectively connected to the negative pole of the power supply, and the first fuse unit and the The protection unit is connected in series, the unidirectional conduction unit is connected in series with the energy storage unit, the energy storage and discharge unit is connected in parallel at the energy storage unit, and the power supply is connected in series with the MOS tube;
  • the first fuse unit and the protection unit are not conductive;
  • the unidirectional conduction unit and the energy storage unit are not conductive;
  • the MOS tube is in the normal Work under voltage; when the input voltage of the power supply is a forward surge voltage, the first fuse unit and the protection unit are conducted; the unidirectional conduction unit and the energy storage unit are not conducted;
  • the unidirectional conduction unit and the energy storage unit are conducted.
  • the second processing module 54 is further configured to switch between the first fuse unit and the protection unit and the unidirectional conduction unit and the energy storage unit when the first fuse unit is connected to the protection unit.
  • the forward surge voltage is clamped to a specified voltage, and the MOS tube operates at the specified voltage.
  • the third processing module 56 is further configured to pass through when the first fuse unit and the protection unit are not conducted and the unidirectional conduction unit is conducted with the energy storage unit
  • the energy storage unit obtains part or all of the negative surge voltage, and after a predetermined time, part or all of the negative surge voltage is discharged through the energy storage discharge unit to make The MOS tube works normally.
  • each of the above modules can be implemented by software or hardware.
  • it can be implemented in the following manner, but not limited to this: the above modules are all located in the same processor; or, the above modules can be combined in any combination.
  • the forms are located in different processors.
  • Fig. 7 is a schematic circuit diagram of another protection circuit according to an alternative embodiment of the present disclosure, as shown in Fig. 7, including: a fuse FU1, a protection device FV1 (that is, a TVS) , Diode D1, capacitor C1 and resistor R1, among them,
  • the protection unit FV1 When a positive surge is applied between the positive pole of the power supply and the negative pole of the power supply, the protection unit FV1 is turned on through the fuse FU1, and the positive surge passes through the turned-on fuse FU1 and the protection unit FV1 to form a surge relief circuit, making the protection unit FV1 Clamp the forward surge under a certain voltage; and, at this time, the diode D1 is off, and there is no voltage across the capacitor C1. Then the subsequent circuits (ie, anti-reverse MOS transistors and slow-start MOS transistors) can work under the clamping voltage.
  • the subsequent circuits ie, anti-reverse MOS transistors and slow-start MOS transistors
  • the capacitor C1 When a negative surge is added between the positive pole of the power supply and the negative pole of the power supply, the capacitor C1 forms a current loop through the diode D1 to absorb the energy of the negative surge, and the negative surge is clamped at a lower operating voltage, making the subsequent device ( That is, the anti-reverse MOS tube and the slow-start MOS tube) can work at a lower voltage.
  • the resistor R1 discharges the capacitor C1 after the negative surge ends, so that the capacitor C1 absorbs the surge energy again when the next negative surge comes.
  • the diode can be a diode with a higher withstand voltage, such as a 200V diode.
  • the capacitor C1 can be an electrolytic capacitor with a capacity greater than 300uF.
  • anti-reverse MOS transistors and slow-start MOS transistors with lower working voltage can be selected, for example, 100V anti-reverse MOS transistors and slow-start MOS transistors can be selected.
  • the above method solves the problem that in the background art solutions 1 and 2 can only choose anti-reverse MOS transistors and slow-start MOS transistors above 200V due to the high operating voltage of the protective device, and the anti-reverse MOS transistors and slow-start MOS transistors with low working voltage
  • the MOS tube has less heat, small size, low cost and high reliability.
  • FIGS. 8 to 18 schematic diagrams of several protection circuits according to alternative embodiments of the present disclosure.
  • FU1 and FU2 are fuses; FV1 and FV2 are TVS; C1 and C2 are electrolytic capacitors; R1 and R2 are resistors; D1 and D2 are diodes; VT1 and VT2 are MOS tubes.
  • the negative surge voltage generated by the positive and negative inputs is also added to the loop composed of FU2, C1, R1, and D1, and the negative surge charges C1 through FU2 and D1.
  • C1 is a capacitor, the voltage across the capacitor cannot change suddenly, so the voltage of C1 can only rise slowly. Part of the energy of the negative surge voltage is absorbed by the capacitor C1 and converted into the energy of the capacitor. C1 absorbs the negative surge voltage energy, so that the surge residual voltage between the input positive and the input negative is further reduced, until the surge residual voltage drops to the safe working voltage of the device. After the negative surge voltage has passed, the capacitor C1 completes the energy release through the resistor R1, ensuring that the capacitor C1 can effectively absorb the negative surge residual voltage before the negative surge voltage occurs again on the input positive and negative input.
  • FV1 and FU1 are circuits with the same functions as Figures 1 and 2, while C1, R1, and D1 are new additions to Figures 1 and 2 Circuit (also called circuit core), due to the existence of C1 and D1, most of the negative surge residual voltage is absorbed by C1, and C1 absorbs the negative surge residual voltage to make the input positive and negative surge voltage before the input negative It can be controlled below 40V.
  • Make the circuit back-stage anti-reverse MOS tube (VT1 in Figure 1 and Figure 2) and slow-start MOS tube (VT2 in Figure 1 and Figure 2) can select MOS tubes with DS voltage less than 100V.
  • the anti-reverse MOS tube and the slow-start MOS tube can be reduced from the selection of the DS voltage of 200V to the MOS tube with the DS voltage of 100V, and the 100V MOS tube has an internal conduction.
  • the resistance is smaller, the volume is smaller, and the cost is lower. Therefore, the 100V MOS tube has a more competitive advantage.
  • Figure 9 changes the diode D1 in Figure 8 to FV2, and FV2 and D1 in Figure 8 play the same role in the circuit. They are both unidirectional and conductive. The current can only flow from the negative input to the positive input.
  • Figure 10 is relative to Figure 8
  • Figure 10 changes the diode D1 in Figure 8 to FV2
  • FV2 and D1 in Figure 8 play the same role in the circuit, both are unidirectional conduction ,
  • the conduction current can only flow from the negative input to the positive input.
  • Fig. 11 As shown in Fig. 11, Fig. 11, compared with Fig. 8, removes FU2, adds the back-stage circuit anti-reverse MOS tube VT1 and slow-start MOS tube VT2, and energy storage capacitor C2.
  • the circuit composed of the circuit cores C1, R1, D1 remains unchanged.
  • the newly added VT1 and VT2 have no effect on the negative surge absorption circuit.
  • C1, R1, and D1 can choose devices with DS voltage less than 100V for the devices used in the later stage. When a negative surge voltage occurs when the input is positive and the input is negative.
  • Fig. 12 is compared with Fig. 8, with FU2, FV1 and FU1 removed, the circuit cores C1, R1, D1 remain unchanged, and the negative surge protection function remains unchanged.
  • Figure 13 As shown in Figure 13, compared to Figure 8, Figure 13 has removed FU2, the circuit cores C1, R1, and D1 remain unchanged, and the negative surge protection function remains unchanged.
  • Fig. 14 is compared with Fig. 8, with FU2 removed.
  • FV1 and C1, R1, D1 share a fuse FU1 in the negative direction surge, and the negative direction surge protection function remains unchanged.
  • Fig. 15 is relative to Fig. 8, with FU2 removed, and Fig. 15 changes FV1 in Fig. 8 to a varistor, and the negative surge protection function remains unchanged.
  • Fig. 16 has FU2 removed from Fig. 8.
  • Figure 16 changes the diode D1 in Figure 8 to a MOS tube VT1. Since there is a parasitic diode in the MOS tube, the parasitic diode is also unidirectionally conductive, and its function is the same as that of the diode. The negative surge protection function remains unchanged.
  • Fig. 17 has FV1, FU1, and FU2 removed from Fig. 8.
  • R1 is removed from the circuit cores C1, R1, and D1, and only C1 and D1 are retained.
  • the negative surge protection function remains unchanged. Since there is no discharge resistor R1, the capacitor C1 discharges slowly, but because the capacitor C1 has an equivalent discharge resistor, the power on the capacitor C1 will be discharged, but the discharge speed is slower.
  • Fig. 18 has removed FU2 and added diode D2 compared to Fig. 8.
  • the circuit cores C1, R1, D1 are retained, and the negative surge protection function remains unchanged.
  • the front-end input of the power supply itself has overcurrent protection devices, such as air switches.
  • the capacitor absorbing the negative surge is not limited to the capacitor, and other methods that can absorb the negative surge are within the protection scope of the present disclosure.
  • the diode and the capacitor form a negative surge absorbing energy loop, which is not limited to the diode, and other methods that can form a negative surge absorbing energy with the capacitor are within the protection scope of the present invention.
  • the TVS and fuse combination diodes and capacitors absorb positive and negative surges, and are not limited to TVS and fuse. Other circuit combination diodes and capacitors absorb positive and negative surges are all within the protection scope of the present disclosure.
  • the embodiment of the present disclosure also provides a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the foregoing method embodiments when running.
  • the aforementioned storage medium may be configured to store a computer program for executing the following steps:
  • the storage medium is also configured to store a computer program for executing the following steps:
  • the storage medium is also configured to store a computer program for executing the following steps:
  • the foregoing storage medium may include, but is not limited to: U disk, Read-Only Memory (Read-Only Memory, ROM for short), Random Access Memory (Random Access Memory, RAM for short), Various media that can store computer programs, such as mobile hard disks, magnetic disks, or optical disks.
  • An embodiment of the present disclosure also provides an electronic device, including a memory and a processor, the memory is stored with a computer program, and the processor is configured to run the computer program to execute the steps in any of the foregoing method embodiments.
  • the aforementioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the aforementioned processor, and the input-output device is connected to the aforementioned processor.
  • the above-mentioned processor may be configured to execute the following steps through a computer program:
  • modules or steps of the above-mentioned embodiments of the present disclosure can be implemented by a general computing device, and they can be concentrated on a single computing device or distributed among multiple computing devices.
  • they can be implemented by the program code executable by the computing device, so that they can be stored in the storage device for execution by the computing device, and in some cases, they can be different from here
  • the steps shown or described are performed in the order of, or they are respectively fabricated into individual integrated circuit modules, or multiple modules or steps of them are fabricated into a single integrated circuit module to achieve. In this way, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.

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Abstract

本公开实施例提供了一种浪涌防护方法及装置、防护电路、存储介质，上述防护电路包括：第一熔断单元、防护单元、单向导通单元、储能单元和储能泄放单元，第一熔断单元与单向导通单元分别连接电源的正极，防护单元与储能单元分别连接电源的负极，第一熔断单元和防护单元串联连接，单向导通单元与储能单元串联连接，在储能单元处并联储能泄放单元，电源与MOS管串联；输入电压为正常电压时，第一熔断单元与防护单元不导通；单向导通单元与储能单元不导通，MOS管在正常电压下工作；输入电压为正向浪涌时，第一熔断单元与防护单元导通；单向导通单元与储能单元不导通；输入电压为负向浪涌时，第一熔断单元与防护单元不导通；单向导通单元与储能单元导通。

Description

浪涌防护方法及装置、防护电路、存储介质 技术领域
本公开实施例涉及通讯电源设备领域，具体而言，涉及一种浪涌防护方法及装置、防护电路、存储介质。
背景技术
在通信设备中，系统设备由直流供电电源供电，直流供电电源关断和开启一般采用金属氧化物半导体场效应管(Metal Oxide Semiconductor Field Effect Transistor，简称MOSFET)，也可简称为MOS。由于直流供电电源要实现防反接，故MOS管要实现防反功能。另外，直流供电电源一般外接电容，故MOS管要实现缓启动，MOS管通过缓启动缓慢开启MOS管给电容充电，实现MOS可靠开启。
自然界产生雷击时，雷击或雷击产生的感应雷浪涌会直接加在直流供电电源上的防反MOS管和缓启MOS管上，由于雷击浪涌产生的能量很大，过大的雷击浪涌能量会损坏MOS管，因此，直流供电电源必须做雷击浪涌防护，以保护防反MOS管和缓启MOS管不会损坏。
当前保护防反MOS管和缓启MOS管不损坏的常用方案有两种：
方案一：如图1所示，直流供电电源输入端加单级防护和MOS管上加防护方案：
当雷击浪涌加在直流供电电源时，因雷击浪涌能量高，尖峰电压高，超出防护器件瞬态电压抑制器(Transient Voltage Suppresser，简称TVS)(即图中VD1、VD2)的动作电压，防护器件VD1、VD2对雷击浪涌能量进行箝位吸收，降低防反MOS管(即图1中VT1)、缓启MOS管(即图1中VT2)两端的尖锋电压，使尖峰电压降至MOS管安全工作范围内。防护器件VD1、VD2在雷击浪涌发生时起到保护作用，确保MOS管在雷击浪涌发生时正常工作。
直流供电电源一般输入范围在-36V～-72V，这个范围内直流供电电源要正常工作，而防护器件VD1和VD2不能工作，这种情况下VD1和VD2只能选择72V以上TVS。但是，用72V以上TVS，直流供电电源发生雷击浪涌时，TVS箝位电压高，TVS两端残压高，使得防反MOS管(即图1中VT1)和缓启MOS管(即图1中VT2)只能选择200V以上MOS管，然而200V以上MOS管存在体积大，内阻大，热耗高，耐压高，成本高等问题。
方案二：如图2所示，直流供电电源输入端加双级防护和MOS上加防护方案：
当雷击浪涌加在直流供电电源时，因雷击浪涌能量高，尖峰电压高，超出防护器件TVS(即图2中VD1、VD2)，压敏电阻RV1的动作电压，VD1、RV1、VD2对雷击浪涌能量进行箝位吸收，降低防反MOS管(即图2中VT1)、缓启MOS管(即图2中VT2)两端的尖锋电压，使尖峰电压降至MOS管安全工作范围内。VD1、RV1、VD2在雷击浪涌发生时起到保护作用，确保MOS管在雷击浪涌发生时正常工作。
直流供电电源一般输入范围在-36V～-72V，这个范围内直流供电电源要正常工作，而防护器件VD1、RV1、VD2不能工作，这样VD1、VD2和RV1只能选择72V以上TVS和压敏电阻。用72V以上TVS和压敏电阻，直流供电电源发生雷击浪涌时，TVS和压敏电阻箝位电压高，使得防反MOS管VT1和缓启MOS管VT2只能选择200V以上MOS管，然而200V以上MOS管存在体积大，内阻大，热耗高，耐压高，成本高的问题。
针对相关技术中，在发生雷击浪涌的情况下，存在防反MOS管和缓启MOS管残压高，只能选择耐压高的防反MOS管和缓启MOS管的问题，尚未提出有效的技术方案。
发明内容
本公开实施例提供了一种浪涌防护方法及装置、防护电路、存储介质，以至少解决相关技术中，在发生雷击浪涌的情况下，存在防反MOS管和 缓启MOS管残压高，只能选择耐压高的防反MOS管和缓启MOS管的问题。
根据本公开的一个实施例，提供了一种防护电路，包括第一熔断单元、防护单元、单向导通单元、储能单元和储能泄放单元，其中，
所述第一熔断单元与所述单向导通单元分别连接电源的正极，所述防护单元与所述储能单元分别连接所述电源的负极，所述第一熔断单元和所述防护单元串联连接，所述单向导通单元与所述储能单元串联连接，在所述储能单元处并联储能泄放单元，所述电源与MOS管串联；其中，
在电源的输入电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
在电源的输入电压为正向浪涌电压的情况下，
所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
在电源的输入电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
根据本公开的一个实施例，提供了一种浪涌防护方法，应用于上述任一项所述的防护电路，所述方法包括：
在电源输入所述防护电路的电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
在电源输入所述防护电路的电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
在电源输入所述防护电路的电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
根据本公开的另一个实施例，提供了一种浪涌防护装置，应用于所述 防护电路，所述装置包括：
第一处理模块，设置为在电源输入所述防护电路的电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
第二处理模块，设置为在电源输入所述防护电路的电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
第三处理模块，设置为在电源输入所述防护电路的电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
根据本公开的又一个实施例，还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
根据本公开的又一个实施例，还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项方法实施例中的步骤。
通过本公开实施例，所述第一熔断单元与所述单向导通单元分别连接电源的正极，所述防护单元与所述储能单元分别连接所述电源的负极，所述第一熔断单元和所述防护单元串联连接，所述单向导通单元与所述储能单元串联连接，在所述储能单元处并联储能泄放单元，所述电源与MOS管串联；其中，在电源的输入电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；在电源的输入电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；在电源的输入电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。解决了相关技术中，在发生雷击浪涌的情况下，存在防反 MOS管和缓启MOS管残压高，只能选择耐压高的防反MOS管和缓启MOS管的问题。
附图说明
此处所说明的附图用来提供对本公开实施例的进一步理解，构成本申请的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1是现有技术中雷击浪涌防护方案电路示意图；
图2是现有技术中另一雷击浪涌防护方案电路示意图；
图3是根据本公开可选实施例的防护电路的电路示意图；
图4是根据本公开可选实施例的另一防护电路的电路示意图；
图5是根据本公开可选实施例的浪涌防护方法的流程图；
图6是根据本公开可选实施例的浪涌防护装置的结构框图；
图7是根据本公开可选实施例的另一防护电路的电路示意图；
图8是根据本公开可选实施例的防护电路的电路示意图(一)；
图9是根据本公开可选实施例的防护电路的电路示意图(二)；
图10是根据本公开可选实施例的防护电路的电路示意图(三)；
图11是根据本公开可选实施例的防护电路的电路示意图(四)；
图12是根据本公开可选实施例的防护电路的电路示意图(五)；
图13是根据本公开可选实施例的防护电路的电路示意图(六)；
图14是根据本公开可选实施例的防护电路的电路示意图(七)；
图15是根据本公开可选实施例的防护电路的电路示意图(八)；
图16是根据本公开可选实施例的防护电路的电路示意图(九)；
图17是根据本公开可选实施例的防护电路的电路示意图(十)；
图18是根据本公开可选实施例的防护电路的电路示意图(十一)。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开实施例。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
实施例1
在本实施例中提供了一种防护电路，图3是根据本公开可选实施例的防护电路的电路示意图，如图3所示，该防护电路包括如下单元：第一熔断单元、防护单元、单向导通单元、储能单元和储能泄放单元，其中，
所述第一熔断单元与所述单向导通单元分别连接电源的正极，所述防护单元与所述储能单元分别连接所述电源的负极，所述第一熔断单元和所述防护单元串联连接，所述单向导通单元与所述储能单元串联连接，在所述储能单元处并联储能泄放单元，所述电源与MOS管串联；其中，
在电源的输入电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
在电源的输入电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
在电源的输入电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
通过本公开实施例，所述第一熔断单元与所述单向导通单元分别连接电源的正极，所述防护单元与所述储能单元分别连接所述电源的负极，所述第一熔断单元和所述防护单元串联连接，所述单向导通单元与所述储能单元串联连接，在所述储能单元处并联储能泄放单元，所述电源与MOS管串联；其中，在电源的输入电压为所述电源的正常电压的情况下，所述 第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；在电源的输入电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；在电源的输入电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。解决了相关技术中，在发生雷击浪涌的情况下，存在防反MOS管和缓启MOS管残压高，只能选择耐压高的防反MOS管和缓启MOS管的问题。
可选地，所述第一熔断单元与所述防护单元导通和所述单向导通单元与所述储能单元不导通，以使所述正向浪涌电压箝位到指定电压下，其中，所述MOS管在所述指定电压下工作。
可选地，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通；以使所述储能单元获取所述负向浪涌电压的部分或全部电压。
可选地，所述储能泄放单元，还设置为在预定时间后，将所述储能单元中的所述负向浪涌电压的部分或全部电压泄放。
可选地，图4是根据本公开可选实施例的另一防护电路的电路示意图如图4所示，所述防护电路还包括：
第二熔断单元，分别与所述电源的负极，所述防护单元，所述储能单元连接，设置为在以下任一单元出现异常时，断开所述第二熔断单元：所述单向导通单元，所述储能单元，所述储能泄放单元。
在本公开实施例中，当电源输入正常电压时，其中，该正常电压可以为-36V～-72V，第一熔断单元串联防护单元不导通，单向导通单元串联储能单元也不导通。此时，第二熔断单元在正常电压下工作，也就是说，当后续电路(即防反MOS管和缓启MOS管)连接在该第二熔断单元之后时，该后续电路也可以在正常电压下工作。
在本公开实施例中，当正向浪涌加在电源正极和电源负极之间时，第 一熔断单元串联防护单元导通，单向导通单元串联储能单元不导通。输入正向浪涌通过导通的第一熔断单元和防护单元形成浪涌泄放回路，防护单元将输入的正向浪涌箝位在某一电压下(即将正向浪涌降低在某一电压下)，使得后续电路(即后续连接的防反MOS管和缓启MOS管)在正常的安全电压下工作。
在本公开实施例中，当负向浪涌加在电源正极和电源负极之间时，第一熔断单元串联防护单元不导通，单向导通单元串联储能单元导通。负向浪涌通过单向导通单元串联储能单元导通形成浪涌泄放回路，储能单元开始储能，将部分或全部的负向浪涌能量储存在储能单元，使得后续电路(即后续连接的防反MOS管和缓启MOS管)在正常的安全电压下工作。其中，储能泄放单元在负向浪涌结束后，对储能单元进行能量泄放，在下一次负向浪涌输入时，储能单元继续储能。另外，第二熔断单元还起保护作用，当导通单元、储能单元、储能泄放单元任一异常时，第二熔断单元断开，保护后续电路(即后续连接的防反MOS管和缓启MOS管)。
实施例2
在本实施例中提供了一种浪涌防护方法，应用于上述防护电路，图5是根据本公开可选实施例的浪涌防护方法的流程图，如图5所示，该流程包括如下步骤：
步骤S402，在电源输入所述防护电路的电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
步骤S404，在电源输入所述防护电路的电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
步骤S406，在电源输入所述防护电路的电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
通过本公开实施例，所述第一熔断单元与所述单向导通单元分别连接电源的正极，所述防护单元与所述储能单元分别连接所述电源的负极，所述第一熔断单元和所述防护单元串联连接，所述单向导通单元与所述储能单元串联连接，在所述储能单元处并联储能泄放单元，所述电源与MOS管串联；其中，在电源的输入电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；在电源的输入电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；在电源的输入电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。解决了相关技术中，在发生雷击浪涌的情况下，存在防反MOS管和缓启MOS管残压高，只能选择耐压高的防反MOS管和缓启MOS管的问题。
可选地，在所述第一熔断单元与所述防护单元导通和所述单向导通单元与所述储能单元不导通的情况下，将所述正向浪涌电压箝位到指定电压下，其中，所述MOS管在所述指定电压下工作。
可选地，在所述第一熔断单元与所述防护单元不导通和所述单向导通单元与所述储能单元导通的情况下，通过所述储能单元获取所述负向浪涌电压的部分或全部电压，在预定时间后，通过所述储能泄放单元将所述负向浪涌电压的部分或全部电压泄放，以使所述MOS管正常工作。
实施例3
在本实施例中还提供了一种浪涌防护装置，应用于上述防护电路，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图6是根据本公开可选实施例的浪涌防护装置的结构框图，如图6所 示，该装置包括：
第一处理模块52，设置为在电源输入所述防护电路的电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
第二处理模块54，设置为在电源输入所述防护电路的电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
第三处理模块56，设置为在电源输入所述防护电路的电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
通过上述各个模块，所述第一熔断单元与所述单向导通单元分别连接电源的正极，所述防护单元与所述储能单元分别连接所述电源的负极，所述第一熔断单元和所述防护单元串联连接，所述单向导通单元与所述储能单元串联连接，在所述储能单元处并联储能泄放单元，所述电源与MOS管串联；其中，在电源的输入电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；在电源的输入电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；在电源的输入电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。解决了相关技术中，在发生雷击浪涌的情况下，存在防反MOS管和缓启MOS管残压高，只能选择耐压高的防反MOS管和缓启MOS管的问题。
可选地，所述第二处理模块54，还设置为在所述第一熔断单元与所述防护单元导通和所述单向导通单元与所述储能单元不导通的情况下，将所述正向浪涌电压箝位到指定电压下，其中，所述MOS管在所述指定电压下工作。
可选地，所述第三处理模块56，还设置为在所述第一熔断单元与所述防护单元不导通和所述单向导通单元与所述储能单元导通的情况下，通过所述储能单元获取所述负向浪涌电压的部分或全部电压，在预定时间后，通过所述储能泄放单元将所述负向浪涌电压的部分或全部电压泄放，以使所述MOS管正常工作。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
以下结合优选实施例对上述技术方案进行说明，但不用于限定本公开实施例的技术方案。
优选实施例1.如图7所示，图7是根据本公开可选实施例的另一防护电路的电路示意图，如图7所示，包括：保险丝FU1，防护器件FV1(即一种TVS)，二极管D1，电容C1以及电阻R1，其中，
当电源输入为正常电压(如-36V～-72V)时，FV1通过FU1保险丝不导通，且电容C1两端无电压，则后续电路(即防反MOS管和缓启MOS管)可以在正常电压下工作。
当正向浪涌加在电源正极和电源负极之间时，防护单元FV1通过保险丝FU1导通，正向浪涌通过导通的保险丝FU1和防护单元FV1形成浪涌泄放回路，使得防护单元FV1将正向浪涌嵌位在某一电压下；并且，此时的二极管D1截止，电容C1两端无电压。则后续电路(即防反MOS管和缓启MOS管)可以在该嵌位电压下工作。
当负向浪涌加电源正极和电源负极之间时，电容C1通过二极管D1形成电流回路吸收负向浪涌的能量，负向浪涌被箝位在一个较低工作电压，使得后级器件(即防反MOS管和缓启MOS管)可以在较低电压下工作。其中，电阻R1在负向浪涌结束后，对电容C1进行放电，使电容C1在下一个负向浪涌过来时，再次吸收浪涌能量。
其中，二极管可以选择耐压较高的二极管，如200V二极管。电容C1 可以选择电解电容，容量大于300uF的电解电容。
通过上述方式，可以选择工作耐压更小的防反MOS管和缓启MOS管，如可以选择100V的防反MOS管和缓启MOS管。
综上，上述方式解决了背景技术中方案一和方案二因防护器件动作电压高，只能选200V以上防反MOS管和缓启MOS管的问题，并且，工作电压低的防反MOS管和缓启MOS管发热少，体积小，成本低，可靠性高。
如图8至图18所示，为根据本公开可选实施例的几种防护电路的电路示意图。
其中，FU1、FU2为保险丝；FV1、FV2为TVS；C1、C2为电解电容；R1、R2为电阻；D1、D2为二极管；VT1和VT2为MOS管。
需要说明的是：
如图8所示，当输入正和输入负发生负向浪涌电压，浪涌电压超过FV1的动作电压时，FV1导通，输入正和输入负通过FV1和FU1组成的串联回路释放能量，降低负向浪涌残压。
同时，输入正和输入负发生负向浪涌电压也加在FU2、C1、R1、D1组成的回路上，负向浪涌通过FU2、D1给C1充电。由于C1为电容，电容两端电压不能突变，故C1电压只能缓慢上升。负向浪涌电压的部分能量被电容C1吸收，并转换为电容的能量。C1吸收负向浪涌电压能量，使输入正和输入负之间的浪涌残压进一步下降，直至浪涌残压降为器件安全工作电压。当负向浪涌电压过后，电容C1通过电阻R1完成能量释放，确保输入正和输入负再次发生负向浪涌电压前，电容C1能有效吸收负向浪涌残压。
需要说明的是，相对于图1和图2中的电路，FV1和FU1为一种与图1和图2功能相同的电路，而C1、R1、D1为相对于图1和图2的新增加电路(也可称为电路核心)，由于C1、D1的存在，大部分负向浪涌残压被C1吸收，C1吸收负向浪涌残压，使输入正和输入负之前的负向浪涌 电压能控制在40V以下。使电路后级防反MOS管(如图1和图2中的VT1)和缓启MOS管(如图1和图2中的VT2)可以选择DS电压小于100V的MOS管。
综上，通过新增电路C1、R1、D1，可以使防反MOS管和缓启MOS管从选择DS电压为200V降至可以选择DS电压为100V的MOS管，而100V的MOS管具有导通内阻更小，体积更小，成本更低的有点，因此，100V的MOS管更具有竞争优势。
如图9所示，相对于图8，图9将图8中的二极管D1改为FV2，且FV2与图8中的D1在电路中所起的作用是一致的，都是单向导通，导通电流只能从输入负流向输入正。
如图10所示，图10相对于图8，图10将图8中的二极管D1改为FV2，且FV2与图8中的D1在电路中所起的作用是一致的，都是单向导通，导通电流只能从输入负流向输入正。
如图11所示，图11相对于图8，去掉了FU2，增加了后级电路防反MOS管VT1和缓启MOS管VT2，以及储能电容C2。电路核心C1、R1、D1所组成的电路不变。新增加的VT1、VT2对负向浪涌吸收回路不影响。C1、R1、D1的后级应用的器件可以选择DS电压小于100V的器件。当输入正和输入负发生负向浪涌电压时。
如图12所示，图12相对于图8，去掉了FU2，FV1和FU1，电路核心C1、R1、D1不变，负向浪涌防护功能不变。
如图13所示，图13相对于图8，去掉了FU2，电路核心C1、R1、D1不变，负向浪涌防护功能不变。
如图14所示，图14相对于图8，去掉了FU2。FV1和C1、R1、D1在负向浪涌共用一个保险丝FU1，负向浪涌防护功能不变。
如图15所示，图15相对于图8，去掉了FU2，图15将图8中FV1改为了压敏电阻，负向浪涌防护功能不变。
如图16所示，图16相对于图8，去掉了FU2。图16将图8中的二极管D1改为了MOS管VT1，由于MOS管内有寄生二极管，寄生二极管也是单向导通，作用与二极管一致。负向浪涌防护功能不变。
如图17所示，图17相对于图8，去掉了FV1、FU1、FU2。电路核心C1、R1、D1中去掉了R1，只保留了C1、D1。负向浪涌防护功能不变。由于没有放电电阻R1，电容C1放电较慢，但由于电容C1内有等效放电电阻，电容C1上电量会被放掉，但放电速度较慢。
如图18所示，图18相对于图8，去掉了FU2，增加了二极管D2。保留了电路核心C1、R1、D1，负向浪涌防护功能不变。在有些情况况下，电源前端输入本身就有过流保护器件，如空气开关等。
需要说明的是，当输入正和输入负发生负向浪涌电压时，对于图9-18的电路是如何工作的可参考图8所示的实现方式，在此不再一一详述。
需要说明的是，电容吸收负向浪涌，不限于电容，其他可吸收负向浪涌方式均在本公开的保护范围内。二极管和电容形成负向浪涌吸收能量回路，不限于二极管，其他能和电容形成负向浪涌吸收能量方式均在本发明的保护范围内。TVS和保险组合二极管和电容吸收正负浪涌的方式，不限TVS和保险，其它电路组合二极管和电容吸收正负浪涌方式均在本公开的保护范围内。
实施例4
本公开的实施例还提供了一种存储介质，该存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
可选地，在本实施例中，上述存储介质可以被设置为存储用于执行以下步骤的计算机程序：
S1，在电源输入所述防护电路的电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
S2，在电源输入所述防护电路的电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
S3，在电源输入所述防护电路的电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
可选地，存储介质还被设置为存储用于执行以下步骤的计算机程序：
S1，在所述第一熔断单元与所述防护单元导通和所述单向导通单元与所述储能单元不导通的情况下，将所述正向浪涌电压箝位到指定电压下，其中，所述MOS管在所述指定电压下工作。
可选地，存储介质还被设置为存储用于执行以下步骤的计算机程序：
S1，在所述第一熔断单元与所述防护单元不导通和所述单向导通单元与所述储能单元导通的情况下，通过所述储能单元获取所述负向浪涌电压的部分或全部电压，在预定时间后，通过所述储能泄放单元将所述负向浪涌电压的部分或全部电压泄放，以使所述MOS管正常工作。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
实施例5
本公开的实施例还提供了一种电子装置，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
可选地，上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
可选地，在本实施例中，上述处理器可以被设置为通过计算机程序执 行以下步骤：
S1，在电源输入所述防护电路的电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
S2，在电源输入所述防护电路的电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
S3，在电源输入所述防护电路的电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本公开实施例的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开实施例不限制于任何特定的硬件和软件结合。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护阈值之内。

Claims (10)

  1. 一种防护电路，包括第一熔断单元、防护单元、单向导通单元、储能单元和储能泄放单元，其中，
    所述第一熔断单元与所述单向导通单元分别连接电源的正极，所述防护单元与所述储能单元分别连接所述电源的负极，所述第一熔断单元和所述防护单元串联连接，所述单向导通单元与所述储能单元串联连接，在所述储能单元处并联储能泄放单元，所述电源与MOS管串联；其中，
    在电源的输入电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
    在电源的输入电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
    在电源的输入电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
  2. 根据权利要求1所述的电路，其中，所述第一熔断单元与所述防护单元导通和所述单向导通单元与所述储能单元不导通，以使所述正向浪涌电压箝位到指定电压下，其中，所述MOS管在所述指定电压下工作。
  3. 根据权利要求1所述的电路，其中，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通；以使所述储能单元获取所述负向浪涌电压的部分或全部电压。
  4. 根据权利要求3所述的电路，其中，所述储能泄放单元，还设置为在预定时间后，将所述储能单元中的所述负向浪涌电压的部分或全部电压泄放。
  5. 根据权利要求1至4任一项所述的电路，其中，所述防护电 路还包括：第二熔断单元，分别与所述电源的负极，所述防护单元，所述储能单元连接，设置为在以下任一单元出现异常时，断开所述第二熔断单元：所述单向导通单元，所述储能单元，所述储能泄放单元。
  6. 一种浪涌防护方法，应用于权利要求1至5任一项所述的防护电路，所述方法包括：
    在电源输入所述防护电路的电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
    在电源输入所述防护电路的电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
    在电源输入所述防护电路的电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
  7. 根据权利要求6所述的方法，其中，所述方法还包括：
    在所述第一熔断单元与所述防护单元导通和所述单向导通单元与所述储能单元不导通的情况下，将所述正向浪涌电压箝位到指定电压下，其中，所述MOS管在所述指定电压下工作。
  8. 根据权利要求6所述的方法，其中，所述方法还包括：
    在所述第一熔断单元与所述防护单元不导通和所述单向导通单元与所述储能单元导通的情况下，通过所述储能单元获取所述负向浪涌电压的部分或全部电压，在预定时间后，通过所述储能泄放单元将所述负向浪涌电压的部分或全部电压泄放，以使所述MOS管正常工作。
  9. 一种浪涌防护装置，应用于权利要求1至5任一项所述的防护电路，所述装置包括：
    第一处理模块，设置为在电源输入所述防护电路的电压为所述电源的正常电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元不导通；所述MOS管在所述正常电压下工作；
    第二处理模块，设置为在电源输入所述防护电路的电压为正向浪涌电压的情况下，所述第一熔断单元与所述防护单元导通；所述单向导通单元与所述储能单元不导通；
    第三处理模块，设置为在电源输入所述防护电路的电压为负向浪涌电压的情况下，所述第一熔断单元与所述防护单元不导通；所述单向导通单元与所述储能单元导通。
  10. 一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求6至8任一项中所述的方法。
PCT/CN2020/118506 2019-10-14 2020-09-28 浪涌防护方法及装置、防护电路、存储介质 WO2021073419A1 (zh)

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CN205407247U (zh) * 2016-02-19 2016-07-27 英飞特电子（杭州）股份有限公司 一种防雷电路和电源设备
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JP2003070156A (ja) * 2001-08-27 2003-03-07 Nittan Co Ltd 避雷システムおよび避雷ユニット
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