WO2021068978A1 - 多处理器通信方法及装置 - Google Patents
多处理器通信方法及装置 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- the invention belongs to the technical field of integrated circuit design, and mainly relates to a multi-processor communication method and device.
- the current integrated circuit (chip) design has more and more complex functions and more and more functions. It also integrates multiple embedded processors, such as CPUs, or applications where the embedded processors and external processors work at the same time. It is becoming more and more common; correspondingly, the amount of data interacting between these processors is also increasing. Whether a fast communication channel can be provided to complete the function of data interaction has become an important factor affecting chip performance.
- the data communication between multiple processors is mostly achieved through MailBox (message box, here specifically refers to the channel for message transmission between processor cores), that is, the processor at the data originating end composes the data to be sent Information in a certain format is passed to the destination processor through the data channel between the processors; after receiving the message, the destination processor parses it to obtain the effective information.
- the data transmission channel can basically be selected arbitrarily.
- the transmission channels are such as Ethernet interface and serial channel.
- the design architecture of the entire system is relatively flexible, but in general, the data transmission efficiency of this scheme is relatively low, which is difficult. Meet the needs of large data volume and fast data interaction.
- Scheme 1 describes the architecture model taking two processors as an example.
- each processor has a data interaction processing module and a communication control module.
- the data interaction processing module is responsible for receiving And sort the processor’s to-be-sent data, and analyze the received data from other processors;
- the communication control module is used to send data to the destination processor and receive the data of the current processor;
- the communication control of the two processors Modules are connected through communication channels between processors, such as Ethernet channels or on-chip bus systems, and complete data interaction.
- Scheme 1 improves the traditional MailBox connection scheme.
- the communication processing of each processor is independent, and each has an independent communication control module.
- the architecture is more flexible, and the data interaction processing module is designed reasonably, and it can also realize large-scale communication more efficiently.
- Data exchange but in scheme 1, each processor needs to have an independent communication processing module, which is a waste of resources; in addition, for existing processors, scheme 1 can only implement data exchange processing modules and The efficiency of the communication control module is greatly reduced.
- the architecture model using two processors as an example is described in Scheme 2; the processors in Scheme 2 share memory and transmit data interaction requests through interruption.
- a certain processor receives an interrupt signal , Determine the source processor of the data to be interacted according to the interrupt type, and then read the data from the memory shared with the processor, and analyze and process it.
- the destination processor can initiate an interrupt as needed to notify the source processor The current message has been processed.
- the purpose of the present invention is to provide a multi-processor communication method, device, equipment and storage medium.
- an embodiment of the present invention provides a multi-processor communication device, the device comprising: a data interaction processing module, and at least one set of sending and receiving components that perform data interaction through the data interaction processing module;
- the sending and receiving components of the group include: a sending module and a receiving module that are independently set;
- the sending module includes: a sending-end processor and a sending-end memory unit, the sending-end processor is used to transfer data when there is a demand for writing data The target data is written into the memory unit of the sending end;
- the receiving module includes: a receiving end processor and a receiving end memory unit, and the receiving end processor is used to read data from the receiving end memory unit when there is a demand for data reading;
- the data interaction processing module is configured with at least one data receiving and data sending channel corresponding to each group of sending and receiving components, which includes: sending data controller, sending interrupt controller, receiving data controller and receiving interrupt controller; said sending data control The device is used to receive the sending data request of the sending end processor,
- the sending end processor before the data is sent, is further configured to: initialize the sending data controller, and the initial configuration includes: configuring the sending data controller with the data to be sent The source address, the type of data to be sent, the size of the data to be sent, the destination address of the data to be sent, and the channel occupied by the data to be sent.
- the sender processor is further configured to write the data to be sent into the matching location of the memory unit of the sender according to the type of the data to be sent.
- the sending end processor when the sending data is completely written into the sending end memory unit and/or when the preset space of the sending end memory unit is full, the sending end processor is also used to send a configuration instruction to the sending end Data controller, start data sending operation;
- the sending data controller When the sending data controller receives the sending configuration instruction, it reads data from the source address corresponding to the memory unit of the sending end according to the data type and data size to be sent and executes the sending operation.
- the transmission interrupt controller is specifically used to generate an interrupt request and modify the local status flag information when monitoring that the data to be sent is sent through the data transmission controller.
- the interrupt request is sent to the sending end processor; or the interrupt request is sent to the sending end processor and the receiving end processor at the same time;
- the sending end processor is specifically configured to: when receiving the interrupt request sent by the sending interrupt controller, release the address of the sending end memory unit occupied by the sent data;
- the receiving end processor is also used for preparing to read data when receiving an interrupt request sent by the sending interrupt controller.
- the receiving end processor before the data is sent, is further configured to: initialize the receiving end memory unit, and the initial configuration includes a reservation for receiving data in the receiving end memory unit The memory space and the address mapping relationship of the configuration received data.
- the receiving data controller is also used for detecting data and addresses from the sending data controller, and writing the data into the receiving end memory unit according to the local address mapping relationship.
- the receiving interrupt controller is specifically used to generate an interrupt request and modify the local status flag signal when monitoring that the receiving end memory unit has received a predetermined amount of data, and send the interrupt request to the receiving end processor;
- the receiving end processor When the receiving end processor receives the interrupt request, it reads data from the receiving end memory unit.
- the receiving end processor when data reading is completed, is further used to instruct the receiving end interrupt controller to send the generated interrupt request to the sending end processor.
- an embodiment of the present invention provides a multi-processor communication method.
- the method includes:
- the sending interrupt controller monitors the data sending process in real time, and sends an interrupt request to the sending end processor according to the status of the sending data controller, or sends the interrupt request to the sending end processor and the receiving end for processing Device
- the method includes:
- the receiving data controller receives the read data and address from the sending data controller, and writes the data into the memory unit of the receiving end;
- the receiving end processor When the receiving end processor receives the interrupt request, it reads data from the receiving end memory unit.
- the beneficial effects of the present invention are: the multi-processor communication method and device of the present invention can realize efficient and fast data interaction between multiple processors, and at the same time minimize the number of processors in the data transfer process.
- the degree of participation of the processor reduces the logic complexity of the processor, reduces the burden of the processor, and there is no big efficiency loss in data interaction in various application scenarios.
- FIGS 1 and 2 are schematic diagrams of the frame structure of multi-processor communication devices according to different implementations proposed by the background art of the present invention
- FIG. 3 is a schematic diagram of the framework structure of a multi-processor communication device proposed in a specific embodiment of the present invention
- 4 and 5 are schematic flowcharts of a multi-processor communication method provided by an embodiment of the present invention.
- the multi-processor communication device includes: a data interaction processing module 100, and at least one group of transmitting and receiving components that perform data interaction through the data interaction processing module 100; each group The sending and receiving component includes: a sending module and a receiving module that are independently set; the sending module includes: a sending-end processor 201 and a sending-end memory unit 203, the sending-end processor 201 is used when the data needs to be written When the target data is written into the transmitting-end memory unit 203; the receiving module includes: a receiving-end processor 301 and a receiving-end memory unit 303. The receiving-end processor 301 is used to read data from The receiving end memory unit 303 reads data;
- the data interaction processing module 100 is configured with at least one data receiving and data sending channel corresponding to each group of sending and receiving components, which includes: a sending data controller 101, a sending interrupt controller 103, a receiving data controller 105, and a receiving interrupt controller 107;
- the sending data controller 101 is used for receiving the sending data request of the sending end processor 201, reading the data from the sending end memory unit 203 and sending it to the receiving end memory unit 303 through the receiving data controller 105;
- sending interrupt controller 103 is used to detect the status of the sending data controller 101, and send an interrupt request to the sending end processor 201 according to the status of the sending data controller 101, or send the interrupt request to the sending end processor 201 and the receiving end processor 301;
- receive The data controller 105 is used to receive the data and address from the sending data controller 101, and write the data into the receiving end memory unit 303;
- the receiving interrupt controller 107 is used to detect the storage status of the receiving end memory unit 303, and according to the receiving end The storage state of the memory unit
- each module and unit in the device realizes the following functions:
- the sending-end processor 201 is also used to: make an initial configuration for the sending data controller 101.
- the initial configuration includes: configuring the sending data controller 101 with the source address of the data to be sent and the source address of the data to be sent. Type, the size of the data to be sent, the destination address of the data to be sent and the channel occupied by the data to be sent.
- multiple channels may be used in the sending data controller 101 to respectively transmit different types of data.
- the sending end processor 201 is further configured to write the data to be sent into the matching position of the sending end memory unit 203 according to the type of the data to be sent.
- the sending end processor 201 When the sending data is completely written into the sending end memory unit 203 and/or when the preset space of the sending end memory unit 203 is full, the sending end processor 201 is also used to send a configuration instruction to the sending data controller 101 to start the data Sending operation; when the sending data controller 101 receives the sending configuration instruction, it reads data from the source address corresponding to the sending end memory unit 203 according to the data type and data size to be sent and executes the sending operation.
- the preset space may be the entire storage space of the memory unit 203 at the sending end, or a part of the set storage space.
- different channels have different start switches for data transmission. For each channel, you can They can be started separately or at the same time; when a channel is started, the sending data controller 101 reads data from a pre-configured source address of a certain type of data to be sent and executes the sending operation; here, when it is necessary to explain, the data
- the physical channel for sending and receiving can be the bus between the embedded processors and/or the PCIe interface between the external processors; further, in order to improve the performance of data processing, it is not necessarily required that all the data to be sent is
- the sending operation is performed after writing to the sending end memory unit 203; in the specific implementation of the present invention, the sending data controller 101 can be configured to start the data after detecting that an appropriate number of data has been written into the sending end memory unit 203 Send operation to save data transmission delay.
- the sending interrupt controller 103 is specifically used to: when monitoring that the data to be sent is sent through the sending data controller 101, generate an interrupt request and modify the local status flag information, and send the interrupt request to the sending end processor 201 and the receiving end processor 301; at this time, when the sending end processor 201 receives the interrupt request, it is also used to release the address of the sending end memory unit 203 occupied by the sent data, so as to apply the released address to the new Storage of data to be sent.
- the receiving end processor 301 When the receiving end processor 301 receives the interrupt request sent by the sending interrupt controller 103, it is ready to read data.
- the sending of the data in the memory unit 203 at the sending end can be directly transferred to the new data sending processing operation flow, or it can wait for the return result of the receiving end processor 301 to facilitate subsequent data processing; here, The receiving end processor 301 sends a return result through the receiving interrupt controller 107, and the return result is, for example, the sending data is completely received, the sending data is wrong, and so on.
- each module and unit in the device realizes the following functions:
- the receiving end processor 301 is configured to initialize the receiving end memory unit 303, and the initial configuration includes reserving a memory space for receiving data in the receiving end memory unit 303.
- the receiving data controller 105 is used to detect the data and the address from the sending data controller 101, and write the data into the receiving end memory unit 303 according to the local address mapping relationship.
- the address information sent by the sending data controller 101 to the receiving data controller 105 is not necessarily the absolute physical address of the receiving end processor 301. Therefore, when the receiving data controller 105 receives the address information, The corresponding processing needs to be done flexibly according to the actual local address mapping relationship.
- the receiving interrupt controller 107 is specifically configured to generate an interrupt request and modify the local status flag signal when monitoring that the receiving end memory unit 303 has received a predetermined amount of data, and send the interrupt request to the receiving end processor 301; further, receiving When the end processor 301 receives the interrupt request, it determines the receiving state of the data according to the interrupt request and the local status flag signal, and reads the data from the receiving end memory unit 303 at an appropriate time.
- the receiving end processor 301 may further instruct the receiving end interrupt controller to send the generated interrupt request to the sending end processor 201 to notify the sending end processor 201 of the completion of data reception.
- an embodiment of the present invention provides a multi-processor communication method. Specifically, when data needs to be written, the method includes:
- the transmitting data controller 101 After the target data is written into the transmitting end memory unit 203, the transmitting data controller 101 is configured. The transmitting data controller 101 reads data from the transmitting end memory unit 203 and writes it into the receiving end memory unit 303 through the receiving end controller. ;
- the sending interrupt controller 103 monitors the data sending process in real time, and sends an interrupt request to the sending end processor 201 according to the status of the sending data controller 101, or sends the interrupt request to the sending end processor 201 And the receiving end processor 301;
- the method includes:
- the receiving data controller 105 receives the read data and address from the sending data controller 101, and writes the data into the receiving end memory unit 303;
- the receiving end processor 301 When the receiving end processor 301 receives the interrupt request, it reads data from the receiving end memory unit 303.
- the method when data needs to be written, before the step S1, the method further includes: before the data is sent, the sending end processor 201 is used to initialize the sending data controller 101
- the initial configuration includes: configuring the source address of the data to be sent, the type of the data to be sent, the size of the data to be sent, the destination address of the data to be sent, and the channel occupied by the data to be sent to the sending data controller 101.
- multiple channels may be used in the sending data controller 101 to respectively transmit different types of data.
- step S1 the sender processor 201 writes the data to be sent into the matching location of the memory unit 203 of the sender according to the type of the data to be sent.
- step S2 when the sending data is completely written into the sending end memory unit 203 and/or when the preset space of the sending end memory unit 203 is full, the sending end processor 201 sends a configuration instruction to the sending data controller 101 to start the data Sending operation; when the sending data controller 101 receives the sending configuration instruction, it reads data from the source address corresponding to the sending end memory unit 203 according to the data type and data size to be sent and executes the sending operation.
- the preset space may be the entire storage space of the memory unit 203 at the sending end, or a part of the set storage space.
- different channels have different start switches for data transmission. For each channel, you can They can be started separately or at the same time; when a channel is started, the sending data controller 101 reads data from a pre-configured source address of a certain type of data to be sent and executes the sending operation; here, when it is necessary to explain, the data
- the physical channel for sending and receiving can be the bus between the embedded processors and/or the PCIe interface between the external processors; further, in order to improve the performance of data processing, it is not necessarily required that all the data to be sent is
- the sending operation is performed after writing to the sending end memory unit 203; in the specific implementation of the present invention, the sending data controller 101 can be configured to start the data after detecting that an appropriate number of data has been written into the sending end memory unit 203 Send operation to save data transmission delay.
- step S3 in the process of sending data, when the sending interrupt controller 103 detects that the data to be sent is sent through the sending data controller 101, an interrupt request is generated and the local status flag information is modified, and the interrupt request is sent to the sending end processor 201 and the receiving end processor 301; at this time, when the sending end processor 201 receives the interrupt request, it is also used to release the address of the sending end memory unit 203 occupied by the sent data, so as to apply the released address to the new Storage of data to be sent.
- the receiving end processor 301 When the receiving end processor 301 receives the interrupt request sent by the sending interrupt controller 103, it is ready to read data.
- the sending of the data in the memory unit 203 at the sending end can be directly transferred to the new data sending processing operation flow, or it can wait for the return result of the receiving end processor 301 to facilitate subsequent data processing; here, The receiving end processor 301 sends a return result through the receiving interrupt controller 107, and the return result is, for example, the sending data is completely received, the sending data is wrong, and so on.
- the method when the data needs to be read, before step M1, the method further includes: before the data is sent, the receiving end processor 301 is used to initialize the receiving end memory unit 303, and the initialization
- the configuration includes reserving a memory space for receiving data in the receiving end memory unit 303.
- the receiving data controller 105 For step M1, waiting for receiving data, the receiving data controller 105 detects the data and the address from the sending data controller 101, and according to the local address mapping relationship, the data is written into the receiving end memory unit 303. It should be noted here that the address information sent by the sending data controller 101 to the receiving data controller 105 is not necessarily the absolute physical address of the receiving end processor 301. Therefore, when the receiving data controller 105 receives the address information, The corresponding processing needs to be done flexibly according to the actual local address mapping relationship.
- step M2 when the receiving interrupt controller 107 detects that the receiving end memory unit 303 has received a predetermined amount of data, it generates an interrupt request and modifies the local status flag signal, and sends the interrupt request to the receiving end processor 301.
- step M3 when the receiving end processor 301 receives the interrupt request, it determines the data receiving state according to the interrupt request and the local status flag signal, and reads the data from the receiving end memory unit 303 at an appropriate time.
- the receiving end processor 301 may further instruct the receiving end interrupt controller to send the generated interrupt request to the sending end processor 201 to notify the sending end processor 201 of the completion of data reception.
- the multi-processor communication method and device of the present invention can realize efficient and fast data interaction between multiple processors, while minimizing the participation of processors in the data transfer process and reducing the logic of the processors.
- the degree of complexity reduces the burden on the processor, and there is no significant loss of efficiency in data interaction in various application scenarios, such as between on-chip multi-processors or off-chip multi-processors.
- modules described as separate components may or may not be physically separated, and the components displayed as modules are logical modules, that is, they may be located in one of the chip logic. In the module, or can also be distributed to multiple data processing modules in the chip. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of this embodiment. Those of ordinary skill in the art can understand and implement it without creative work.
- This application can be used in many general-purpose or special-purpose chip designs. For example: switch chips, router chips, server chips and so on.
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Abstract
本发明提供一种多处理器通信方法及装置，所述装置包括：数据交互处理模块，以及至少一组通过数据交互处理模块进行数据交互的发送接收组件；每组发送接收组件包括：独立设置的发送模块和接收模块；发送模块包括：发送端处理器和发送端内存单元，发送端处理器用于当数据有写入的需求时，将目标数据写入发送端内存单元；接收模块包括：接收端处理器和接收端内存单元，接收端处理器用于当有数据读出的需求时，从接收端内存单元读出数据；数据交互处理模块对应每组发送接收组件至少配置一个数据接收和数据发送通道，其包括：发送数据控制器、发送中断控制器、接收数据控制器和接收中断控制器。本发明可以在多个处理器之间实现高效、快速的数据交互。
Description
本申请要求了申请日为2019年10月9日，申请号为201910953078.8，发明名称为“多处理器通信方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本发明属于集成电路设计技术领域，主要涉及一种多处理器通信方法及装置。
当前的集成电路(芯片)设计，功能越来越复杂，功能也越来越多，在芯片中集成多个内嵌处理器，如CPU，或者内嵌处理器与外部处理器同时工作的应用也越来越普遍；相应的，这些处理器之间交互的数据量也越来越多，能否提供一个快速的通信通道以完成数据交互的功能成为影响芯片性能的一个重要因素。
现有技术中，多个处理器之间的数据通信大多是通过MailBox(消息盒子，此处特指处理器核间消息传递的通道)的方式实现，即数据发起端的处理器将待发送数据组成某种格式的信息，通过处理器之间的数据通道传递到目的处理器；目的处理器则在接收到该消息后，对其进行解析，获取其中的有效信息。以上的实现方案中，数据传递通道基本可以任意选择，其传递通道例如：以太网接口、串口通道，整个系统的设计架构相对灵活，但总体上该方案在数据传递效率上相对较低，很难满足大数据量且快速的数据交互需求。
基于以上方案的缺陷，较多的新技术涌现出来，主要有以下两种实现方案。
如图1所示，方案1中描述以两个处理器为例的架构模型，在该示例中，每个处理器都各自有一个数据交互处理模块和一个通信控制模块，数据交互处理模块负责接收和整理处理器的待发送数据，并解析接收到的来自其他处理器的数据；通信控制模块用于发送数据到目的处理器和接收目的地为本处理器的数据；两个处理器的通信控制模块通过处理器之间的通信通道，例如：以太网通道或片上总线系统连接，并完成数据交互。
方案1改进了传统的MailBox的连接方案，每个处理器的通信处理各自独立，且均具有独立的通信控制模块，在架构上较为灵活，数据交互处理模块设计合理，也可以较为高效地实现大数据量的数据交互，但方案1中，每个处理器都需要具备独立的通信处理模块，比较浪费资源；另外，对于已有的处理器，方案1只能通过软件方式实现数据交互处理模块和通信控制模块的功能，效率大大降低。
如图2所示，方案2中描述以两个处理器为例的架构模型；方案2中的处理器之间共享内存，通过中断方式传递数据交互的请求，某个处理器接收到中断信号后，根据中断类型判断待交互数据的源处理器，再从与该处理器共享的内存中读取数据，并解析处理，数据处理完成后，根据需要目的处理器可以发起中断，以通知源处理器当前消息已处理完成。
方案2中，处理器之间共享内存，数据不需要多次搬移，只要源处理器执行写操作，而目的处理器执行读操作即可，因此处理效率较高；但方案2中，两个处理器必须有可以共享的内存才可以实现以上方案，相应的，其限定应用场景，其需要所有处理器同处于一个芯片上，且在芯片设计之初就确定共享内存方案；如此，对于现有的、独立的处理器芯片之间做数据交互时，该方案难以实现；如果通过处理器的已有通信接口共同连接一个独立的内存芯片，虽然可以实现共享内存，但处理器的数据访问效率必会大大降低。
发明内容
为解决上述技术问题，本发明的目的在于提供一种多处理器通信方法、装置、设备及存储介质。
为了实现上述发明目的之一，本发明一实施方式提供一种多处理器通信装置，所述装置包括：数据交互处理模块，以及至少一组通过数据交互处理模块进行数据交互的发送接收组件；每组所述发送接收组件包括：独立设置的发送模块和接收模块；所述发送模块包括：发送端处理器和发送端内存单元，所述发送端处理器用于当数据有写入的需求时，将目标数据写入发送端内存单元；所述接收模块包括：接收端处理器和接收端内存单元，所述接收端处理器用于当有数据读出的需求时，从接收端内存单元读出数据；所述数据交互处理模块对应每组发送接收组件至少配置一个数据接收和数据发送通道，其包括：发送数据控制器、发送中断控制器、接收数据控制器和接收中断控制器；所述发送数据控制器用于接收发送端处理器的发送数据请求，将数据从发送端内存单元中读出并通过接收数据控制器发送给接收端内存单元；发送中断控制器用于检测发送数据控制器的状态，并根据发送数据控制器的状态发送中断请求给发送端处理器，或将中断请求发送给发送端处理器和接收端处理器；接收数据控制器用于接收来自发送数据控制器的数据及地址，并将数据写入接收端内存单元；接收中断控制器用于检测接收端内存单元的存储状态，并根据接收端内存单元的存储状态发送中断请求给接收端处理器，或将中断请求发送给发送端处理器和接收端处理器。
作为本发明一实施方式的进一步改进，在数据发送之前，所述发送端处理器还用于：对发送数据控制器做初始化配置，所述初始化配置包括：对发送数据控制器配置待发送数据的源地址、待发送数据的类型，待发送数据的大小，待发送数据的目的地址和待发送数据占用的通道。
作为本发明一实施方式的进一步改进，所述发送端处理器还用于根据待 发送数据的类型将待发送数据写入发送端内存单元的匹配位置中。
作为本发明一实施方式的进一步改进，当发送数据完全写入发送端内存单元和/或当发送端内存单元预设空间被写满时，所述发送端处理器还用于发送配置指令至发送数据控制器，启动数据发送操作；
当发送数据控制器接收到发送配置指令时，按照待发送数据类型和数据大小从发送端内存单元对应的源地址读取数据并执行发送操作。
作为本发明一实施方式的进一步改进，数据发送过程中，发送中断控制器具体用于：在监测到待发送数据通过发送数据控制器发出时，产生中断请求以及修改本地的状态标志信息，并将中断请求发送给发送端处理器；或将中断请求同时发送给发送端处理器和接收端处理器；
发送端处理器具体用于：当接收到发送中断控制器发送的中断请求时，释放已发送数据占用的发送端内存单元的地址；
接收端处理器还用于：当接收到发送中断控制器发送的中断请求时，准备读出数据。
作为本发明一实施方式的进一步改进，在数据发送之前，所述接收端处理器还用于：对接收端内存单元做初始化配置，所述初始化配置包括在接收端内存单元中预留接收数据的内存空间以及配置接收数据的地址映射关系。
作为本发明一实施方式的进一步改进，接收数据控制器还用于：检测来自发送数据控制器的数据和地址，根据本地的地址映射关系，将数据写入接收端内存单元。
作为本发明一实施方式的进一步改进，接收中断控制器具体用于在监测到接收端内存单元接收完成预定数量数据时，产生中断请求以及修改本地的状态标志信号，并将中断请求发送给接收端处理器；
接收端处理器接收到中断请求时，自接收端内存单元读出数据。
作为本发明一实施方式的进一步改进，数据读出完成时，接收端处理器还用于指示接收端中断控制器将产生的中断请求发送给发送端处理器。
为了实现上述发明目的之一，本发明一实施方式提供一种多处理器通信方法，当数据有写入的需求时，所述方法包括：
S1、将目标数据写入发送端内存单元；
S2、在目标数据写入发送端内存单元后，配置发送数据控制器，发送数据控制器从发送端内存单元读出数据，并经过接收端控制器写入接收端内存单元中；
S3、在数据发送过程中，通过发送中断控制器实时监测数据发送进程，并根据发送数据控制器的状态发送中断请求给发送端处理器，或将中断请求发送给发送端处理器和接收端处理器；
当数据有读出需求时，所述方法包括：
M1、接收数据控制器自发送数据控制器接收读出的数据及地址，将数据写入接收端内存单元；
M2、在接收收据过程中，通过接收中断控制器实时监测接收端内存单元的存储状态，并根据接收端内存单元的存储状态发送中断请求给接收端处理器，或将中断请求发送给发送端处理器和接收端处理器；
M3、接收端处理器接收到中断请求时，自接收端内存单元读出数据。
与现有技术相比，本发明的有益效果是：本发明的多处理器通信方法及装置可以在多个处理器之间实现高效、快速的数据交互，同时尽量减少数据传递过程中的处理器的参与程度，降低处理器的逻辑复杂程度，减轻处理器的负担，并在各种应用场景中的数据交互时，均不会有大的效率损失。
图1、图2是本发明背景技术提出的不同实施方式的多处理器通信装置的框架结构示意图；
图3是本发明具体实施方式中提出的多处理器通信装置的框架结构示意图；
图4、图5是本发明一实施方式提供的多处理器通信方法的流程示意图。
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
如图3所示，本发明一实施方式提供的多处理器通信装置，所述装置包括：数据交互处理模块100，以及至少一组通过数据交互处理模块100进行数据交互的发送接收组件；每组所述发送接收组件包括：独立设置的发送模块和接收模块；所述发送模块包括：发送端处理器201和发送端内存单元203，所述发送端处理器201用于当数据有写入的需求时，将目标数据写入发送端内存单元203；所述接收模块包括：接收端处理器301和接收端内存单元303，所述接收端处理器301用于当有数据读出的需求时，从接收端内存单元303读出数据；
所述数据交互处理模块100对应每组发送接收组件至少配置一个数据接收和数据发送通道，其包括：发送数据控制器101、发送中断控制器103、接收数据控制器105和接收中断控制器107；所述发送数据控制器101用于接收发送端处理器201的发送数据请求，将数据从发送端内存单元203中读出并通过接收数据控制器105发送给接收端内存单元303；发送中断控制器103用于检测发送数据控制器101的状态，并根据发送数据控制器101的状态发送中断请求给发送端处理器201，或将中断请求发送给发送端处理器201和接收端处理器301；接收数据控制器105用于接收来自发送数据控制器101的数据及地址，并将数据写入接收端内存单元303；接收中断控制器107用于检测接收端内存单元303的存储状态，并根据接收端内存单元303的存储状态发送中断请求给接收端处理器301，或将中断请求发送给发送端处理器201和接收端处理器301。
本发明具体实施方式中，发送数据流程中，所述装置中的各个模块及单 元实现如下功能：
在数据发送之前，所述发送端处理器201还用于：对发送数据控制器101做初始化配置，所述初始化配置包括：对发送数据控制器101配置待发送数据的源地址、待发送数据的类型，待发送数据的大小，待发送数据的目的地址和待发送数据占用的通道。
相应的，为了灵活处理，以及各类型之间的独立性，发送数据控制器101中可以用多个通道分别传输不同类型的数据。
所述发送端处理器201还用于根据待发送数据的类型将待发送数据写入的发送端内存单元203的匹配位置中。
当发送数据完全写入发送端内存单元203和/或当发送端内存单元203预设空间被写满时，所述发送端处理器201还用于发送配置指令至发送数据控制器101，启动数据发送操作；当发送数据控制器101接收到发送配置指令时，按照待发送数据类型和数据大小从发送端内存单元203对应的源地址读取数据并执行发送操作。
所述预设空间可以为发送端内存单元203的全部存储空间，也可以为设定的部分存储空间，该实施方式中，不同通道的数据发送有不同的启动开关，针对于每一通道，可以分别启动也可以同时启动；当某一通道启动后，发送数据控制器101从预先配置好的某种类型的待发送数据的源地址读取数据并执行发送操作；这里，需要说明的时，数据发送和接收的物理通道可以是内嵌处理器之间的总线和/或外挂处理器之间的PCIe等接口；进一步的，为了提高数据处理的性能，并不一定要求在所有待发送数据都被写入发送端内存单元203后才执行发送操作；本发明具体实现方式中，可以配置发送数据控制器101，在检测到有适当个数的数据已被写入发送端内存单元203后就启动数据发送操作，以节省数据发送的延时。
发送数据过程中，发送中断控制器103具体用于：在监测到待发送数据通过发送数据控制器101发出时，产生中断请求以及修改本地的状态标志信息，并将中断请求发送给发送端处理器201以及接收端处理器301；此时， 当发送端处理器201接收到中断请求时，其还用于释放已发送数据占用的发送端内存单元203的地址，以将释放的地址应用于新的待发送数据的存储。
当接收端处理器301接收到发送中断控制器103发送的中断请求时，准备读出数据。
进一步的，待发送端内存单元203中的数据发送完成时，可以直接转入新的数据的发送处理操作流程，也可以等待接收端处理器301的返回结果，以便于后续的数据处理；这里，接收端处理器301通过接收中断控制器107发送返回结果，该返回结果例如：发送数据完全接收，发送数据出错等。
本发明具体实施方式中，读出数据的流程中，所述装置中的各个模块及单元实现如下功能：
在数据发送之前，所述接收端处理器301用于：对接收端内存单元303做初始化配置，所述初始化配置包括在接收端内存单元303中预留接收数据的内存空间。
等待接收数据，接收数据控制器105用于检测来自发送数据控制器101的数据和地址，根据本地的地址映射关系，将数据写入接收端内存单元303。这里需要说明的时，发送数据控制器101发送到接收数据控制器105的地址信息，并不一定是接收端处理器301的决对物理地址，如此，接收数据控制器105接收到地址信息时，需要根据本地的实际地址映射关系灵活地做相应处理。
接收中断控制器107具体用于在监测到接收端内存单元303接收完成预定数量数据时，产生中断请求以及修改本地的状态标志信号，并将中断请求发送给接收端处理器301；进一步的，接收端处理器301接收到中断请求时，根据中断请求以及本地的状态标志信号确定数据的接收状态，并在适当时间自接收端内存单元303读出数据。
较佳的，接收端处理器301在数据读出完成时，还可以进一步的指示接收端中断控制器将产生的中断请求发送给发送端处理器201，以通知发送端处理器201数据接收完成。
结合图4、图5所示，本发明一实施方式提供一种多处理器通信方法，具体的，当数据有写入的需求时，所述方法包括：
S1、将目标数据写入发送端内存单元203；
S2、在目标数据写入发送端内存单元203后，配置发送数据控制器101，发送数据控制器101从发送端内存单元203读出数据，并经过接收端控制器写入接收端内存单元303中；
S3、在数据发送过程中，通过发送中断控制器103实时监测数据发送进程，并根据发送数据控制器101的状态发送中断请求给发送端处理器201，或将中断请求发送给发送端处理器201和接收端处理器301；
当数据有读出需求时，所述方法包括：
M1、接收数据控制器105自发送数据控制器101接收读出的数据及地址，将数据写入接收端内存单元303；
M2、在接收收据过程中，通过接收中断控制器107实时监测接收端内存单元303的存储状态，并根据接收端内存单元303的存储状态发送中断请求给接收端处理器301，或将中断请求发送给发送端处理器201和接收端处理器301；
M3、接收端处理器301接收到中断请求时，自接收端内存单元303读出数据。
本发明具体实施方式中，当数据有写入的需求时，所述步骤S1之前，所述方法还包括：在数据发送之前，通过所述发送端处理器201对发送数据控制器101做初始化配置，所述初始化配置包括：对发送数据控制器101配置待发送数据的源地址、待发送数据的类型，待发送数据的大小，待发送数据的目的地址和待发送数据占用的通道。相应的，为了灵活处理，以及各类型之间的独立性，发送数据控制器101中可以用多个通道分别传输不同类型的数据。
对于步骤S1，发送端处理器201根据待发送数据的类型将待发送数据写入的发送端内存单元203的匹配位置中。
对于步骤S2，当发送数据完全写入发送端内存单元203和/或当发送端内存单元203预设空间被写满时，通过发送端处理器201发送配置指令至发送数据控制器101，启动数据发送操作；当发送数据控制器101接收到发送配置指令时，按照待发送数据类型和数据大小从发送端内存单元203对应的源地址读取数据并执行发送操作。
所述预设空间可以为发送端内存单元203的全部存储空间，也可以为设定的部分存储空间，该实施方式中，不同通道的数据发送有不同的启动开关，针对于每一通道，可以分别启动也可以同时启动；当某一通道启动后，发送数据控制器101从预先配置好的某种类型的待发送数据的源地址读取数据并执行发送操作；这里，需要说明的时，数据发送和接收的物理通道可以是内嵌处理器之间的总线和/或外挂处理器之间的PCIe等接口；进一步的，为了提高数据处理的性能，并不一定要求在所有待发送数据都被写入发送端内存单元203后才执行发送操作；本发明具体实现方式中，可以配置发送数据控制器101，在检测到有适当个数的数据已被写入发送端内存单元203后就启动数据发送操作，以节省数据发送的延时。
对于步骤S3，发送数据过程中，通过发送中断控制器103监测到待发送数据通过发送数据控制器101发出时，产生中断请求以及修改本地的状态标志信息，并将中断请求发送给发送端处理器201以及接收端处理器301；此时，当发送端处理器201接收到中断请求时，其还用于释放已发送数据占用的发送端内存单元203的地址，以将释放的地址应用于新的待发送数据的存储。
当接收端处理器301接收到发送中断控制器103发送的中断请求时，准备读出数据。
进一步的，待发送端内存单元203中的数据发送完成时，可以直接转入新的数据的发送处理操作流程，也可以等待接收端处理器301的返回结果，以便于后续的数据处理；这里，接收端处理器301通过接收中断控制器107发送返回结果，该返回结果例如：发送数据完全接收，发送数据出错等。
本发明具体实施方式中，当数据有读出需求时，在步骤M1之前，所述方法还包括：在数据发送之前，通过接收端处理器301对接收端内存单元303做初始化配置，所述初始化配置包括在接收端内存单元303中预留接收数据的内存空间。
对于步骤M1，等待接收数据，通过接收数据控制器105检测来自发送数据控制器101的数据和地址，根据本地的地址映射关系，将数据写入接收端内存单元303。这里需要说明的时，发送数据控制器101发送到接收数据控制器105的地址信息，并不一定是接收端处理器301的决对物理地址，如此，接收数据控制器105接收到地址信息时，需要根据本地的实际地址映射关系灵活地做相应处理。
对于步骤M2，接收中断控制器107在监测到接收端内存单元303接收完成预定数量数据时，产生中断请求以及修改本地的状态标志信号，并将中断请求发送给接收端处理器301。
进一步的，对于步骤M3，接收端处理器301接收到中断请求时，根据中断请求以及本地的状态标志信号确定数据的接收状态，并在适当时间自接收端内存单元303读出数据。
较佳的，接收端处理器301在数据读出完成时，还可以进一步的指示接收端中断控制器将产生的中断请求发送给发送端处理器201，以通知发送端处理器201数据接收完成。
综上所述，本发明的多处理器通信方法及装置可以在多个处理器之间实现高效、快速的数据交互，同时尽量减少数据传递过程中的处理器的参与程度，降低处理器的逻辑复杂程度，减轻处理器的负担，并在各种应用场景中的数据交互时，均不会有大的效率损失，所述应用场景例如：片上多处理器之间或片外多处理器之间。
以上所描述的系统实施方式仅仅是示意性的，其中所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件是逻辑模块，即可以位于芯片逻辑中的一个模块中，或者也可以分布到芯片内的多 个数据处理模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施方式方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
本申请可用于众多通用或专用的芯片设计中。例如：交换芯片、路由器芯片，服务器芯片等等。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。
Claims (10)
- 一种多处理器通信装置，其特征在于，包括：数据交互处理模块，以及至少一组通过数据交互处理模块进行数据交互的发送接收组件；每组所述发送接收组件包括：独立设置的发送模块和接收模块；所述发送模块包括：发送端处理器和发送端内存单元，所述发送端处理器用于当数据有写入的需求时，将目标数据写入发送端内存单元；所述接收模块包括：接收端处理器和接收端内存单元，所述接收端处理器用于当有数据读出的需求时，从接收端内存单元读出数据；所述数据交互处理模块对应每组发送接收组件至少配置一个数据接收和数据发送通道，其包括：发送数据控制器、发送中断控制器、接收数据控制器和接收中断控制器；所述发送数据控制器用于接收发送端处理器的发送数据请求，将数据从发送端内存单元中读出并通过接收数据控制器发送给接收端内存单元；发送中断控制器用于检测发送数据控制器的状态，并根据发送数据控制器的状态发送中断请求给发送端处理器，或将中断请求发送给发送端处理器和接收端处理器；接收数据控制器用于接收来自发送数据控制器的数据及地址，并将数据写入接收端内存单元；接收中断控制器用于检测接收端内存单元的存储状态，并根据接收端内存单元的存储状态发送中断请求给接收端处理器，或将中断请求发送给发送端处理器和接收端处理器。
- 根据权利要求1所述的多处理器通信装置，其特征在于，在数据发送之前，所述发送端处理器还用于：对发送数据控制器做初始化配置，所述初始化配置包括：对发送数据控制器配置待发送数据的源地址、待发送数据的类型，待发送数据的大小，待发送数据的目的地址和待发送数据占用的通道。
- 根据权利要求1所述的多处理器通信装置，其特征在于，所述发送端处理器还用于根据待发送数据的类型将待发送数据写入发送端内存单元的匹配位置中。
- 根据权利要求1所述的多处理器通信装置，其特征在于，当发送数据完全写入发送端内存单元和/或当发送端内存单元预设空间被写满时，所述发送端处理器还用于发送配置指令至发送数据控制器，启动数据发送操作；当发送数据控制器接收到发送配置指令时，按照待发送数据类型和数据大小从发送端内存单元对应的源地址读取数据并执行发送操作。
- 根据权利要求1所述的多处理器通信装置，其特征在于，数据发送过程中，发送中断控制器具体用于：在监测到待发送数据通过发送数据控制器发出时，产生中断请求以及修改本地的状态标志信息，并将中断请求发送给发送端处理器；或将中断请求同时发送给发送端处理器和接收端处理器；发送端处理器具体用于：当接收到发送中断控制器发送的中断请求时，释放已发送数据占用的发送端内存单元的地址；接收端处理器还用于：当接收到发送中断控制器发送的中断请求时，准备读出数据。
- 根据权利要求1所述的多处理器通信装置，其特征在于，在数据发送之前，所述接收端处理器还用于：对接收端内存单元做初始化配置，所述初始化配置包括在接收端内存单元中预留接收数据的内存空间以及配置接收数据的地址映射关系。
- 根据权利要求1所述的多处理器通信装置，其特征在于，接收数据控制器还用于：检测来自发送数据控制器的数据和地址，根据本地的地址映射关系，将数据写入接收端内存单元。
- 根据权利要求1所述的多处理器通信装置，其特征在于，接收中断控制器具体用于在监测到接收端内存单元接收完成预定数量数据时，产生中断请求以及修改本地的状态标志信号，并将中断请求发送给接收端处理器；接收端处理器接收到中断请求时，自接收端内存单元读出数据。
- 根据权利要求8所述的多处理器通信装置，其特征在于，数据读出完成时，接收端处理器还用于指示接收端中断控制器将产生的中断请求发送给发送端处理器。
- 一种多处理器通信方法，其特征在于，当数据有写入的需求时，所述方法包括：S1、将目标数据写入发送端内存单元；S2、在目标数据写入发送端内存单元后，配置发送数据控制器，发送数据控制器从发送端内存单元读出数据，并经过接收端控制器写入接收端内存单元中；S3、在数据发送过程中，通过发送中断控制器实时监测数据发送进程，并根据发送数据控制器的状态发送中断请求给发送端处理器，或将中断请求发送给发送端处理器和接收端处理器；当数据有读出需求时，所述方法包括：M1、接收数据控制器自发送数据控制器接收读出的数据及地址，将数据写入接收端内存单元；M2、在接收收据过程中，通过接收中断控制器实时监测接收端内存单元的存储状态，并根据接收端内存单元的存储状态发送中断请求给接收端处理器，或将中断请求发送给发送端处理器和接收端处理器；M3、接收端处理器接收到中断请求时，自接收端内存单元读出数据。
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