WO2021068669A1 - Filter circuit, method for improving performance of filter circuit, and signal processing device - Google Patents

Filter circuit, method for improving performance of filter circuit, and signal processing device Download PDF

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Publication number
WO2021068669A1
WO2021068669A1 PCT/CN2020/111341 CN2020111341W WO2021068669A1 WO 2021068669 A1 WO2021068669 A1 WO 2021068669A1 CN 2020111341 W CN2020111341 W CN 2020111341W WO 2021068669 A1 WO2021068669 A1 WO 2021068669A1
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resonators
resonator
filter circuit
parallel
designated
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PCT/CN2020/111341
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French (fr)
Chinese (zh)
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庞慰
蔡华林
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天津大学
诺思(天津)微系统有限责任公司
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Publication of WO2021068669A1 publication Critical patent/WO2021068669A1/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks

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  • the transition band between various frequency bands is getting narrower and narrower.
  • the roll-off requirements of the filter are getting higher and higher.
  • the filter has the characteristics of high Q value, it has better roll-off and insertion loss advantages than LC (resonant circuit) and SAW (surface acoustic wave, surface acoustic wave filter), but with further performance requirements
  • LC resonant circuit
  • SAW surface acoustic wave, surface acoustic wave filter
  • the present application provides a filter circuit, a method for improving the performance of the filter circuit, and a signal processing device to improve the performance of the filter circuit.
  • the designated parallel resonator is connected in series or in parallel with a parallel resonator.
  • an embodiment of the present application provides a method for improving the performance of a filter circuit.
  • the filter circuit includes a plurality of resonators, and the plurality of resonators includes a first number of series resonators and a second number of series resonators.
  • Parallel resonators, and the input terminal of the circuit is connected with a first inductor, the output terminal of the circuit is connected with a second inductor, and the ground terminal of the circuit is connected with a third inductor; the method includes:
  • At least one designated parallel resonator is provided in the second number of parallel resonators, and the attribute parameters of the split resonator of the designated parallel resonator are different from those of other parallel resonators, and the attribute parameters include : The frequency of the resonator.
  • the method further includes: connecting an input end of the designated parallel resonator to two of the series resonators, and connecting an output end of the designated parallel resonator to a third inductor.
  • the method further includes: setting the two resonators split by the designated parallel resonator to have a frequency difference and have unequal areas and/or shapes.
  • the filter circuit, the method for improving the performance of the filter circuit, and the signal processing device provided by the embodiments of the present application are provided by providing at least one designated parallel resonator in the second number of parallel resonators, and the frequency of the designated parallel resonator is The frequency of the parallel resonator is different from that of other parallel resonators, which can significantly improve the insertion loss and roll-off of the filter circuit, thereby obtaining better performance than the filter circuit in the prior art.
  • FIG. 1 is a schematic diagram of the structure of a filter circuit in the prior art.
  • Fig. 2a is a schematic structural diagram of a first filter circuit shown in an exemplary embodiment of the present application
  • Fig. 2b is a schematic diagram of the impedance of the first filter circuit shown in an exemplary embodiment of the present application
  • 2c is a schematic diagram of the roll-off improvement effect of the first filter circuit shown in an exemplary embodiment of the present application;
  • Fig. 4a is a schematic structural diagram of a third filter circuit shown in an exemplary embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of a fourth filter circuit shown in an exemplary embodiment of the present application.
  • Fig. 6a is a schematic structural diagram of a fifth filter circuit shown in an exemplary embodiment of the present application.
  • Fig. 6b is a schematic diagram of impedance of a fifth filter circuit shown in an exemplary embodiment of the present application.
  • Fig. 7 is a schematic structural diagram of a sixth filter circuit shown in an exemplary embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of a sixth filter circuit shown in an exemplary embodiment of the present application.
  • Fig. 9b is a schematic diagram of impedance of a seventh filter circuit shown in an exemplary embodiment of the present application.
  • FIG. 9c is a schematic diagram showing a roll-off improvement effect of a seventh filter circuit according to an exemplary embodiment of the present application.
  • FIG. 10a is a schematic diagram showing the comparison result of the overall curves before and after parallel splitting according to an exemplary embodiment of the present application.
  • FIG. 10b is a schematic diagram showing the comparison result of Rs at the Fs frequency before and after parallel splitting according to an exemplary embodiment of the present application;
  • FIG. 10c is a schematic diagram showing a comparison result of Rp at Fp before and after serial splitting according to an exemplary embodiment of the present application.
  • Figure 11 is a schematic diagram of the resonator split.
  • Figure 2a is a schematic structural diagram of the first filter circuit shown in an exemplary embodiment of the present application; referring to Figure 2a, in the filter circuit provided in this embodiment, a designated series resonator 70 is provided, and the designated series resonance The input terminal and the output terminal of the device 70 are respectively connected to a parallel resonator, and the electromechanical coupling coefficient of the designated series resonator 70 is different from the electromechanical coupling coefficient of other series resonators.
  • FIG. 2b shows the relationship between the frequency and impedance of the combined resonator in FIG. 2a
  • the dashed line is the impedance diagram of the resonator in the prior art
  • the solid line is proposed in the embodiment of the present application.
  • the impedance diagram of the new combined structure, in which for the series resonator, the two high impedances formed are used as the zero points for out-of-band suppression. It can be seen from the figure that the position of the out-of-band zero point is more advanced than the one that only changes the frequency, which can better improve the right roll-off.
  • FIG. 2c shows a schematic diagram of the roll-off improvement effect of the above-mentioned first filter circuit
  • the solid line is the roll-off curve of the first filter circuit in this embodiment
  • the dashed line is the existing
  • the third filter circuit provided in the embodiment of the present application improves the roll-off by 1.5 MHz for the same suppression (for example, -50 dB).
  • FIG. 3 is a schematic structural diagram of a second type of filter circuit shown in an exemplary embodiment of the present application.
  • this embodiment includes a designated series resonator 70, and the designated series resonator 70 is connected to a series resonator. After the devices are connected in series, they are connected to the parallel resonator respectively. Specifically, referring to FIG. 3, the input end of the designated series resonator 70 is connected to a parallel resonator and a series resonator, and the output end of the designated series resonator is only connected to another series resonator.
  • the second number of parallel resonators includes at least one designated parallel resonator, and the electromechanical coupling coefficient of the designated parallel resonator is different from the electromechanical coupling coefficient of other parallel resonators.
  • FIG. 4a is a schematic structural diagram of a third filter circuit shown in an exemplary embodiment of the present application.
  • a designated parallel resonator 60 is provided, and the designated parallel resonator The input end of the designated parallel resonator 60 is connected to two series resonators, and the output end of the designated parallel resonator 60 is connected to the third inductance.
  • the electromechanical coupling coefficient of the designated parallel resonator 60 is different from that of other parallel resonators.
  • 4b is the impedance diagram of the third filter shown in FIG. 4a
  • the dashed line is the impedance diagram of the resonator in the prior art
  • the solid line is the impedance diagram of the combined structure in this embodiment.
  • the two low impedances formed are used as the zero points for out-of-band suppression, and the position of the out-of-band zero point is more advanced than in the prior art, which can better improve the left roll-off.
  • the designated parallel resonator can be connected in series with any parallel resonator, and the number of the designated parallel resonator can be multiple, and the designated parallel resonator can be set in any one of the parallel resonators.
  • the aforementioned attribute parameter is the frequency of the resonator.
  • the above-mentioned first number of series resonators includes at least one designated series resonator, and the resonator frequency of the designated series resonator is different from the frequencies of other series resonators.
  • Fig. 6a is a schematic structural diagram of a fifth filter circuit shown in an exemplary embodiment of the present application.
  • a designated series resonator 70 is provided in the filter circuit provided in this embodiment.
  • the input terminal and the output terminal of the device 70 are respectively connected to a parallel resonator, and the frequency of the designated series resonator 70 is different from the frequencies of other series resonators.
  • the insertion loss and roll-off are improved by setting the first number of series resonators to include one or more designated series resonators 70 with different frequencies.
  • Fig. 6b shows the impedance diagram of the fifth filter circuit shown in Fig. 6a.
  • the dashed line is the impedance diagram of the resonator in the prior art, and the solid line is the new one proposed in this embodiment.
  • the impedance diagram of the combined structure For the series resonator, the two high impedances formed are used as the zero points for out-of-band suppression, and the position of the out-of-band zero points is earlier than the original one, which can improve the roll-off on the right.
  • FIG. 7 is a schematic structural diagram of a sixth filter circuit shown in an exemplary embodiment of the present application.
  • the first number of series resonators includes a designated series resonator 70, which The frequency of the designated series resonator 70 is different from the frequencies of the other series resonators 20. And the two ends of the designated resonator 70 are respectively connected to the series resonator and the parallel resonator.
  • the input end of the designated series resonator 70 is connected to a parallel resonator and a series resonator, and the output end of the designated series resonator is connected to only one series resonator.
  • the second number of parallel resonators includes at least one designated parallel resonator, and the resonator frequency of the designated parallel resonator is different from the attribute parameters of the other parallel resonators.
  • FIG. 8 is a schematic structural diagram of a sixth filter circuit shown in an exemplary embodiment of this application.
  • the designated parallel resonator 60 is connected in series with a parallel resonator.
  • the input end of the designated parallel resonator 60 is connected to two series resonators, and the designated parallel resonator 60 is connected in series.
  • the output terminal of the resonator 60 is connected to a parallel resonator.
  • the resonator frequency of the designated parallel resonator 60 is different from the resonator frequencies of other parallel resonators.
  • the designated parallel resonator is obtained by splitting the difference frequency with unequal area.
  • the left side of the upper figure in the figure is a single resonator, the two upper ones on the right represent series splitting, and the lower one represents parallel splitting.
  • the area, frequency and even structure of the two resonators split in series or in parallel in the parallel resonator in this application can be different.
  • the number of splits is not limited to two, but can also be three or more than three.
  • Fig. 10a is a schematic diagram showing the comparison result of the overall curve before and after parallel splitting according to an exemplary embodiment of the present application. Except for the impedances at points Fs and Fp, the other impedances are basically unchanged. Therefore, when the actual splitting is performed, the other impedances of the filter are not changed. There is no impact on performance.
  • the solid line is after splitting, and the dashed line is before splitting.
  • Figure 10b is a schematic diagram showing the comparison result of Rs at the Fs frequency before and after parallel splitting according to an exemplary embodiment of the present application. It can be seen from Figure 5b that after splitting, Rs is significantly reduced, and the decrease of Rs affects the left of the passband. There is a significant improvement on the side.
  • the solid line is after splitting, and the dashed line is before splitting.
  • Fig. 10c is a schematic diagram showing the comparison result of Rp at Fp before and after the serial splitting according to an exemplary embodiment of the present application. It can be seen from Fig. 5c that after splitting, Rp is significantly reduced, and the reduction of Rp affects the right side of the passband. There is deterioration.
  • the solid line is after splitting, and the dashed line is before splitting.
  • Fig. 9a is a schematic structural diagram of a seventh filter circuit shown in an exemplary embodiment of the present application.
  • a designated parallel resonator 60 is provided in the filter circuit provided in this embodiment.
  • the input end of the resonator 60 is connected to two series resonators, the output end of the designated parallel resonator 60 is connected to the third inductor, and the resonator frequency of the designated parallel resonator 60 is the same as that of other parallel resonators. different.
  • Figure 9b is a schematic diagram of the impedance of the seventh filter circuit shown in Figure 9a
  • the dashed line is the impedance diagram of the resonator in the prior art
  • the solid line is the schematic diagram of the impedance of the combined structure proposed in this embodiment.
  • the two low impedances formed are used as zero points for out-of-band suppression. It can be seen from the above figure that the position of the out-of-band zero point is earlier than the original, which can improve the left roll-off.
  • Fig. 9c is a schematic diagram of the roll-off improvement effect of the filter circuit shown in Fig. 9a; referring to Fig. 9c, the solid line is the roll-off curve of the filter circuit in this embodiment, and the dashed line is the roll-off curve of the filter circuit in the prior art The curve can be clearly obtained.
  • the filter circuit provided in the embodiment of the present application improves the roll-off of the same suppression (for example -50dB) by 2MHz.
  • the frequency difference between the aforementioned parallel resonators may be realized by adding an additional metal layer to the upper electrode of the split parallel resonator.
  • the upper electrode of the designated parallel resonator electrode is provided with a first additional metal layer.
  • the area of the electrode of the designated parallel resonator by setting the area of the electrode of the designated parallel resonator to be different from the area of the electrode of the parallel resonator connected in series, it is possible to better fill the space of the chip through the flexible design of the area, which is conducive to tighter arrangement Therefore, the chip area can be fully utilized, which helps to reduce the cost of the chip.
  • the signal processing device provided in this embodiment has better roll-off and insertion loss performance, so the signal processing effect is better.
  • An embodiment of the present application also provides a method for improving the performance of a filter circuit.
  • the filter circuit includes a plurality of resonators, and the plurality of resonators includes a first number of series resonators and a second number of parallel resonances.
  • the input terminal of the circuit is connected with a first inductor, the output terminal of the circuit is connected with a second inductor, and the ground terminal of the circuit is connected with a third inductor; the method includes:
  • the method further includes: the designated parallel resonator is connected in series with a parallel resonator.
  • the above method further includes: connecting the input end of the designated parallel resonator to the two series resonators, and connecting the output end of the designated parallel resonator to the third inductor.
  • the above method further includes: setting the designated parallel resonator to be obtained by a splitting method with unequal area of difference frequency.
  • the above method further includes: disposing a first additional metal layer or other mass load materials on the upper electrode of the designated parallel resonator electrode.
  • the designated parallel resonator can be connected in series with any parallel resonator, and the number of the designated parallel resonator can be multiple, and the designated parallel resonator can be set in any one of the parallel resonators.
  • the filter circuit described in the foregoing embodiment of the present application may include both a designated series resonator and a designated parallel resonator, which is not limited in the present invention.

Abstract

The present application provides a filter circuit, a method for improving the performance of a filter circuit, and a signal processing device. The filter circuit comprises: a plurality of resonators. The plurality of resonators comprise a first number of series resonators and a second number of parallel resonators. The input end of the circuit is connected to a first inductor, the output end of the circuit is connected to a second inductor, and the grounding end of the circuit is connected to a third inductor. The second number of parallel resonators comprise at least one specified parallel resonator, the attribute parameters of the specified parallel resonator are different from those of other parallel resonators, and the attribute parameters comprise frequency. In this way, the insertion loss and roll-off of the filter circuit can be improved.

Description

一种滤波电路及提高滤波电路性能的方法和信号处理设备Filter circuit and method for improving filter circuit performance and signal processing equipment 技术领域Technical field
本申请涉及电路元件技术领域,具体而言,涉及一种滤波电路及提高滤波电路性能的方法和信号处理设备。This application relates to the technical field of circuit elements, and in particular to a filter circuit and a method and signal processing equipment for improving the performance of the filter circuit.
背景技术Background technique
在无线通信系统中,由于对频段的利用率越来越高,各个频段之间的过渡带越来越窄。为了保证滤波器的插损以及对相邻频段的抑制,对滤波器的滚降要求越来越高。滤波器由于具有高Q值的特点,相比LC(谐振电路)和SAW((surface acoustic wave,声表面波滤波器)等有更好的滚降和插损优势,但是随着性能需求的进一步提高,仅仅依靠滤波器的高Q值优势难以获得更好的性能。因此,需要在电路拓扑结构上来改善滤波器的性能。In the wireless communication system, due to the increasing utilization of frequency bands, the transition band between various frequency bands is getting narrower and narrower. In order to ensure the insertion loss of the filter and the suppression of adjacent frequency bands, the roll-off requirements of the filter are getting higher and higher. Because the filter has the characteristics of high Q value, it has better roll-off and insertion loss advantages than LC (resonant circuit) and SAW (surface acoustic wave, surface acoustic wave filter), but with further performance requirements To improve, it is difficult to obtain better performance only by relying on the high Q value of the filter. Therefore, it is necessary to improve the performance of the filter in the circuit topology.
发明内容Summary of the invention
有鉴于此,本申请提供一种滤波电路及提高滤波电路性能的方法和信号处理设备,以改善滤波电路的性能。In view of this, the present application provides a filter circuit, a method for improving the performance of the filter circuit, and a signal processing device to improve the performance of the filter circuit.
具体地,本申请是通过如下技术方案实现的:Specifically, this application is implemented through the following technical solutions:
第一方面,本申请实施例中提供了一种滤波电路,所述滤波电路包括:多个谐振器,所述多个谐振器包括第一数量的串联谐振器和第二数量的并联谐振器,并且所述电路的输入端连接有第一电感,所述电路的输出端连接有第二电感,所述电路的接地端连接有第三电感;所述第二数量的并联谐振器中包含有至少一个指定并联谐振器,所述指定并联谐振器拆分谐振器的属性参数与其他所述并联谐振器的属性参数不同,所述属性参数包括:谐振器的频率。In a first aspect, an embodiment of the present application provides a filter circuit, the filter circuit includes: a plurality of resonators, the plurality of resonators include a first number of series resonators and a second number of parallel resonators, And the input end of the circuit is connected with a first inductance, the output end of the circuit is connected with a second inductance, and the ground end of the circuit is connected with a third inductance; the second number of parallel resonators includes at least A designated parallel resonator, the attribute parameter of the split resonator of the designated parallel resonator is different from the attribute parameters of other parallel resonators, and the attribute parameter includes: the frequency of the resonator.
可选地,所述指定并联谐振器与一所述并联谐振器串联或者并联。Optionally, the designated parallel resonator is connected in series or in parallel with a parallel resonator.
可选地,所述指定并联谐振器的输入端与两个所述串联谐振器相连接,所述指定并联谐振器的输出端与第三电感相连接。Optionally, the input end of the designated parallel resonator is connected to the two series resonators, and the output end of the designated parallel resonator is connected to the third inductor.
可选地,所述指定并联谐振器拆分的两个谐振器具有频率差且有不等的面积和 /或形状。Optionally, the two resonators split by the designated parallel resonator have a frequency difference and have unequal areas and/or shapes.
第二方面,本申请实施例中提供了一种信号处理设备,包括:信号输入电路、信号输出电路和如第一方面所述的滤波电路;所述信号输入电路与所述滤波电路相连接,所述滤波电路与所述信号输出电路相连接。In a second aspect, an embodiment of the present application provides a signal processing device, including: a signal input circuit, a signal output circuit, and the filter circuit as described in the first aspect; the signal input circuit is connected to the filter circuit, The filter circuit is connected to the signal output circuit.
第三方面,本申请实施例中提供了一种提高滤波电路性能的方法,所述滤波电路包括:多个谐振器,所述多个谐振器包括第一数量的串联谐振器和第二数量的并联谐振器,并且所述电路的输入端连接有第一电感,所述电路的输出端连接有第二电感,所述电路的接地端连接有第三电感;所述方法包括:In a third aspect, an embodiment of the present application provides a method for improving the performance of a filter circuit. The filter circuit includes a plurality of resonators, and the plurality of resonators includes a first number of series resonators and a second number of series resonators. Parallel resonators, and the input terminal of the circuit is connected with a first inductor, the output terminal of the circuit is connected with a second inductor, and the ground terminal of the circuit is connected with a third inductor; the method includes:
在所述第二数量的并联谐振器中设置至少一个指定并联谐振器,所述指定并联谐振器的拆分谐振器的属性参数与其他所述并联谐振器的属性参数不同,所述属性参数包括:谐振器的频率。At least one designated parallel resonator is provided in the second number of parallel resonators, and the attribute parameters of the split resonator of the designated parallel resonator are different from those of other parallel resonators, and the attribute parameters include : The frequency of the resonator.
可选地,所述方法还包括:所述指定并联谐振器与一所述并联谐振器串联或者并联。Optionally, the method further includes: the designated parallel resonator is connected in series or in parallel with a parallel resonator.
可选地,所述方法还包括:将所述指定并联谐振器的输入端与两个所述串联谐振器相连接,所述指定并联谐振器的输出端与第三电感相连接。Optionally, the method further includes: connecting an input end of the designated parallel resonator to two of the series resonators, and connecting an output end of the designated parallel resonator to a third inductor.
可选地,所述方法还包括:设置所述指定并联谐振器拆分的两个谐振器具有频率差且有不等的面积和/或形状。Optionally, the method further includes: setting the two resonators split by the designated parallel resonator to have a frequency difference and have unequal areas and/or shapes.
本申请实施例所提供的一种滤波电路及提高滤波电路性能的方法和信号处理设备,通过在第二数量的并联谐振器中设有至少一个指定并联谐振器,并且该指定并联谐振器的频率与其他所述并联谐振器的频率不同,能够显著的改善滤波电路的插损和滚降,进而得到相对于现有技术中的滤波电路更优的性能。The filter circuit, the method for improving the performance of the filter circuit, and the signal processing device provided by the embodiments of the present application are provided by providing at least one designated parallel resonator in the second number of parallel resonators, and the frequency of the designated parallel resonator is The frequency of the parallel resonator is different from that of other parallel resonators, which can significantly improve the insertion loss and roll-off of the filter circuit, thereby obtaining better performance than the filter circuit in the prior art.
附图说明Description of the drawings
图1是现有技术中的一种滤波电路的结构示意图。FIG. 1 is a schematic diagram of the structure of a filter circuit in the prior art.
图2a是本申请一示例性实施例示出的第一种滤波电路的结构示意图;Fig. 2a is a schematic structural diagram of a first filter circuit shown in an exemplary embodiment of the present application;
图2b是本申请一示例性实施例示出的第一种滤波电路的阻抗示意图;Fig. 2b is a schematic diagram of the impedance of the first filter circuit shown in an exemplary embodiment of the present application;
图2c是本申请一示例性实施例中示出的第一种滤波电路的滚降改善效果示意图;2c is a schematic diagram of the roll-off improvement effect of the first filter circuit shown in an exemplary embodiment of the present application;
图3是本申请一示例性实施例示出的第二种滤波电路的结构示意图;Fig. 3 is a schematic structural diagram of a second filter circuit shown in an exemplary embodiment of the present application;
图4a是本申请一示例性实施例示出的第三种滤波电路的结构示意图;Fig. 4a is a schematic structural diagram of a third filter circuit shown in an exemplary embodiment of the present application;
图4b是本申请一示例性实施例示出的第三种滤波电路的阻抗示意图;FIG. 4b is a schematic diagram of impedance of a third filter circuit shown in an exemplary embodiment of the present application;
图5是本申请一示例性实施例示出的第四种滤波电路的结构示意图;Fig. 5 is a schematic structural diagram of a fourth filter circuit shown in an exemplary embodiment of the present application;
图6a是本申请一示例性实施例示出的第五种滤波电路的结构示意图;Fig. 6a is a schematic structural diagram of a fifth filter circuit shown in an exemplary embodiment of the present application;
图6b是本申请一示例性实施例示出的第五种滤波电路的阻抗示意图;Fig. 6b is a schematic diagram of impedance of a fifth filter circuit shown in an exemplary embodiment of the present application;
图7是本申请一示例性实施例示出的第六种滤波电路的结构示意图;Fig. 7 is a schematic structural diagram of a sixth filter circuit shown in an exemplary embodiment of the present application;
图8是本申请一示例性实施例示出的第六种滤波电路的结构示意图;Fig. 8 is a schematic structural diagram of a sixth filter circuit shown in an exemplary embodiment of the present application;
图9a是本申请一示例性实施例示出的第七种滤波电路的结构示意图;Fig. 9a is a schematic structural diagram of a seventh filter circuit shown in an exemplary embodiment of the present application;
图9b是本申请一示例性实施例示出的第七种滤波电路的阻抗示意图;Fig. 9b is a schematic diagram of impedance of a seventh filter circuit shown in an exemplary embodiment of the present application;
图9c是本申请一示例性实施例示出的第七种滤波电路的滚降改善效果示意图;FIG. 9c is a schematic diagram showing a roll-off improvement effect of a seventh filter circuit according to an exemplary embodiment of the present application;
图10a是本申请一示例性实施例示出的并联拆分前后整体曲线的对比结果示意图;FIG. 10a is a schematic diagram showing the comparison result of the overall curves before and after parallel splitting according to an exemplary embodiment of the present application; FIG.
图10b是本申请一示例性实施例示出的并联拆分前后Fs频率处的Rs的对比结果示意图;FIG. 10b is a schematic diagram showing the comparison result of Rs at the Fs frequency before and after parallel splitting according to an exemplary embodiment of the present application;
图10c是本申请一示例性实施例示出的串联拆分前后Fp处的Rp对比结果示意图;FIG. 10c is a schematic diagram showing a comparison result of Rp at Fp before and after serial splitting according to an exemplary embodiment of the present application; FIG.
图11是谐振器拆分示意图。Figure 11 is a schematic diagram of the resonator split.
具体实施方式Detailed ways
这里将详细地对示例性实施例进行说明,其示例表示在附图中。下面的描述涉及附图时,除非另有表示,不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反,它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。The exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the application as detailed in the appended claims.
图1为现有技术中的一种滤波电路的结构示意图。参照图1所示,现有技术中的滤波电路包括多个谐振器,该多个谐振器包括第一数量的串联谐振器20和第二数量的并联谐振器40,图中以包含有5个串联谐振器20和4个并联谐振器40为例, 并且该滤波电路的输入端连接有第一电感10,滤波电路的输出端连接有第二电感30,滤波电路的接地端分别连接有第三电感50,每个第三电感50一端与并联谐振器连接,另一端接地。Fig. 1 is a schematic structural diagram of a filter circuit in the prior art. 1, the filter circuit in the prior art includes a plurality of resonators, the plurality of resonators include a first number of series resonators 20 and a second number of parallel resonators 40, the figure includes 5 Take the series resonator 20 and the four parallel resonators 40 as an example, and the input end of the filter circuit is connected to the first inductor 10, the output end of the filter circuit is connected to the second inductor 30, and the ground end of the filter circuit is respectively connected to the third inductor. Inductors 50, one end of each third inductance 50 is connected to the parallel resonator, and the other end is grounded.
图2a是本申请一示例性实施例示出的第一种滤波电路的结构示意图;参照图2a所示,在本实施例中提供的滤波电路中,设置一指定串联谐振器70,该指定串联谐振器70的输入端和输出端分别与并联谐振器连接,该指定串联谐振器70的机电耦合系数与其他串联谐振器的机电耦合系数不同。Figure 2a is a schematic structural diagram of the first filter circuit shown in an exemplary embodiment of the present application; referring to Figure 2a, in the filter circuit provided in this embodiment, a designated series resonator 70 is provided, and the designated series resonance The input terminal and the output terminal of the device 70 are respectively connected to a parallel resonator, and the electromechanical coupling coefficient of the designated series resonator 70 is different from the electromechanical coupling coefficient of other series resonators.
进而本实施例中,通过设置第一数量的串联谐振器中包含有一个或多个具有不同机电耦合系数的指定串联谐振器70来改善插损和滚降。以下结合图2b加以说明,图2b是本申请一示例性实施例示出的第一种滤波电路的阻抗示意图。Furthermore, in this embodiment, the insertion loss and roll-off are improved by setting the first number of series resonators to include one or more designated series resonators 70 with different electromechanical coupling coefficients. It will be described below with reference to FIG. 2b. FIG. 2b is a schematic diagram of the impedance of the first filter circuit shown in an exemplary embodiment of the present application.
本申请实施例中,图2b示出的是图2a中的组合谐振器的频率和阻抗之间的关系,虚线是现有技术中的谐振器的阻抗图,实线是本申请实施例中提出新的组合结构的阻抗示意图,其中对于串联谐振器来说,形成的两个高阻抗作为带外抑制的零点。从图中可以看出,带外零点的位置相比只改变频率的更加提前,从而能够更好的改善右侧滚降。In the embodiments of the present application, FIG. 2b shows the relationship between the frequency and impedance of the combined resonator in FIG. 2a, the dashed line is the impedance diagram of the resonator in the prior art, and the solid line is proposed in the embodiment of the present application. The impedance diagram of the new combined structure, in which for the series resonator, the two high impedances formed are used as the zero points for out-of-band suppression. It can be seen from the figure that the position of the out-of-band zero point is more advanced than the one that only changes the frequency, which can better improve the right roll-off.
具体的,图2c中示出了上述第一种滤波电路的滚降改善效果示意图;参照图4c所示,实线是本实施例中的第一种滤波电路的滚降曲线,虚线是现有技术中的滤波电路的滚降曲线,可以明显的看出,本申请实施例提供的第三滤波电路对于相同的抑制(比如-50dB来说)滚降改善了1.5MHz。Specifically, FIG. 2c shows a schematic diagram of the roll-off improvement effect of the above-mentioned first filter circuit; referring to FIG. 4c, the solid line is the roll-off curve of the first filter circuit in this embodiment, and the dashed line is the existing For the roll-off curve of the filter circuit in the technology, it can be clearly seen that the third filter circuit provided in the embodiment of the present application improves the roll-off by 1.5 MHz for the same suppression (for example, -50 dB).
图3是本申请一示例性实施例示出的第二种滤波电路的结构示意图,参照图3所示,本实施例中包含有一个指定串联谐振器70,该指定串联谐振器70与一串联谐振器串联以后,再分别与并联谐振器连接。具体的,参照图3所示,该指定串联谐振器70的输入端连接一并联谐振器和一串联谐振器,该指定串联谐振器的输出端只连接另一串联谐振器。FIG. 3 is a schematic structural diagram of a second type of filter circuit shown in an exemplary embodiment of the present application. Referring to FIG. 3, this embodiment includes a designated series resonator 70, and the designated series resonator 70 is connected to a series resonator. After the devices are connected in series, they are connected to the parallel resonator respectively. Specifically, referring to FIG. 3, the input end of the designated series resonator 70 is connected to a parallel resonator and a series resonator, and the output end of the designated series resonator is only connected to another series resonator.
需要说明的是,本实施例中上述的指定串联谐振器的数量和连接位置可以是任意的,本申请对此不作限定。It should be noted that the number and connection positions of the above-mentioned designated series resonators in this embodiment can be arbitrary, which is not limited in this application.
本申请一实施例中,上述第二数量的并联谐振器中包含有至少一个指定并联谐振器,该制定并联谐振器的机电耦合系数与其他并联谐振器的机电耦合系数不同。In an embodiment of the present application, the second number of parallel resonators includes at least one designated parallel resonator, and the electromechanical coupling coefficient of the designated parallel resonator is different from the electromechanical coupling coefficient of other parallel resonators.
图4a是本申请一示例性实施例示出的第三种滤波电路的结构示意图,参照图4a所示,在本实施例中提供的滤波电路中,设置指定并联谐振器60,该指定并联谐振器60的输入端与两个串联谐振器相连接,该指定并联谐振器60的输出端第三电感相连接,该指定并联谐振器60的机电耦合系数与其他并联谐振器的机电耦合系数不同。FIG. 4a is a schematic structural diagram of a third filter circuit shown in an exemplary embodiment of the present application. Referring to FIG. 4a, in the filter circuit provided in this embodiment, a designated parallel resonator 60 is provided, and the designated parallel resonator The input end of the designated parallel resonator 60 is connected to two series resonators, and the output end of the designated parallel resonator 60 is connected to the third inductance. The electromechanical coupling coefficient of the designated parallel resonator 60 is different from that of other parallel resonators.
图4b是上述图4a所示的第三种滤波器的阻抗图示意,虚线是现有技术中的谐振器的阻抗图,实线是本实施例中的组合结构的阻抗示意图,其中对于并联谐振器来说,形成的两个低阻抗作为带外抑制的零点,带外零点的位置相比于现有技术更加提前,从而能够更好的改善左侧滚降。4b is the impedance diagram of the third filter shown in FIG. 4a, the dashed line is the impedance diagram of the resonator in the prior art, and the solid line is the impedance diagram of the combined structure in this embodiment. In terms of the device, the two low impedances formed are used as the zero points for out-of-band suppression, and the position of the out-of-band zero point is more advanced than in the prior art, which can better improve the left roll-off.
本发明另一实施例中,上述的指定并联谐振器60可以是与一并联谐振器串联;图5是本申请一示例性实施例示出的第四种滤波电路的结构示意图,参照图5所示,本实施例中以包含有一个指定并联谐振器60为例,该指定并联谐振器60与一并联谐振器串联,具体的,该指定并联谐振器60的输入端与两个串联谐振器相连接,该指定并联谐振器60的输出端与一并联谐振器相连接。In another embodiment of the present invention, the above-mentioned designated parallel resonator 60 may be connected in series with a parallel resonator; FIG. 5 is a schematic structural diagram of a fourth filter circuit shown in an exemplary embodiment of the present application. In this embodiment, it is taken as an example that a designated parallel resonator 60 is included. The designated parallel resonator 60 is connected in series with a parallel resonator. Specifically, the input end of the designated parallel resonator 60 is connected with two series resonators. , The output terminal of the designated parallel resonator 60 is connected to a parallel resonator.
需要说明的是,本实施例中,该指定并联谐振器可以是与任一个并联谐振器串联,并且该指定并联谐振器的数量可以是多个,并且该指定并联谐振器可以是设置在任何一个并联谐振器与第三电感所在的支路上。本申请另一实施例中,上述的属性参数为谐振器的频率。It should be noted that in this embodiment, the designated parallel resonator can be connected in series with any parallel resonator, and the number of the designated parallel resonator can be multiple, and the designated parallel resonator can be set in any one of the parallel resonators. The branch where the parallel resonator and the third inductor are located. In another embodiment of the present application, the aforementioned attribute parameter is the frequency of the resonator.
可选的,上述第一数量的串联谐振器中包含有至少一个指定串联谐振器,所述指定串联谐振器的谐振器频率与其他串联谐振器的频率不同。Optionally, the above-mentioned first number of series resonators includes at least one designated series resonator, and the resonator frequency of the designated series resonator is different from the frequencies of other series resonators.
图6a是本申请一示例性实施例示出的第五种滤波电路的结构示意图,参照图6a所示,在本实施例中提供的滤波电路中,设置一指定串联谐振器70,该指定串联谐振器70的输入端和输出端分别与并联谐振器连接,该指定串联谐振器70的频率与其他串联谐振器的频率不同。Fig. 6a is a schematic structural diagram of a fifth filter circuit shown in an exemplary embodiment of the present application. Referring to Fig. 6a, in the filter circuit provided in this embodiment, a designated series resonator 70 is provided. The input terminal and the output terminal of the device 70 are respectively connected to a parallel resonator, and the frequency of the designated series resonator 70 is different from the frequencies of other series resonators.
进而本实施例中,通过设置第一数量的串联谐振器中包含有一个或多个具有不同频率的指定串联谐振器70来改善插损和滚降。Furthermore, in this embodiment, the insertion loss and roll-off are improved by setting the first number of series resonators to include one or more designated series resonators 70 with different frequencies.
图6b示出的是上述图6a所示的第五种滤波电路的阻抗示意图,参照图6b所示,虚线是现有技术中的谐振器的阻抗图,实线是本实施例提出的新的组合结构的阻抗 示意图,其中对于串联谐振器来说,形成的两个高阻抗作为带外抑制的零点,带外零点的位置相比原来提前,从而能够改善右侧滚降。Fig. 6b shows the impedance diagram of the fifth filter circuit shown in Fig. 6a. With reference to Fig. 6b, the dashed line is the impedance diagram of the resonator in the prior art, and the solid line is the new one proposed in this embodiment. The impedance diagram of the combined structure. For the series resonator, the two high impedances formed are used as the zero points for out-of-band suppression, and the position of the out-of-band zero points is earlier than the original one, which can improve the roll-off on the right.
图7是本申请一示例性实施例示出的第六种滤波电路的结构示意图,参照图7所示,本实施例中,第一数量的串联谐振器中包含有一个指定串联谐振器70,该指定串联谐振器70的频率与其他串联谐振器20的频率不同。并且该指定谐振器70的两端点分别连接串联谐振器和并联谐振器。FIG. 7 is a schematic structural diagram of a sixth filter circuit shown in an exemplary embodiment of the present application. Referring to FIG. 7, in this embodiment, the first number of series resonators includes a designated series resonator 70, which The frequency of the designated series resonator 70 is different from the frequencies of the other series resonators 20. And the two ends of the designated resonator 70 are respectively connected to the series resonator and the parallel resonator.
具体的,该指定串联谐振器70的输入端连接并联谐振器和串联谐振器,该指定串联谐振器的输出端只连接一串联谐振器。Specifically, the input end of the designated series resonator 70 is connected to a parallel resonator and a series resonator, and the output end of the designated series resonator is connected to only one series resonator.
本发明另一实施例中,第二数量的并联谐振器中包含有至少一个指定并联谐振器,该指定并联谐振器的谐振器频率与其他所述并联谐振器的属性参数不同。In another embodiment of the present invention, the second number of parallel resonators includes at least one designated parallel resonator, and the resonator frequency of the designated parallel resonator is different from the attribute parameters of the other parallel resonators.
可选的,上述的指定并联谐振器60可以是与一并联谐振器串联;图8是本申请一示例性实施例示出的第六种滤波电路的结构示意图,参照图8所示,本实施例中以包含有一个指定并联谐振器60为例,该指定并联谐振器60与一并联谐振器串联,具体的,该指定并联谐振器60的输入端与两个串联谐振器相连接,该指定并联谐振器60的输出端与一并联谐振器相连接。该指定并联谐振器60的谐振器频率与其他并联谐振器的谐振器频率不同。Optionally, the aforementioned designated parallel resonator 60 may be connected in series with a parallel resonator; FIG. 8 is a schematic structural diagram of a sixth filter circuit shown in an exemplary embodiment of this application. Taking as an example a designated parallel resonator 60, the designated parallel resonator 60 is connected in series with a parallel resonator. Specifically, the input end of the designated parallel resonator 60 is connected to two series resonators, and the designated parallel resonator 60 is connected in series. The output terminal of the resonator 60 is connected to a parallel resonator. The resonator frequency of the designated parallel resonator 60 is different from the resonator frequencies of other parallel resonators.
可选的,指定并联谐振器采用差频不等面积的拆分方式得到。参照图10所示,图中上图左边是单个谐振器,右边两个上面表示串联拆分,下面表示并联拆分。本申请中并联谐振器中串联或者并联拆分的两个谐振器的面积和频率甚至结构都是可以不同的。拆分的数量不限于2个,也可以是三个甚至三个以上。Optionally, the designated parallel resonator is obtained by splitting the difference frequency with unequal area. Referring to Figure 10, the left side of the upper figure in the figure is a single resonator, the two upper ones on the right represent series splitting, and the lower one represents parallel splitting. The area, frequency and even structure of the two resonators split in series or in parallel in the parallel resonator in this application can be different. The number of splits is not limited to two, but can also be three or more than three.
本实施例中,本实施例具有以下积极效果:保证工艺制造可靠性;非线性拆分保证器件非线性性能较好:功率拆分,在高功率应用的时候,会使用多个谐振器来进行拆分来减小功率分布;版图布局更加灵活,有利于充分利用die面积,减小diesiz。In this embodiment, this embodiment has the following positive effects: ensuring process manufacturing reliability; non-linear splitting ensures better non-linear performance of the device: power splitting, in high-power applications, multiple resonators will be used to perform Split to reduce power distribution; layout layout is more flexible, which is conducive to making full use of die area and reducing diesiz.
图10a是本申请一示例性实施例示出的并联拆分前后整体曲线的对比结果示意图,除了Fs和Fp点的阻抗以外,其余的阻抗基本没有变化,因此实际拆分的时候,对滤波器其他性能没有影响。实线是拆分后,虚线是拆分前。Fig. 10a is a schematic diagram showing the comparison result of the overall curve before and after parallel splitting according to an exemplary embodiment of the present application. Except for the impedances at points Fs and Fp, the other impedances are basically unchanged. Therefore, when the actual splitting is performed, the other impedances of the filter are not changed. There is no impact on performance. The solid line is after splitting, and the dashed line is before splitting.
图10b是本申请一示例性实施例示出的并联拆分前后Fs频率处的Rs的对比结果示意图,从图5b可以看出,并拆分后,Rs明显的降低,Rs的降低对通带左侧有 明显的改善。实线是拆分后,虚线是拆分前。Figure 10b is a schematic diagram showing the comparison result of Rs at the Fs frequency before and after parallel splitting according to an exemplary embodiment of the present application. It can be seen from Figure 5b that after splitting, Rs is significantly reduced, and the decrease of Rs affects the left of the passband. There is a significant improvement on the side. The solid line is after splitting, and the dashed line is before splitting.
图10c是本申请一示例性实施例示出的串联拆分前后Fp处的Rp对比结果示意图,从图5c可以看出,并拆分后,Rp有明显的降低,Rp的降低对通带右侧有恶化。实线是拆分后,虚线是拆分前。Fig. 10c is a schematic diagram showing the comparison result of Rp at Fp before and after the serial splitting according to an exemplary embodiment of the present application. It can be seen from Fig. 5c that after splitting, Rp is significantly reduced, and the reduction of Rp affects the right side of the passband. There is deterioration. The solid line is after splitting, and the dashed line is before splitting.
可选的,并联拆分上通过凸起结构、凹陷结构、悬翼结构或者质量负载来调节频率,包含其余的调节频率的方式,以对应改善左侧滚降和插损。图9a是本申请一示例性实施例示出的第七种滤波电路的结构示意图,参照图9a所示,在本实施例中提供的滤波电路中,设置有一个指定并联谐振器60,该指定并联谐振器60的输入端与两个串联谐振器相连接,该指定并联谐振器60的输出端与第三电感相连接,该指定并联谐振器60的谐振器频率与其他并联谐振器的谐振器频率不同。Optionally, in parallel splitting, the frequency can be adjusted through the convex structure, the concave structure, the suspended wing structure or the mass load, including other ways of adjusting the frequency, to correspondingly improve the roll-off and insertion loss on the left side. Fig. 9a is a schematic structural diagram of a seventh filter circuit shown in an exemplary embodiment of the present application. Referring to Fig. 9a, in the filter circuit provided in this embodiment, a designated parallel resonator 60 is provided. The input end of the resonator 60 is connected to two series resonators, the output end of the designated parallel resonator 60 is connected to the third inductor, and the resonator frequency of the designated parallel resonator 60 is the same as that of other parallel resonators. different.
图9b是图9a所示的第七种滤波电路的阻抗示意图,虚线是现有技术中的谐振器的阻抗图,实线是本实施例提出的组合结构的阻抗示意图,其中对于并联谐振器来说,形成的两个低阻抗作为带外抑制的零点。从上图可以看出,带外零点的位置相比原来提前,从而能够改善左侧滚降。Figure 9b is a schematic diagram of the impedance of the seventh filter circuit shown in Figure 9a, the dashed line is the impedance diagram of the resonator in the prior art, and the solid line is the schematic diagram of the impedance of the combined structure proposed in this embodiment. In other words, the two low impedances formed are used as zero points for out-of-band suppression. It can be seen from the above figure that the position of the out-of-band zero point is earlier than the original, which can improve the left roll-off.
图9c是图9a所示的滤波电路的滚降改善效果示意图;参照图9c所示,实线是本实施例中的滤波电路的滚降曲线,虚线是现有技术中的滤波电路的滚降曲线,可以明显的得到,本申请实施例中所提供的滤波电路对于相同的抑制(比如-50dB来说)滚降改善了2MHz。Fig. 9c is a schematic diagram of the roll-off improvement effect of the filter circuit shown in Fig. 9a; referring to Fig. 9c, the solid line is the roll-off curve of the filter circuit in this embodiment, and the dashed line is the roll-off curve of the filter circuit in the prior art The curve can be clearly obtained. The filter circuit provided in the embodiment of the present application improves the roll-off of the same suppression (for example -50dB) by 2MHz.
可选的,上述并联谐振器之间的频率的差异可以是通过拆分的并联谐振器的上电极加入额外的金属层来实现。示例性的,在指定并联谐振器电极的上电极设有第一附加金属层。Optionally, the frequency difference between the aforementioned parallel resonators may be realized by adding an additional metal layer to the upper electrode of the split parallel resonator. Exemplarily, the upper electrode of the designated parallel resonator electrode is provided with a first additional metal layer.
可选的,指定并联谐振器电极的面积和与其串联的并联谐振器电极的面积不同。Optionally, the area of the designated parallel resonator electrode is different from the area of the parallel resonator electrode connected in series.
本实施例中,通过设置指定并联谐振器的电极的面积和与其串联的并联谐振器的电极的面积不同,可以实现通过面积的灵活设计更好的填充芯片的空间,有利于更加紧密的排布,因此可以充分利用芯片面积,有助于降低芯片成本。In this embodiment, by setting the area of the electrode of the designated parallel resonator to be different from the area of the electrode of the parallel resonator connected in series, it is possible to better fill the space of the chip through the flexible design of the area, which is conducive to tighter arrangement Therefore, the chip area can be fully utilized, which helps to reduce the cost of the chip.
本发明一实施例中还提供了一种信号处理设备,包括:信号输入电路、信号输出电路和上述任一的滤波电路;所述信号输入电路与所述滤波电路相连接,所述滤波电路与所述信号输出电路相连接。An embodiment of the present invention also provides a signal processing device, including: a signal input circuit, a signal output circuit, and any one of the foregoing filter circuits; the signal input circuit is connected to the filter circuit, and the filter circuit is connected to The signal output circuit is connected.
本实施例中提供的信号处理设备,由于具有更好滚降和插损性能,因此信号处理效果更佳。The signal processing device provided in this embodiment has better roll-off and insertion loss performance, so the signal processing effect is better.
本申请一实施例中还提供了一种提高滤波电路性能的方法,所述滤波电路包括:多个谐振器,所述多个谐振器包括第一数量的串联谐振器和第二数量的并联谐振器,并且所述电路的输入端连接有第一电感,所述电路的输出端连接有第二电感,所述电路的接地端连接有第三电感;所述方法包括:An embodiment of the present application also provides a method for improving the performance of a filter circuit. The filter circuit includes a plurality of resonators, and the plurality of resonators includes a first number of series resonators and a second number of parallel resonances. The input terminal of the circuit is connected with a first inductor, the output terminal of the circuit is connected with a second inductor, and the ground terminal of the circuit is connected with a third inductor; the method includes:
在所述第二数量的并联谐振器中设置至少一个指定并联谐振器,所述指定并联谐振器的属性参数与其他所述并联谐振器的属性参数不同,所述属性参数包括:谐振器的频率。At least one designated parallel resonator is set in the second number of parallel resonators, the attribute parameter of the designated parallel resonator is different from the attribute parameters of other parallel resonators, and the attribute parameter includes: the frequency of the resonator .
本实施例中,通过在第二数量的并联谐振器中设有至少一个指定并联谐振器,并且该指定并联谐振器的频率与其他所述并联谐振器的频率不同,能够显著的改善滤波电路的插损和滚降,进而得到相对于现有技术中的滤波电路更优的性能。In this embodiment, by providing at least one designated parallel resonator in the second number of parallel resonators, and the frequency of the designated parallel resonator is different from that of other parallel resonators, the performance of the filter circuit can be significantly improved. Insertion loss and roll-off, thereby obtaining better performance than the filtering circuit in the prior art.
可选地,所述方法还包括:所述指定并联谐振器与一所述并联谐振器串联。Optionally, the method further includes: the designated parallel resonator is connected in series with a parallel resonator.
需要说明的是,本实施例中,可以是设置该指定并联谐振器可以是与任一个并联谐振器串联,并且该指定并联谐振器的数量可以是多个,并且该指定并联谐振器可以是设置在任何一个并联谐振器与第三电感所在的支路上。It should be noted that in this embodiment, the designated parallel resonator can be set in series with any parallel resonator, and the number of designated parallel resonators can be multiple, and the designated parallel resonator can be set On any branch where the parallel resonator and the third inductor are located.
可选地,上述方法还包括:将所述指定并联谐振器的输入端与两个所述串联谐振器相连接,所述指定并联谐振器的输出端与第三电感相连接。Optionally, the above method further includes: connecting the input end of the designated parallel resonator to the two series resonators, and connecting the output end of the designated parallel resonator to the third inductor.
可选地,上述方法还包括:设置所述指定并联谐振器采用差频不等面积的拆分方式得到。Optionally, the above method further includes: setting the designated parallel resonator to be obtained by a splitting method with unequal area of difference frequency.
可选地,上述方法还包括:在所述指定并联谐振器电极的上电极设置第一附加金属层或者其他质量负载材料。Optionally, the above method further includes: disposing a first additional metal layer or other mass load materials on the upper electrode of the designated parallel resonator electrode.
需要说明的是,本实施例中,该指定并联谐振器可以是与任一个并联谐振器串联,并且该指定并联谐振器的数量可以是多个,并且该指定并联谐振器可以是设置在任何一个并联谐振器与第三电感所在的支路上。It should be noted that in this embodiment, the designated parallel resonator can be connected in series with any parallel resonator, and the number of the designated parallel resonator can be multiple, and the designated parallel resonator can be set in any one of the parallel resonators. The branch where the parallel resonator and the third inductor are located.
可选的,本申请上述实施例所述的滤波电路可以是同时包含有指定串联谐振器和指定并联谐振器,本发明对此不做限定。Optionally, the filter circuit described in the foregoing embodiment of the present application may include both a designated series resonator and a designated parallel resonator, which is not limited in the present invention.
以上所述仅为本申请的较佳实施例而已,并不用以限制本申请,凡在本申请的 精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本申请保护的范围之内。The above are only the preferred embodiments of this application and are not intended to limit this application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in this application Within the scope of protection.

Claims (9)

  1. 一种滤波电路,所述滤波电路包括:多个谐振器,所述多个谐振器包括第一数量的串联谐振器和第二数量的并联谐振器,并且所述电路的输入端连接有第一电感,所述电路的输出端连接有第二电感,所述电路的接地端连接有第三电感;其特征在于:A filter circuit includes: a plurality of resonators, the plurality of resonators include a first number of series resonators and a second number of parallel resonators, and the input of the circuit is connected with the first Inductance, a second inductance is connected to the output end of the circuit, and a third inductance is connected to the ground end of the circuit; characterized in that:
    所述第二数量的并联谐振器中包含有至少一个指定并联谐振器,所述指定并联谐振器拆分谐振器的属性参数与其他所述并联谐振器的属性参数不同,所述属性参数包括:谐振器的频率。The second number of parallel resonators includes at least one designated parallel resonator, and the attribute parameters of the split resonator of the designated parallel resonator are different from those of other parallel resonators, and the attribute parameters include: The frequency of the resonator.
  2. 根据权利要求1所述的滤波电路,其特征在于,所述指定并联谐振器与一所述并联谐振器串联或者并联。The filter circuit according to claim 1, wherein the designated parallel resonator is connected in series or in parallel with a parallel resonator.
  3. 根据权利要求1所述的滤波电路,其特征在于,所述指定并联谐振器的输入端与两个所述串联谐振器相连接,所述指定并联谐振器的输出端与第三电感相连接。The filter circuit according to claim 1, wherein the input terminal of the designated parallel resonator is connected to two of the series resonators, and the output terminal of the designated parallel resonator is connected to a third inductor.
  4. 根据权利要求2所述的滤波电路,其特征在于,所述指定并联谐振器拆分的两个谐振器具有频率差且有不等的面积和/或形状。The filter circuit according to claim 2, wherein the two resonators split by the designated parallel resonator have a frequency difference and have unequal areas and/or shapes.
  5. 一种信号处理设备,其特征在于,包括:信号输入电路、信号输出电路和如权利要求1-4任一所述的滤波电路;所述信号输入电路与所述滤波电路相连接,所述滤波电路与所述信号输出电路相连接。A signal processing device, comprising: a signal input circuit, a signal output circuit, and the filter circuit according to any one of claims 1-4; the signal input circuit is connected to the filter circuit, and the filter The circuit is connected to the signal output circuit.
  6. 一种提高滤波电路性能的方法,所述滤波电路包括:多个谐振器,所述多个谐振器包括第一数量的串联谐振器和第二数量的并联谐振器,并且所述电路的输入端连接有第一电感,所述电路的输出端连接有第二电感,所述电路的接地端连接有第三电感;其特征在于,所述方法包括:A method for improving the performance of a filter circuit, the filter circuit comprising: a plurality of resonators, the plurality of resonators including a first number of series resonators and a second number of parallel resonators, and an input end of the circuit A first inductor is connected, the output terminal of the circuit is connected with a second inductor, and the ground terminal of the circuit is connected with a third inductor; characterized in that, the method includes:
    在所述第二数量的并联谐振器中设置至少一个指定并联谐振器,所述指定并联谐振器的拆分谐振器的属性参数与其他所述并联谐振器的属性参数不同,所述属性参数包括:谐振器的频率。At least one designated parallel resonator is set in the second number of parallel resonators, and the attribute parameters of the split resonator of the designated parallel resonator are different from those of other parallel resonators, and the attribute parameters include : The frequency of the resonator.
  7. 根据权利要求6所述的方法,其特征在于,还包括:将所述指定并联谐 振器与一所述并联谐振器串联或者并联。The method according to claim 6, further comprising: connecting the designated parallel resonator and a parallel resonator in series or parallel.
  8. 根据权利要求6所述的方法,其特征在于,还包括:将所述指定并联谐振器的输入端与两个所述串联谐振器相连接,所述指定并联谐振器的输出端与第三电感相连接。The method according to claim 6, further comprising: connecting the input end of the designated parallel resonator to the two series resonators, and the output end of the designated parallel resonator is connected to the third inductor. Connected.
  9. 根据权利要求7所述的方法,其特征在于,还包括:设置述指定并联谐振器拆分的两个谐振器具有频率差且有不等的面积和/或形状。8. The method according to claim 7, further comprising: setting the two resonators split by the designated parallel resonator to have a frequency difference and have unequal areas and/or shapes.
PCT/CN2020/111341 2019-10-11 2020-08-26 Filter circuit, method for improving performance of filter circuit, and signal processing device WO2021068669A1 (en)

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