WO2021068011A1

WO2021068011A1 - Synchronization circuit with reduced latency and increased throughput

Info

Publication number: WO2021068011A1
Application number: PCT/AT2019/060332
Authority: WO
Inventors: Markus PFAFF
Original assignee: Pfaff Markus
Priority date: 2019-10-07
Filing date: 2019-10-07
Publication date: 2021-04-15

Abstract

The description below relates to a method and a circuit for synchronizing asynchronous digital signals. According to an exemplary embodiment, the circuit has a first series circuit comprising a first input flip-flop and a first output flip-flop and a second series circuit comprising a second input flip-flop and a second output flip-flop, wherein the first series circuit and the second series circuit are supplied with an input signal, the level of which represents a binary value. The circuit also has a combination logic circuit designed to receive as input values an output value of the first series circuit, an output value of the second series circuit and a stored old value of a synchronized output signal and to take these as a basis for producing an updated value of the synchronized output signal. The first input flip-flop is clocked with a first clock signal, and the second input flip-flop is clocked with a second clock signal, which is delayed in relation to the first clock signal by a delay time.

Description

SYNCHRONIZATION WITH REDUCED LATENCY AND INCREASED THROUGHPUT

TECHNICAL AREA

The present description relates to the field of digital circuit technology, in particular a circuit for synchronizing asynchronous digital signals.

BACKGROUND

Digital circuits are constructed according to the current state of the art on the basis of the so-called synchronous design paradigm. A clock signal controls the loading of new contents into all flip-flops or registers of the system or subsystem. The signals at the inputs of the memory elements must remain stable for a short time before as well as after the actual time of reading in new memory values, i.e. they must not change. These periods of time are called setup and hold times. In order to always meet this condition, it is possible, for example, to work with a single clock signal within the entire system. However, this approach is not always possible due to constraints. For example, different tasks in the overall system often require several clock signals with different clock frequencies.

The areas created in this way, which work with different clock frequencies, are referred to as clock domains. These clock domains are typically asynchronous to one another, i.e. the clock signals do not have a fixed phase relation to one another. Therefore, the setup and hold times mentioned above for signals that pass from one clock domain to another may be violated. This situation can only be circumvented under certain, but often impractical, conditions.

The same situation occurs when asynchronous input signals are brought up to a synchronously clocked circuit, which is also a common case in practice. The solution to this fundamental problem lies in the use of so-called synchronization circuits. The most common circuits of this type have been known for decades, but new approaches have long been the subject of research because of their not always satisfactory properties. This is a proposal Made for such a circuit, which offers advantages over the approaches encountered in literature and practice.

The reliability of the circuit, the synchronization latency and the throughput can be used as characteristic parameters for evaluating synchronization circuits. The reliability of the circuit is mostly represented by the MTBF (Me - an Time Between Failures). The synchronization latency (hereinafter also referred to as latency) indicates the delay measured from the occurrence of a signal change at the input of the circuit until it arrives within the clock domain to which it is synchronized. The throughput indicates the rate at which signal changes can be applied to the input of the synchronization circuit without any of these changes being lost during synchronization.

The inventor has set himself the task of improving existing circuits for Syn chronization of asynchronous signals in terms of latency and / or throughput with acceptable MTBF.

SUMMARY

The above-mentioned object is achieved by the circuit according to claim 1 and the method by claim 8. Various exemplary embodiments and further developments are the subject of the dependent claims.

A method and a circuit for synchronizing asynchronous digital signals are described below. According to one embodiment, the circuit has a first series circuit comprising a first input flip-flop and a first output flip-flop and a second series circuit comprising a second input flip-flop and a second output flip-flop, the first series circuit and the second series circuit having an input signal is supplied, the level of which represents a binary value. The circuit also has a combinational logic circuit which is designed to receive an output value of the first series circuit, an output value of the second series circuit and a stored old value of a synchronized output signal as input values and to generate an updated value of the synchronized output signal based thereon . The first input flip-flop is clocked with a first clock signal, and the second input flip-flop is with a second clock signal is clocked, which is delayed with respect to the first clock signal by a delay time.

According to one embodiment, the method comprises sampling an input signal synchronously with a first clock signal and storing the sampled value in a first input flip-flop and sampling the input signal synchronously with a second clock signal and storing the sampled value in a second An input flip-flop, the second clock signal being delayed by a delay time with respect to the first clock signal. The method further comprises forwarding the value stored in the first input flip-flop to a first output flip-flop and forwarding the value stored in the second input flip-flop to a second output flip-flop and combining the value in the first output flip-flop and the second output flip-flop stored values with a stored old value of a synchronized output signal by means of a combinational Fogik circuit, the result of the combination presenting the new value of the synchronized output signal re.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, exemplary embodiments are explained in more detail with reference to figures. The illustrations are not necessarily true to scale and the exemplary embodiments are not limited to the aspects shown. Rather, emphasis is placed on illustrating the principles on which the exemplary embodiments are based.

Figure 1 illustrates a standard synchronization circuit consisting of two flip-flops connected directly one behind the other.

FIGS. 2-4 use timing diagrams to show examples of possible signal waveforms for the circuit from FIG. 1.

Figure 5 illustrates a synchronization circuit according to an exemplary embodiment.

FIGS. 6 and 7 use timing diagrams to show examples of possible signal profiles for the circuit from FIG. 5. FIG. 8 uses timing diagrams to show the signal curves in the circuit from FIG. 5 for an input signal, as in the circuit from FIG. 1 leads to maximum latency.

FIG. 9 illustrates the points in time of a reliably correct sampling of the input signal in the circuit from FIG. 5 at different phase positions of the input signal.

DETAILED DESCRIPTION

Fig. 1 illustrates a very common synchronization circuit for synchronizing (with respect to a clock signal) asynchronous signals. Such a circuit is described, for example, in U. Tietze, C. Schenk, Electronic Circuits, 2nd ed., Springer-Verlag, 2008, ISBN 978-3-540- 00429-5, pp. 679-680. Accordingly, the asynchronous input signal iAsync is fed to the input D of a clock edge-controlled D flip-flop LI. The level of the input signal iAsync represents a binary value (i.e. 0 or 1), which can also be interpreted as a Boolean state (“true” or “false”). The value / state of the input signal iAsync is transmitted to the output Q of the D flip-flop LI on every positive edge of the clock signal CLKa. Since the input signal can change almost simultaneously with the positive clock edge, metastable states can occur in the D flip-flop LI. In order to avoid incorrect states, the signal MayMeta available at the output Q of the first D flip-flop LI is not used as the output signal, but the output Q of the D flip-flop LI is followed by a further D flip-flop L2, which is clocked with the same clock signal CLK is. That is, the output Q of the first D flip-flop LI is connected to the input D of the second D flip-flop L2. At the output Q of the second D flip-flop L2, the synchronized signal Syncd is available as an output signal.

The clocked circuit, to whose clock the asynchronous input signal iAsync is to be synchronized, is referred to as the “clock domain”. Within a clock domain, the states of signals change synchronously with the clock signal that belongs to the respective clock domain.

In FIGS. 2 to 4, various examples of signal waveforms are shown. In general, the gray-shaded interval around the positive clock edges (times t ₀ , t _l etc.) of the clock signal CLK represents the sum of the setup Time ts _ETUP ^unc l holding time t _H0LD . That is, with respect to the time _t0 occurring clock edge, the gray shaded interval represents the interval from t ₀ - t _SETUP to t ₀ + t _H o _LD The same applies to Fig. 6 and 7.

2 shows the case of minimal latency, a change of state (from low to high in the present example) of the input signal iAsync occurring at the end of the hold time, that is to say at time t ₀ + t _HOLD . In this case, the D flip-flop LI can assume a met astable state and, if the D flip-flop LI falls from the metastability into the new state (which does not necessarily have to be the case), the value of the input signal is at the point in time

= t ₀ + T _{CLK available} in the clock domain of the D flip-flop L2. The synchronization latency of the output signal Syncd with respect to the input signal iAsync is in this case somewhat smaller than the period T _{CLK of} the clock signal CLK and is T _CLK -t _H0LD .

Fig. 3 shows the case of maximum latency, a change of state of the input signal iAsync (in the present example from low to high) occurs at the beginning of the setup time, ie at time t ₀ - t _SETUP . In this case, the D-flip-flop LI can assume a metastable state and, if the D-flip-flop LI falls from the metastability to the old state, the current state is only two periods later, ie at the time ^ 2 ⁼ ^ o + 2 T _CLK , available in the clock domain of the D flip-flop L2. The synchronization latency of the signal change of the input signal iAsync up to the arrival of the signal change synchronized to the clock in the clock domain is in this case slightly greater than twice the period duration 2 T _{CLK of} the clock signal CLK, namely 2 T _CLK + t _SETUP . This duration only refers to the arrival of the input signal change in the clock domain. There, after the rising clock edge, a further time t _DEL , the signal propagation delay, elapses between the clock edge and the occurrence of the signal change at the output of the D flip-flop L2. However, this time elapses after the input signal arrives in the receiving clock domain. It is therefore not added to the synchronization latency. For this reason, this time period is not shown in the example from FIG.

Fig. 4 illustrates several asynchronous state changes of the input signal iAsync to represent the maximum achievable throughput in the synchronization according to FIG. 1. The first state change occurs at the beginning of the setup time, ie at time t ₀ - t _SET up In this example, the D flip-flop LI temporarily assumes a metastable state and then falls back into the old state, ie the MayMeta signal remains in that Low state up to time t ₁ + t _DEL and the change of state only becomes “visible” in the output signal Syncd _{at time iq + t DEL.} Shortly after the time iq, the input signal iAsync changes back to a low state. This can no longer be detected by the D flip-flop LI in the same clock period and consequently this change of state is only visible in the signal MayMeta at time t ₂ + t _DEL and in the output signal Syncd only at time t ₃ + t _DEL , etc.

Of the properties of the circuit from FIG. 1, the values for the latency and the throughput are examined in more detail below. The latency is in a range from just below one clock period, ie approximately T _CLK − t _H0LD , to a little more than two clock periods, ie 2 T _CLK + t _SETUP . The rising clock edge of the clock signal CLK of the receiving clock domain is regarded as the time of arrival. At this point in time (see. Fig. 4, times iq, t ₂ , etc.) the input signal can be viewed as synchronized, even if a small additional delay time (signal transit time t _DEL ) is required until this synchronized output signal Syncd can affect the following combinational circuit.

The throughput is determined by the time span between two signal changes, which must be at least T _CLK + t _SETUP + t _H0LD (see FIG. 4). The clock signal CLK of the receiving clock domain must therefore always have a higher clock frequency than the (asynchronously) sending clock domain. The same clock frequency is not enough. The MTBF is determined by the circuit properties of the D flip-flop LI, mainly by the time span T _CLK - (t _SETUP + t _DEL ), which is available to it to resolve any metastability that may occur. If this time span is exceeded, the metastable state is applied as an input value at flip-flop L2, which in turn can result in its metastability. In this case the synchronization would not be successful.

The exemplary embodiments described below relate to a concept for improving existing circuits for synchronizing asynchronous signals with regard to latency and / or throughput with an acceptable MTBF. The procedure described below can enable the improvement mentioned. First of all, it is detected whether there is metastability within the synchronization circuit. In this regard, two examples will be explained later. Depending on whether a metastable state has been detected, conclusions can be drawn as to the correct state. Binary signals as used in digital circuits have only two states / values, namely 0 (low state) or 1 (high state). If there is metastability, this can only have been caused by a change in the status of the input signal either from 0 to 1 or from 1 to 0. If metastability has been detected, then the negation of the last valid state of the synchronous output signal (in the synchronous clock domain) is the correct value for further use. This also applies in a trivial way to the presence of a signal change that has not caused metastability. The proposed procedure thus determines a valid new clock-synchronous state from the old state (of the synchronized output signal) and the determination of whether metastability or a signal change is present or not.

The presence of metastability (or a signal change) can be recognized by comparing the values from two synchronization chains (two D flip-flops one behind the other according to FIG. 1) if the first D flip-flop of one of the chains is around the value ts _ETUP + t _HOLD receives delayed clock. This measure guarantees that one of the two synchronization chains always carries the correct signal at the output, but it cannot be detected which of the two synchronization chains is delivering the correct signal. If these two output signals are different, there is metastability (or a signal change). This procedure can be easily implemented by means of techniques known per se (integration by means of a field programmable gate array, FPGA, or as an application-specific integrated circuit, ASIC) and is explained in more detail below using the example from FIG. 5.

The circuit arrangement from FIG. 5 comprises two synchronization chains (D flip-flops LI and L2 and D flip-flops L3 and L4), each of which is constructed like the circuit of FIG. 1. The D flip-flops LI and L2 The first synchronization chain and the D flip-flop L4 of the second synchronization chain are clocked with the clock signal CLKa to which synchronization is to take place. The D flip-flop L3 of the second synchronization chain is clocked with the clock signal CLKb, which is delayed compared to CLKa. Both clock signals CLKa and CLKb therefore have the same clock frequency T _{CiÄ ·} ^-1 , the clock signal CLKb being delayed by a small fraction DT of a clock period T _CLK compared to the clock signal CLKa (where DT> t _SETUP + t _H0LD ). According to one example, the Delay AT between the clock signals CLKa and CLKb is only slightly greater than the sum t _SETUP + t _H0LD . The clock signal CLKb can be derived from the clock signal CLKa using methods known per se (for example by means of a delay-locked loop, DLL, a phase-locked loop, PLL, or a wide variety of delay circuits).

According to FIG. 5, the (asynchronous) input signal iAsync is fed to the first D flip-flop of both synchronization chains, that is to say the flip-flops LI and L3. The output signals from the flip-flops LI and L3 are designated MayMetaA and MayMetaB, and these are fed to the inputs of the subsequent flip-flops L2 and L4. The output signals of the synchronization chains (i.e. flip-flops L2 and L4) are labeled A and B. Due to the delay of the clock signal CLKb, which is used for the first flip-flop L3 of the second synchronization chain (flip-flops L3 and L4), unequal states of the output signals A and B (i.e. AB) necessarily mean that either of the two flip-flops LI or L3 is metastable or a simple signal change has occurred, and without further information it is not known which of the output signals, A or B, correctly represents the input signal iAsync.

[0030] The "reconstruction" of the correct state (logic level) of the input signal iAsync is carried out with a sequential logic (sequentie _l l Logic, switching power) which is a combinational logic comprises CL1 (combinational logic, derailleur) and a further D flip-flop L5 , whose input D the output signal N of the combinational logic CL1 is supplied. The D flip-flop L5 is also clocked with the clock signal CLKa. The combinational logic CL1 receives the output signals A, B of the two synchronization chains and the fed-back output signal O of the further D flip-flop L5 as input signals.

The mode of operation of the combinational logic CL1 is shown in FIG. 5 with the aid of a truth table. Their statement is put into words: If the states of the signals A and B are the same (which indicates that there is no metastability), then the combinational logic CL1 forwards this state to the flip-flop L5 (N =

A = B). If the states of the signals A and B are unequal (which indicates metastability or a signal change on the input signal), then the combinatorial logic CL1 passes the inverted output signal O to the flip-flop L5 (N = Ö). Expressed as a combinational equation, the state of the output signal N output of the combinational logic CL1 corresponds to the following equation: Syncd - N - AB + A - 0 + B —O (1) where “+” denotes an OR, an AND link and “-” denotes a negation.

A procedure according to FIG. 5 for the detection of metastability and - if metastability occurs - for determining the correct state of the input signal iAsync allows a fast and circuit-efficient implementation (e.g. in an FPGA). The decision as to whether there is metastability can be made very quickly.

As mentioned, due to the delay DT between the clock signals CLKa and CLKb (clock offset) when the state of the input signal iAsync changes, only one of the two input flip-flops of the two synchronization chains (ie the flip-flop LI or the flip-flop L3) become metastable. This change of state can either be a transition from 0 to 1 or from 1 to 0. In the following, a general change of state from OldVal to NewVal is considered. After a clock edge of the clock signal CLKb and a period of time, which can only be described statistically, for the decay of metastability, one of the two output signals, MayMetaA or MayMetaB, represents the correct, new state NewVal of the input signal iAsync, whereas the other output signal in the case of metastability has an unreliable condition (ie the condition can be correct, but it can also be incorrect). The D flip-flop (LI, respectively L3), which outputs the correct state of the input signal iAsync at its output Q, is referred to below as a "sure-correct flip-flop", whereas the D flip-flop (L3, or LI) in the other synchronization chain is referred to as a “dubious state flip-flop”.

As mentioned, it is not known a priori which of the two synchronization chains contains the safe-correct flip-flop. Which of the two flip-flops - LI or L3 - takes on the role of the safe-correct flip-flop depends on the time relationship between the time of the (asynchronous) change in state of the input signal iAsync and the rising clock edge in the clock signal CLKa. In any case, shortly after the rising edge of the delayed clock signal CLKb (and thus also after the edge of the clock signal CLKa that occurs shortly before) the correct state NewVal of the input signal iAsync has been saved. For the doubtful state However, flip-flops have two options. First, it can adopt the correct state NewVal or become metastable and choose the correct state when the metastability is resolved. In this case it has the same state as the safe-correct flip-flop (namely NewVal). Second, it can decide in favor of the wrong value OldVal (e.g. due to the violation of t _SETUP or t _H0LD or the phase position of the signal change of the input signal iAsync relative to the clock edge) or it can become metastable and, when the metastability is resolved, the old ( and wrong) value OldVal. In this case it has a different value than the sure-correct flip-flop (namely OldVal). The state of the flip-flops LI and L3 is manifested by the state / level of the associated output signals MayMetaA and MayMetaB.

The states output by the D flip-flops LI and L3 (ie the levels of the signals MayMetaA and MayMetaB) are transported to the downstream D flip-flops L2 and L4 and are read and stored by them on the next edge of the clock signal CLKa . There is only a low probability that metastability will occur if enough time was available for the metastability that may be present in flip-flop LI or L3 to subside. The amount of time available is an important factor in determining the MTBF.

The combinational logic circuit CL1, which is connected to the outputs Q of the D flip-flops L2 and L4, is able, as already mentioned above, to take into account the state / level O last output (stored in D flip-flop 5) to determine the new synchronized state of the output signal Syncd. If the levels of the signals MayMetaA and MayMetaB are the same, their value is the new level NewVal of the output signal Syncd, since one of the two D flip-flops LI and L3 certainly contains the correct value. In the truth table shown in FIG. 5, this case corresponds to the two upper and the two lower lines of the table. If the levels of the signals MayMetaA and MayMetaB are different, one of the D flip-flops LI and L3 contains the correct value and the other contains the incorrect value. Since this case could only occur by changing the level of the input signal iAsync, the old value OldVal stored in the D flip-flop L5 must be the incorrect value, and consequently the correct new value NewVal can be determined by negating the value stored in the flip-flop L5 . These cases are represented by the middle four lines of the truth table mentioned (see also Equation 1, which is equivalent to the table). The exemplary embodiment according to FIG. 5 has significantly better properties compared to the circuit from FIG. 1, despite moderate implementation outlay in terms of latency and throughput. The latency until arrival in the receive clock domain ranges from just under one clock period (T _CLK ) to just under two clock periods (t _SETUP + (T _CLK - DT) + T _CLK ). The maximum latency is thus better than with the circuit from FIG. 1. This has a positive effect on the response times to events occurring asynchronously. In certain circumstances, the fact that the maximum latency is a little less than two clock cycles 2 T _{CLK can be} a key benefit. The latency times will be discussed in more detail later with reference to FIGS. 6 and 7.

With regard to the time information on the latency, what has already been said in the discussion of FIGS. 2-4 applies. In the application case, the signal propagation time t _F for the combinational circuit CL1 (see FIG. 5) within the receiving clock domain must also be taken into account in the present example, although this is not to be added to the synchronization latency. Fig. 6 shows the case of minimal latency. A change of state (from low to high, ie from 0 to 1, in the present example) of the input signal iAsync occurs at the end of the hold time, ie at time t ₀ + t _H0LD . In this case, the D flip-flop LI can assume a metastable state and, if the D flip-flop LI changes to the new state (which does not necessarily have to be the case), the current state is approximately one period later, ie at time G = t ₀ + T _CLK , available at the output of the D flip-flop L2 (signal A). The latency until the arrival of the signal change on the input signal iAsync in the clock domain of CLKa is in this case somewhat smaller than the period T _{CLK of} the clock signal CLK and is T _CLK - t _H0LD . The signal change occurs synchronously within the clock domain of CLKa by the time period t _DEL + t _F after the rising edge of CLKa, but this is automatically taken into account in the system circuit design by the static timing analysis usually used there. Since this period of time passes within the receiving clock domain, it is not added to the synchronization latency.

Fig. 7 shows the case of maximum latency, with a change of state (from low to high, or 0 to 1, in the present example) of the input signal iAsync at the beginning of the setup time of the D flip-flop L3 occurs, ie for Time t ₀ '- t _SETUP . In the worst case, the flip-flop LI can no longer change the state of the input signal iAsync detect and the flip-flop L3 could detect the change in state, but becomes metastable and falls back to the old value after the metastability has subsided. The time t ₀ '= t ₀ + DT denotes the time of the delayed clock edge of the clock signal CLKb with respect to CLKa. In the present example, the D flip-flop L3 assumes a metastable state and, as mentioned, falls into the old state, and consequently the current state only comes about two periods later, ie at time t ₂ = t ₀ + 2 in the clock cycle. Domain of CLKa, in the D flip-flop L5. According to FIG. 7, the synchronization _{latency is} ts ETUP + (T _CLK -DG) + T _CLK <2 T _CLK . The signal change occurs synchronously within the clock domain of CLKa by the time period t _DEL + t _F after the rising edge of CLKa, which, however, is automatically taken into account in the system circuit design by the static timing analysis usually used there. Since this time passes within the receiving clock domain, it is not added to the synchronization latency.

FIG. 8 illustrates a situation (change of state in the input signal iAsync at time t ₀ −t _SETUP ) which, in the example from FIG. 1, has led to maximum latency. In the circuit according to FIG. 5, this situation leads to a significantly shorter latency. According to FIG. 8, in this extreme case the flip-flop LI becomes metastable and then falls back to the old value. Due to the delayed clock CLKb, the flip-flop L3 can correctly detect _{the new state of the input signal at time t 0 '.} At the next clock edge of the clock signal CLKa, the metastability manifests itself in an inconsistency of the output signals A and B (ie A and B have different values). This inconsistency is recognized by the combinational logic CL1 (see FIG. 5) and _{corrected within the signal propagation time t F} (by inverting the old value O). The correct result is already available in the output signal Syncd = N at the time iq + t _DEL + t _F. One cycle later, the flip-flop L5 makes this new value available at its output as the old value O then again.

The throughput is determined by the shortest time span between two signal changes during which all signal changes arrive in the receiving clock domain. This is a minimum of T _{CLK here} . The receiving clock domain can therefore have the same clock frequency as the (asynchronously to it) sending clock domain. This time span is achieved because at most one of the two synchronization chains (flip flops LI + L2 and L3 + L4) always has an input flip-flop (flip-flop LI or L3) in a met- has astable state, while the other flip-flop is correctly scanning the signal. In the example from FIG. 9, the sampling times for different phase positions of the input signal iAsync with respect to the clock CLKa are highlighted by circles. In the first variant of the input signal iAsync (FIG. 9, third diagram from the top), a change from 0 to 1 occurs before time t ₀ -t _SETUP and the input signal iAsync is correctly sampled by D flip-flop LI _{at time t 0} . In the second variant of the input signal iAsync (FIG. 9, fourth diagram from the top), a change from 0 to 1 occurs after time t ₀ -t _SETUP but before time t ₀ , ie metastability can occur in the D flip-flop LI and the D flip-flop L3 is the sure-correct flip-flop, which correctly scans the input signal iAsync _{at time t 0} '= t _{0 + DT.} The same applies to the third variant of the input signal iAsync (FIG. 9, fifth diagram from the top), in which the change from 0 to 1 occurs precisely at time t ₀ . In the fourth variant of the input signal iAsync (FIG. 9, sixth diagram from the top), a change from 0 to 1 occurs at time t ₀ '- t _SETUP , and the old value (i.e. 0) of input signal iAsync becomes at time t ₀ sampled from the D flip-flop LI, whereas metastability can occur in the D flip-flop L3. The same applies to the fifth variant of the input signal iAsync (FIG. 9, seventh diagram from the top), in which the change from 0 to 1 in the input signal iAsync occurs between t ₀ '- t _SETUP and t ₀ '. In the sixth variant (Fig. 9, bottom diagram) of the input signal iAsync (Fig.

9, eighth diagram from above) the change from 0 to 1 occurs between t _Q 'and t ₀ ' + t _H0LD , and consequently the D flip-flop LI still scans the old value and metastability can occur in the D flip-flop L3. In the last variant, the change from 0 to 1 in the input signal iAsync only occurs after time t _Q '+ t _H0LD , ie the D flip-flop LI still scans _{the old value at time t 0} and metastability can occur in the D flip-flop L3 The D flip-flop L3 can only detect the change from 0 to 1 at this point in time.

The time span between two changes in the input signal iAsync may fall below the time span T _CLK within a certain framework, if this is adhered to at least over time.

It goes without saying that a person skilled in the art is able to modify the example from FIG. 5 without significantly changing its function and its effect. For example, D flip-flops can also be implemented by other types of edge-controlled flip-flops or level-controlled flip-flops (latches). Furthermore, it is also problem- It is possible without any problems to trigger one, several or all of the edge-controlled flip-flops with the falling edges of the clock signals. The synchronization chains used in FIG. 5 according to FIG. 1 can also be formed by connecting more than two flip-flops in series for the purpose of increasing the MTBF. Furthermore - depending on the circuit technology available in a specific application - the implementation of the individual circuit components can be different. For example, the combinational logic CL1 defined by a truth table in FIG. 5 can be implemented in many different ways by combinations of different gate circuits. Furthermore, it goes without saying that, depending on the application, a binary value “0” or a logic state “false” can be represented by both a high level and a low level of the input signal iAsync. The same applies to the value “1” or the logical state “true”, which is represented by the inverse level of the input signal. The function of the circuit is also not changed if it has an inverting characteristic overall. This means that a value “1” of the input signal iAsync can also be translated into a value “0” of the output signal Syncd and vice versa.

Claims

PATENT CLAIMS

A circuit comprising: a first series circuit comprising a first input flip-flop (LI) and a first output flip-flop (L2) and a second series circuit comprising a second input flip-flop (L3) and a second output flip-flop (L4 ), wherein the first series circuit and the second series circuit an input signal (iAsync) is supplied, whose level represents a binary value; and a combinational logic circuit (CL1) which is designed to receive as input values an output value (A) of the first series circuit, an output value (B) of the second series circuit and a stored old value (O) of a synchronized output signal (Syncd) and based thereon to generate an updated value of the synchronized output signal (Syncd), wherein the first input flip-flop (LI) is clocked with a first clock signal (CLKa), and the second input flip-flop (L3) with a second clock signal (CLKb) ) is clocked, which is delayed by a delay time (AT) with respect to the first clock signal (CLKa).

2. The circuit of claim 1 further comprising; a further flip-flop (L5) which is designed to store the updated value (Syncd) and to supply it to the combinational logic circuit (CL1) as the old value (O) in a subsequent clock cycle.

3. The circuit according to claim 1 or 2, wherein the first output flip-flop (L2) and the second output flip-flop (L4) are clocked with the first clock signal (CLKa).

4. The circuit according to one of claims 1 to 3, wherein the first input flip-flop (LI) and the second input flip-flop (L3) have a setup time (t _SETUP ) and a hold time (t _H0LD ) and wherein the delay time (AT) is greater than the sum of the setup time (^ SETUP) and hold time (t _H0LD) .

5. The circuit according to one of claims 1 to 4, wherein the logic circuit (CL1) is designed to output a value as the updated value of the synchronized output signal (Syncd) which corresponds to the output output value (A) of the first series circuit if the output values (A, B) of the first and second series circuit are the same, and to output a value as the updated value of the synchronized output signal (Syncd) that corresponds to the negated old value (O) when the output values (A, B) of the first and second series circuit are not the same.

6. The circuit according to one of claims 1 to 5, wherein the logic circuit (CL1) has a transfer characteristic which is characterized by the following equation:

Syncd = (ABA - 0 B - O), where Syncd denotes the current value of the synchronized output signal (Syncd), A denotes the output value of the first series circuit and B the output value of the second series circuit, and 0 denotes the stored, old value of the synchronized Output signal (Syncd).

7. The circuit according to one of claims 1 to 6, wherein the input flip-flops (LI, L3) and the output flip-flops (L2, L4) are edge-controlled D flip-flops.

8. A process that includes:

Sampling an input signal (iAsync) synchronously with a first clock signal (CLKa) and storing the sampled value in a first input flip-flop (LI);

Sampling the input signal (iAsync) synchronously with a second clock signal (CLKb) and storing the sampled value in a second input flip-flop (L3), the second clock signal (CLKb) in relation to the first clock signal (CLKa) by a delay time (DG) is delayed;

Forwarding of the value (MayMetaA) stored in the first input flip-flop (LI) to a first output flip-flop (L2) and forwarding of the value (MayMetaB) stored in the second input flip-flop (L3) to a second output flip-flop (L4);

Linking the values (A, B) stored in the first output flip-flop (L2) and the second output flip-flop (L4) with a stored old value (O) of a synchronized output signal (Syncd) by means of a combinational logic Circuit (CL1), the result of the combination representing the new value of the synchronized output signal (Syncd).

9. The method according to claim 8,

Storing the new value of the synchronized output signal (Syncd) in a further flip-flop (L5), which is designed so that it is available as a stored old value (O) in a subsequent clock cycle.

10. The method according to claim 8 or 9, wherein the logic circuit (CL1) is designed to output a value as the updated value of the synchronized output signal (Syncd) which corresponds to the output value (A) of the first series circuit when the output values (A , B) of the first and the second series circuit are the same, and to output a value as the updated value of the synchronized output signal (Syncd) which corresponds to the negated old value (O) if the output values (A, B) of the first and second Series connections are not the same.