DE19713660A1 - Phase adjustment of fast parallel signals - Google Patents

Abstract

According to the invention, when fast signals are transmitted via several data lines, delay elements are used at least for data signals. A known edge of the data signal is checked against a nominally simultaneous edge of a reference signal by means of a phase comparator, and the delay elements are adjusted according to the results of the comparison.

Description

Technical field

The invention relates to an operating method including a scarf device for the parallel, synchronous transmission of very fast bursts of signals, preferably in digital re kitchen systems.

State of the art

Multiple data signals are often used in computing systems at the same time, i.e. on electrically parallel lines, transferred from a data source to a data sink. Each the greater the number of lines, the greater be known that which is transferable at a given clock rate Amount of information, so this technique with a large Number of 32 or more lines in the circuits is used by high-performance central processing units.

Especially at clock rates of 100 MHz or above however, it turns out that the transit times of the signals differ on the different lines. With egg A clock rate of 100 MHz is two consecutive Clock edges 10 ns apart so that a phase accurate speed of at least 1 ns is necessary. This time speaks a line length of 15 cm, because in lines the speed of the electric waves at first half the speed of light. In the Connection of electrical circuits in one High performance system with these and higher frequencies is therefore not to avoid running time differences cause that parallel transmitted signals with as far un different terms arrive at the recipient that  the signals can no longer be reliably received nen.

Since the lines on the receivers no longer exist are accessible for external measuring equipment any kind of manual adjustment of the run times not possible. It was also observed that the running times also in operation, e.g. B. by heating, move.

In the US Pat. No. 5,513,377 an arrangement is given in which eight data lines and a clock line represent a connection unidirectionally. Runtimes on the data lines are individually compensated by using, as shown in FIG. 4, a tapped delay element to which a large number of devices are connected, which are used to detect and evaluate the edges of the data signals.

A circuit is disclosed in US Pat. No. 5,487,095 given by means of which a data signal is in phase with a Clock can be brought. With this circuit, a Number of differently delayed versions of the input signal for the purpose of detecting the edges and off selection of a suitable version of the parallel delayed versions of the input signal are evaluated. Here too is a tapped delay device necessary.

It is the object of the invention, an alternative, less complex operating procedure and a suitable one Arrangement to indicate such that an automatic correction ture of the run times on the data lines. In particular in particular, the solution should be independent of the type of digi tal adjustable delay line.  

Presentation of the invention

The invention is based on the consideration that the barrel times are very slow in relation to the cycle times change. It therefore uses adjustable delay links that are only adjusted when one predetermined edge of a reference signal is nominally equal with an edge of the respective data signal lies. The necessary delay elements come with each a data input and output as well as a control input, with a very small number of lines and can be realized in different techniques, as detailed in the description.

In a first, preferred embodiment, meh parallel data lines and an additional control instruction used. The control line transmits an Si gnal, on the one hand for the reconstruction of the reception clock tes via a phase corrected oscillator. she is also used to block data, i.e. H. several seri successive and related data sets labeling. It is assumed that the data blocks to be transferred into a number of Da word words are divided, the number of data lines equal to the number of bits in a data word and the data words belonging to a block unmit consecutively, also referred to as synchronous, be transmitted. This is also referred to as transfer Called frame. The reference signal then shows the Be beginning and at the same time through the beginning of the next that End of the previous data block or frame. If no user data are present, matching blocks of data sent, in which there are predetermined edge changes and who are then used to correct the runtimes the. The beginning of a frame is rising Edge shown. Choosing whether a data frame or Synchronization frame is given by the length of the  Reference signal displayed. The falling edge of the Refe The reference signal is then the reference point for the runtime equal. The predetermined one is determined via phase comparators Edge of the data signal compared to the nominally time-constant Chen edge of the reference signal compared. Corresponding The delay elements become the comparison result adjusted.

Further designs, variants and embodiments can be found in the following description.

Brief description of the drawings

Show it

Fig. 1 is a schematic representation of a circuit for carrying out the invention,

Fig. 2 is a schematic representation of a tarry approximately member,

Fig. 3 is a signal diagram for the case in which separate data and matching frames are transmitted,

Fig. 4 is a signal diagram for the event that is carried in a frame at the same time balance and Datenübertra supply,

Fig. 5 shows a variant for different edges of the data signal,

Fig. 6 shows a further development of the variant of FIG. 5,

Fig. 7 shows a variant for automatic detection of the matchable reference times.

Description of an embodiment of the invention

The invention is described using an example in which eight data bits on two data lines with four clock cycles klen are transmitted, i.e. using a frame mens of four bars. In practice, there will be many more Data lines used; for example, the content a cache line of 64 bytes with 32 data lines transmitted in a frame of 16 clocks.

In addition to the data signals D0, D1 is a reference transmit signal REF from which the receiver uses the clock Φ wins, recognizes the beginning of a frame and the one Reference edge for the phase correction of the data lines contains.

A phase correction can only be carried out by delaying the edges of the faster arriving signals to such an extent that they arrive simultaneously with the edges of the slowest signal. A number of solutions are available to the person skilled in the art for an adjustable delay of signals. A preferred embodiment is shown in FIG. 2a. A delay chain is formed by connecting an even number of inverters in series. The input signal is present at each (even) connection, delayed by a factor of twice the transfer time of an inverter, and is tapped by a multiplexer in accordance with the delay to be set. Alternatively, a chain of cells can also be used, as shown in FIG. 2b as a circuit, which can be switched between a small and a larger delay if a relatively large minimum delay is advantageous compared to the gain due to the ease of integration. It is also known to slow the edge by a capacitance and to scan it by means of a threshold switch, the threshold value of which is set by a simple digital-to-analog converter. In all cases, it has proven itself to provide the delay elements internally with an up-down counter, which has a release input, a clock input and an input “±” for switching between up-counting and down-counting. In the following, it is always assumed for the sake of simplicity that a zero count means minimum delay, the counters are all set to zero by a reset signal and the counters remain in the extreme positions, ie do not count modularly.

In Fig. 1, the arrangement on the basis of which the invention is further described is shown schematically. The reference signal REF and the two data signals D0 and D1 are delayed via delay elements 11 , 13 a and 13 b and result in the ultimately phase-synchronous delayed signals REF ', D0' and D1 '. A clock signal Φ is obtained from the delayed reference signal RFF ', for example by a phase-controlled oscillator 17 (PLL), with which the delayed data signals D0', D1 'are sampled. As mentioned, the input "±" increases or decreases the adjustable delay by one value with each cycle. Furthermore, each of the delay elements 13 a, 13 b is provided with an output marked with “= 0”, which indicates that the delay is set to the smallest possible value. A higher-level control, not shown, releases the inputs "±" for the times of the adjustment and blocks them during the transmission of user data; the detection of these two operating conditions is described below. Since this control prevents the circuit from being changed during the transmission of user data, the following description always refers to the operating state of the phase adjustment, unless stated otherwise.

After resetting the circuit at the start of operation, the delay times should all be set to the minimum value. The delay element 11 belonging to a further development is not effective, so that the signals REF and REF 'are the same. In a first control loop, the data signals D0 'and D1' are now set to be in phase with the reference signal REF '. For this purpose, phase comparators 15 a and 15 b are provided, which are connected on the one hand to the reference signal REF 'and on the other hand to the respective delayed data signal D0', D1 '. In the simplest case, XOR gates are possible as phase comparators, the output of which is sampled by suitable clock signals. Preferably, the likewise known solution via a D flip-flop is used as the phase discriminator, at whose clock input the reference signal REF 'and at whose data input the delayed data signal D0', D1 'is applied. In this case, the falling edge of the reference signal REF 'is used to take over the data, which likewise undergo a transition from H to L at this point in time. The output of the phase comparator 15 a, 15 b is connected to the input "±" of the respective delay element 13 a, 13 b, so that the following mode of operation results: If the phase discriminator delivers the signal H, then at the time of the relevant falling edge Reference signal REF 'the data signal D0', D1 'is still high, ie the falling edge is still ahead. The signal is too fast and must be delayed, which is why the H level at the output of the phase comparator leads to the delay value of the delay element being increased. If the output of the phase comparator 15 a, 15 b is at an L level, then the relevant falling edge of the reference signal REF 'lies before the falling edge of the data signal; So this is possibly too slow and is controlled via the input "±" of the respective delay element with L level and thus accelerated.

There is a constant oscillation of the values for the delay of the data signals because the data signals either delayed or accelerated with each comparison will. With a correspondingly fine resolution, this is the Delays, however, are of no importance if these changes as described, with the start of user data transmissions are blocked. Also in the delay be provided that the last two bits the binary representation of the delay time as given in an up-down counter is stored, not at all for delay be used and thus remain ineffective. Other means, such as random walk filters, are also possible.

Another possibility with fixed frames of e.g. B. 16 Clocking is to advance an up-down counter hen, which corresponds to the output of a Phase comparator counts up or down and this Er to evaluate the result at the end of a framework with threshold values ten, so that, for example, only at a meter reading un the delay element below four or above eleven is adjusted. This will be the side grid of the phases dampened comparator.

The arrangement described so far presupposes that other measures, for example a fixed delay for the signal REF ', ensure that the reference signal REF' is always slower than the data signals. A further improvement can be achieved if, as shown in FIG. 1, the delay of the reference signal is dynamically adjusted. For this purpose, the outputs "= 0" of the delay elements for the data signals are used, which are evaluated by a non-and element 19 . Its output goes to the H level as soon as one of the delay elements 13 a, 13 b for the data signals is set to minimum delay. Via an integrator 21 , the effect of which will be explained in more detail, this signal is applied to the input “±” of the delay circuit of FIG. 11 for the reference signal. This has the effect that, if at least one data signal is minimally delayed, the delay for the reference signal is increased. The output "= 0" of a delay element 13 a, 13 b for a data signal D0, D1 is thus seen as an indicator that this could be accelerated even further. Since this is not possible, the reference signal must instead be delayed and, as a result, all other data signals must be delayed until all data signals are operated in the control range of their delay elements. The output "= 0" can also be set before reaching the minimum delay, for example at about 10%. In particular, the measures against control vibrations described below are accelerated.

Since this development involves two coupled control loops, measures are necessary to avoid control vibrations. If a control delay is already included in the control loops for the delay of the data signals, for example by the counter listed above and thus only one adjustment per frame, the output signal of the non-and-gate 19 , which is not associated with edge gratings, can be sent directly to the control input of the delay element 11 for the reference signal are placed, so that the delay element 21 shown in FIG. 1 is not necessary.

Otherwise, when the outputs of the phase comparators for the data signals take effect without delay, the simplest measure is an integrator 21 , which slows down the control loop for the reference signal REF '. The integrator can be created in analog technology by a threshold switch with hysteresis. Solutions in digital technology such as random walk filters are also possible, for example with an up-down counter, whose counter reading is compared to 1/3 or 2/3 of the total range, depending on the output, and thus a hysteresis of 1 / 3 of the range. Another variant consists in a shift register, the outputs of which must all be at H level or L level in order to switch a subsequent RS flip-flop. Preferably, a higher-level control, not shown, adds a predetermined number of example 16 cycles, the output of the non-and element 19 by a previously reset counter, and finally generates the integrated signal by means of a threshold value comparison, the threshold value comparison preferably passing through half the range Use the most significant bit of a binary counter. Other measures known to the person skilled in control technology which bring about the stability of the two nested control loops can also be used.

A signal diagram is shown in FIG. 3. In this case, four useful data words are first transmitted in one frame during the time marked with DATA, which is followed by an equally long time for the phase adjustment in this example. The reference signal REF indicates the beginning of a new frame with its rising edge. This impulse lies in the transmission of data for one clock cycle on H and for the remaining clock cycles on L.

If there is no user data, this should be the framework be used for a synchronization, so it is Reference signal REF for at least the first two cycles to H level and then one for the remaining clocks Frame at L level so that the H level in the second clock can serve to free the procedures described above admit. Preferably the levels on the data lines are conditions equal to the level of the reference signal, so that in the case of play all signal lines show an H-L transition, the through the methods and circuits described Simultaneity is regulated in the receiver. You can  of course, several data phases directly on top of each other follow as well as several synchronization phases. It ver it is clear that for the synchronization phase se those frames are used where none Data pending for transmission. Of course you can also a short reference signal for the Sychronisati phases and a long one used for the data phases will. In this case it is easily possible in mer two clocks for synchronization and several clocks to use for a data frame, so that by the Dead time caused by synchronization times is low.

For cases in which a continuous data stream must be secured and therefore no adjustment frames can be inserted, the first two clock cycles can also serve, as indicated in FIG. 4, for synchronization by the reference as well as the data signals in the first clock cycle H level and in the second cycle to L level and then the following cycles are used for the transmission of user data.

Another variant is to always use the clock with reference signal at H level for synchronization and only the subsequent clocks for user data transmission. For this purpose, the data word to be transmitted in the clock thereafter is inverted in the clock in which the reference signal has an H level. As shown in Fig. 5, the output of the phase comparator 15 a is inverted when the data signal after the phase comparison is at the H level and thus there was a rising edge. Instead of the inversion shown by an XOR gate, a phase comparison circuit 15 a with a complementary output, which is selected by the current data signal, can of course also be used.

Another development according to FIG. 6 allows the continuous transmission of user data without requiring frames for the phase adjustment, provided that a change in the level of the data from the first to the second cycle of a frame marked by the signal REF is often sufficient. For this purpose, a D flip-flop 61 is used , the output of which has the data level of the preceding clock. A negated XOR 62 links the current level and the previous level, thereby indicating that a level change has taken place. This results in a release of the result of the phase comparator 15 a, symbolized by the switch 64 , which thereby activates the input ± of the delay element. In this case, as before, a selection corresponding to the current level must follow, as is symbolized by the XOR element 51 . Furthermore, not shown in FIG. 6, the entire process is enabled by the reference signal, because only then is there a defined level change in the comparison signal REF.

Another development of the invention shown in FIG. 7 wins the release signal for the change in the delay element itself. Here, the reference signal of the previous clock is stored by the D flip-flop 71 . A combinatorial logic 63 is then fed both the reference and data signal of the current clock, the reference and data signal of the previous clock and the result of the phase comparator 15 a. The combinatorial logic 73 then supplies an output signal X according to the following table:

The output signal X is capable of three values, namely a neutral, which does not change the delay element 13 a and is assumed in all cases not listed in the table, a positive and a negative, in which the delay is increased or decreased. The table states that when changing from H to L of the reference signal and when changing from H to L of the data signal, the result of the phase comparator 15 a is used as a positive or negative output and in the same situation for the reference signal and a change from L after H of the data signal, the result of the phase comparator is used inverted.

Claims (10)

1. Operating method for a phase correction of at least two simultaneously transmitted digital data signals (D0, D1) by means of a likewise transmitted reference signal (REF ') with the following features:

• - The data signals (D0, D1) are delayed by an adjustable delay element ( 13 a, 13 b) to delayed data signals (D0 ', D1'),
• the delayed data signals (D0 ', D1') are sampled by a clock signal which is phase-locked to the reference signal (REF '),
• - the delayed data signals (D0 ', D1') are compared with the reference signal (REF ') by a phase comparator ( 15 a, 15 b),
• - The result of the respective phase comparison ( 15 a, 15 b) adjusts the respective delay element ( 13 a, 13 b) in such a way that delayed data signals that lead the reference signal are delayed more strongly and lagging data signals less.

2. The method according to claim 1, wherein an incoming reference signal (REF) to the reused, delayed reference signal (REF ') is delayed by an adjustable delay element ( 11 ) and its delay is increased when one of the delay elements ( 13 a , 13 b) for the data signals indicates that one of the lowest possible delays is set. 3. The method according to claim 2, wherein the change of Delay either the reference signal or each Data signal to avoid control oscillations is steamed. 4. The method according to claim 1, 2 or 3, wherein a Ver The set delays only change during  a synchronizer determined by the reference signal sationsphase takes place. 5. The method of claim 4, wherein during a syn chronization phase the data signals predetermined Pe go through gel changes. 6. The method according to any one of the preceding claims, whereby both data phases and Synchronisati transmitted onsphasen in frames of predetermined length the beginning of which is indicated by the reference signal shows is between the length of the reference signal data phase and synchronization phase under will be divorced. 7. The method according to claim 1 or 2, wherein by the Zu meeting a change in level of the reference signal with a change in level of a data signal change in the delay of the data signal accordingly release the comparison result of the phase comparator will give. 8. The method according to any one of the preceding claims, an adjustment of the delay elements, at for example through a random walk filter, only then occurs when an adjustment is made several times in succession in the same direction. 9. Arrangement for a phase correction of at least two simultaneously transmitted digital data signals (D0, D1) with respect to a simultaneously transmitted reference signal (REF ') with the following features:

• - The data signals (D0, D1) are each connected to an adjustable delay element ( 13 a, 13 b),
• - The outputs of the adjustable delay elements ( 13 a, 13 b) are each connected to a phase comparator ( 15 a, 15 b), the other reference input of which is connected to the reference signal (REF '),
• the output of each phase comparator ( 15 a, 15 b) is connected to an adjustment input of the respective adjustable delay element directly or via damping means,
• - An enable signal releases the adjustment inputs of the delay elements, provided that there was both a level change on the reference signal and a level change on the data signal.

10. The arrangement of claim 9, wherein

• - A delay element ( 11 ) for the reference signal (REF) generates a delayed reference signal (REF '),
• - Each of the delay elements ( 13 a, 13 b) for the data signals comprises a zero output ("= 0"), which indicates that the delay is set to a minimum,
• each of these outputs ("= 0") is connected to an OR circuit, the output of which indicates that at least one of the delay elements is set to a minimum,
• - The output of the OR circuit directly or via damping means with the adjustment input ("±") of the delay element for the reference signal is the verbun.