WO1998044674A1

WO1998044674A1 - Fast parallel signal phase adjustment

Info

Publication number: WO1998044674A1
Application number: PCT/DE1998/000358
Authority: WO
Inventors: Jürgen STALLMANN; Lorenz Unruhe
Original assignee: Siemens Nixdorf Informationssysteme Ag
Priority date: 1997-04-02
Filing date: 1998-02-09
Publication date: 1998-10-08
Also published as: DE19713660A1

Abstract

According to the invention, when fast signals are transmitted via several data lines, delay elements are used at least for data signals. A known edge of the data signal is checked against a nominally simultaneous edge of a reference signal by means of a phase comparator, and the delay elements are adjusted according to the results of the comparison.

Description

Phase adjustment of fast parallel signals

The invention relates to an operating method including a circuit for the parallel, synchronous transmission of very fast signal bundles, preferably in digital computing systems.

State of the art

In data processing systems, several data signals are often transmitted simultaneously from one data source to one data sink, ie on electrically parallel lines. As is known, the greater the number of lines, the greater the amount of information that can be transmitted at a given clock rate, so that this technology is used with a large number of 32 or more lines in the circuits of high-performance central processing units.

Particularly at clock rates of 100 MHz or above, however, it turns out that the transit times of the signals on the different lines differ. At a clock rate of 100 MHz, two successive clock edges are 10 ns apart, so that a phase accuracy of at least 1 ns is necessary. This time corresponds to a line length of 15 cm, because in lines the speed of the electrical waves is approximately half the speed of light. When connecting electrical circuits in a high-performance system with these and higher frequencies, it cannot be avoided that differences in transit time lead to the fact that signals transmitted in parallel with differing transit times arrive at the receiver the signals can no longer be reliably received.

Furthermore, since the lines at the receivers are no longer accessible to measuring devices attached from the outside, it is not possible to manually adjust the transit times in any way. It was also observed that the runtimes also change during operation, e.g. by warming, shift.

US Pat. No. 5,513,377 specifies an arrangement in which eight data lines and one clock line unidirectionally represent a connection. Runtimes on the data lines are individually compensated for, as shown in FIG. 4, by using a tapped delay element to which a large number of devices are connected, which are used to detect and evaluate the edges of the data signals.

US Pat. No. 5,487,095 specifies a circuit by means of which a data signal can be brought into phase with a clock. With this circuit, a number of differently delayed versions of the input signal is evaluated for the purpose of detecting the edges and selecting a suitable version of the delayed versions of the input signal which are present in parallel. A tapped delay device is also necessary here.

It is an object of the invention to provide an alternative, less complex operating method and an arrangement suitable therefor in such a way that the transit times are automatically corrected on the data lines. In particular, the solution should be independent of the type of digitally adjustable delay line. nar-πt-.pl liing the Frfindπng

The invention is based on the consideration that the running times change very slowly in relation to the cycle times. It therefore uses adjustable delay elements which are only adjusted when a predetermined edge of a reference signal is nominally present at the same time as an edge of the respective data signal. The necessary delay elements come with one data input and one output as well as one control input, that is to say with a very small number of lines, and can be implemented using various techniques, as is described in more detail in the description.

In a first, preferred embodiment, a plurality of parallel data lines and an additional control line are used. The control line transmits a signal which, on the one hand, is used to reconstruct the reception clock via a phase-corrected oscillator. It is also used to identify blocks of data, ie several sets of data that are consecutive and belong together. It is assumed that the data blocks to be transmitted are divided into a number of data words, the number of data lines being equal to the number of bits in a data word, and the data words belonging to a block being transmitted directly in succession, also referred to as synchronous become. In terms of transmission, this is also called a frame. The reference signal then indicates the beginning and, at the same time, the end of the previous data block or frame through the beginning of the next. If no user data is present, adjustment blocks of data are sent which have predetermined edge changes and which are then used to correct the transit times. The beginning of a frame is indicated by the rising edge. The choice of whether a data frame or synchronization frame is present is determined by the length of the Reference signal displayed. The falling edge of the reference signal is then the reference point for the runtime adjustment. The predetermined edge of the data signal is compared with the nominally simultaneous edge of the reference signal using phase comparators. The delay elements are adjusted according to the comparison result.

Further configurations, variants and embodiments can be found in the description below.

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1 is a schematic representation of a circuit for implementing the invention,

2 shows a schematic illustration of a delay element,

3 shows a signal diagram in the event that separate data and matching frames are transmitted,

4 shows a signal diagram in the event that comparison and data transmission take place simultaneously in one frame,

5 shows a variant for different edges of the data signal,

6 shows a further development of the variant according to FIG. 5,

Fig. 7 shows a variant for automatic detection of the matchable reference times. Rp.ςrhrpihnng an A sfi'ihrnngπfnrm of the invention

The invention is described using an example in which eight data bits are transmitted on two data lines with four clock cycles, that is to say using a frame of four clocks. In practice, far more data lines are used; for example, the content of a 64-byte cache line is transmitted with 32 data lines with a frame of IG clocks.

In addition to the data signals DO, D1, a reference signal REF is transmitted, from which the receiver obtains the clock 0, recognizes the start of a frame and contains a reference edge for the phase correction of the data lines.

A phase correction can only be carried out by delaying the edges of the signals arriving faster that they arrive simultaneously with the edges of the slowest signal. A number of solutions are available to the person skilled in the art for an adjustable delay of signals. A preferred embodiment is shown in FIG. 2a. A delay chain is formed by connecting an even number of inverters in series. The input signal is present on each (even) connection, delayed by a multiple of twice the transfer time of an inverter, and is tapped by a multiplexer in accordance with the delay to be set. Alternatively, a chain of cells can also be used, as shown in FIG. 2b as a circuit, which can be switched between a small and a larger delay if a relatively large minimum delay compared to the gain is advantageous due to the simple integration. It is also known to slow down the edge by means of a capacitance and to scan it by means of a threshold value switch, the threshold value of which is achieved by a simple digital-analog Converter is set. In all cases, it has proven useful to provide the delay elements internally with an up-down counter, which has a release input, a clock input and an input "+/-" for switching between up-counting and down-payment. In the following, for the sake of simplicity, it is always assumed that a counter reading zero means minimal delay, the counters are all set to zero by a reset signal and the counters remain in the extreme positions, ie do not count modularly.

In Fig. 1, the arrangement on the basis of which the invention is further described is shown schematically. The reference signal REF and the two data signals DO and D1 are delayed via delay elements 11, 13a and 13b and result in the ultimately phase-synchronous delayed signals REF ', DO' and Dl '. A clock signal 0 is obtained from the delayed reference signal RFF ', for example by a phase-controlled oscillator 17 (PLL), with which the delayed data signals DO', Dl 'are sampled. As mentioned, the "+/-" input increases or decreases the adjustable delay by one value with each cycle. Furthermore, the delay elements 13a, 13b each have an output marked with “-0”, which indicates that the delay is set to the smallest possible value. A higher-level control, not shown, enables the inputs "+/-" for the times of the adjustment and blocks them during the transmission of user data; the detection of these two operating states is described below. Since this control blocks the circuit against changes during the transmission of user data, the following description always relates to the operating state of the phase adjustment, unless stated otherwise.

After resetting the circuit at the start of operation, the delay times are all set to the minimum value. poses. The delay element 11 belonging to a further development is not effective, so that the signals REF and REF 'are the same. In a first control loop, the data signals DO 'and Dl' are now set to be in phase with the reference signal REF '. For this purpose, phase comparators 15a and 15b are provided, which are connected on the one hand to the reference signal REF 'and on the other hand to the respective delayed data signal DO ¹ , Dl'. In the simplest case, XOR gates are possible as phase comparators, the output of which is sampled by suitable clock signals. Preferably, the likewise known solution via a D flip-flop is used as the phase discriminator, to the clock input of which the reference signal REF 'and to the data input of which the delayed data signal DO', Dl 'is applied. In this case, the falling edge of the reference signal REF 'is used to take over the data, which likewise undergo a transition from H to L at this point in time. The output of the phase comparator 15a, 15b is connected to the input "+/-" of the respective delay element 13a, 13b, so that the following mode of operation results: If the phase discriminator delivers the signal H, the relevant falling edge of the reference signal is at the time REF 'the data signal DO', Dl 'is still high, ie the falling edge is still ahead. The signal is therefore too fast and has to be delayed, which is why the H level at the output of the phase comparator means that the delay value of the delay element is increased. If the output of the phase comparator 15a, 15b results in an L level, then the relevant falling edge of the reference signal REF 'lies before the falling edge of the data signal; this is therefore possibly too slow and is controlled via the input "+/-" of the respective delay element with L level and thus accelerated.

There is a constant oscillation of the values for the delay of the data signals because of the data signals be either delayed or accelerated with each comparison. This is irrelevant if the delays are appropriately resolved if these changes, as described, are blocked at the start of useful data transmissions. It can also be provided in the delay element that the last two bits of the binary representation of the delay time, as stored in an up-down counter, are not used at all for the delay and thus remain ineffective. Other means, such as random walk filters, are also possible.

Another option for fixed frames of e.g. 16 clocks consists of providing an up-down counter, which counts up or down for each clock according to the output of a phase comparator and evaluates this result at the end of a frame with threshold values, so that, for example, only when the count is below four or above the delay element is adjusted by eleven. This dampens the edge grid of the phase comparator.

The arrangement described so far presupposes that other measures, for example a fixed delay for the signal REF ', ensure that the reference signal REF' is always slower than the data signals. A further improvement can be achieved if, as shown in FIG. 1, the delay of the reference signal is also dynamically adjusted. The outputs "= 0" of the delay elements for the data signals, which are evaluated by a non-and element 19, serve for this purpose. Its output goes to the H level as soon as one of the delay elements 13a, 13b is set to minimum delay for the data signals. Via an integrator 21, the effect of which will be explained in more detail, this signal is applied to the input “+/-” of the delay element 11 for the reference signal. This causes that if at least one data signal is minimally delayed, the delay for the reference signal is reduced. The output "= 0" of a delay element 13a, 13b for a data signal DO, Dl is therefore regarded as an indicator that this could be accelerated even further. Since this is not possible, the reference signal must instead be accelerated and, as a result, all data signals must be delayed until all data signals are operated in the control range of their delay elements. The output "= 0" can also be set before the minimum delay is reached, for example at about 10%. In particular, the measures against control vibrations described below are accelerated.

Since this development involves two coupled control loops, measures are necessary to avoid control vibrations. If a control delay is already included in the control loops for the delay of the data signals, for example by means of the counter listed above and thus only one adjustment per frame, the output signal of the non-AND element 19, which is not provided with edge gratings, can be sent directly to the control input of the delay element 11 for the reference signal, so that the delay element 21 shown in FIG. 1 is not necessary.

Otherwise, if the outputs of the phase comparators for the data signals take effect without delay, the simplest measure is an integrator 21, which slows down the control loop for the reference signal REF '. The integrator can be created in analog technology by a threshold switch with hysteresis. Solutions in digital technology such as random walk filters are also possible, for example using an open-A counter, the counter reading of which is compared with 1/3 or 2/3 of the total range, depending on the output, and thus a hysteresis of 1 / 3 of the range causes. Another variant consists in a shift register, the outputs of which must all be at H level or L level in order to switch a subsequent RS flip-flop. Preferably, a higher-level control, not shown, adds up a predetermined number, for example 16 cycles, of the output of the non-and element 19 by a previously reset counter and finally generates the integrated signal by means of a threshold value comparison, the threshold value comparison preferably using half the range of the most significant bit of a binary counter. Other measures known to the person skilled in control technology which bring about the stability of the two nested control loops can also be used.

A signal diagram is shown in FIG. 3. In this case, four useful data words are first transmitted in one frame during the time marked with DATA, which is followed by an equally long time for the phase adjustment in this example. The reference signal REF indicates the beginning of a new frame with its rising edge. This impulse lies in the transmission of data for one clock cycle on H and for the remaining clock cycles on L.

If no user data is available, but this frame is to be used for synchronization, then the reference signal REF is at H level for at least the first two clock cycles and then for the remaining clock cycles of a frame at L level, so that the H level in second bar can serve to release the methods described above. The levels on the data lines are preferably equal to the level of the reference signal, so that in the example all signal lines show an HL transition, which is regulated by the described methods and circuits for synchronism in the receiver. Of course, several data phases can follow one another directly, as can several synchronization phases. It it is clear that those frames for which no data are available for transmission are preferably used for the synchronization phase. Of course, a short reference signal can also be used for the synchronization phases and a long one for the data phases. In this case it is readily possible to always use two clock cycles for the synchronization and several clock cycles for one data frame, so that the dead time caused by the synchronization times is low.

For cases in which a continuous data stream must be secured and therefore no adjustment frames can be inserted, the first two clock cycles can also be used for synchronization, as indicated in FIG. 4, in that the reference as well as the data signals in the first clock cycle are high - Level and in the second cycle to L level and then serve the following clocks for the transmission of user data.

Another variant is to always use the clock with reference signal at H level for synchronization and only the subsequent clocks for user data transmission. For this purpose, in the cycle in which the reference signal has an H level, the data word to be subsequently transmitted in the cycle is placed inverted on the data lines. As shown in FIG. 5, the output of the phase comparator 15a is inverted when the data signal is at the H level after the phase comparison and there was therefore a rising edge. Instead of the inversion shown by an XOR gate, it is of course also possible to use a phase comparison circuit 15a with a complementary output, which is selected by the current data signal.

Another development according to FIG. 6 permits the continuous transmission of user data without frames being required for the phase adjustment, provided that it is often sufficient to change the level of the data from the first to the second clock of a frame identified by the signal REF. A D flip-flop 61 is used for this purpose, the output of which has the data level of the preceding clock. A negated XOR 62 links the current level and the previous level, thereby indicating that a level change has taken place. This results in a release of the result of the phase comparator 15a, symbolized by the switch 64, which thereby activates the input +/- of the delay element. As before, a selection must be made according to the current level, as symbolized by the XOR element 51. Furthermore, not shown in FIG. 6, the entire process is enabled by the reference signal, because only then is there a defined level change in the comparison signal REF.

A further development of the invention shown in FIG. 7 wins the release signal for the change in the delay element itself. In this case, the reference signal of the previous clock is stored by the D flip-flop 71. A combinatorial logic 63 is then supplied with both the reference and data signal of the current clock, the reference and data signal of the previous clock and the result of the phase comparator 15a. The combinatorial logic 73 then supplies an output signal X according to the following table:

REF * REF DO * DO X

H L H L V

HLLH / v The output signal X is capable of three values, namely a neutral one, which does not change the delay element 13a and is accepted in all cases not listed in the table, a positive and a negative one, in which the delay is increased or decreased. The table states that when the reference signal changes from H to L and the data signal changes from H to L, the result of the phase comparator 15a is used as a positive or negative output and, in the same situation, for the reference signal and a change from L to H of the data signal, the result of the phase comparator is used inverted.

Claims

claims

1. Operating method for a phase correction of at least two simultaneously transmitted digital data signals (DO, Dl) by means of a likewise transmitted reference signal (REF) with the following features:

- The data signals (DO, Dl) are delayed by an adjustable delay element (13a, 13b) to delayed data signals (DO ', Dl'),

the delayed data signals (DO ', Dl') are sampled by a clock signal which is phase-locked to the reference signal (REF),

- The delayed data signals (DO ', Dl') are compared by a phase comparator (15a, 15b) with the reference signal (REF) or a delayed reference signal (REF '),

- The result of the respective phase comparison (15a, 15b) adjusts the respective delay element (13a, 13b) in such a way that delayed data signals (DO ', Dl') leading in advance of the reference signal (REF, REF ') are delayed more strongly and lagging ones less.

2. The method according to claim 1, wherein the delayed reference signal (REF ¹ ) from the incoming reference signal (REF) is formed by an adjustable delay element (11) and the delay is reduced when one of the delay elements (13a, 13b) indicates for the data signals that one of the lowest possible delays is set.

3. The method of claim 2, wherein changing the delay of either the reference signal or each

Data signal is damped to avoid control vibrations.

4. The method according to claim 1, 2 or 3, wherein a change in the set delays takes place only during a synchronization phase determined by the reference signal.

5. The method of claim 4, wherein during a synchronization phase, the data signals go through predetermined level changes.

6. The method according to any one of the preceding claims, wherein both data phases and synchronization phases are transmitted in frames of a predetermined length, the beginning of which is indicated by the reference signal, and a distinction is made between the data phase and the synchronization phase by the length of the reference signal.

7. The method of claim 1 or 2, wherein the change in the delay of the data signal is released according to the comparison result of the phase comparator by the coincidence of a level change of the reference signal with a level change of a data signal.

8. The method according to any one of the preceding claims, wherein an adjustment of the delay elements, for example by a random alk filter, only takes place if an adjustment in the same direction is present several times in succession.

9. Arrangement for a phase correction of at least two simultaneously transmitted digital data signals (DO, Dl) with respect to a simultaneously transmitted reference signal (REF ') with the following features: - The data signals (DO, Dl) are each provided with an adjustable delay element (13a, 13b ) connected,

- The outputs of the adjustable delay elements (13a, 13b) are each compared with a phase rather (15a, 15b), whose other reference input is connected to the reference signal (REF '),

the output of each phase comparator (15a, 15b) is connected to an adjustment input of the respective adjustable delay element directly or via damping means,

- An enable signal releases the adjustment inputs of the delay elements, provided that there was both a level change on the reference signal and a level change on the data signal.

10. The arrangement of claim 9, wherein

- A delay element (11) for the reference signal

(REF) generates a delayed reference signal (REF '),

- each of the delay elements (13a, 13b) for the data signals comprises a zero output ("= 0") which indicates that the delay is set to a minimum, - each of these outputs ("= 0") with an OR circuit is connected, the output of which indicates that at least one of the delay elements is set to a minimum,

- The output of the OR circuit directly or via damping means with the adjustment input ("+/-") of the

Delay element for the reference signal is connected.