EP1721407A1

EP1721407A1 - Interface device and method for synchronizing data

Info

Publication number: EP1721407A1
Application number: EP05734842A
Authority: EP
Inventors: Jörn Angel; Georg Stäbner
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2004-03-01
Filing date: 2005-03-01
Publication date: 2006-11-15
Also published as: DE102004010562A1; DE102004010562B4; KR20060131876A; KR100817270B1; US20070064846A1; US7650523B2; WO2005086408A1; CN1926798B; CN1926798A

Abstract

The invention relates to an interface device (4) comprising a first register device (6) and a second register device (7) connected in parallel thereto, which are configured for accepting a data word (DW). The interface device (4) comprises a synchronizing means (52) to which a first and second clock signal (T1, T2) are fed and which is configured for outputting a selection signal derived from the first clock signal in order to select the first or second register device (6, 7) for storing a data word (DW) at the data input (41). In addition, the synchronizing means (52) is configured for outputting an actuating signal (MUX) derived from the selection signal and from the second clock signal to an actuating output (55). The actuating output (55) is coupled to a selecting means (8) via which the output of one of the two register devices (6, 7) can be connected to the data output (42) of the interface device. An additional register device can be foregone due to the comparison of the selection signal with the second clock signal (T2).

Description

description

Interface device and method for synchronizing data

The invention relates to an interface device for the synchronous transmission of a data word and a method for synchronizing a data word between two circuit blocks clocked at the same frequency.

In clocked systems, data often has to be exchanged between two different circuit blocks. The individual circuit blocks can, for example, exchange data, which are then further processed in the respective circuit blocks. The two circuit blocks are each clocked with a clock signal of the same frequency. In order to avoid data errors during the data exchange, the data exchange must take place synchronously, that is, the data to be exchanged must always be present at the circuit blocks at the correct times. , '

Due to the spatially offset arrangement of the circuit blocks, there may be runtime differences between the two clock signals of the circuit blocks. Lines of different lengths for the two clock signals also lead to differences in runtime. A time difference results in a phase difference between the clock signals of the two circuit blocks. In addition, an unknown phase difference between the two clock signals from one another is caused by a slight random variation, which is called "jitter", and also by various frequency processing measures. If the frequencies of the clock signal are the same, but from different come from different signal sources, so they usually have an unknown phase relationship to each other.

In the case of a data exchange, a circuit block outputs the data to be exchanged at its output during a clock cycle, for example on a rising edge of its clock signal. For example, the second circuit block reads the data present at its input on a rising clock edge of its clock signal and processes it further. Due to the phase difference of the two clock signals of the circuit blocks from one another, the data output is provided or the reading process at the data input takes place at different times in each case. It can therefore happen that a read cycle starts before the first circuit block has made the data to be transferred available at its data output. This results in data loss and thus an error in the data transmission between the blocks.

To avoid such a loss of data, synchronization circuits and, in particular, so-called FIFO buffers (FIFO = First In First Out) are connected between the individual circuit blocks. The buffer circuits used temporarily store the data to be transferred in flip-flop circuits and output them again if necessary. The data that are stored first in the buffer are also released as the first data.

FIG. 3 shows an example of a synchronous interface with a FIFO buffer. The synchronization circuit 3 is connected between the two circuit blocks 1 and 2. The circuit block 1 emits a data word at its output at each clock period of its clock signal. The data word comprises one or more dates and is stored in one of the three register banks 32 connected in parallel. The register banks 32 each comprise a plurality of flip-flop circuits connected in parallel, each of which stores a date of the data word. The control device 31 selects which of the three register banks 32 the data word of the circuit block 1 is stored in. The stored data word is read out via a multiplexer unit 33, which uses a control signal from the control unit 31 to send one of the three register banks 32 to the output of the Synchronization circuit 3 switches and thus feeds the data word to the second circuit block 2. The data word is delivered in the order in which it was also stored in the register banks 32.

After reading out a register bank and providing it to the second circuit block, the content of the register bank is deleted and this is released again for a new write operation. The synchronization of the reading and writing process takes place via the control device 31, to which the clock signals of the circuit block 1 and of the circuit block 2 are supplied.

If the data is written and read using two different clock signals of the same frequency, at least three memory locations must exist for each data item to be synchronized. 3 * n storage locations are therefore necessary for the synchronization of n data present in parallel, which result in a data word. Each of the register banks 32 shown thus contains n memory locations. The third register bank is required to ensure that large fluctuations in the phase relationship between the clock signal of the first circuit block and the clock signal of the two- th circuit blocks in the positive as well as in the negative direction. Especially in the case of circuit blocks whose data word to be synchronized comprises a great deal of parallel data, the need for a third storage location per data in the synchronization circuit leads to a large number of storage locations. This increases the space requirement and creates additional costs.

The object of the invention is to provide an interface device with reduced effort, which requires only two register banks for synchronization. Another object of the invention is to provide a method for synchronizing a data word between two circuit blocks clocked at the same frequency with simple means.

These objects are solved with the subject matter of claims 1 and 14. Advantageous refinements result from the subclaims.

According to the invention, an interface device for the synchronous transmission of a data word comprises a data input for the data word and a data output for the data word. A first register device and a second register device connected in parallel to the first are coupled with one input each to the data input and have a selection input and an output. The first and second register devices are designed to store a data word present on the input side and to deliver the data word to the output. The interface device further comprises a selection means which is connected to the output of the first register device and to the output of the second register device. The means is for coupling the output of the first or second register ter device with the data output depending on an actuating signal. The means thus forms a multiplexer unit. The interface device further comprises a first clock input for supplying a first clock signal and a second clock input for supplying a second clock signal. Ultimately, it contains a synchronization device which is coupled to the selection means with the first and the second clock input and with an actuating output. The synchronization device is designed to emit a selection signal derived from the first clock signal for a selection of the first or the second register device for storing a data word present at the data input. The device is preferably designed to emit a selection signal to the first and the second register device. Furthermore, the synchronization device is designed to emit the control signal to the control output, the control signal being derived from the selection signal and the second clock signal.

With the synchronization device and the selective activation of the first and second register devices, a third register device with additional storage locations is not required. A synchronization between the clock signals of the two circuit blocks is concentrated on the synchronization device instead of using the three register banks for this as before. This device only has to be designed once for the entire interface device. It ensures that the data to be exchanged between the circuit blocks is ready at the right time at the output of the interface device according to the invention without errors. In particular, the data word to be transmitted is present at the output of the interface device according to the invention at the point in time at which the circuit block is on Data word applied to its input is accepted and processed.

This is preferably done by temporally evaluating the selection signal with the second clock signal and deriving the control signal as a function thereof. The implementation effort of the invention is thereby less and less with a synchronous exchange of many parallel data in comparison to the conventional implementation with three register banks.

It is particularly advantageous if, in an advantageous embodiment, the first and the second register device comprise a clock signal input which forms the selection input. The first and the second register device are designed to deliver a data word present at their data input to an output of an edge of a clock signal derived from the selection signal. These register devices, which are known from the prior art, can thus continue to be used. The register devices contain several flip-flop circuits arranged in parallel for each individual date of the data word.

In order to increase data security, in a further development of the invention a first buffer circuit is connected between the data input of the interface device and the first and second register devices. This is designed to deliver a data word present at the data input of the interface device to the first and the second register device on a clock edge of the first clock signal. This is preferably the falling clock edge. This ensures that a valid data word is present at the data input of the first and second register devices when the first and second register devices are increasing Edge of the applied clock signal takes over the data word at its data input.

In another development of the invention, a second buffer device is connected between the selection means and the data output of the interface device. It is designed to deliver a data word output at the data output of the selection means to the output of the interface device on a falling clock edge of the second clock signal. This ensures that the data word synchronized with the second clock signal is securely present at the data output of the interface device on a rising clock edge of the second clock signal. In this way, the data word with this clock edge of the second clock signal can be transferred to the circuit block for further processing. Alternatively, the direction of the clock edges in the first or second buffer circuit can also be interchanged.

In a development of the invention, the synchronization device comprises a selection means or a selector, which is designed to generate the selection signal for selecting the respective other register device at each clock period of the first clock signal. The selection signal is formed in such a way that it alternately selects between the two register devices. The frequency of the selection signal corresponds to half the frequency of the first clock signal. The selection means or the selector preferably comprises a D-toggle flip-flop clocked with the first clock signal. The data output of the toggle flip-flop is coupled to a first input of a first logic gate and via an inverter to its first input of a second logic gate and to its data input. The feedback D-toggle flip-flop therefore acts as a frequency divider, which the fre- frequency of the first clock signal halved. Alternatively, any other circuit that generates a clock signal at half the frequency of the input clock can be used.

In an expedient development of the invention, a second input of the first and the second logic gate is coupled to the first clock input and the output of the first logic gate is connected to the selection input of the first register device in order to emit the selection signal. The output of the second logic gate is coupled to the selection input of the second register device. As a result of this logic interconnection, a clock signal with half the frequency of the first clock signal is present at the selection input of the first and the second register device. The signals applied to the selection inputs of the register devices are 90 ° out of phase with one another. In this way, a selection signal can be generated in a simple manner, which can also be used as a clock signal for the first and second register devices, which in each case read in a data word at the synchronization input of the synchronization device in alternating form.

In another development of the invention, the synchronization device comprises a scanning device clocked with the second clock signal. The scanning device is designed to detect a change in the selection signal and to deliver the actuating signal to the selection means. The control signal is switched so that it connects the output of the register device selected by the selection signal with the data output of the interface device. Such a design is particularly advantageous since the scanning device thus uses the selection signal to register the direction detected, which has saved the next data word to be synchronized.

As soon as a change is registered that indicates a new register device, the control signal is sent to the selection means. The synchronization device is designed such that the data output of the selected register device is switched to the data output of the synchronization device. This ensures that the register device is only switched to the output of the synchronization device when a valid data word is emitted by the register device.

In another advantageous embodiment, the scanning device for detecting a change comprises a first and at least a second flip-flop circuit. The selection signal can be fed to the data inputs of the first and the at least one second flip-flop circuit. A clock input of the first flip-flop circuit is connected to the second clock input and a clock input of the at least one second flip-flop circuit is connected to the second clock input via at least one first delay element. The delay element is designed for a time delay of the second clock signal. The formation with at least two flip-flop circuits, the clock signal inputs of which are connected to the second clock input, makes it possible to detect the time of a signal change in the selection signal. This provides information about the register device which contains the next data word to be output.

It is also expedient if the scanning device contains a third flip-flop circuit whose clock input is connected to the second clock input via a second delay element. is coupled. The data input of the third flip-flop circuit is connected to the data outputs of the first and the at least one second flip-flop circuit via at least one logic gate. The logic circuit is designed to evaluate the temporal detection of a change in the selection signal by the first and the at least one second flip-flop circuit. The data output of the third flip-flop circuit is preferably coupled to the control input of the selection means. The control signal of the synchronization device can thus be tapped at the data output of the third flip-flop circuit.

In addition to providing a first register device and a second register device for a data word output by the first circuit block, the method for synchronizing a data word comprises selecting one of the two register devices by means of a selection signal. The value of the selection signal is assigned to one of the register devices. Furthermore, a data word output by the first circuit block is transferred to the selected register device with a rising clock edge of a first clock signal. The selection signal is detected by evaluating the time behavior of the selection signal with a second clock signal. This detects which of the two register devices was selected to take over the data word output by the circuit block. After such a detection, the adopted data word is delivered to the second circuit block on a rising clock edge of the second clock signal. According to the invention, the synchronization is thus concentrated on detection of a level transition in the selection signal. This detection is carried out by evaluating the comparison of the selection signal with the second clock signal over time. Therefore, only two register devices are necessary for the synchronization, in which the data word to be synchronized is alternately adopted. As soon as it is ensured that the register device has taken over the data word present at the input of the interface device, this is output at the data output with the clock of the second clock signal.

In this context, it is advantageous if the selection signal is generated with a first and a second logic level. The first and the second logic level are inverted with each clock period of the first clock signal, one of the two register devices being assigned to each logic level. The selection signal is therefore a signal that inverts its level with each period of the first clock signal. In a preferred embodiment, the selection signal is generated from the first clock signal by halving the first clock signal. The logically high level is assigned to the first register device, the logically low level to the second register device. The selection signal can thus preferably be used directly for generating a clock signal for the register devices.

In an expedient embodiment, a phase offset of half a clock period of the first clock signal for the respective selection signals is provided at the clock input of the first and second register devices. These signals can preferably be generated by applying the selection signal and the first clock signal to a first logic gate and inverting the selection signal and applying the inverted selection signal and the first clock signal to a second logic gate. In another preferred embodiment, a third and a fourth clock signal with a pulse duty factor of 3: 1 are generated, the third clock signal having a phase shift of half a clock period from the fourth clock signal. The third clock signal is fed to the clock input of the first register device and the fourth clock signal to the clock signal of the second register device. With a rising clock edge at the clock input, the register devices thus take over a data word output by the first circuit block.

The selection signal is preferably detected by detecting a clock edge of the selection signal by means of a logical evaluation. The exact time detection takes place by delaying the second clock signal and then feeding the second delayed clock signal to a clock input of a flip-flop circuit. Depending on the delay, the data output of the flip-flop circuit is only switched when there is a level transition in the selection signal. The output signals of the data output of the flip-flop circuits are evaluated in the logic circuit and from this the time is determined at which the data word stored in the registration device can be transferred to the output of the synchronization device.

In the following, the invention is explained in detail on the basis of exemplary embodiments with the aid of the drawings. Show it:

FIG. 1 shows a first exemplary embodiment of the invention, FIG. 2 shows a detailed block diagram of an interface device,

FIG. 3 shows a known interface device,

Figure 4 is a timing diagram with selected signals within the interface device.

FIG. 1 shows a schematic block diagram with the interface device according to the invention. An interface is required when data is exchanged between different blocks, the circuit blocks being clocked with their own clock signal. The clock signal for the first circuit block as well as for the second circuit block have the same frequency, but their phase relationship to one another is different. It can also be changed by jitter or natural fluctuations. The interface device allows the synchronous exchange of data between the circuit blocks. The term synchronous here means the correct delivery of the data word present at the input of the interface device at its output when the second circuit block is ready to take it over. The "synchronous" exchange thus ensures that the correct data word to be exchanged is taken over by the second circuit block with a clock edge of the second clock signal.

For this purpose, an interface device 4 according to the invention is connected between the output 11 of a first circuit block 1 and the input 21 of a second circuit block 2. The interface device 4 contains a data input 41 for the data word to be transmitted, which is connected to the input 11 of the first circuit block, and a data output. gear 42 for the delivery of a data word, which is connected to the input 21 of the second circuit block 2. Furthermore, the interface device according to the invention comprises two clock inputs 43 and 44. A clock signal T1 is present at the first clock input 43, which is also the clock signal of the first circuit block 1. A second clock signal T2 is present at the second clock input 44 and is also used as a clock signal for the second circuit block 2. The two inputs are thus designed for clock signals of the first and second circuit blocks 1, 2.

The data input 41 is connected to a first register device 6 and a register device 7 connected in parallel thereto. The two register devices 6 and 7 temporarily store a data word DW applied to the data input 41 and each output this at their output. The storage and the delivery of the data word is done via a control input 61 or 71 for the register devices 6 or

7 controlled. The outputs of the register devices 6 and 7 are connected to a multiplexer unit 8. The unit

8 shows a switch which, depending on a control signal at its control input 81, connects one of its two inputs 82 and 83 to its output 84. The output 84 of the multiplexer unit 8 is connected to the data output 42 of the interface device 4.

The interface device 4 further comprises a synchronization means or a synchronization device 5. The synchronization means 5 has two inputs 51 and 52. The first input 51 is connected to the first clock input 43 and the second input 52 to the second clock input 44. The device 5 contains a selection or selection means or selector 56. The selection means 56 generates a selection signal from the clock signal at input 43. The selection signal is output as a selection signal either at the output 53 or 54. The selection means 56 selects the register device 6 or 7 via the signal, so that the selected register device buffers the next data word DW present at the data input 41.

For example, the selection means 56 generates a selection signal and outputs it at the data output 53. With the next rising clock edge of the first clock signal at clock input 43, the selection signal is output at output 53. The rising clock edge of the first clock signal also causes a data word DW output by circuit block 1 to be present at data input 41. The register device 6 is controlled by the selection signal at the output 53, so that it temporarily stores the data word DW present at the data input 41. With the next rising clock edge of the first clock signal at clock input 43, the selection means generates a selection signal at output 54, so that register device 7 is activated. Since a new data word is present at the data input 41 with this clock edge, this is now transferred to the register device 7.

At the same time, the selection or selection means 56 outputs the selection signal to a scanning device 57. The scanning device is connected to the second input 52 and thus to the second clock input 44 for the second clock signal. The scanning device 57 is designed such that it uses the selection signal to recognize in which register device 6 or 7 the data word DW present at the data input 41 is stored. This takes place, for example, in that a transition of a level from the selection signal takes place from a first level to a second level, the transition indicates the point in time for a transfer of the data word into the correspondingly selected register device. As soon as the scanning device 57 thus registers a transition, the adopted data word is output at the data output of the selected register device. From this point in time, the data word can therefore be passed on to the data output 42 of the interface device 4.

For this purpose, the scanning device 57 generates a control signal MUX at the control output 55 from the second clock signal at the second clock input 44 and the transition of the selection signal. The control output 55 is connected to the control input 81 of the data multiplexer 8. The multiplexer 8 thus switches depending on the control signal MUX at the input 81 at the point in time at which it is ensured that a valid data word is present at the corresponding input 82 or 83. The selection means 56 and the scanning device 57 register a phase shift of the two clock signals relative to one another in the positive as well as in the negative direction and the switching of the multiplexer unit 8 is controlled in such a way that the data words present at the data input 41 of the synchronization circuit 4 are clock and phase synchronized with the second clock signal are output at the second clock input 44 at the data output 42 of the interface device 4. As a result, data is exchanged synchronously with the clocks of the two circuit blocks 1 and 2.

A detailed embodiment of the interface device 4 is shown in FIG. 2. The same components have the same reference numerals. The interface device according to the invention shown in FIG. 4 is controlled with positive clock edges. A positive clock edge indicates a rising Clock edge, a negative clock edge is equivalent to a falling clock edge.

The interface device shown in FIG. 2 is designed for the synchronous exchange of a data word from a plurality of parallel data between two circuit blocks. In the present example, six parallel data form a data word. However, the interface device shown here can also be used to synchronize data words with significantly more parallel data. To do this, simply increase the number of parallel flip-flop circuits in the individual components of the data path marked by a thick line.

The data input 41 for the data word DW is connected to an input D of a buffer circuit 9 comprising a plurality of flip-flop circuits connected in parallel. The outputs of the flip-flop circuits connected in parallel form the output Q of the data buffer 9 and are each connected to the input D of the register devices 6 and 7. The register devices 6 and 7, which are also referred to as register banks 6 and 7, also comprise a plurality of flip-flop circuits connected in parallel. A flip-flop circuit is provided for storing a date of the data word. The outputs Q of the register devices 6 and 7 are connected to the inputs 82 and 83 by a multiplexer unit.

The output 84 of the multiplexer unit 8 is in turn connected to a data input D of a second buffer circuit 9A. The buffer circuit 9A, like the buffer circuit 9, comprises the same number of flip-flops connected in parallel which transmit their data to the data outputs at their respective outputs Q. deliver gear 42. The input buffer 9 as well as the output buffer 9A are optional components of the interface device 4 according to the invention, which enable additional security in the provision of the data. A write or read error in the register devices is prevented by the two buffer circuits.

The clock signal input of the buffer circuit 9 is connected via an inverter 561 to the first clock input 43 for the first clock signal T1. In the event of a falling or negative clock edge of the first clock signal T1, the buffer circuit 9 reads a data word present at the input 41 and outputs it to its data output Q again.

The clock signal T1 inverted with the inverter 561 is also fed to a clock signal input of a D-toggle flip-flop 60. The data input D of the D-toggle flip-flop 60 is connected to the data output Q of the D-toggle flip-flop 60 via an inverter 601. The output of the D toggle flip-flop 60 is fed back to its input and thus inverts its output Q on each falling clock edge of the first clock signal T1. It therefore also acts as a frequency divider. The signal emitted at its output is the selection signal SEL for the selection of the register device 6 or 7, which next takes over a data word.

The output Q of the D toggle flip-flop 60 ^' is also connected to a first input of a logic AND gate 607, the second input of which is connected to the first clock input 43. The data input of the D toggle flip-flop 60, which is connected to the output of the inverter 601, is also connected to a first input of a second logic AND gate 606. The second input of the logi- see AND gate 606 is connected to the first clock input 43. The outputs of the logical AND gates 606 and 607 lead to an inverter 605 and 604, respectively. The output of the inverter 605 forms the output 53 for the selection signal R0. The output of the inverter 604 forms the output 54 for the signal R1 and is connected to the clock signal input of the register device 7. The selection signal R0 as well as the selection signal Rl thus form a clock signal for the register devices 6 and 7. In the event of a rising or positive clock edge of the respective output signals R0 or Rl, these take over a data word DW applied to their data input D into their buffer and give this at the Q output. The clock inputs of the two register devices 6 and 7 thus represent the two selection inputs 61 and 71 according to FIG. 1. The flip-flop 60 and the logic gates 606 and 607 form the selection or selection means 56.

The logic gates 606 and 607 generate the selection signals R0 and Rl from the selection signal SEL and the first clock signal Tl, each of which has a pulse duty factor of 1: 3. The clock period of the two signals R0 and Rl is twice as large as the clock period of the first clock signal Tl. In addition, the two signals R0 and Rl are out of phase with each other by half a period of their clock. As a result, the first register device 6 takes over the data word present at its data input on a rising clock edge of the first clock signal T1 and outputs it at the output Q. On the next rising clock edge of the first clock signal T1, the second register device 7 takes over the data word DW present at its data input D. Thus, the data word present at the input is always taken over alternately by the register device 6 or 7 at each clock period and passed on to its respective output. The information in which of the two register devices 6 and 7 the data word is next transferred is important for the synchronous data exchange. For this purpose, the flip-flop circuit 61 is used. Data input is connected to the data output Q of the toggle flip-flop 60. The clock input of the flip-flop 61 is connected to the first clock input. With each rising clock edge of the first clock signal T1, the information in which of the two register devices 6 and 7 are currently present is passed on to the output Q of the flip-flop circuit 61 in the form of the selection signal SEL ^λ . The flip-flop circuit 61 simultaneously forms the interface which logically combines the first clock signal T1 and the second clock signal T2> in order to ensure error-free data exchange.

The selection switch 8 is now to be switched so that it connects the register device, to which new data are present, to the buffer circuit 9A. In the exemplary embodiment shown, it is provided that this takes place with the rising edge of the output clock T2, so that the data present at the data input D of the buffer circuit 9A are transferred to the buffer circuit 9A in synchronism with the falling output edge of the second clock signal and at the data output 42 of the interface device 4 can be delivered.

For this purpose, the output Q of the flip-flop circuit 61 is connected to a respective data input of a first, second and third sampling flip-flop 63, 64, 65. The clock signal input of the first sampling flip-flop 63 is connected to the second clock input 44 of the interface device according to the invention. The clock signal input of the second sampling flip-flop 64 is via a delay element 71 with the second clock input connected. The clock input for the third sampling flip-flop 65 is in turn coupled to the second clock input 44 via the delay element 72 and the delay element 71. The second clock signal T2 is delayed by the two delay elements 71 and 72 and reaches the clock inputs of the scanning flip-flops 63, 64 and 65 at different times. A sampling of the selection signal SEL ^λ , which is output from the output Q of the flip-flop 61 is delivered is carried out at three different times. If there is a transition in the selection signal SEL from a high level to a low level or vice versa during this period, this is registered by at least one of the three scanning flip-flops 63, 64 and 65.

For example, the register device 6 is switched to the register device 7 by the selection signal SEL. As a result, with a rising clock edge of the first clock signal T1, the data word DW present at the data input 41 is taken over into the register bank 7 and at the same time a positive edge of the selection signal SEL is generated at the output Q of the flip-flop 61. The positive edge at the output of the flip-flop 61 takes place, for example, at a point in time which is slightly later than the rising clock edge of the second clock signal T2. As a result, the first sampling flip-flop 63 registers a low level of the selection signal SEL 'at its data input on the rising clock edge of the second clock signal T2 and outputs it inverted at its output QN.

The rising clock edge of the second clock signal T2 is delayed by the delay element 71. If the selection signal SEL changes to the other level during this delay time, this is done by the scanning flip-flop 64 and also by the Tast flip-flop 65 registered and a correspondingly inverted signal emitted at their outputs QN. This indicates that the register device 7 now contains the next data word and that its output is to be coupled to the output 42 of the interface device 4.

Switching the register banks from bank 6 to bank 7 is characterized by a positive edge in the selection signal SEL or SEL ^X , while switching the register device from device 7 to device 6 is represented by the corresponding negative edge. The sampling flip-flops 63, 64 and 65 detect this transition in the selection signal at different times due to the delay elements connected to their clock inputs. The logic levels 0-0-1 and 0-1-1 for the inverting outputs QN of the scanning flip-flops 63, 64 and 65 identify a negative clock edge of the selection signal SEL and thus a transition of the registration device from 7 to 6. The order 1-0-0 and 1-1-0 of the output levels indicate a positive transition of the selection signal SEL 'and thus a transition of the register device from 6 to 7.

The output of the first sampling flip-flop 63 is connected to an inverter 81 and to a first input of a NAND gate 82. The inverting output QN of the scan flip-flop 64 is connected to a second input of the gate 82. The inverted output QN of the flip-flop 65 is connected to an inverter 83 and to a third input of the NAND gate 82. The outputs of the inverters 81 and 83 are connected to the inputs of a NAND gate 84. The output of the NAND gate 82 is connected to the first input of a NAND gate 85. The outputs of the two NAND gates 84 and 85 are one another NAND gate 86 connected. Its output is connected to a data input of a selection flip-flop circuit 90.

The clock input of the selection flip-flop circuit 90 is connected to the second delay element 72 via a further delay element 73. The inverted output QN of the selection flip-flop 90 is fed back to the second input of the logic NAND gate 85. In addition, it is connected to the control input 81 of the selection means 8 via an inverter 91, which forms the output 55 for the control signal MUX. The complete logic circuit comprising the logic gates 81 to 86 and the selection flip-flop 90 generates the actuating signal MUX from the information data output by the scanning flip-flops.

The control signal MUX switches the selection switch 8 to the input at which the next data word to be output at the data output 42 is present. The toggle flip-flop 90, which is driven by a positive clock edge of the second clock signal T2 delayed by the delay devices 71, 72 and 73, thus outputs an actuating signal MUX to the control input 81 of the selection means 8. The data output by the register device 6 or 7 is safely accepted by the buffer circuit 9A with the next falling clock edge of the second clock signal T2 and output to the data output 42.

The delay element 73 is sufficiently large in the time delay of the second clock signal. The logic circuit from the gates 81 to 86 is already completely switched before the rising clock edge of the clock signal T2 switches the output QN of the toggle flip-flop 90. Sufficient time remains until the falling clock edge of the second clock signal T2, which applies the data word output by the multiplexer 8 to the output 42 of the interface device 4. The selection flip-flop 90, the inverter 91 and the selection means have then already switched over. The delays required thereby determine the maximum sampling frequency of the first and the second clock signal.

FIG. 3 shows a time course of various signals. The first curve shows the first clock signal T1 with a specific frequency. After a first clock period ΔT1, the selection signal SEL switches from the logic low level 0 to the logic high level 1. After a further clock period ΔT2, the selection signal SEL is inverted again by the toggle flip-flop 60. As can be seen, the toggle flip-flop acts as a frequency divider for the first clock signal T1. The selection signal SEL is fed to the logic gates 606 and 607 together with the first clock signal.

The output signals Rl and R0 result from the logical combination and the inversion connected to it through inverters 605 and 604, respectively. The clock ratio of 1: 3 can be clearly seen, the logically high level for the respective selection signal Rl or R0 being only half a clock period of the first clock signal T1. Furthermore, the two signals Rl and R0 are out of phase with each other by half a period of their clock period. The respective rising edge of the signal Rl or R0 always occurs at the time of a rising edge of the first clock signal.

With each rising clock edge of the signal R1, the register device 7 takes over a data word DW present at the input. The same applies to the register device 6. This too takes over with every rising clock edge of its clock signal R0 a data word present at the input. Thus, a data word present at the data input is transferred to the respective register device alternately with each rising clock edge of the first clock signal T1.

At time Tx, the selection signal SEL produces a transition from a logic low to a logic high level, which indicates that the data word present at the input is to be transferred to the register device 7 on the next rising clock edge of the first clock signal T1.

The selection signal SEL is only accepted by the flip-flop 61 with the subsequent rising clock edge of the clock signal T1 and is output as a selection signal SEL 'at its output Q. It is therefore out of phase with the selection signal SEL generated by the D toggle flip-flop 60 by half a period. The selection signal SEL 'has a rising edge at the time of a rising edge of the signal Rl, a falling edge at a rising edge of the signal R0. At the point in time when the register device 7 takes over a data word, the selection signal SEL 'is present at the respective data inputs of the scanning flip-flops 63 to 65 with a logic high level. This is also assigned to the register device 7.

The output clock, given by the second clock signal T2, is 90 ° out of phase with the first clock signal T1. At time Tz, at which the selection signal SEL 'has not yet changed, a rising edge occurs in the second clock signal T2. The scanning flip-flop 63 thus does not yet register a level change in the selection signal SEL '. However, the rising clock edge of the second clock signal T2 is delayed and reached by the delay elements 71 and 72, respectively at later times to the respective clock inputs. The scan flip-flops register a level change, which they emit at their outputs. The new logic levels 1-0-0 at the inputs of the logic gates 81, 82 and 83 are processed by them and a signal with a logic high level is generated therefrom which is fed to the selection flip-flop 90 at its data input D. After a further delay by the delay unit 73, the rising edge of the clock signal T2 reaches the clock input of the flip-flop 90 and generates a logic low level at its inverted output. The selection flip-flop 90 thus evaluates the information into which register bank has just been written as well as the previous position of the multiplexer 8. The first information results from the selection signal SEL ', the second from the output of the selection flip-flop 90 itself. The output level of the selection flip-flop 90 is only changed when the selection signal SEL' changes.

In this exemplary embodiment, the register device 7 switches the data word present at its data input D to its output Q at approximately the same time due to a rising clock edge in the signal R1. It is therefore present at the output 83 of the multiplexer unit 8. The control signal MUX output by the flip-flop 90 and inverted by the inverter 91 is applied to the control input 81 of the switching device 8. The switching device 8 then switches the input 83 to its output and thus feeds the data word output by the register device 7 to the input D of the output buffer circuit 9A. On the next falling clock edge of the clock signal T2, the data word is output by the output buffer circuit 9A to the data output 42 of the interface device 4. At time Ty, the selection signal SEL 'changes to the logic low level and thus indicates that the register device 6 has taken over the next data word. On the next rising clock edge of the second clock signal T2, this change in the selection signal SEL 'is registered again, whereupon the selection flip-flop 90 generates an actuating signal for switching the selection switch 8.

The basis of the invention is thus two register devices which are alternately written with data, always reading from the respective other register device. Thereby. ensures that the data is not incorrect. The synchronization between the two circuit blocks or between the two clock signals with the same frequency but different phase takes place at the point which defines a selection for reading out the register devices. This is the flip-flop 61, which indicates the register device on which new data are already present. The synchronization is carried out by comparing the change in level of the selection signal with the second clock signal over time. The reading can therefore be carried out with a new edge of the second clock signal T2, which switches the selection switch 8 to the corresponding register bank. With the subsequent falling clock edge of the second clock signal, the data are transferred to the output buffer 9. Additional flip-flop circuits for the register devices in a conventional synchronization circuit can therefore be dispensed with.

The embodiment shown here is implemented with flip-flop circuits controlled by positive clock edges. Of course, the invention is not so limited. she can can also be implemented with flip-flops controlled by negative clock edges. Instead of the scan flip-flops, another comparison logic is conceivable, which creates a temporal relationship between the first and second clock signals. Inverting outputs QN of the scanning flip-flops can be dispensed with if the downstream logic is suitably designed. The logic that links the selection signal SEL 'with the signal MUX can also be implemented in any other form. The logic inverts the signal MUX, which switches the selection means, whenever a level change in the signal SEL 'has taken place. The logic gates can be implemented not only as AND gates, but also as NAND gates with inverters. The entire circuit can be implemented in both CMOS logic and pure MOS logic.

Reference character list

1, 2: circuit blocks

3: synchronization circuit

4: Interface device

6, 7, 32: register devices

5: synchronization means

8, 33: Selection switch

43, 44: clock signal inputs

41: Data input

42: Data output

9, 9a: buffer circuits

8: Selection switch

82, 83: data inputs

81: Control input

55: control output

56: Selection means

57: scanner

53, 54: selection output

601, 604, 605, 81, 83, 91, 561. : Inverter

606, 607, 82, 84, 85, 86: non-AND gate

63, 64, 65: scan flip-flops

71, 72, 73: delay element

61: flip-flop

62: Toggle flip-flop

T1, T2: clock signals

SEL, SEL ': selection signals

Rl, R2: selection signal, clock signal

Claims

claims

An interface device (4) for the synchronous exchange of a data word between two circuit blocks (1, 2), comprising:

- A data input (41) for a data word (DW) and a data output (42) for the data word (DW);

- A first register device (6) and a second register device (7) connected in parallel, each with an input coupled to the data input (42), a selection input (61, 71) and an output, which are used for storing a data word on the input side and for output of the data word are formed at the respective output;

a selection means (8) which is connected to the output of the first register device (6) and to the output of the second register device (7) and for coupling the output of the first or the second register device (6, 7) to the data output ( 42) is designed as a function of a control signal (MUX);

- a first clock input (43) for supplying a first clock signal (Tl);

- a second clock input (44) for supplying a second clock signal (T2);

- A synchronization means (52), which is coupled to the first and the second clock input (43, 44), which comprises a control output (55) coupled to the selection means (8), which output for the one derived from the first clock signal (Tl) Selection signal (SEL) for a selection of the first or the second register device (6, 7) for storing a data word (DW) present at the data input (41) and which is derived for outputting the control signal (MUX) to the control output (55) out the selection signal (SEL) and the second clock signal (T2) is formed.

2. Interface device (4) according to claim 1, characterized in that the first and the second register device (6, 7) each comprise a clock signal input, which in each case the selection input (61, 71) for the first and the second register device (6, 7 ) and the first and second register devices (6, 7) are designed to emit a data word present at their data input (D) on an edge of a clock signal (R0, Rl) derived from the selection signal (SEL) at their output.

3. Interface device (4) according to one of claims 1 to 2, characterized by a first buffer circuit (9), which is connected between the data input (41) of the interface device (4) and the first and second register device (6, 7), which is for delivery a data word (DW) present at the data input (41) of the interface device (4) is formed on the first and second register devices (6, 7) on a clock edge of the first clock signal (Tl).

4. Interface device (4) according to one of claims 1 to 3, characterized by a second buffer circuit (9A), which is connected between the selection means (8) and data output (42) of the interface device (4) and for delivering one to the selection means (8) data word applied to the data output (42) is formed on a clock edge of the second clock signal (T2).

5. Interface device (4) according to one of claims 1 to 4, characterized in that the synchronization means (52) comprises a selection means (56) for generating the selection signal (SEL) for selecting the respective other register device (6, 7) each clock period of the first clock signal (Tl) is formed.

6. Interface device (4) according to one of claims 1 to 5, characterized in that the selection means (56) comprises a flip-flop circuit (60) clocked with the first clock signal (Tl), the data output (Q) of which is via an inverter (601) with a first input of a first logic gate (606), with a first input of a second logic gate (607) and via the inverter (601) with its data input (D).

7. Interface device (4) according to claim 6, characterized in that a respective second input of the first logic gate (606) and the second logic gate (607) are coupled to the first clock input (43) and the output of the first logic gate ( 606) are coupled to the selection input of the first register device (6) and the output of the second logic gate (607) to the selection input of the second register device (7).

8. Interface device (4) according to one of claims 6 to 7, characterized in that the first and second logic gates (606, 607) each comprise a logic AND gate.

9. Interface device (4) according to one of claims 1 to 8, characterized in that the synchronization means (52) comprises a scanning device (57) clocked with the second clock signal (T2), which for detecting a change in the selection signal (SEL) and is designed to emit the control signal (MUX) to the selection means (8).

10. Interface device (4) according to one of claims 1 to 9, characterized in that the selection means (8) has two ingestible states, the output of the first register device (6) with the data output (42) of the interface device (6) in a first state. 4) and in a second state the output of the second register device (7) is coupled to the data output (42) of the interface device (4).

11. Interface device (4) according to one of claims 1 to 10, characterized in that the scanning device (57) for detecting a change in the selection signal (SEL) comprises a first and at least a second flip-flop circuit (63, 64), whose data inputs (D) are designed to supply the selection signal (SEL), a clock input of the first flip-flop circuit (63) to the second clock input (44) and a clock input of the at least one second flip-flop circuit (64) via at least a first delay element (71) for time delay tion of the second clock signal (T2) are connected to the second clock input (44).

12. Interface device (4) - according to one of claims 1 to 11, characterized in that the scanning device. (57) comprises a third flip-flop circuit (90), the clock input of which is coupled to the second clock input (44) via a second delay element (72, 73), the data input (D) of which is connected to the data outputs via at least one logic gate the first and the at least one second flip-flop circuit (63, 6 ^' 4) are connected.

13. Interface device (4) according to one of claims 1 to 12, characterized in that the clock input of the third flip-flop circuit (90) via the second delay element (73, 72) and the at least one first delay element (71) to the second clock input is connected.

14. A method for synchronizing a data word between two circuit blocks (1, 2) clocked at the same frequency, comprising the steps:

- Providing a first register device (6) and a second register device (7) for storing a data word (DW) output by the first circuit block (1);

- Selection of one of the two register devices (6, 7) by a value of a selection signal (SEL) assigned to the respective register device;

- Accepting the data word (DW) output by the first circuit block (1) into the selected register device (6, 7) with a clock edge of a first clock signal (Tl); - Detecting the selected register device by evaluating the time behavior of the selection signal (SEL) with a second clock signal (T2);

- Dispensing the data word (DW) adopted in the selected register device (6, 7) to a second circuit block (2) after detection when a clock edge of the second clock signal (T2) occurs.

15. The method according to claim 14, characterized in that the step of selecting comprises the steps:

- generating the selection signal (SEL) with a first and a second logic level which is inverted with each clock period of the first clock signal (Tl), the first logic level of the first register device (6) and the second logic level of the second register device (7 ) is assigned.

16. The method according to claim 15, characterized in that the step of selecting comprises the steps:

- applying the selection signal (SEL) and the first clock signal (Tl) to a first logic gate (606);

Inverting the selection signal (SEL) and applying the inverted selection signal (SEL) and the first clock signal (Tl) to a second logic gate (607),

17. The method according to claim 14 to 16, characterized in that the step of taking over comprises the steps:

- Generating a third and a fourth clock signal (RO, Rl) with half the clock frequency of the first clock signal

(Tl), the third clock signal (R0) having a phase shift from half a clock period to the fourth clock signal (R1);

- Feeding the third and fourth clock signals (R0, Rl) to a clock input of each of the first and second register devices (6, 7), which on each clock edge of the third and fourth clock signals (R0, Rl) one of a first circuit block (1) Take over the given data word (DW).

18. The method according to claim 14 to 17, characterized in that detecting the selected register device comprises the steps:

- Delaying the second clock signal (T2) by a certain period of time;

- Detecting a level change in the selection signal with the second clock signal (T2) and the delayed second clock signal (T2);

- Determining the point in time at which the data word (DW) can be output by the selected register device (6, 7) to the second circuit block (2).

19. The method according to any one of claims 14 to 18, characterized in that the step of releasing comprises the steps:

- generating an actuating signal (MUX);

- Switching a switching device (8) with the control signal (MUX);

- Delivery of the data word (DW) to the second circuit block (2) when a clock edge of the second clock signal (T2) occurs.