WO2021063819A1 - Verfahren zur herstellung von optoelektronischen halbleiterchips und optoelektronischer halbleiterchip - Google Patents
Verfahren zur herstellung von optoelektronischen halbleiterchips und optoelektronischer halbleiterchip Download PDFInfo
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- WO2021063819A1 WO2021063819A1 PCT/EP2020/076869 EP2020076869W WO2021063819A1 WO 2021063819 A1 WO2021063819 A1 WO 2021063819A1 EP 2020076869 W EP2020076869 W EP 2020076869W WO 2021063819 A1 WO2021063819 A1 WO 2021063819A1
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- active zone
- barrier layers
- mixing
- semiconductor
- quantum well
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 140
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 76
- 238000000034 method Methods 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000000873 masking effect Effects 0.000 claims abstract description 25
- 230000005855 radiation Effects 0.000 claims abstract description 8
- 238000002156 mixing Methods 0.000 claims description 72
- 229910052782 aluminium Inorganic materials 0.000 claims description 41
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 38
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 9
- 229910052725 zinc Inorganic materials 0.000 claims description 9
- 239000011701 zinc Substances 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 2
- HQWPLXHWEZZGKY-UHFFFAOYSA-N diethylzinc Chemical compound CC[Zn]CC HQWPLXHWEZZGKY-UHFFFAOYSA-N 0.000 claims description 2
- AXAZMDOAUQTMOW-UHFFFAOYSA-N dimethylzinc Chemical compound C[Zn]C AXAZMDOAUQTMOW-UHFFFAOYSA-N 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 17
- 230000000875 corresponding effect Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- 238000005215 recombination Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- USZGMDQWECZTIQ-UHFFFAOYSA-N [Mg](C1C=CC=C1)C1C=CC=C1 Chemical compound [Mg](C1C=CC=C1)C1C=CC=C1 USZGMDQWECZTIQ-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/305—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table characterised by the doping materials
Definitions
- a method for producing optoelectronic semiconductor chips is specified.
- an optoelectronic semiconductor chip is specified.
- One problem to be solved is to specify a method for producing relatively small optoelectronic semiconductor chips with a high level of efficiency.
- the method is used to produce optoelectronic semiconductor chips.
- the finished semiconductor chips are in particular light-emitting diode chips, or LED chips for short.
- laser diode chips can be produced, for example surface-emitting laser diode chips or also edge-emitting laser diode chips.
- the optoelectronic semiconductor chips are detector chips, in particular photodiodes.
- the method comprises the step of growing a semiconductor layer sequence.
- the semiconductor layer sequence is grown on a growth substrate along a growth direction.
- the growth substrate is in particular a GaAs substrate.
- the semiconductor layer sequence is preferably based on a III-V compound semiconductor material.
- the semiconductor layer sequence is particularly preferably based on the phosphide material system AlInGaAsP.
- the semiconductor layer sequence comprises both Al and In, Ga and P.
- the semiconductor layer sequence can have dopants and additional components. For the sake of simplicity, however, only the essential components of the crystal lattice of the semiconductor layer sequence, that is to say Al, As, Ga, In or P, are given, even if these can be partially replaced and / or supplemented by small amounts of further substances.
- the semiconductor layer sequence can also be based on AlInGaN or AlInGaAs.
- AlInGaAsP or AlInGaP can apply accordingly to AlInGaN or AlInGaAs, in which case N or As is to be put in place of P.
- the semiconductor layer sequence comprises an active zone.
- the active zone is preferably set up for generating radiation, but can alternatively be designed for radiation detection.
- the active zone is in particular a multi-quantum well structure, or MQW for short.
- quantum well layers and barrier layers are alternately arranged.
- the active zone consists of the alternately arranged quantum well layers and barrier layers.
- the method comprises the step of producing a structured masking layer.
- the masking layer can be part of the semiconductor layer sequence and can therefore still be present in the finished semiconductor chips.
- the masking layer is a layer specially produced for this purpose, for example a soft mask such as a photoresist layer or a hard mask such as an oxide layer.
- the method comprises the step of mixing the quantum well layers and the barrier layers in regions.
- Mixing is carried out by applying a mixing aid.
- the mixing aid in particular zinc, is introduced into the active zone through openings in the masking layer, so that the mixing aid is located in at least one mixing area.
- the mixing aid induces mixing of crystal components of the semiconductor layer sequence, in particular of Al, Ga and / or In.
- a temperature is preferably significantly above room temperature and also a later intended operating temperature of the finished semiconductor chips.
- Mixing can take place homogeneously over all quantum well layers. Alternatively, the mixing takes place inhomogeneously.
- the mixing region preferably extends completely through the active zone into an n-doped region. It is true that there is preferably one per active zoner or per side flank active zone there is only a single mixing area, but there can also be several mixing mixtures per active zone or per side flank, which can be interrupted by an unmixed area along the direction of growth.
- the method comprises the step of dividing the semiconductor layer sequence into subregions for the semiconductor chips.
- the separation takes place, for example, by means of etching, but can alternatively also take place by means of sawing or scoring and breaking.
- the barrier layers are grown from [(Al x Ga ] __ x ) yln ] __y] Z P ] _- Z.
- the method is used to produce optoelectronic semiconductor chips and comprises the following steps, particularly preferably in the order given:
- Comprises radiation generation and the active zone is composed of several alternating quantum well layers and barrier layers,
- a local diffusion of impurities and a subsequent mixing of quantum wells is a possible method to specifically improve the low current behavior of optoelectronic semiconductor chips. This applies in particular to light-emitting diode chips with small dimensions, also referred to as pLEDs, especially with an emission in the red spectral range. Sufficiently long diffusion times must be observed, in particular in a MOVPE reactor, in order to achieve a significant degree of intermixing on a wafer with densely packed pLEDs.
- the degree of intermixing is not only dependent on the diffusion time, but also on a packing factor of the pLEDs.
- the degree of mixing tends to decrease as the packing factor increases.
- the barrier layers have an aluminum content, expressed by the variable x in [(Al x Ga ] __ x ) yln ] __y] Z P ] __ Z , of approximately 50%.
- the reason for such a comparatively low aluminum content is that a threshold voltage usually rises with a higher aluminum content, especially in the case of active zones with several tens of barrier layers and quantum well layers.
- Zone usually limited to a maximum of 50.
- the masking layer is formed by a contact layer, in particular by a p-contact layer, of the semiconductor layer sequence.
- a separate masking layer is used, for example in the form of a correspondingly structured permanent passivation layer or in the form of a temporary layer, such as a photoresist layer.
- the contact layer specifically the p-contact layer, is completely penetrated by the openings in step B). This means that the contact layer is completely removed in places.
- the contact layer preferably comprises or consists of Al v Ga ] __ v As.
- v ⁇ 0.35 or v ⁇ 0.1 applies.
- v> 0, in particular v> 0.01 or v> 0.05 applies.
- the contact layer can also be formed from a combination of GaAs layers and such AlGaAs layers.
- the mixing in step C) takes place along the growth direction completely through the active zone. This means that the mixing area completely penetrates the active zone towards the growth substrate. Alternatively, the mixing area extends through the active zone, but does not extend, or only in places, to the growth substrate.
- the isolation in step D) takes place only in the at least one
- the quantum well layers in step A) are off
- an emission wavelength of maximum intensity of the active zone can be set via the aluminum content in the quantum well layers. It is possible that all quantum well layers are nominally grown in the same way, that is to say within the scope of the manufacturing tolerances with regard to their
- Material composition and also in terms of their thickness do not differ from one another.
- differently structured quantum well layers are grown so that, for example, a thickness profile or a profile in the aluminum content of the quantum well layers is achieved along the direction of growth in the active zone.
- Such quantum well layers with varying properties are also referred to as chirped MQW.
- 0.47 ⁇ yd 0.53 and 0.47 ⁇ z ⁇ 0.53 and / or 0.47 ⁇ bd 0.53 and 0.47 ⁇ cd 0.53 or also 0.48 ⁇ yd apply 0.52 and 0.48 ⁇ z ⁇ 0.52 and / or 0.48 ⁇ bd 0.52 and 0.48 ⁇ cd 0.52 for the quantum well layers made of [(Al a Ga ] __ a ) pln ⁇ -p ] C P ] __ C and for the barrier layers from [(Al x Ga ] __ x ) yln ] __y] Z P ] _- Z.
- c ⁇ 0.5 and z ⁇ 0.5 and / or b> 0.5 and y> 0.5 preferably apply.
- the active zone can be grown in a targeted manner in a tense manner, so that values for y, z and / or for b, c different from the above-mentioned areas are specifically used.
- step C) includes a temperature treatment of the semiconductor layer sequence.
- an elevated temperature is present for a period of at least 0.2 hours or 0.5 hours and / or at most 10 hours or 2 hours.
- the elevated temperature is, for example, at least 400 ° C or 500 ° C and / or at most 700 ° C or 600 ° C. In particular, this temperature is between 500 ° C and 540 ° C inclusive.
- the active zone is located between a first semiconductor region and a second semiconductor region.
- the first and / or the second semiconductor region can each be composed of one or more partial layers.
- the second semiconductor region comprises a plurality of partial layers.
- the first semiconductor region is n-doped and the second semiconductor region is p-doped.
- the p-contact layer can be that partial layer of the second semiconductor region which is located farthest from the active zone after step A).
- the openings extend to at least 50 nm or at least 100 nm through the contact layer in the direction of the active zone into the remaining second semiconductor region. These openings end at a distance from the active zone. This distance from the active zone is preferably at least 150 nm or 250 nm or 300 nm.
- a total thickness of the second semiconductor region is in particular at least 0.3 gm or 0.4 gm. Alternatively or additionally, the total thickness can be at most 10 ⁇ m or 1 ⁇ m, for example or 0.6 pm.
- the p-contact layer preferably only has a relatively small thickness, for example a thickness of at most 50 nm or 20 nm and / or at least 4 nm or 8 nm.
- the subregions of the semiconductor layer sequence for the semiconductor chips produced in step D) each have an average edge length of at most 150 ⁇ m or 100 ⁇ m or 70 ⁇ m or 30 ⁇ m or 10 ⁇ m when viewed from above.
- the finished semiconductor chips are therefore pLEDs. If the subregions are not square or rectangular when viewed from above, a mean diameter of the subregions can be used instead of the average edge length.
- the at least one intermixing region after step D) extends into the active zone in the direction perpendicular to the growth direction by at least 0.1 ⁇ m or 0.2 ⁇ m. Alternatively or additionally, this value is at most 1.5 pm or 1 pm or 0.5 pm or 0.3 pm. This means that only a comparatively small proportion of the active zone, seen in plan view, is mixed. This means that, seen in plan view, the mixing area is comparatively small relative to the active zone and in particular amounts to at most 3% or 1% or 0.2% of the area of the active zone, again seen in plan view.
- the at least one intermixing region extends completely through the semiconductor layer sequence in the direction parallel to the growth direction. This means that the mixing area can extend as far as the growth substrate or also into the growth substrate.
- the active zone comprises at least 2 or 3 or 4 of the quantum well layers after step A). Alternatively or additionally, the number of quantum well layers is at most 50 or 30 or 20 or 10 or 5.
- the quantum well layers each have a thickness of at least 2 nm or 4 nm.
- the thicknesses of the quantum well layers are each at most 15 nm or 10 nm or 7 nm or 4 nm.
- the barrier layers each have a thickness of at least 2 nm or 3 nm or 5 nm.
- the thickness of the barrier layers is at most 353 nm or 25 nm or 15 nm or 10 nm.
- the thickness of the barrier layers is 7 nm, for example with a tolerance of at most 1 nm or 2 nm.
- the active zone is set up to generate an emission wavelength of maximum intensity of at least 560 nm or 590 nm or 610 nm or 620 nm.
- the emission wavelength of maximum intensity is at most 670 nm or 655 nm or 635 nm. That is to say, the finished semiconductor chips are set up in particular to generate red light.
- the barrier layers are grown in such a way that some or all of the barrier layers after step A) and at least before step C) have different proportions of aluminum.
- Blocks of immediately successive barrier layers can nominally have grown the same. It is possible for the barrier layers to have aluminum proportions that differ from one another in pairs.
- the relevant aluminum content is constant within the respective barrier layer. That is to say, the individual barrier layers are then grown without gradients in the aluminum component, each seen within the relevant barrier layer. Alternatively, the individual barrier layers can already be covered with an aluminum gradient in step A).
- a minimum and a maximum aluminum proportion of the barrier layers in the active zone after step A) and up to at least before step C) differ by at least a factor of 1.05 or 1.1 or 1.2. Alternatively or additionally, this factor is at most 1.7 or 1.6 or 1.5 or 1.4.
- barrier layers have different thicknesses from one another.
- Barrier layers of the same thickness can be combined in blocks, or all barrier layers have different thicknesses from one another in pairs.
- a minimum and a maximum thickness of the barrier layers in the active zone differ by at least a factor of 1.2 or 1.5 or 2 or 2.5. Alternatively or additionally, this factor is a maximum of 8 or 6 or 4 or 3.
- the barrier layers in the active zone are arranged asymmetrically at least after step A) up to before step C) with regard to a variation in thickness and / or a variation in aluminum content. This means that in the active zone there is no plane of symmetry which is oriented perpendicular to the direction of growth, with regard to a design of the barrier layers. Alternatively, the barrier layers are distributed symmetrically, so that such a plane of symmetry exists in the active zone with respect to the barrier layers.
- the mixing aid is zinc.
- the zinc is applied in step C) in particular by means of gas phase deposition, for example in the form of diethyl zinc, DEZn for short, or as dimethyl zinc, DMZn for short.
- gas phase deposition for example in the form of diethyl zinc, DEZn for short, or as dimethyl zinc, DMZn for short.
- magnesium can be used, which is applied using bis (cyclopentadienyl) magnesium, or Cp2Mg for short.
- a passivation layer is applied to the severed intermixing regions, that is to say to side surfaces of the semiconductor layer sequence produced in the isolation.
- the passivation layer is made, for example, of an oxide such as silicon dioxide or of a nitride such as silicon nitride.
- a thickness of the passivation layer is preferably relatively small and is, for example, at least 50 nm and / or at most 250 nm.
- the growth substrate is removed after step C), either immediately after step C) or only after further steps Intermediate steps.
- a replacement carrier can be attached to the semiconductor layer sequence before the growth substrate is removed.
- Such a replacement carrier is preferably attached before the separation in step D).
- the separation that is to say step D), can be carried out before or after the removal of the growth substrate, depending on when the optional replacement carrier is attached.
- an optoelectronic semiconductor chip is specified.
- the semiconductor chip is preferably produced using a method as described in connection with one or more of the above-mentioned embodiments. Features of the semiconductor chip are therefore also disclosed for the method and vice versa.
- the optoelectronic semiconductor chip comprises an AlInGaAsP semiconductor layer sequence, the semiconductor layer sequence comprising an active zone for generating radiation and the active zone being composed of several alternating quantum well layers and barrier layers.
- the semiconductor layer sequence comprises a structured masking layer, in particular the p-contact layer.
- the quantum well layers and the barrier layers are mixed in some areas in the active zone in a mixing area and a mixing aid, in particular zinc, is present in the mixing area.
- the mixing region seen in plan view, preferably extends in a closed path all around the semiconductor layer sequence.
- the semiconductor chips are red-emitting light-emitting diode chips with an average edge length of at most 50 ⁇ m.
- the mixing region extends into the active zone in the direction perpendicular to a growth direction of the semiconductor layer sequence by at least 0.1 ⁇ m and / or at most 0.5 ⁇ m .
- FIGS 1 to 5 are schematic sectional views of
- FIGS. 6 and 7 are schematic sectional views of
- Figure 8 is a schematic sectional view of a
- Figure 9 is a schematic plan view of a
- FIG. 10 shows a schematic representation of a profile of an aluminum component in a modification of a semiconductor chip
- FIGS. 11 to 14 are schematic representations of FIG.
- FIGS. An exemplary embodiment of a production method for optoelectronic semiconductor chips 1 is illustrated in FIGS. According to FIG. 1, a semiconductor layer sequence 3 is epitaxially grown along a growth direction G on a growth substrate 2.
- the semiconductor layer sequence 3 comprises a first semiconductor region 31, for example an n-doped region, directly on the growth substrate 2.
- the first semiconductor region 31 is drawn as only one layer in each case. In a departure from this, the first semiconductor region 31 can be composed of a plurality of partial layers. In particular, the first semiconductor region 31 does not point towards the growth substrate 2 drawn buffer layer and / or a non-drawn n-contact layer.
- the first semiconductor region 31 is followed by an active zone 33
- the active zone 33 comprises a plurality of quantum well layers 61 and barrier layers 62, which are arranged alternately. In particular, orange or red light is generated in the active zone 33 when the finished semiconductor chips 1 are in operation.
- a second semiconductor region 32 follows the active zone 33 along the growth direction G.
- the second semiconductor region 32 is p-doped, for example.
- the second semiconductor region 32 comprises a p-contact layer 34 as the top layer, which is furthest away from the growth substrate 2.
- a remaining second semiconductor region 35 is located between the p-contact layer 34 and the active zone 33.
- the semiconductor layer sequence 3 is based on the AlGalnAsP material system.
- the quantum well layers are preferably made of [(Al a Ga ] __ a ) pln ⁇ -p] C P ] __ C with 0.1 ⁇ ad 0.3, depending on the wavelength to be generated.
- the barrier layers are made of [(Al x Ga ] __ x ) yln ] __y] Z P ] __ Z with xh 0.6, in particular xh 0.8.
- the barrier layers thus have a relatively high aluminum content x.
- the p-contact layer 34 is in particular made of Al v Ga ] __ v As with v ⁇ 0.2.
- Al v Ga ] __ v As with v ⁇ 0.2 For the parameters b, c, y and z, it is particularly true that these parameters are around 0.5, especially 0.51 and 0.49, respectively.
- the active zone 33 comprises between 5 and 15, inclusive, of the quantum well layers 62.
- a plurality of openings 50 are produced through the p-contact layer 34.
- the openings 50 extend into the rest of the second semiconductor region 35.
- a depth of the openings 50 is, for example, between 50 nm and 200 nm inclusive.
- a distance between the openings 50 and the active zone 33 is preferably at least 300 nm.
- the remaining second semiconductor region 35 has a thickness between 300 nm and 600 nm, for example.
- a thickness of the p-contact layer 34 is, for example, between 5 nm and 20 nm inclusive.
- the p-contact layer 34 thus simultaneously serves as a masking layer 5 for a subsequent process step, see FIG. 3.
- a further masking layer, with which the openings 50 are produced in the p-contact layer 34 can also be removed before the method step in FIG.
- FIG. 3 illustrates that a gaseous precursor 56 is brought up to the semiconductor layer sequence 3.
- the precursor 56 is, for example, DMZn or DEZn.
- zinc is provided as a mixing aid 55 via the precursor 56.
- a solid layer can also be deposited for the mixing aid 55, for example a zinc layer a few nm thick.
- the mixing aid 55 diffuses preferably at an elevated temperature of, for example, approximately 550 ° C into the semiconductor layer sequence 3.
- the AlGaAs p-contact layer 34 is impermeable to the mixing aid 55.
- Mixing areas 51 in which the mixing aid 55 is present, thus form at the openings 50.
- the materials of the barrier layers 62 and the barrier layers are mixed
- Quantum well layers 61 This is illustrated further below in connection with FIGS. 11 to 14.
- the intermixing regions 51 extend, for example, to at least 0.2 gm or 0.5 gm below the p-contact layer 34. The same can also apply to all other exemplary embodiments.
- the semiconductor layer sequence 3 is separated in the region of the openings 50 to form subregions 39 for the semiconductor chips 1. This separation takes place, for example, by means of etching. Isolation trenches 8 thus arise between the subregions 39. In a departure from the illustration in FIG. 4, the isolation trenches 8 can also extend into the growth substrate 2.
- An edge length of the sub-region 39, seen in plan view, is preferably small and is below 100 ⁇ m or 50 ⁇ m.
- the isolation trenches 8 are each located in the area of the intermixing regions 51.
- the isolation trenches 8 result in side walls of the semiconductor layer sequence 3 which, according to FIG. 4, are only partially formed by the intermixing regions 51.
- the intermixing regions 51 Towards the On the growth substrate 2, the intermixing regions 51 begin on a side of the p-contact layer 34 facing the active zone 33.
- the intermixing regions 51 preferably extend under the p-contact layer 34, as shown.
- FIG. 4 illustrates that a plurality of second electrodes 42 are applied to the p-contact layer 34 and that a passivation layer 7 is produced. Masking layers for producing the second electrode 42 and / or for producing the passivation layer 7 are not shown.
- FIG. 5 it is also shown as an option that the growth substrate is removed from the subregions.
- a first electrode 41 is attached to the first semiconductor region 31.
- the passivation layer 7 is largely removed from the second electrode 42.
- the semiconductor chip 1 is thus preferably a light-emitting diode chip for generating red light.
- the electrodes 41, 42 are only indicated schematically in FIG.
- the electrodes 41, 42 which comprise at least one metal and / or a transparent conductive oxide, are designed, for example, as described in FIG. 3 and in paragraphs 59 to 62 of the publication US 2012/0248494 A1.
- FIGS. 6 and 7 A further manufacturing method is shown in FIGS. 6 and 7, only a few method steps being illustrated are. The remaining process steps can be carried out analogously to FIGS. 1 to 5.
- the mixing aid 55 is applied through the openings 50 and the mixing regions 51 are produced.
- the masking layer 5 is a hard mask, for example made of silicon nitride or silicon dioxide.
- the intermixing regions 51 can thus reach up to the masking layer 5.
- FIG. 6 shows that the intermixing regions 51 completely penetrate the semiconductor layer sequence 3 and thus extend as far as the growth substrate 2.
- a corresponding design of the mixing areas 51 is also possible in the method of FIGS. 1 to 5.
- the isolation trenches 8 are produced, which extend at least as far as the growth substrate 2.
- side walls of the semiconductor layer sequence 3 and thus of the isolation trenches 8 in areas below the masking layer 5 can be formed completely by the intermixing areas 51.
- the masking layer 5 also serves as a mask for producing the isolation trenches 8. That is to say, the isolation trenches 8 and the openings 50 can run congruently with one another when viewed from above, deviating from the illustration in FIGS. 1 to 5. Corresponding isolation trenches 8 can alternatively also in the method as illustrated in connection with FIGS. 1 to 5.
- the p-contact layer 34 again serves as a masking layer 5.
- the isolation trenches 8 and the openings 50 are arranged congruently as seen in plan view.
- the intermixing areas 51 affected by the singulation still extend to the growth substrate 2 even after the singulation.
- the intermixing regions 51 only extend into regions up to the growth substrate 2, which are subsequently removed by the singulation.
- a corresponding arrangement is also possible in the methods of FIGS. 1 to 5 and FIGS. 6 and 7.
- FIG. 9 schematically shows a top view of the semiconductor layer sequence 3 after the separation, in particular as shown in the method in FIGS. 6 and 7 and in the method in FIG. That is, the isolation trenches 8 and the openings 50 run congruently.
- a corresponding structure with isolation trenches 8, which are narrower than the openings 50, can also be used.
- the intermixing regions 51 each encircle the subregions 39 of the semiconductor layer sequence 3 in a closed path.
- the subregions 39 for the semiconductor chips 1 are each approximately square or rectangular. Edge lengths of the subregions 39 are below 100 ⁇ m.
- a distance between adjacent subregions 39 and thus a width of the openings 50 and the isolation trenches 8 is preferred relatively small and is, for example, at most 10% or 5% or 2% of an average edge length of the subregions 39.
- the openings 50 and / or the isolation trenches 8 have a width of at most 5 mpi or 3 mpi or 1 mpi and / or at least 0 , 5 mpi or 1 mpi. That is to say, the subregions 39 are arranged tightly packed on the growth substrate 2, so that comparatively little space remains for the mixing aid 55 to diffuse in.
- FIG. 10 shows a modification 10 of a semiconductor chip.
- a ratio of an aluminum proportion to a sum of the aluminum proportion and a gallium proportion is plotted over the growth direction G, given in percent.
- the left part of the figure relates to an unmixed area 52 of the active zone 33, whereas the right part of the figure relates to the mixed area 51 of the active zone 33.
- the same representation is also used in FIGS. 11 to 14.
- the barrier layers 62 have a relatively low aluminum content. This results in a comparatively flat profile of the aluminum component in the mixing areas 51 after mixing and thus a comparatively small increase in a band gap compared to the quantum well layers 61. This means that recombination losses of charge carriers on the side walls of the sub-areas 39 and thus the semiconductor chips 1 can only be reduced relatively poorly.
- Such edge effects hardly play a role in conventional LEDs, since an edge line only plays a subordinate role relative to the total area of an active zone. In the pLEDs described here, on the other hand, due to the small edge length of the subregions 39 corresponding effects on the side walls a potentially significant loss channel.
- FIG. 11 shows a profile of the aluminum component for an exemplary embodiment of the semiconductor chip 1.
- the barrier layers 62 have a significantly higher aluminum content of approximately 85% than in FIG. 10. This results in a significantly higher band gap in the mixing region 51 between the quantum well layers 61 in the non-mixed region 52 and the mixed structure in the mixing region 51.
- the quantum well layers 51 and barrier layers 62 have grown identically and are thus present unchanged in the unmixed region 52 along the direction of growth G.
- the barrier layers 62 according to FIGS. 12 to 14 each have at least one gradient in terms of thickness and / or material composition.
- the barrier layers 62 are designed along the growth direction G with a decreasing aluminum content.
- the aluminum content of the barrier layers 62 is constant along the growth direction G, but the thickness of the barrier layers 62 decreases.
- FIG. 14 is a combination of the configurations from FIGS. 12 and 13, so that along the growth direction G both the aluminum content decreases and a thickness of the barrier layers becomes smaller.
- FIGS. 11 to 14 five quantum well layers 61 are shown in each case only to simplify the illustration. It In each case, more or fewer than the illustrated quantum well layers can be present in the active zone 33.
- the barrier layers 62 of FIGS. 12 to 14 are arranged asymmetrically in the active zone 33, so that the active zone 33 does not have a plane of symmetry to which the barrier layers 62 are designed mirror-symmetrically.
- symmetrical sequences of barrier layers 62 are also possible, so that, for example, analogously to FIG. 12, an aluminum content of the barrier layers 62 first increases along the growth direction G and then decreases to the same extent. The same applies to embodiments according to FIGS. 13 and 14.
- the components shown in the figures preferably follow one another directly in the specified order, unless otherwise indicated. Layers that do not touch one another in the figures are preferred to one another spaced. As far as lines are drawn parallel to one another, the corresponding surfaces are preferably also aligned parallel to one another. The relative positions of the drawn components are also shown correctly in the figures, unless otherwise indicated.
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JP2022520332A JP2022551589A (ja) | 2019-10-01 | 2020-09-25 | オプトエレクトロニクス半導体チップの製造方法およびオプトエレクトロニクス半導体チップ |
US17/765,657 US20220384680A1 (en) | 2019-10-01 | 2020-09-25 | Method for Producing Optoelectronic Semiconductor Chips, and Optoelectronic Semiconductor Chip |
KR1020227006167A KR20220038456A (ko) | 2019-10-01 | 2020-09-25 | 광전자 반도체 칩들의 제조 방법 및 광전자 반도체 칩 |
CN202080069301.3A CN114521295A (zh) | 2019-10-01 | 2020-09-25 | 用于制造光电子半导体芯片的方法和光电子半导体芯片 |
JP2024014934A JP2024045405A (ja) | 2019-10-01 | 2024-02-02 | オプトエレクトロニクス半導体チップの製造方法およびオプトエレクトロニクス半導体チップ |
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JP (2) | JP2022551589A (de) |
KR (1) | KR20220038456A (de) |
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WO2023072408A1 (en) * | 2021-10-29 | 2023-05-04 | Ams-Osram International Gmbh | Otpoelectronic device and method for processing the same |
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US20120248494A1 (en) | 2009-12-11 | 2012-10-04 | Franz Eberhard | Optoelectronic Semiconductor Chip and Method for Fabricating an Optoelectronic Semiconductor Chip |
US20170170360A1 (en) * | 2015-01-06 | 2017-06-15 | Apple Inc. | Led structures for reduced non-radiative sidewall recombination |
US10396241B1 (en) * | 2016-08-04 | 2019-08-27 | Apple Inc. | Diffusion revealed blocking junction |
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JP2752423B2 (ja) * | 1989-03-31 | 1998-05-18 | 三菱電機株式会社 | 化合物半導体へのZn拡散方法 |
JPH07162086A (ja) * | 1993-12-10 | 1995-06-23 | Mitsubishi Electric Corp | 半導体レーザの製造方法 |
KR20080035865A (ko) * | 2006-10-20 | 2008-04-24 | 삼성전자주식회사 | 반도체 발광 소자 |
DE102008011848A1 (de) * | 2008-02-29 | 2009-09-03 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterkörper und Verfahren zur Herstellung eines solchen |
KR20110057541A (ko) * | 2009-11-24 | 2011-06-01 | 삼성엘이디 주식회사 | 질화물 반도체 발광소자 |
US8604491B2 (en) * | 2011-07-21 | 2013-12-10 | Tsmc Solid State Lighting Ltd. | Wafer level photonic device die structure and method of making the same |
US9484492B2 (en) * | 2015-01-06 | 2016-11-01 | Apple Inc. | LED structures for reduced non-radiative sidewall recombination |
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US20120248494A1 (en) | 2009-12-11 | 2012-10-04 | Franz Eberhard | Optoelectronic Semiconductor Chip and Method for Fabricating an Optoelectronic Semiconductor Chip |
US20170170360A1 (en) * | 2015-01-06 | 2017-06-15 | Apple Inc. | Led structures for reduced non-radiative sidewall recombination |
US10396241B1 (en) * | 2016-08-04 | 2019-08-27 | Apple Inc. | Diffusion revealed blocking junction |
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CN114521295A (zh) | 2022-05-20 |
JP2024045405A (ja) | 2024-04-02 |
KR20220038456A (ko) | 2022-03-28 |
JP2022551589A (ja) | 2022-12-12 |
US20220384680A1 (en) | 2022-12-01 |
DE102019126506A1 (de) | 2021-04-01 |
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