WO2021057158A1 - 一种自适应zvs电路及其控制方法 - Google Patents

一种自适应zvs电路及其控制方法 Download PDF

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WO2021057158A1
WO2021057158A1 PCT/CN2020/100117 CN2020100117W WO2021057158A1 WO 2021057158 A1 WO2021057158 A1 WO 2021057158A1 CN 2020100117 W CN2020100117 W CN 2020100117W WO 2021057158 A1 WO2021057158 A1 WO 2021057158A1
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power supply
inductor
voltage
switching tube
comparison unit
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PCT/CN2020/100117
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English (en)
French (fr)
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卢鹏飞
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广州金升阳科技有限公司
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to a switching power supply, in particular to an adaptive ZVS switching converter circuit and a control method thereof.
  • Figure 1 is a Buck circuit with synchronous rectification function
  • Figure 2 is a timing diagram corresponding to Figure 1.
  • the condition for MOS tube Q1 to achieve zero voltage turn-on (ZVS) is when the current IL of the inductor L is a certain negative current at t2 Turn off the MOS transistor Q2; when the MOS transistor Q2 is turned off at t1, the current IL of the inductor L at t1 is greater than the current at t2, so that the MOS transistor Q1 loses the condition to realize the ZVS turn-on, as shown by the dotted line in Figure 2.
  • the absolute value of the negative current at the moment when the MOS transistor Q2 is turned off must be large enough, but if the absolute value of the negative current is too large, although the ZVS of the MOS transistor Q1 is turned on, unnecessary current is generated to circulate in the inductor L. Reduce circuit efficiency. Therefore, the absolute value of the negative current at the moment when the MOS transistor Q2 is turned off must be an appropriate value, which cannot be too large or too small.
  • the switching frequency of the circuit is getting higher and higher, and the inductance of the inductor is getting smaller and smaller. The time left for the detection circuit and the control circuit is getting smaller and smaller, so the control flow through the inductor L
  • the negative current at an appropriate value becomes a technical problem that needs to be overcome.
  • Figure 3 Figure 4 and Figure 5 are the drawings of the United States patent abstract with the application number US13/027,830 and the invention titled "ADAPTIVE CONTROL OF SWITCHING LOSSES IN POWER CONVERTERS".
  • the inventive concept of this patent is the current reversal detection in Figure 4
  • the device 214 detects when the polarity of the current IL of the inductor L in FIG. 3 is reversed, and provides a high output signal to the controller 202 and the timer 218, so that the output of the controller 202 becomes low and the output of the timer 218 becomes high. And start counting, so that the output of the corresponding OR gate 216 is still at a high level and the switch S2 in FIG.
  • the sampling and holding circuit 222 samples and holds the Vs voltage at time t7 in FIG. 5, and then uses the Vin signal as the input of the error amplifier 220 and generates an error signal e 2.
  • the timer 218 receives the error signal e 2 and adjusts the timer 218
  • the counting time corresponds to the period from t3 to t4 in Figure 5, that is, the duration of the negative current of the inductor L is adjusted by detecting the Vs voltage at t7, so that the negative current of the inductor L is adjusted to a suitable value This will minimize losses and improve power efficiency.
  • the Vs voltage continuously changes rapidly. It is very difficult to sample and maintain the Vs voltage at time t7, whether it is a digital circuit or an analog circuit, which makes it difficult to realize adaptive ZVS.
  • the technical problem to be solved by the present invention is to propose an adaptive ZVS circuit and its control method, which realizes the adaptive ZVS turn-on of the switch tube through the double comparison method, and has simple circuit. Easy to realize, minimize loss and improve power efficiency.
  • An adaptive ZVS circuit including power supply V1, power supply V2, power supply V3, switching tube Q1, switching tube Q2, inductor L and dual comparison unit; the drain of switching tube Q1 and one input end of the dual comparison unit are connected to the power supply V1, the source of the switch Q1, the drain of the switch Q2 and the other input of the dual comparison unit are connected to one end of the inductor L1, the source of the switch Q2 is connected to the power supply V2, and the other end of the inductor L1 is connected To power supply V3.
  • the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
  • the inductor L is an inductor or a winding of a transformer.
  • the dual comparison unit is two comparators.
  • two input terminals of the comparator are respectively connected to the power supply V1 and one end of the inductor L1.
  • At least one of the two input terminals of the comparator is connected to one end of the power supply V1 and the inductor L1 after adding a bias voltage.
  • the power supply V1 and one end of the inductor L1 are respectively connected to the two input terminals of the comparator after passing through a voltage divider circuit.
  • the voltage divider circuit is a plurality of resistor series voltage divider circuits or several resistor series voltage divider circuits connected in series with a voltage source, a constant current source or a voltage stabilizing device.
  • the present invention also provides the control method of the above-mentioned adaptive ZVS circuit. From the time when the switch Q2 is turned off to the time when the switch Q1 is turned on, according to the voltage of the power supply V1, the voltage at one end of the inductor L1 and the double comparison unit obtain two high and low values. Level output, relative to the turn-off time of the switch Q2 in the current cycle, the two high and low outputs of the dual comparison unit adjust the switch Q2 to remain in the next cycle, and turn off earlier or later.
  • the present invention also provides another switching converter with the same inventive concept.
  • the technical solution is: an adaptive ZVS circuit, including a power supply V1, a power supply V2, a power supply V3, a switching tube Q1, a switching tube Q2, an inductor L, and a dual comparator Unit; the drain of the switch Q1 is connected to the power supply V1, the source of the switch Q1, the drain of the switch Q2 and one input end of the dual comparison unit are connected to one end of the inductor L1, the source of the switch Q2 and the dual The other input terminal of the comparison unit is connected to the power supply V2, and the other end of the inductor L1 is connected to the power supply V3.
  • the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
  • the inductor L is an inductor or a winding of a transformer.
  • the dual comparison unit is two comparators.
  • the two input terminals of the comparator are respectively connected to the power supply V2 and one end of the inductor L1.
  • At least one of the two input terminals of the comparator is connected to one end of the power supply V2 and the inductor L1 after adding a bias voltage.
  • the present invention also provides the control method of the above-mentioned adaptive ZVS circuit. From the time when the switch Q1 is turned off to the time when the switch Q2 is turned on, according to the voltage of the power supply V2, the voltage at one end of the inductor L1 and the double comparison unit obtain two highs and lows. Level output, and then relative to the turn-off time of the switch Q1 in the current cycle, the two output high and low levels of the dual comparison unit adjust the switch Q1 to be maintained in the next cycle, and turn off earlier or later.
  • the drain of the switching tube For MOS tube, it refers to the drain, for the triode, it is the collector, and for IGBT, it is the drain.
  • Other switching tubes can correspond according to the knowledge of those skilled in the art, no longer one by one. Enumerate
  • the source of the switching tube For MOS tube, it refers to the source, for the triode, it is the emitter, and for IGBT, it is the source.
  • Other switching tubes can correspond to the knowledge of those skilled in the art, no longer one by one. Enumerate.
  • the present invention has the following beneficial effects:
  • the highest voltage at one end of the inductor L1 during the time period from when the switching tube Q2 is turned off to the time when the switching tube Q1 is turned on, or the inductor in the time period from the time when the switching tube Q1 is turned off to the time when the switching tube Q2 is turned on The lowest voltage at one end of L1 is controlled within a suitable range.
  • the highest or lowest voltage at one end of the inductor L1 is positively related to the current of the inductor L that realizes the switching of the switch tube ZVS. Therefore, the current is steadily adjusted to an appropriate value. Minimize losses and improve power efficiency.
  • Figure 1 is a schematic diagram of Buck circuit with synchronous rectification function
  • Figure 2 is a working sequence diagram of Figure 1;
  • FIG. 3 is a schematic diagram of Buck circuit with application number US13/027,830;
  • Figure 4 is an adaptive ZVS control block diagram of application number US13/027,830;
  • FIG. 5 is a working sequence diagram of application number US13/027,830;
  • Figure 6 is a schematic block diagram of the present invention.
  • FIG. 7 is another principle block diagram of the present invention.
  • Fig. 8 is a schematic diagram of an adaptive ZVS circuit using dual comparison units in the first embodiment of the present invention.
  • Fig. 9 is a working sequence diagram of the first embodiment of the present invention.
  • Fig. 10 is a truth table of the first embodiment of the present invention.
  • FIG. 11 is a schematic diagram of an adaptive ZVS circuit using dual comparison units in the second embodiment of the present invention.
  • FIG. 12 is a schematic diagram of an adaptive ZVS circuit using dual comparison units in the third embodiment of the present invention.
  • Fig. 13 is a truth table of the third embodiment of the present invention.
  • Fig. 6 is a principle block diagram of the present invention, including power supply V1, power supply V2, power supply V3, switching tube Q1, switching tube Q2, inductor L and dual comparison unit; the drain of switching tube Q1 and one input end of the dual comparison unit Connected to the power supply V1, the source of the switching tube Q1, the drain of the switching tube Q2 and the other input terminal of the dual comparison unit are connected to one end of the inductor L1, and the source of the switching tube Q2 is connected to the power supply V2, the inductor L1 The other end is connected to the power supply V3; the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
  • Fig. 7 is another principle block diagram of the present invention. Including power supply V1, power supply V2, power supply V3, switching tube Q1, switching tube Q2, inductor L and dual comparison unit; the drain of switching tube Q1 is connected to power supply V1, the source of switching tube Q1, and the drain of switching tube Q2 One input end of the dual comparison unit is connected to one end of the inductor L1, the source of the switch Q2 and the other input end of the dual comparison unit are connected to the power supply V2, and the other end of the inductor L1 is connected to the power supply V3; The voltage is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
  • Coss1 and Coss2 in FIGS. 6 and 7 are the output capacitors of the switching tube Q1 and the switching tube Q2, respectively, and D1 and D2 are the body diodes of the switching tube Q1 and the switching tube Q2, respectively.
  • switching tube Q1 and the switching tube Q2 are replaced with MOS tubes, and other types of switching tubes such as triodes and IGBTs are common methods used by those skilled in the art.
  • FIG 8 is a schematic diagram of an adaptive ZVS circuit using a dual comparison unit in this embodiment.
  • the dual comparison unit includes a comparator COMP1, a comparator COMP2 and a voltage source U; the reverse end of the comparator COMP1 and the forward end of the voltage source U Connected to the power supply V1, the negative terminal of the voltage source U is connected to the reverse terminal of the comparator COMP2, the positive terminal of the comparator COMP1 and the positive terminal of the comparator COMP2 are connected to the node SW (that is, one end of the inductor L1) ,
  • the output terminals of the comparator COMP1 and the comparator COMP2 are respectively connected to the anodes of the diodes D3 and D4, and the cathodes of the diodes D3 and D4 are respectively connected to the output C1 and the output C2.
  • the working time of the dual comparison unit is from the moment when the switching tube Q2 is turned off to the moment when the switching tube Q1 is turned on, and its working principle is:
  • the voltage of the power supply V1 and the voltage of the node SW are compared as the reverse and forward inputs of the comparator COMP1 respectively. If the voltage of the node SW (ie the end of the inductor L1) is greater than In the case of the V1 voltage, the output C1 is at a high level, indicating that the negative current is too large, and the switch Q2 needs to be turned off in the next cycle relative to the current cycle.
  • the comparator COMP2 After the bias voltage U is added to the voltage of the power supply V1, and the voltage of the node SW (that is, the end of the inductor L1) are compared as the reverse and forward inputs of the comparator COMP2, if the node SW (that is, the inductor L1 If the voltage at one end) does not appear to be greater than the V1-U voltage, the output C2 is low, indicating that the negative current is too small, and the switch Q2 needs to be turned off after the next cycle relative to the current cycle.
  • the output C1 is low, and the voltage of the circuit node SW (ie the end of the inductor L1) appears to be greater than V1-U In the case of voltage, the output C2 is at a high level, and there is no need to advance or delay the turn-off operation of the switch Q2 relative to the current cycle.
  • the ZVS turn-on of the switch refers to the switch on when the voltage difference between the drain and the source is 0V; in a broad sense, the ZVS turn-on of the switch refers to the switch between the drain and the source.
  • the switch tube is turned on. According to the actual debugging results of the circuit, there is little difference between the narrow sense ZVS turn-on and the broad sense ZVS turn-on.
  • the present invention uses the broad sense ZVS, as long as the voltage of the node SW (that is, one end of the inductor L1) reaches the switch tube Q2 when the switch tube Q2 is turned off.
  • the switching tube Q1 When Q1 is turned on, it can reach between the voltage of V1 and the voltage of V1-U in the dead time period. It is considered that the switching tube Q1 can realize the ZVS opening. Only two comparison units are needed to judge whether the switching tube Q1 realizes the ZVS opening. According to the result of the judgment, the turn-off time of the switching tube Q2 is adjusted in the next cycle. Since the comparison speed is extremely fast, the present invention is particularly suitable for occasions with relatively high switching frequency. Since the core device is a comparator, compared to the invention patent with application number 13/027,830, the circuit is simple and easy to implement, low cost, and easy to implement. High-frequency applications can minimize losses and improve power supply efficiency.
  • Figure 9 shows the working sequence of the first embodiment, assuming that the voltage of the power supply V1 is greater than the voltage of the power supply V3, as follows:
  • t0 ⁇ t1 stage at t0, the switch Q1 is turned on, the voltage across the inductor L1 is V1-V3, and the inductor L1 is excited, the current IL of the inductor L rises, and the switch Q1 is turned off at the time t1;
  • Stage t1 ⁇ t2 After the switching tube Q1 is turned off, the current IL of the inductor L charges the output capacitance Coss1 of the switching tube Q1 and discharges the output capacitance Coss2 of the switching tube Q2. At time t2, the voltage of the circuit node SW (that is, one end of the inductor L) drops from V1 to V2, and the switch Q2 realizes the ZVS turn-on;
  • Phase t4 ⁇ t0+T The current IL of the inductor L charges the output capacitance Coss2 of the switching tube Q2, and discharges the output capacitance Coss1 of the switching tube Q1, and the switching tube Q1 is turned on at t0+T. From t4 to t0+T, when the highest voltage of the circuit node SW (that is, one end of the inductor L1) is between V1-U and V1, according to the generalized ZVS definition: the switch Q1 realizes the ZVS turn-on;
  • the switching transistor Q2 'turn-off time 4 waveforms shown in long dashed line in FIG. 9, t' in the T 4 to time t0 + T circuit node SW (i.e., end of the inductor L1) is lower than the voltage has been V1-U, then the next cycle for an extended 'duration. 4, the length of the extension according to the setting of step length for each cycle is accumulated adjusted until t' t3 to T 4 to t0 + T timing circuit node SW (i.e., inductor The highest voltage at the end of L1 is between V1-U and V1.
  • the waveform is shown by the short dashed line in Figure 9.
  • the highest voltage of the circuit node SW that is, one end of the inductor L1 from t" 4 to t0+T is greater than V1, and it is switched Tube Q1 body diode D1 clamps to V1+Vf, Vf is the conduction voltage drop of body diode D1, then the next cycle will reduce the duration from t3 to t′′ 4 , and the duration will be reduced according to the set step duration.
  • the cumulative adjustment is performed in each cycle until the highest voltage at the circuit node SW (that is, one end of the inductor L1) at the time t"4 to t0+T is between V1-U and V1.
  • the comparator COMP1 and the comparator COMP2 are used to determine the highest voltage of the circuit node SW (that is, one end of the inductor L1) from t4 to t0+T, and record the highest voltage as SWM4.
  • the truth table obtained is shown in Figure 10, according to Figure 10. To determine whether the duration from t3 to t4 is extended, decreased or unchanged in the next cycle, when C1 or C2 is high, the diode connected to the output of the comparator COMP1 and the comparator COMP2 is used to maintain the high level of C1 or C2. C1 and C2 are reset once every cycle.
  • the T in the above t0+T represents the time length of one cycle.
  • Fig. 11 is a schematic circuit diagram of the second embodiment of the present invention.
  • the input terminals of the comparator COMP1 and the comparator COMP2 are changed from being directly connected to the power supply V1 and the node SW (that is, one end of the inductor L1) to indirectly connected through a voltage divider circuit, and a voltage stabilizing device is used.
  • Z1 replaces the voltage source U, and the voltage divider circuit mainly solves the problem that the voltage at one end of the power supply V1 and the inductor L1 exceeds the maximum withstand voltage of the input end of the comparison unit.
  • the working sequence of the second embodiment is similar to the working sequence of the first embodiment, except that the power supply V1 and one end of the inductor L1 are scaled down, and the rated voltage value Z of the voltage stabilizing device Z1 is used to replace the first embodiment.
  • the voltage U of the voltage source U Other content will not be repeated here.
  • Fig. 12 is a schematic circuit diagram of the third embodiment of the present invention.
  • the included devices are basically the same as the first embodiment, and the main difference lies in the connection relationship: the reverse end of the comparator COMP1 and the forward end of the voltage source U are connected to the node SW (that is, the end of the inductor L1), and the comparator COMP1 The positive terminal and the positive terminal of the comparator COMP2 are connected to the power supply V2.
  • the third embodiment still uses the principle of the generalized ZVS.
  • the entire working process and principle are similar to the first embodiment.
  • the comparator COMP1 and the comparator COMP2 are used to determine the circuit node SW (ie, the inductor from time t1 to t2) in FIG.
  • the lowest voltage at the end of L1) record the lowest voltage as SWm1, and the obtained truth table is shown in Fig. 13. From the truth table, it is judged whether the duration from t0 to t1 is extended, decreased or unchanged in the next cycle.
  • C1 or C2 is high
  • the diode connected to the output of the comparator COMP1 and the comparator COMP2 is used to maintain the high level of C1 or C2, and C1 and C2 are reset once in each cycle. Other content will not be repeated here.

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本发明公开了一种自适应ZVS电路及其控制方法，自适应ZVS电路包括电源V1，电源V2，电源V3，开关管Q1、开关管Q2、电感器L和双比较单元；开关管Q1的漏极和双比较单元的一个输入端连接到电源V1，开关管Q1的源极，开关管Q2的漏极和双比较单元的另一个输入端连接到电感器L1的一端，开关管Q2的源极连接到电源V2，电感器L1的另一端连接到电源V3。本发明利用广义ZVS的定义，通过双比较单元可以简单快速的判定开关管是否实现ZVS开通，并告诉控制电路下一个周期是否调节以及如何调节电路时序实现开关管的自适应ZVS开通，由于比较的速度远快于采样和保持电路的速度，所以在高频应用时优势更加明显。

Description

一种自适应ZVS电路及其控制方法 技术领域
本发明涉及开关电源，特别涉及自适应ZVS开关变换器电路及其控制方法。
背景技术
图1为具有同步整流功能的Buck电路，图2为图1对应的时序图，MOS管Q1实现零电压开通(ZVS)的条件是在t2时刻电感器L的电流IL为一定的负向电流时关断MOS管Q2；当MOS管Q2在t1时刻关断，t1时刻电感器L的电流IL大于t2时刻的电流，使MOS管Q1失去了实现ZVS开通的条件，如图2中虚线所示，因此MOS管Q2关断时刻的负向电流绝对值必须足够大，但是如果负向电流绝对值过大虽然实现了MOS管Q1的ZVS开通，但是产生了不必要的电流在电感器L中循环，使电路效率降低。所以MOS管Q2关断时刻的负向电流绝对值必须为一个合适的值，不能太大，也不能太小。随着软开关技术的应用，电路的开关频率越来越高，电感器的感量也是越来越小，留给检测电路和控制电路的时间越来越小，所以控制流过电感器L的负向电流在一个合适的值成为一项需要攻克的技术难题。
图3，图4和图5为申请号US13/027,830，发明名称为《ADAPTIVE CONTROL OF SWITCHING LOSSES IN POWER CONVERTERS》的美国专利摘要附图，该专利的发明构思是通过图4中的电流反转检测器214来检测图3中的电感器L的电流IL极性何时反转，并向控制器202和计时器218提供高输出信号，使控制器202输出变低，计时器218的输出变高并开始计数，使对应或门216的输出依然为高电平并维持图3中的开关S2导通。采样和保持电路222在图5的t7时刻采样Vs电压并保持住，然后和Vin信号作为误差放大器220的输入，并产生一个误差信号e 2，计时器218接收误差信号e 2并调节计时器218的计数时间，计数时间对应图5中的t3到t4时段，即：通过检测t7时刻的Vs电压来调节电感器L负向电流的持续时间，使电感器L的负向电流大小调整到一个合适的值，这将最大限度地减少损耗，提高电源效率。但是Vs电压不断的快速变化，对t7时刻的Vs电压采样到并进行保持，不管是数字电路还是模拟电路，都是特别困难的，导致自适应ZVS难以实现。
发明内容
鉴于现有自适应ZVS电路的技术缺陷，本发明要解决的技术问题是提出一种自适应ZVS电路及其控制方法，通过双比较的方式实现了开关管的自适应ZVS开通，具有电路简单，易实现，最大限度地减少损耗，提高电源效率。
为了实现上述发明目的，本发明采用以下技术方案：
一种自适应ZVS电路，包括电源V1，电源V2，电源V3，开关管Q1、开关管Q2、电感器L和双比较单元；开关管Q1的漏极和双比较单元的一个输入端连接到电源V1，开关管Q1的源极，开关管Q2的漏极和双比较单元的另一个输入端连接到电感器L1的一端，开关管Q2的源极连接到电源V2，电感器L1的另一端连接到电源V3。
优选的，电源V1的电压高于电源V2的电压，电源V3的电压高于电源V2的电压。
优选的，所述的电感器L为电感或变压器的一个绕组。
优选的，所述的双比较单元为两个比较器。
作为上述比较器的第一种实施方式，所述比较器的两个输入端分别连接电源V1和电感器L1的一端。
作为上述比较器的第二种实施方式，所述比较器的两个输入端至少其中一个添加偏置电压后分别连接到电源V1和电感器L1的一端。
作为上述比较器的第三种实施方式，电源V1和电感器L1的一端分别经过分压电路后再分别连接到比较器的两个输入端。
作为上述分压电路的一种实施方式，所述分压电路为若干电阻串联分压电路或串联有电压源、恒流源或稳压器件的若干电阻串联分压电路。
本发明还提供上述自适应ZVS电路的控制方法，从开关管Q2关断时刻到开关管Q1开通时刻的时间段内，根据电源V1电压，电感器L1的一端电压和双比较单元得到两路高低电平输出，然后相对于当前周期开关管Q2的关断时刻，由双比较单元的两路高低电平输出来调节开关管Q2在下一个周期保持，提前或延后关断。
本发明还提供另外一种相同发明构思的开关变换器，技术方案为：一种自适应ZVS电路，包括电源V1，电源V2，电源V3，开关管Q1、开关管Q2、电感 器L和双比较单元；开关管Q1的漏极连接到电源V1，开关管Q1的源极，开关管Q2的漏极和双比较单元的一个输入端连接到电感器L1的一端，开关管Q2的源极和双比较单元的另一个输入端连接到电源V2，电感器L1的另一端连接到电源V3。
优选的，电源V1的电压高于电源V2的电压，电源V3的电压高于电源V2的电压。
优选的，所述的电感器L为电感或变压器的一个绕组。
优选的，所述的双比较单元为两个比较器。
作为上述比较器的第一种实施方式，所述比较器的两个输入端分别连接到电源V2和电感器L1的一端。
作为上述比较器的第二种实施方式，所述比较器的两个输入端至少其中一个添加偏置电压后分别连接到电源V2和电感器L1的一端。
本发明还提供上述自适应ZVS电路的控制方法，从开关管Q1关断时刻到开关管Q2开通时刻的时间段内，根据电源V2电压，电感器L1的一端电压和双比较单元得到两路高低电平输出，然后相对于当前周期开关管Q1的关断时刻，由双比较单元的两路输出高低电平来调节开关管Q1在下一个周期保持，提前或延后关断。
术语含义说明：
开关管的漏极：对于MOS管指的是漏极、对于三极管指的是集电极、对于IGBT指的是漏极，其它开关管依据本领域的技术人员的知识可以自行对应，不再一一列举；
开关管的源极：对于MOS管指的是源极、对于三极管指的是发射极、对于IGBT指的是源极，其它开关管依据本领域的技术人员的知识可以自行对应，不再一一列举。
与现有技术相比，本发明具有如下有益效果：
1)采用双比较的方式实现开关管的自适应ZVS开通，电路简单易实现，成本低，特别适用于开关频率比较高的场合，实现开关管自适应ZVS开通；
2)采用双比较的方式将开关管Q2关断时刻到开关管Q1开通时刻的时间段内电感器L1一端的最高电压或开关管Q1关断时刻到开关管Q2开通时刻的时间 段内电感器L1一端的最低电压控制在一个合适的范围内，电感器L1一端的最高或最低电压与实现开关管ZVS开通的电感器L电流大小正相关，所以此电流稳定的调节至一个合适的值，将最大限度地减少损耗，提高电源效率。
附图说明
图1为具有同步整流功能的Buck电路原理图；
图2为图1的工作时序图；
图3为申请号US13/027,830的Buck电路原理图；
图4为申请号US13/027,830的自适应ZVS控制框图；
图5为申请号US13/027,830的工作时序图；
图6为本发明的一个原理框图；
图7为本发明的另一个原理框图；
图8为本发明第一实施例应用双比较单元的自适应ZVS电路原理图；
图9为本发明第一实施例的工作时序图；
图10为本发明第一实施例的真值表；
图11为本发明第二实施例应用双比较单元的自适应ZVS电路原理图；
图12为本发明第三实施例应用双比较单元的自适应ZVS电路原理图；
图13为本发明第三实施例的真值表。
具体实施方式
图6为本发明的一个原理框图，包括电源V1，电源V2，电源V3，开关管Q1、开关管Q2、电感器L和双比较单元；开关管Q1的漏极和双比较单元的一个输入端连接到电源V1，开关管Q1的源极，开关管Q2的漏极和双比较单元的另一个输入端连接到电感器L1的一端，开关管Q2的源极连接到电源V2，电感器L1的另一端连接到电源V3；电源V1的电压高于电源V2的电压，电源V3的电压高于电源V2的电压。
图7为本发明的另一个原理框图。包括电源V1，电源V2，电源V3，开关管Q1、开关管Q2、电感器L和双比较单元；开关管Q1的漏极连接到电源V1，开关管Q1的源极，开关管Q2的漏极和双比较单元的一个输入端连接到电感器L1的一端，开关管Q2的源极和双比较单元的另一个输入端连接到电源V2，电感器L1的另一端连接到电源V3；电源V1的电压高于电源V2的电压，电源V3 的电压高于电源V2的电压。
图6和图7中的Coss1和Coss2分别为开关管Q1和开关管Q2的输出电容，D1和D2分别为开关管Q1和开关管Q2的体二极管。
据此发明技术方案，以下结合附图对相关实施例的效果进行说明。需要说明的是：将开关管Q1和开关管Q2替换为MOS管，三极管和IGBT等其它类型的开关管为本领域技术人员的惯用手段。
第一实施例
图8为本实施例应用双比较单元的自适应ZVS电路原理图，该双比较单元包括比较器COMP1、比较器COMP2和电压源U；比较器COMP1的反向端和电压源U的正向端连接到电源V1，电压源U的负向端连接到比较器COMP2的反向端，比较器COMP1的正向端和比较器COMP2的正向端连接到结点SW(即电感器L1的一端)，比较器COMP1和比较器COMP2的输出端分别连接到二极管D3和D4的阳极，二极管D3和D4的阴极分别连接到输出C1和输出C2。
该双比较单元的工作时间从开关管Q2关断时刻到开关管Q1开通时刻，其工作原理为：
对于比较器COMP1：电源V1电压和结点SW(即电感器L1一端)的电压分别作为比较器COMP1的反向和正向输入进行比较，如果出现结点SW(即电感器L1一端)的电压大于V1电压的情况，则输出C1为高电平，说明负向电流过大，相对于当前周期需要在下个周期提前关断开关管Q2。
对于比较器COMP2：电源V1电压添加偏置电压U后和结点SW(即电感器L1一端)的电压分别作为比较器COMP2的反向和正向输入进行比较，如果结点SW(即电感器L1一端)的电压没有出现大于V1-U电压的情况，则输出C2为低电平，说明负向电流过小，相对于当前周期需要在下个周期延后关断开关管Q2。
如果结点SW(即电感器L1一端)的电压没有出现大于电源V1电压的情况，则输出C1为低电平，同时电路结点SW(即电感器L1一端)的电压出现了大于V1-U电压的情况，则输出C2为高电平，相对于当前周期就不需要对开关管Q2进行提前或延后关断操作。
从狭义上讲，开关管的ZVS开通是指开关管在漏极和源极之间电压差为0V时开通开关管；从广义上讲，开关管的ZVS开通是指开关管在漏极和源极之间 电压差低于某一电压时开通开关管。根据电路的实际调试结果，狭义ZVS开通和广义ZVS开通差别很小，本发明正是利用广义ZVS，只要结点SW(即电感器L1的一端)的电压在开关管Q2关断时刻到开关管Q1开通时刻的死区时间段内能达到V1电压至V1-U电压之间就认为开关管Q1可以实现ZVS开通，只需要两个比较单元就可以对开关管Q1是否实现ZVS开通进行判断，然后根据判断的结果在下一个周期对开关管Q2的关断时刻进行调整。由于比较的速度特别快，因此本发明在开关频率比较高的场合特别适用，由于核心器件是比较器，所以相对于申请号为13/027,830的发明专利，具有电路简单易实现，成本低，易高频应用，能最大限度地减少损耗，提高电源效率。
图9所示为第一实施例工作时序，假设电源V1的电压大于电源V3的电压，具体如下：
t0～t1阶段：在t0时刻开关管Q1导通，电感器L1两端的电压为V1-V3，对电感器L1励磁，电感器L的电流IL上升，在t1时刻关断开关管Q1；
t1～t2阶段：开关管Q1关断后，电感器L的电流IL给开关管Q1的输出电容Coss1充电，给开关管Q2的输出电容Coss2放电。在t2时刻电路结点SW(即电感器L一端)的电压由V1降为V2，开关管Q2实现ZVS开通；
t2～t4阶段：电感器L两端的电压为V3-V2，对电感器L1去磁，电流IL下降，在t3时刻降为0A，在t4时刻关断开关管Q2；
t4～t0+T阶段：电感器L的电流IL给开关管Q2的输出电容Coss2充电，给开关管Q1的输出电容Coss1放电，在t0+T时刻开关管Q1开通。从t4至t0+T时刻当电路结点SW(即电感器L1一端)的最高电压在V1-U至V1之间，根据广义ZVS的定义得：开关管Q1实现了ZVS开通；
本周期结束，下一个工作周期开始，重复上面的阶段。
如果开关管Q2在t′ 4时刻关断，波形用图9中长虚线所示，t′ 4至t0+T时刻电路结点SW(即电感器L1一端)的电压一直低于V1-U，则下一个周期需延长t3至t′ 4的时长，时长的延长按照设定的步进时长进行，每个周期进行累加调整，直至t′ 4至t0+T时刻电路结点SW(即电感器L1一端)的最高电压在V1-U至V1之间。
如果开关管Q2在t″ 4时刻关断，波形用图9中短虚线所示，t″ 4至t0+T时刻电路结点SW(即电感器L1一端)的最高电压大于V1，并且被开关管Q1体二极管D1钳位至V1+Vf，Vf为体二极管D1的导通压降，则下一个周期减小t3至t″ 4的时长，时长的减小按照设定的步进时长进行，每个周期进行累加调整，直至t″ 4至t0+T时刻电路结点SW(即电感器L1一端)的最高电压在V1-U至V1之间。
通过比较器COMP1和比较器COMP2来判定t4至t0+T时刻电路结点SW(即电感器L1一端)的最高电压，将最高电压记为SWM4，得到的真值表为图10，根据图10来判定t3至t4时长在下一个周期是延长，减小还是不变，当C1或C2为高电平时，比较器COMP1和比较器COMP2输出连接的二极管用来保持C1或C2的高电平，每个周期对C1和C2复位一次。
由于电路为周期性的工作，上述t0+T中的T代表的含义为一个周期的时间长度。
第二实施例
图11为本发明第二实施例的电路原理图。在第一实施例的基础上，将比较器COMP1和比较器COMP2输入端从直接连接至电源V1和结点SW(即电感器L1一端)改为通过分压电路间接连接，并且用稳压器件Z1来代替电压源U，通过分压电路主要解决电源V1和电感器L1的一端电压超过比较单元输入端最大承受电压的问题。
第二实施例工作时序与第一实施例工作时序相似，只是电源V1和电感器L1的一端进行了比例缩小，并且用稳压器件Z1的额定稳压值Z来等效替代第一实施例中电压源U的电压U。其它内容在此不再赘述。
第三实施例
图12为本发明的第三实施例的电路原理图。所包含的器件与第一实施例基本相同，主要差异在于连接关系：比较器COMP1的反向端和电压源U的正向端连接到结点SW(即电感器L1一端)，比较器COMP1的正向端和比较器COMP2的正向端连接到电源V2。
第三实施例依然利用广义ZVS的原理，整个工作过程和原理与第一实施例相似，差异在于通过比较器COMP1和比较器COMP2来判定图9中t1至t2时刻 电路结点SW(即电感器L1一端)的最低电压，将最低电压记为SWm1，得到的真值表为图13，由真值表来判定t0至t1时长在下一个周期是延长，减小还是不变，当C1或C2为高电平时，比较器COMP1和比较器COMP2输出连接的二极管用来保持C1或C2的高电平，每个周期对C1和C2复位一次。其它内容在此不再赘述。
上述实施方式不应视为对本发明的限制，本发明的保护范围应当以权利要求所限定的范围为准。对于本技术领域的普通技术人员来说，在不脱离本发明的精神和范围内，还可以做出若干等同替换、改进和润饰，如根据应用场合的不同，通过器件的简单串并联等手段对电路微调，这些改进和润饰也应视为本发明的保护范围。

Claims (16)

  1. 一种自适应ZVS电路，其特征在于：包括电源V1，电源V2，电源V3，开关管Q1、开关管Q2、电感器L和双比较单元；开关管Q1的漏极和双比较单元的一个输入端连接到电源V1，开关管Q1的源极，开关管Q2的漏极和双比较单元的另一个输入端连接到电感器L1的一端，开关管Q2的源极连接到电源V2，电感器L1的另一端连接到电源V3。
  2. 根据权利要求1所述的自适应ZVS电路，其特征在于：电源V1的电压高于电源V2的电压，电源V3的电压高于电源V2的电压。
  3. 根据权利要求1所述的自适应ZVS电路，其特征在于：所述的电感器L为电感或变压器的一个绕组。
  4. 根据权利要求1所述的自适应ZVS电路，其特征在于：所述的双比较单元为两个比较器。
  5. 根据权利要求4所述的自适应ZVS电路，其特征在于：所述比较器的两个输入端分别连接电源V1和电感器L1的一端。
  6. 根据权利要求4所述的自适应ZVS电路，其特征在于：所述比较器的两个输入端至少其中一个添加偏置电压后分别连接到电源V1和电感器L1的一端。
  7. 根据权利要求4所述的自适应ZVS电路，其特征在于：电源V1和电感器L1的一端分别经过分压电路后再分别连接到比较器的两个输入端。
  8. 根据权利要求7所述的自适应ZVS电路，其特征在于：所述分压电路为若干电阻串联分压电路或串联有电压源、恒流源或稳压器件的若干电阻串联分压电路。
  9. 一种权利要求1-8任一项所述的自适应ZVS电路的控制方法，其特征在于：从开关管Q2关断时刻到开关管Q1开通时刻的时间段内，根据电源V1电压，电感器L1的一端电压和双比较单元得到两路高低电平输出，然后相对于当前周期开关管Q2的关断时刻，由双比较单元的两路高低电平输出来调节开关管Q2在下一个周期保持，提前或延后关断。
  10. 一种自适应ZVS电路，其特征在于：包括电源V1，电源V2，电源V3，开关管Q1、开关管Q2、电感器L和双比较单元；开关管Q1的漏极连接到电源 V1，开关管Q1的源极，开关管Q2的漏极和双比较单元的一个输入端连接到电感器L1的一端，开关管Q2的源极和双比较单元的另一个输入端连接到电源V2，电感器L1的另一端连接到电源V3。
  11. 根据权利要求10所述的自适应ZVS电路，其特征在于：电源V1的电压高于电源V2的电压，电源V3的电压高于电源V2的电压。
  12. 根据权利要求10所述的自适应ZVS电路，其特征在于：所述的电感器L为电感或变压器的一个绕组。
  13. 根据权利要求10所述的自适应ZVS电路，其特征在于：所述的双比较单元为两个比较器。
  14. 根据权利要求13所述的自适应ZVS电路，其特征在于：所述比较器的两个输入端分别连接到电源V2和电感器L1的一端。
  15. 根据权利要求13所述的自适应ZVS电路，其特征在于：所述比较器的两个输入端至少其中一个添加偏置电压后分别连接到电源V2和电感器L1的一端。
  16. 一种权利要求11-15任一项所述的自适应ZVS电路的控制方法，其特征在于：从开关管Q1关断时刻到开关管Q2开通时刻的时间段内，根据电源V2电压，电感器L1的一端电压和双比较单元得到两路高低电平输出，然后相对于当前周期开关管Q1的关断时刻，由双比较单元的两路输出高低电平来调节开关管Q1在下一个周期保持，提前或延后关断。
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