WO2021051289A1 - 像素电路、阵列基板与显示装置 - Google Patents

像素电路、阵列基板与显示装置 Download PDF

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Publication number
WO2021051289A1
WO2021051289A1 PCT/CN2019/106288 CN2019106288W WO2021051289A1 WO 2021051289 A1 WO2021051289 A1 WO 2021051289A1 CN 2019106288 W CN2019106288 W CN 2019106288W WO 2021051289 A1 WO2021051289 A1 WO 2021051289A1
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Prior art keywords
switch
electrically connected
driving
terminal
sub
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PCT/CN2019/106288
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English (en)
French (fr)
Inventor
连振杰
种田贵之
境川亮
井上昌秀
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华为技术有限公司
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Priority to PCT/CN2019/106288 priority Critical patent/WO2021051289A1/zh
Publication of WO2021051289A1 publication Critical patent/WO2021051289A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • This application relates to the field of display driving, in particular to a pixel circuit, an array substrate and a display device.
  • the scan driving circuit is required to provide gate scan signals, which are used to cooperate with the data driving circuit to provide image data signals to drive the pixel unit array arranged in the image display area to perform image display.
  • Each pixel unit includes three sub-pixels of red, green, and blue that perform image display and three driving circuits for driving the three sub-pixels, and each driving element includes a thin film transistor and a capacitor.
  • each sub-pixel needs a complete driving circuit to drive its light emission, which will cause the three driving circuits in each pixel unit to occupy a large space, which will cause the display panel to be unable to meet the high image resolution.
  • the embodiment of the present application provides a pixel circuit with lower power consumption and better display effect.
  • a pixel circuit in an embodiment of the present application, includes a driving circuit and a plurality of sub-pixels.
  • the driving circuit includes a conversion circuit and one or more driving execution circuits, and the conversion circuit is used to receive an analog form. And convert the analog image data signal into a digital image data signal.
  • the drive circuit includes one drive execution circuit, the drive execution circuit is electrically connected to the conversion circuit for receiving the digital image data signal and dividing it according to the digital image data signal
  • the driving current is provided to the plurality of sub-pixels, the plurality of sub-pixels (103) are driven to perform image display.
  • the driving circuit includes a plurality of the driving execution circuits
  • the plurality of the driving execution circuits and the plurality of the sub-pixels are one-to-one, and each of the driving execution circuits is electrically connected to the conversion circuit And the corresponding sub-pixels. Since a driving circuit can drive multiple sub-pixels to emit light at the same time to perform image display, the area occupied by the pixel circuit and the number of electronic components of the pixel circuit are effectively reduced, and the area of the pixel circuit and the power consumption during image display are effectively reduced, thereby satisfying The demand for image display resolution makes the image display better.
  • the conversion circuit includes a scan switch, a storage capacitor (and a comparator.
  • the scan switch is turned on when receiving a scan signal to transmit the analog image data signal to all The storage capacitor.
  • the storage capacitor is electrically connected to the first phase input terminal of the comparator, and is used to receive and store the analog image data signal and load it to the comparator.
  • the second of the comparator The phase input terminal receives a first reference signal, and the first reference signal is a ramp signal.
  • the comparator is based on the comparison result of the voltage value in the analog image data signal and the first reference signal.
  • the pulse signal output terminal of the device outputs a digital pulse signal, and the digital pulse signal represents the digital image data signal.
  • the comparator can accurately and accurately output the pulse signal corresponding to the duty cycle of the image data signal, and then accurately convert the analog image data signal into the corresponding digital form.
  • the pulse signal of the image data signal By comparing the image data signal with the first reference signal as the ramp signal, the comparator can accurately and accurately output the pulse signal corresponding to the duty cycle of the image data signal, and then accurately convert the analog image data signal into the corresponding digital form.
  • the pulse signal of the image data signal can accurately and accurately output the pulse signal corresponding to the duty cycle of the image data signal, and then accurately convert the analog image data signal into the corresponding digital form.
  • the first reference signal is a triangular wave signal, so as to accurately output pulse signals with different duty cycles according to the image data signal.
  • the scan switch is a P-type thin film transistor
  • the gate of the P-type thin film transistor is used to receive the scan signal
  • the source of the P-type thin film transistor is used to receive an image data signal
  • the drain of the P-type thin film transistor is electrically connected to the first phase input terminal through a data output node
  • the storage capacitor is electrically connected between the data output node and the ground terminal.
  • the scan switch is an N-type thin film transistor, and the gate of the N-type thin film transistor is used to receive the scan signal; the source of the N-type thin film transistor is used to receive image data signals
  • the drain of the N-type thin film transistor is electrically connected to the first phase input terminal through a data output node, and the storage capacitor is electrically connected between the first driving voltage terminal and the data output node.
  • the scan switch is an N-type thin film transistor with a small leakage current, which results in low power consumption and can accurately maintain the voltage stability of the data output node (Ncst).
  • the first phase input terminal is an inverting input terminal
  • the second phase input terminal is a non-inverting input
  • the voltage value of the first reference signal gradually decreases and then gradually increases, and The voltage value increases and decreases at the same speed.
  • the pulse signal when the voltage value of the first reference signal is less than the analog image data signal, the pulse signal is at a low level; when the voltage value of the first reference signal is greater than the In the case of an image data signal in an analog form, the pulse signal is at a high potential.
  • the first reference signal with a symmetrical triangular waveform can more accurately output the pulse signal corresponding to the duty cycle according to the image data signal.
  • the comparator includes a first input switch, a second input switch, a first mirror switch, a second mirror switch, a first output switch, a second output switch, and a first reference switch.
  • the first input switch, the second input switch, the first reference switch (and the first output switch are P-type thin film transistors, the first mirror switch, the second mirror switch, and the second output switch are N-type thin film transistors.
  • the first The gate of the input switch is electrically connected to the first phase input terminal, the source of the first input switch is electrically connected to the first reference switch, and the drain of the first input switch is electrically connected to the first mirror Switch.
  • the gate of the second input switch is electrically connected to the second phase input terminal, the source of the second input switch is electrically connected to the first reference switch, and the drain of the second input switch Is electrically connected to the second mirror switch.
  • the gate and drain of the first mirror switch are directly electrically connected and electrically connected to the drain of the first input switch, and the gate of the first mirror switch It is electrically connected to the gate of the second mirror switch, and the source of the first mirror switch is electrically connected to the first low voltage terminal.
  • the drain of the second mirror switch is electrically connected to the second input
  • the drain of the switch, the source of the second mirror switch is electrically connected to the first low voltage terminal, the drain of the second mirror switch and the drain of the second input switch are simultaneously electrically connected to the comparator Intermediate node.
  • the gate of the first reference switch receives a reference voltage
  • the drain of the first reference switch is electrically connected to the first input switch and the second input switch
  • the source of the first reference switch The pole is electrically connected to the first driving voltage terminal, and the reference voltage controls the first reference switch to be in a normally open state.
  • the gate of the first output switch is electrically connected to the comparison intermediate node, and the first The source of the output switch is electrically connected to the first driving voltage terminal, and the drain of the first output switch is electrically connected to the pulse output terminal.
  • the gate of the second output switch is electrically connected to the middle At the node, the source of the second output switch is electrically connected to the first low voltage terminal, and the drain of the second output switch is electrically connected to the pulse signal output terminal.
  • the comparator further includes a comparison reset switch, the comparison reset switch is electrically connected to the pulse signal output terminal and the first low voltage terminal, when the comparison reset switch is controlled by the reset signal When the bottom is turned on, the pulse signal output terminal is controlled to stop outputting the pulse signal.
  • the comparison reset switch can accurately control the time when the comparator outputs the pulse signal.
  • the comparator includes a first input switch, a second input switch, a first mirror switch, a second mirror switch, and a first output switch, a second output switch, and a first reference switch.
  • the first input switch, the second input switch, the first reference switch, and the first output switch are N-type thin film transistors, and the first mirror switch, the second mirror switch, and the second output switch are P-type thin film transistors.
  • the gate of the first input switch is electrically connected to the first phase input terminal, the source of the first input switch is electrically connected to the first reference switch, and the drain of the first input switch is electrically connected Connect the first mirror switch.
  • the gate of the second input switch is electrically connected to the second phase input terminal, the source of the second input switch is electrically connected to the first reference switch, and the drain of the second input switch is electrically connected Connect the intermediate nodes.
  • the gate and drain of the first mirror switch are directly and electrically connected to the drain of the first input switch at the same time, and the gate of the first mirror switch is electrically connected to the gate of the second mirror switch.
  • the electrode is electrically connected, and the source of the first mirror switch is electrically connected to the first driving voltage terminal.
  • the drain of the second mirror switch is electrically connected to the drain of the second input switch, the source of the second mirror switch is electrically connected to the first driving voltage terminal, and the second mirror switch is electrically connected to the drain of the second input switch.
  • the drain and the drain of the second input switch are electrically connected to the comparison intermediate node at the same time.
  • the gate of the first reference switch receives a reference voltage
  • the drain of the first reference switch is electrically connected to the first input switch and the second input switch
  • the source of the first reference switch is electrically connected
  • the first low voltage terminal is connected, and the reference voltage controls the first reference switch to be in a normally open state.
  • the gate of the first output switch is electrically connected to the comparison intermediate node
  • the source of the first output switch is electrically connected to the first driving voltage terminal
  • the drain of the first output switch is electrically connected to The pulse output terminal.
  • the gate of the second output switch is electrically connected to the comparison intermediate node
  • the source of the second output switch is electrically connected to the first low voltage terminal
  • the drain of the second output switch is electrically connected to The pulse signal output terminal.
  • the comparator further includes a comparison reset switch, the comparison reset switch is electrically connected to the pulse signal output terminal and the first driving voltage terminal, when the comparison reset switch is resetting When the signal control is turned on, the pulse signal output terminal is controlled to stop outputting the pulse signal.
  • the first phase input terminal is a non-inverting input terminal
  • the second phase input terminal is an inverting input terminal
  • the voltage of the first reference signal gradually increases from a low potential to a high potential Then it gradually decreases from the high potential to the low potential, and the voltage value decreases at the same speed as the increase.
  • the comparator includes a first input switch, a second output switch, a first reference switch, a first output switch, a first mirror switch, a second mirror switch, and a second output switch.
  • the first input switch, the second input switch, the first reference switch, and the first output switch are P-type thin film transistors, and the first mirror switch, the second mirror switch, and the second output switch are N-type thin film transistors.
  • the gate of the first input switch is electrically connected to the second phase input terminal, the source of the first input switch is electrically connected to the first reference switch, and the drain of the first input switch is electrically connected Connect the first mirror switch.
  • the gate of the second input switch is electrically connected to the first phase input terminal, the source of the second input switch is electrically connected to the first reference switch, and the drain of the second input switch is electrically connected Connect the second mirror switch.
  • the gate and drain of the first mirror switch are directly and electrically connected to the drain of the first input switch at the same time, and the gate of the first mirror switch is electrically connected to the gate of the second mirror switch.
  • the electrode is electrically connected, and the source of the first mirror switch is electrically connected to the first low voltage terminal.
  • the drain of the second mirror switch is electrically connected to the drain of the second input switch, the source of the second mirror switch is electrically connected to the first low voltage terminal, and the second mirror switch is electrically connected to the drain of the second input switch.
  • the drain and the drain of the second input switch are electrically connected to the comparison middle node at the same time.
  • the gate of the first reference switch receives a reference voltage
  • the drain of the first reference switch is electrically connected to the first input switch and the second input switch
  • the source of the first reference switch is electrically connected
  • the first driving voltage terminal is connected, and the reference voltage controls the first reference switch to be in a normally open state.
  • the gate of the first output switch is electrically connected to the comparison intermediate node
  • the source of the first output switch is electrically connected to the first driving voltage terminal
  • the drain of the first output switch is electrically connected to The pulse output terminal.
  • the gate of the second output switch is electrically connected to the comparison intermediate node
  • the source of the second output switch is electrically connected to the first low voltage terminal
  • the drain of the second output switch is electrically connected to The pulse signal output terminal.
  • the comparator further includes a hysteresis unit, the hysteresis unit is electrically connected to the pulse signal output terminal, the first phase input terminal and the data output node, and the hysteresis unit is used for When the voltage difference between the signals received by the first phase input terminal and the second phase input terminal is controlled to be greater than a first threshold or less than a second threshold, the potential of the pulse signal changes, and the first threshold Less than the second threshold.
  • the hysteresis unit electrically includes a first hysteresis resistor and a second hysteresis resistor, the first hysteresis resistor is electrically connected between the first phase input terminal and the data output node), and the first hysteresis resistor Two hysteresis resistors are electrically connected between the first phase input terminal and the pulse signal output terminal.
  • the hysteresis unit delays the output pulse signal time when the image data signal is compared, thereby effectively eliminating the influence of the image data signal on the output pulse signal when the image data signal has noise, and ensuring the accuracy and stability of the pulse signal output.
  • the drive execution circuit includes a drive control terminal, a first drive transistor, a drive capacitor, a first reset switch, and a drive output terminal.
  • the driving capacitor is electrically connected between the first driving voltage terminal and the driving control terminal, and the driving capacitor is used to gradually store or release the pulse signal within a preset time period, and maintain the voltage of the driving control terminal and the driving control terminal.
  • the pulse signal voltage value is the same.
  • the first driving transistor is electrically connected to the first driving voltage terminal, the driving control terminal, and the driving output terminal, and the first driving transistor is controlled by the pulse signal provided by the driving control terminal Turning on or off, when the first driving transistor is turned on, the first driving transistor cooperates with the driving voltage provided by the first driving voltage terminal to output the driving current from the driving output terminal.
  • the first reset switch is electrically connected to the drive output terminal, and is used to provide a reset voltage to the drive output terminal when the sub-pixel (stops image display).
  • the drive execution circuit can accurately provide a drive current to the drive output terminal according to the pulse signal. Each sub-pixel can drive the sub-pixel to accurately emit light to display an image.
  • the drive execution circuit further includes a compensation unit electrically connected to the drive control terminal for compensating for the threshold voltage drift of the first drive transistor, and the compensation unit includes A first compensation transistor, which is electrically connected between the drive control terminal and the drive output terminal, and is used to store the threshold voltage of the first drive transistor in the drive control terminal in advance, When the first driving transistor outputs the driving current, the threshold voltage stored in the driving control terminal (Ndrv) cancels the threshold voltage in the driving current.
  • the compensation unit further includes a second compensation transistor, which is electrically connected to the drive input terminal, and is used to combine the auxiliary voltage with the auxiliary voltage when the threshold voltage of the first drive transistor is stored in the drive control terminal.
  • the threshold voltage is synchronously applied to the drive control terminal.
  • the compensation unit can effectively eliminate the influence of the threshold voltage drift of the first driving transistor itself on the driving current, that is, the driving current can accurately drive the sub-pixels to accurately emit light and ensure the accuracy of the displayed image.
  • the drive execution circuit further includes a second reset switch, and the second reset switch is electrically connected between the drive control terminal and the first low voltage terminal for receiving When the reset signal is reached, the first low voltage terminal (the provided low voltage is loaded to the drive control terminal to reset the drive control terminal.
  • the second reset switch can accurately reset the drive control terminal, thereby ensuring that the sub-pixel The accuracy of the drive current output during the image display period.
  • the drive execution circuit further includes a pulse receiving switch, which is electrically connected to the conversion circuit for receiving the pulse signal, and selectively switches the pulse signal according to the control of the pulse signal.
  • the driving voltage is provided to the first driving transistor, and when the pulse receiving switch is turned on under the control of the pulse signal, the first driving voltage is transmitted to the first driving transistor through the pulse receiving switch When the pulse receiving switch is turned off under the control of the pulse signal, the driving voltage stops transmitting to the first driving transistor.
  • the pulse receiving switch can accurately provide the driving voltage to the first driving transistor according to the pulse signal, so that the first driving transistor can accurately provide the driving current.
  • the first driving transistor, the pulse receiving switch, the first compensation transistor, and the second compensation transistor are P-type thin film transistors
  • the first reset switch and the second reset switch are N-type thin film transistor
  • each sub-pixel includes a selection switch and a light-emitting element
  • the light-emitting element is electrically connected to the drive output terminal of the drive execution circuit through the selection switch, and when the selection switch is turned on under the control of a selection signal ,
  • the driving current is transmitted to the light-emitting element through the selection switch to drive the light-emitting element to emit light and display the image data
  • the selection switch is a P-type thin film transistor
  • the light-emitting element electrically passes through the selection The switch is electrically connected between the drive output terminal and the second low voltage terminal.
  • the first driving transistor, the pulse receiving switch, the first compensation transistor and the second compensation transistor, and the selection switch Tw which are P-type thin film transistors on the driving circuit are all P-type thin film transistors, so that the driving execution circuit and the sub-pixel are all P-type thin film transistors.
  • the threshold voltage drift in is small.
  • the first reset switch and the second reset switch on the other branches are N-type thin film transistors, and the leakage current is small and the control response speed is faster.
  • the first driving transistor, the pulse receiving switch, the first compensation transistor, and the second compensation transistor are N-type thin film transistors
  • the first reset switch and the second reset switch are P-type thin film transistor
  • each sub-pixel includes a selection switch and a light-emitting element
  • the light-emitting element is electrically connected to the drive output end of the drive execution circuit through the selection switch, and when the selection switch is turned on under the control of a selection signal ,
  • the driving current is transmitted to the light-emitting element through the selection switch to drive the light-emitting element to emit light and display the image data
  • the selection switch is an N-type thin film transistor
  • the light-emitting element is electrically connected through the selection switch.
  • the driving output terminal and the second driving voltage terminal are electrically connected, and the second driving voltage terminal is used to provide a driving voltage to cooperate with the first driving transistor to provide the driving current.
  • the pixel circuit includes three sub-pixels, and the three sub-pixels receive the image data signal provided by the same data line and receive the scan signal provided by the same scan line, and the scan signal includes Three sub-scanning periods; or,
  • the pixel circuit includes six sub-pixels, the six sub-pixels receive the image data signal provided by the same data line and receive the scan signal provided by the same scan line, and the scan signal includes six sub-scan periods.
  • the three sub-pixels when the pixel circuit includes three sub-pixels, the three sub-pixels respectively emit light of different colors; when the pixel circuit includes six sub-pixels, every two pixels emit light of the same color. Light, the six sub-pixels respectively emit three different colors of light, and any two adjacent sub-pixels emit different colors of light.
  • the pixel circuit when the pixel circuit includes six sub-pixels, at least two adjacent sub-pixels do not emit light in adjacent sub-scan periods, so as to ensure that the light emitted from the pixel circuit is relatively uniform.
  • the conversion circuit includes a storage capacitor, a first preset switch, a second preset switch, and a conversion transistor.
  • the storage capacitor is electrically connected to the data output node, and is used to charge the received image data signal to the data output node to the same potential as the image data signal.
  • the conversion transistor is electrically connected to the data output node, the first driving voltage terminal, and the pulse signal output terminal, and is used to turn on or turn off under the voltage control of the data output node.
  • the first driving voltage is transmitted to the pulse signal output terminal through the conversion transistor, and a high potential is used as the potential of the pulse signal.
  • the first preset switch is electrically connected between the data output node and the pulse signal output terminal, and is used to directly connect the data output node and the pulse signal output terminal under the control of the first preset signal.
  • the second preset switch (Tpe2) is electrically connected between the pulse signal output terminal and the first low voltage terminal, and is used to electrically connect the first low voltage terminal and the pulse signal output terminal under the control of the second preset signal. Turn on, so that the pulse signal output from the pulse signal output terminal is at a low level.
  • the driving execution circuit includes a pulse receiving switch, a first driving transistor and a driving capacitor,
  • the pulse receiving switch is electrically connected between the pulse output terminal, the second driving voltage terminal, and the driving input terminal, and is used for selectively loading the driving voltage to the driving input terminal under the control of the pulse signal output from the pulse output terminal .
  • the first driving transistor is electrically connected to the first driving voltage terminal, the driving control terminal, and the driving output terminal, and the first driving transistor is controlled by the pulse signal provided by the driving control terminal On or off, when the first driving transistor is turned on, the first driving transistor cooperates with the driving voltage provided by the first driving voltage terminal to output the driving current from the driving output terminal.
  • the driving capacitor is electrically connected to the second driving voltage terminal and the driving control terminal, and is used to store and maintain the driving control terminal at a stable potential within a preset time period to control the first driving transistor at a preset time Maintain the conduction within.
  • the conversion circuit directly converts the analog image data signal into a pulse signal corresponding to the duty cycle, and provides the pulse signal to the driving execution circuit, so that the driving circuit has fewer circuit elements and simpler structure, which can further reduce the space occupied by the pixel circuit.
  • the drive execution circuit further includes a first reset switch and a second reset switch.
  • the first reset switch and the second reset switch are electrically connected to the drive control terminal and the drive control terminal, respectively.
  • the output terminal is used to control the drive control terminal and the drive output terminal to reset when the sub-pixel stops displaying images.
  • each sub-pixel includes a selection switch and a light-emitting element.
  • the light-emitting element is electrically connected to the drive execution circuit through the selection switch.
  • the selection switch When the selection switch is turned on under the control of the display selection signal, the light-emitting element is electrically connected to the drive execution circuit.
  • the driving current is transmitted to the light-emitting element through the selection switch to drive the light-emitting element to emit light and display the image data.
  • the drive execution circuit further includes a preset reset switch, which is electrically connected to the drive control terminal, and is used for a reset period before the sub-pixel emits light
  • a preset reset switch which is electrically connected to the drive control terminal, and is used for a reset period before the sub-pixel emits light
  • An auxiliary voltage is applied to the driving control terminal, and the auxiliary voltage is used to control the first driving transistor to be turned on.
  • the drive execution circuit further includes a compensation unit electrically connected to the drive control terminal for compensating for the threshold voltage drift of the first drive transistor, and the compensation unit includes A first compensation transistor and a second compensation transistor.
  • the first compensation transistor is electrically connected between the drive control terminal and the drive output terminal, and is used to store the threshold voltage of the first drive transistor in advance. In the driving control terminal, when the first driving transistor outputs the driving current, the threshold voltage stored in the driving control terminal cancels the threshold voltage in the driving current.
  • the second compensation transistor is electrically connected to the driving input terminal, and is used to load the auxiliary voltage and the threshold voltage to the driving control terminal when the threshold voltage of the first driving transistor is stored in the driving control terminal. end.
  • the pixel circuit includes three sub-pixels or six sub-pixels, and the three pixel units or the six display units receive the image data signal provided by the same data line and receive the same image data signal.
  • the scan signal provided by the scan line, the scan signal includes three sub-scan periods or six sub-scan periods.
  • the three sub-pixels when the pixel circuit includes three sub-pixels, the three sub-pixels respectively emit light of different colors; when the pixel circuit includes six sub-pixels, every two sub-pixels emit light of the same color. Light, the six sub-pixels respectively emit light of three different colors, any two adjacent sub-pixels emit light of different colors, and at least two adjacent sub-pixels do not emit light in adjacent sub-scan periods.
  • the switch and the second compensation switch are P-type thin film transistors, and the light-emitting element in each sub-pixel is electrically connected between the driving output terminal and the second low voltage terminal through the selection switch.
  • the manufacturing process of the P-type thin film transistor is relatively simple, and the threshold voltage is relatively stable.
  • the switch and the second compensation switch are N-type thin film transistors, and the light-emitting element in each sub-pixel is electrically connected between the driving output terminal and the second driving voltage terminal through the selection switch, and the second driving The voltage terminal is used to provide a driving voltage and cooperate with the first driving transistor to provide the driving current.
  • the leakage current of the N-type thin film transistor is small, so that the power consumption is low, and the voltage of the data output node can be accurately maintained.
  • the sub-pixels are Micro-LED display units.
  • an array substrate includes a plurality of the aforementioned pixel circuits for performing image display, a plurality of data lines, and a plurality of scan lines located in a display area.
  • the data lines extend in the first direction and are insulated and arranged at a predetermined distance along the second direction.
  • the data lines are insulated and arranged at a predetermined distance along the second direction.
  • the first direction is perpendicular to the first direction.
  • the data line is used to provide the image data signal
  • the scan line is used to provide the scan signal
  • any two adjacent data lines and any two adjacent scan lines define One pixel unit
  • the pixel unit is provided with one pixel circuit.
  • a display device which includes the aforementioned array substrate.
  • FIG. 1 is a schematic diagram of a planar structure of a display panel in an embodiment of the application
  • FIG. 2 is a schematic diagram of a side structure of the display panel shown in FIG. 1;
  • FIG. 3 is a schematic diagram of the planar structure of the array substrate in the display panel shown in FIG. 2. ;
  • FIG. 4 is a circuit block diagram of any one of the pixel circuits shown in FIG. 3 in the first embodiment of the application;
  • FIG. 5 is a circuit block diagram of any one of the pixel circuits shown in FIG. 3 in the second embodiment of the application;
  • FIG. 6 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 4 in the first embodiment of the application;
  • FIG. 7 is a schematic diagram of the circuit structure of a comparator in the pixel circuit shown in FIG. 6;
  • FIG. 8 is a timing diagram of the comparator shown in FIG. 7 in the first embodiment of the application when it is working;
  • FIG. 9 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the first embodiment of the application.
  • FIG. 10 is a working timing diagram of the pixel circuit shown in FIG. 9;
  • FIG. 11 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the third embodiment of the application;
  • FIG. 12 is a working timing diagram of the pixel circuit shown in FIG. 11;
  • FIG. 13 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the fourth embodiment of the application;
  • FIG. 14 is a working timing diagram of the pixel circuit shown in FIG. 13;
  • FIG. 15 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the fifth embodiment of the application;
  • FIG. 16 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the sixth embodiment of the application;
  • FIG. 17 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the seventh embodiment of the application;
  • FIG. 18 is a circuit block diagram of the pixel circuit shown in FIG. 4 in the eighth embodiment of this application.
  • FIG. 19 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 18;
  • FIG. 20 is a timing diagram of the comparator shown in FIG. 19 when it is working;
  • FIG. 21 is a timing circuit diagram of the pixel circuit shown in FIG. 18;
  • FIG. 22 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the ninth embodiment of this application;
  • FIG. 23 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the tenth embodiment of this application;
  • FIG. 24 is a timing diagram of input and output signals of the hysteresis unit shown in FIG. 23;
  • FIG. 25 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the eleventh embodiment of this application;
  • FIG. 26 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the twelfth embodiment of this application;
  • FIG. 27 is a working timing diagram of a sub-pixel in the pixel circuit shown in FIG. 26;
  • FIG. 28 is a working timing chart of the pixel circuit shown in FIG. 26 during the display period of one frame of image;
  • FIG. 29 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the thirteenth embodiment of this application;
  • FIG. 30 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the fourteenth embodiment of this application;
  • FIG. 31 is a schematic diagram of a specific circuit structure of the pixel circuit shown in FIG. 4 in the fifteenth embodiment of this application.
  • FIG. 1 is a schematic diagram of a planar structure of a display panel 11 in an embodiment of the application.
  • the display panel 11 is used to perform image display.
  • one side of the display panel 11 includes a display area 11a and a non-display area 11b.
  • the display area 11a is used to perform image display
  • the non-display area 11b is arranged around the display area 11a to set other auxiliary components or modules.
  • the display panel 11 can be applied to augmented reality (AR) or Virtual display (Virtual Reality, VR), TV, mobile smart terminal or tablet computer and other electronic products.
  • AR augmented reality
  • VR Virtual display
  • TV mobile smart terminal or tablet computer and other electronic products.
  • FIG. 2 is a schematic diagram of the side structure of the display panel 11 shown in FIG. 1.
  • the display panel 11 includes an array substrate 11c and a counter substrate 11d, and a display medium layer 11e sandwiched between the array substrate 11c and the counter substrate 11d.
  • the display medium in the display medium layer is a Micro-Light Emitting Diode (Micro-LED/u-LED).
  • FIG. 3 is a schematic diagram of the planar structure of the array substrate 11 c in the display panel 11 shown in FIG. 2.
  • the area corresponding to the image display area 11a in the array substrate 11c includes a plurality of n*m pixel units (Pixel) P, m data lines (Data Line) 120, and n scan lines ( Scan Line) 130, m and n are both natural numbers greater than 1.
  • the plurality of data lines 120 are arranged in parallel along the second direction Y, and every two adjacent data lines 120 of the plurality of data lines 120 are separated by a first predetermined distance.
  • the plurality of scan lines 130 are arranged in parallel along the first direction X, and every two adjacent scan lines 130 of the plurality of scan lines 130 are separated by a second predetermined distance.
  • the multiple data lines 120 are insulated from each other, the multiple scan lines 130 are insulated from each other, and the multiple scan lines 130 and the multiple data lines 120 are insulated from each other. It should be noted that the first direction X and the second direction Y are perpendicular to each other.
  • the m data lines 120 are respectively defined as Da1, Da2,..., Dam according to the position order;
  • the n scan lines 130 are respectively defined as Ga1, Ga2,... Gan according to the position order.
  • Any two adjacent scan lines 130 and any two adjacent data lines 120 define an area of a pixel unit P, and a pixel circuit (PC) is arranged in the area of the pixel unit P, and each pixel circuit PC A scan line 130 extending along the first direction X and a data line 120 extending along the second direction Y are sexually connected.
  • PC pixel circuit
  • the non-display area 11b is provided with a timing control circuit 101 for driving the pixel circuit PC for image display, a data driver circuit 102, and a scan driver circuit 103.
  • the timing control circuit 101, the data drive execution circuit 102 and the scan drive circuit 103 are all disposed on the array substrate 11c.
  • the data drive execution circuit 102 is electrically connected to the plurality of data lines 120, and is used to transmit image data (Data) to be displayed to the plurality of pixel units P through the plurality of data lines 120 in an analog form.
  • the scan driving circuit 103 is used for electrically connecting with the plurality of scan lines 130, and is used for outputting a scan signal through the plurality of scan lines 130, and the scan signal is used to control when the pixel circuit PC receives image data. Wherein, the scan driving circuit 103 sequentially outputs scan signals G1, G2, ..., Gn from the scan lines Ga1, Ga2,..., Gan according to the sequence of the positions of the plurality of scan lines 130.
  • j is a natural number greater than or equal to 1 and less than or equal to n.
  • the timing control circuit 101 is electrically connected to the data drive execution circuit 102 and the scan drive circuit 103, respectively, and is used to control the working timing of the data drive execution circuit 102 and the scan drive circuit 103, that is, to respectively output corresponding timing control signals to the data drive.
  • the execution circuit 102 and the scan driving circuit 103 control when to output the corresponding scan signal and image data.
  • the circuit elements in the scan driving circuit 103 and the pixel units P in the display panel 11 are manufactured in the display panel 11 using the same process, and the process may be, for example, a GOA (Gate Driver on Array) process.
  • GOA Gate Driver on Array
  • FIG. 4 is a circuit block diagram of any one pixel circuit 100 among the plurality of pixel circuits PC shown in FIG. 3 in the first embodiment of the application.
  • the pixel circuit 100 includes a driving circuit DC (Driving Execution Circuit) and K sub-pixels 103.
  • the drive circuit DC includes a conversion circuit 101 and a drive execution circuit 102.
  • K is a natural number, greater than or equal to 2.
  • the conversion circuit 101 is electrically connected to the data line Di and the scan line Gaj, and is used to receive the scan signal Gj from the scan line Gaj and work under the control of the scan signal Gj. At the same time, it receives the analog image data signal Vdata from the data line Di, and The analog image data signal Vdata is converted into a digital pulse signal Vout.
  • i is a natural number greater than or equal to 1 and less than or equal to m.
  • the pulse width (duty ratio) of the pulse signal Vout corresponds to the voltage of the image data signal Vdata.
  • the driving execution circuit 102 is electrically connected to the conversion circuit 101 and the K sub-pixels 103 for receiving the digital pulse signal Vout, and providing a driving current Idrv to the plurality of sub-pixels 103 in a time division according to the pulse signal Vout.
  • the K sub-pixels 103 emit light according to the received driving current Idrv, thereby performing image display corresponding to the image data signal Vdata.
  • the analog signal is a continuously changing voltage or current
  • the digital signal is a voltage or current having at least two fixed values, for example, a digital signal having only a high potential and a low potential voltage. , Only a digital signal with a drive current of 1A or a current of 0A.
  • a pixel circuit 100 includes a plurality of sub-pixels 103, that is, a conversion circuit 101 can provide a plurality of sub-pixels 103 with a pulse signal Vout corresponding to an analog image data signal at the same time, and then time-sharing according to the pulse signal Vout
  • the driving current Idrv is provided to drive the sub-pixel 103 to emit corresponding light.
  • the number of conversion circuits 101 to be provided in the array substrate 11c is effectively reduced, the wiring difficulty is reduced, the resolution of the display panel is improved, and the power consumption of each pixel unit P is effectively reduced.
  • FIG. 5 is a circuit block diagram of any one pixel circuit 200 among the plurality of pixel circuits PC shown in FIG. 3 in the second embodiment of the application.
  • the pixel circuit 200 includes a drive circuit DC (Drive Circuit, DC) and K sub-pixels 103.
  • the driving circuit DC includes a conversion circuit 101 and K driving execution circuits 102.
  • K is a natural number and greater than or equal to 2.
  • the conversion circuit 101 is electrically connected to the data line Dai and the scan line Gaj, and is used to receive the scan signal Gj from the scan line Gj and work under the control of the scan signal Gj. Both receive the analog image data signal Vdata from the data line Dai, and The analog image data signal Vdata is converted into a digital pulse signal Vout.
  • i is a natural number greater than or equal to 1 and less than or equal to m.
  • the pulse width (duty ratio) of the pulse signal Vout corresponds to the voltage of the image data signal Vdata.
  • each drive execution circuit 102 and the K sub-pixels 103 are electrically connected in a one-to-one manner.
  • each drive execution circuit 102 is also electrically connected to the conversion circuit 101, that is, one drive execution circuit 102.
  • it is electrically connected between the conversion circuit 101 and a sub-pixel 103.
  • the K driving execution circuits 102 receive the digital pulse signal Vou in a time-sharing manner, and provide a driving current Idrv to the respective corresponding sub-pixels 103 according to the pulse signal Vou.
  • the K sub-pixels 103 emit light according to the received driving current, thereby performing image display corresponding to the image data signal.
  • FIG. 6 is a schematic diagram of the circuit structure of the pixel circuit 100 shown in FIG. 4 in the first embodiment of the application.
  • the conversion circuit 101 includes a scan switch T1, a storage capacitor Cst1, and a comparator CP1.
  • the scan switch T1 is turned on when receiving the scan signal Gj to transmit the image data signal in the analog form to the first storage capacitor Cst1.
  • the scan switch T1 is a P-type thin film transistor (TFT).
  • the gate g of the P-type thin film transistor is electrically connected to the scanning line Gaj for receiving the scanning signal Gj;
  • the source electrode s of the P-type thin film transistor is electrically connected to the data line Di for receiving the analog form Image data signal Vdata;
  • the drain d of the P-type thin film transistor is electrically connected to the data output node Ncst for providing the received image data signal Vdata to the comparator CP1.
  • the first storage capacitor Cst1 is electrically connected between the data output node Ncst and the ground terminal GND, and is electrically connected to the first phase input terminal Vin1 of the comparator CP1 through the data output node Ncst, for receiving and storing the analog
  • the morphological image data signal Vdata is loaded to the comparator CP1.
  • the second phase input terminal Vin2 of the comparator CP1 is used to receive the first reference signal Vsweep, and the first reference signal number Vsweep is a ramp signal.
  • the first phase input terminal Vin1 is an inverting input terminal
  • the second phase input terminal Vin2 is a non-inverting input terminal.
  • the comparator CP1 outputs a digital pulse signal Vout from the pulse signal output terminal Vout of the comparator CP1 according to the comparison result of the analog image data signal Vdata and the voltage value in the first reference signal Vsweep.
  • the pulse signal Vout represents the digital image data signal, that is, the waveform of the pulse signal Vout and the image data signal Vdata correspond to each other at high and low potentials.
  • the analog image data signal Vdata is also represented by a voltage value, so the comparator CP1 compares the analog image data signal Vdata and the first reference signal Vsweep. The magnitude of the voltage value.
  • the driving execution circuit 102 includes a driving control terminal Ndrv, a first driving transistor Td1, a driving capacitor Cd1, a first reset switch Tr1, and a driving output terminal Ncon.
  • the drive control terminal Ndrv is electrically connected to the pulse signal output terminal Vout for receiving the pulse signal Vout.
  • the driving execution circuit 102 outputs a corresponding driving current Idrv to the sub-pixel 103 from the driving output terminal Ncon according to the duty ratio of the pulse signal Vout.
  • the driving capacitor Cd1 is electrically connected between the first driving voltage terminal VDD1 and the driving control terminal Ndrv.
  • the driving capacitor Cd1 is used to gradually store or release the pulse signal Vout within a preset period of time, and maintain the voltage of the driving control terminal Ndrv and the voltage value of the pulse signal Vout to be the same.
  • the first driving transistor Td1 is electrically connected to the first driving voltage terminal VDD1, the driving control terminal Ndrv, and the driving output terminal Ncon.
  • the first driving transistor Td1 is turned on or turned off under the control of the pulse signal Vout provided by the driving control terminal Ndrv.
  • the first driving transistor Td1 When the first driving transistor Td1 is turned on, the first driving transistor Td1 cooperates with the driving voltage VDD provided by the first driving voltage terminal VDD1 to output a driving current Idrv from the driving output terminal Ncon.
  • the first driving transistor Td1 stops outputting the driving current Idrv from the driving output terminal Ncon.
  • the first driving transistor Td1 is a P-type thin film transistor.
  • the gate of the P-type thin film transistor is electrically connected to the driving control terminal Ndrv to receive the pulse signal Vout;
  • the source of the P-type thin film transistor is electrically connected to the first driving voltage terminal VDD1 for receiving the driving voltage VDD;
  • the drain (not shown) of the thin film transistor TFT is electrically connected to the driving output terminal Ncon.
  • the first reset switch Tr1 is electrically connected to the drive output terminal Ncon, and is used to provide a reset voltage to the drive output terminal Ncon according to the reset signal Vrst when the sub-pixel 103 stops displaying images (reset time period) to ensure that the drive output terminal Ncon is maintained at
  • the reset state ensures that the sub-pixel 103 accurately receives the image data signal Vdata during the input period of the image data signal Vdata.
  • the reset voltage is used to drive the output terminal Ncon to maintain the reset state.
  • the reset voltage may be a low reference voltage Vss.
  • the first reset switch Tr1 is an N-type thin film transistor (TFT), and the gate (not shown) of the thin film transistor as the first reset switch Tr1 is used to receive the reset signal Vrst; as the first reset switch Tr1
  • the source (not shown) of the thin film transistor is electrically connected to the first low voltage terminal Vss1 for receiving the low reference voltage Vss; the drain (not shown) of the thin film transistor as the first reset switch Tr1 is electrically connected to The drive output terminal Ncon is used to output the reset voltage to the drive output terminal Ncon during the reset period.
  • the reset voltage is the low reference voltage Vss.
  • the sub-pixel 103 When the sub-pixel 103 receives the selection signal WT, it receives the driving current Idrv from the driving output terminal Ncon and emits light to perform image display.
  • Each sub-pixel 103 includes a selection switch Tw and a light-emitting element (EM).
  • the selection switches Tw in the plurality of sub-pixels 103 are marked in the order of Tw1, Tw2,..., Twk , And the light-emitting elements in the plurality of sub-pixels 103 are sequentially marked in the order of EM1, EM2, ..., EMK.
  • K is an integer greater than or equal to 2.
  • the selection switch Twi and the light-emitting element EMi are located in the same sub-pixel 103, and i is any integer between 1 and K. For example, as shown in FIG.
  • the selection switch Tw1 and the light-emitting element EM1 are located in the same sub-pixel 103, and so on, the selection switch Twn and the light-emitting element EMn are located in the same sub-pixel 103.
  • the sub-pixels 103 differ only in the color of the light emitted by the light-emitting element EM, and the rest of the circuit structure and working principle are the same.
  • circuit structure of the first sub-pixel 103 on the left in FIG. 6 is taken as an example.
  • the sub-pixel 103 includes a selection switch Tw1 and a light-emitting element EM1.
  • the light emitting element EM1 is located between the selection switch TW1 and the second low voltage terminal Vss2, and is electrically connected to the driving output terminal Ncon through the selection switch TW1.
  • the second low voltage terminal Vss2 is used to provide a low reference voltage Vss.
  • the low reference voltage Vss provided by the first low voltage terminal Vss1 and the second low voltage terminal Vss2 is the same, for example, -3V.
  • the selection switch Tw1 is turned on or off under the control of the selection signal WT1.
  • the selection switch Tw1 is turned on, the driving current Idrv is loaded into the light-emitting element EM1 through the selection switch Tw1, thereby driving the light-emitting element EM1 to emit light and display the image Data signal Vdata.
  • the selection switch Tw1 can be provided by the timing control circuit 101 shown in FIG. 3.
  • the selection switch Tw1 is a P-type thin film transistor
  • the gate of the P-type thin film transistor receives the selection signal WT1
  • the source of the P-type thin film transistor is electrically connected to the driving output terminal Ncon
  • the drain of the P-type thin film transistor is The pole is electrically connected to the light-emitting element EM1.
  • the anode of the light emitting element EM1 is electrically connected to the drain of the thin film transistor as the selection switch Tw1, and the anode of the light emitting element EM1 is electrically connected to the second low voltage terminal Vss2.
  • FIG. 7 is a schematic diagram of the circuit structure of the comparator CP1 in the pixel circuit 100 shown in FIG. 6.
  • the comparator CP1 includes a first input switch Tin1, a second input switch Tin2, a first mirror switch Tmi1, a second mirror switch Tmi2, a first reference switch Trf1, a first output switch Tou1, and a second output switch Tou2.
  • the first input switch Tin1, the second input switch Tin2, the first reference switch Trf1, and the first output switch Tou1 are P-type thin film transistors.
  • the first mirror switch Tmi1, the second mirror switch Tmi2, and the second output switch Tou2 are N-type thin film transistors.
  • the gate of the first input switch Tin1 is electrically connected to the first phase input terminal Vin1
  • the source of the first input switch Tin1 is electrically connected to the first reference switch Trf1
  • the drain of the first input switch Tin1 is electrically connected to the first mirror switch Tmi1.
  • the gate of the second input switch Tin2 is electrically connected to the second phase input terminal Vin2, the source of the second input switch Tin2 is electrically connected to the first reference switch Trf1, and the drain of the second input switch Tin2 is electrically connected to the second mirror switch Tmi2.
  • the gate and drain of the first mirror switch Tmi1 are directly electrically connected and both are electrically connected to the drain of the first input switch Tin1, and the gate of the first mirror switch Tmi1 is electrically connected to the gate of the second mirror switch Tmi2 ,
  • the source of the first mirror switch Tmi1 is electrically connected to the first low voltage terminal Vss1.
  • the drain of the second mirror switch Tmi2 is electrically connected to the drain of the second input switch Tin2, and the source of the second mirror switch Tmi2 is electrically connected to the first low voltage terminal Vss1.
  • the drain of the second mirror switch Tmi2 and the drain of the second input switch Tin2 are both electrically connected to the comparison intermediate node Nmin.
  • the gate of the first reference switch Trf1 receives the reference voltage Vrf
  • the drain of the first reference switch Trf1 is electrically connected to the first input switch Tin1 and the second input switch Tin2
  • the source of the first reference switch Trf1 is electrically connected to the first driver Voltage terminal VDD1.
  • the reference voltage Vref controls the first reference switch Trf1 to be in a normally open state, that is, the reference voltage Vref outputs a low-level voltage signal after the display panel 11 is powered on to control the first reference switch Trf1 to be always on.
  • the gate of the first output switch Tou1 is electrically connected to the comparison intermediate node Nmid, the source of the first output switch Tou1 is electrically connected to the first driving voltage terminal VDD1, and the drain of the first output switch Tou1 is electrically connected to the pulse output terminal Vout.
  • the gate of the second output switch Tou2 is electrically connected to the comparison intermediate node Nmid, the source of the second output switch Tou2 is electrically connected to the first low voltage terminal Vss1, and the drain of the second output switch Tou2 is electrically connected to the pulse signal output terminal Vout .
  • FIG. 8 is a timing diagram of the comparator CP1 shown in FIG. 7 in the first embodiment of the application when it is working.
  • each pixel circuit 100 has a scanning period T (not shown in FIG. 8, but the scanning period T is shown in FIG. 10, so please refer to the description in FIG. 10). Show to understand).
  • the sub-scanning period Ts further includes a data writing period Ha and a light emitting period He that are continuous in time and have no interval.
  • the comparator CP1 first, in conjunction with FIGS. 6-8, it will be specifically explained in the sub-scanning period Ts corresponding to one sub-pixel that the comparator CP1 operates in two time periods: the data writing period Ha and the light-emitting period He. The specific working process and working principle.
  • the scan line Gaj provides the scan signal Gj to the pixel circuit 100, and the scan switch T1 is at the scan signal (the scan signal is at a low potential) It is turned on under the control of the analog form of the image data signal Vdata to transmit the data output node Ncst.
  • the image data signal Vdata gradually increases the voltage Vcst of the data output node Ncst by charging the storage capacitor Cst1.
  • the first reference signal Vsweep enters the ramp signal phase, that is, the first reference signal Vsweep gradually changes from a low potential at a constant speed and a constant amplitude.
  • the principle that the comparator CP1 outputs the pulse signal Vout according to the magnitude of the first reference signal Vsweep and the image data signal Vdata is described.
  • the driving currents of the second input switch Tin2 and the second mirror switch Tmi2 in the comparator CP1 are dominant, so the driving voltage VDD passes through the normally open first reference
  • the switch Trf1 is transmitted to the comparison intermediate node Nmin through the second input switch Tin2, so that the comparison intermediate node Nmin is at a high potential (VDD1), and the second output switch Tou2 is turned on under the control of the high potential, thereby passing the low reference voltage Vss through the first
  • the second output switch Tou2 is applied to the pulse signal output terminal Vout. As a result, the pulse signal output terminal Vout is at a low potential.
  • the driving current of the first input switch Tin1 and the first mirror switch Tmi1 in the comparator CP1 is dominant, so the driving voltage VDD passes through the normally open first reference switch Trf1 is transmitted to the gates of the first mirror switch Tmi1 and the second mirror switch Tmi2 through the first input switch Tin1.
  • the first mirror switch Tmi1 and the second mirror switch Tmi2 are turned on, so that the low reference voltage Vss passes through the second mirror switch Tmi2 is loaded to the comparison intermediate node Nmin, making the comparison intermediate node Nmin a low reference voltage Vss, and the first output switch Tou1 is turned on under the control of the low reference voltage Vss at a low potential, and then the driving voltage VDD is loaded through the first output switch Tou1 To the pulse signal output terminal Vout. As a result, the pulse signal output terminal Vout is at a high potential.
  • the comparator CP1 outputs the corresponding pulse signal Vout according to the comparison result of the magnitude of the first reference signal Vsweep and the image data signal Vdata. Since the pulse signal Vout is in a digital form, the analog image data signal Vdata is converted into Digital form. In addition, the duty ratio of the pulse signal Vout is determined by the image data signal Vdata. Since the drive current Idrv provided by the drive execution circuit 102 is determined by the duty ratio of the pulse signal Vout, the pulse signal Vout can be accurate Characterize the size of the image data signal Vdata.
  • FIG. 9 is a schematic diagram of a specific circuit structure of the pixel circuit 100 shown in FIG. 4 in the first embodiment of the application
  • FIG. 10 is a working timing diagram of the pixel circuit 100 shown in FIG. 9.
  • the comparator CP1 in addition to the specific circuit structure of the comparator CP1 shown in FIG. 7, the comparator CP1 also includes a comparison reset switch Trc, which is used to perform the comparison output pulse signal Vout in the comparator CP1.
  • Trc the control-comparison intermediate node Nmid is at a low potential, so that the pulse signal output terminal Vout is at a high potential and the output of the pulse signal Vout is stopped.
  • the pulse signal Vout is a low potential characterizing that the driving execution circuit 102 provides a driving current Idrv to the display unit 103 to perform image display.
  • the comparison reset switch Trc is an N-type thin film transistor, the gate of the comparison reset switch Trc receives the reset signal Vrst; the source of the comparison reset switch Trc is electrically connected to the first low reference voltage terminal Vss1; the comparison reset switch Trc The drain is electrically connected to the intermediate node Nmid.
  • the control comparison reset switch Trc is turned on, the low reference voltage Vss is applied to the comparison intermediate node Nmid, and the pulse signal output terminal Vout is controlled to stop outputting the pulse signal Vout.
  • the pixel circuit 100 includes six sub-pixels 103, that is, K is 6.
  • the six sub-pixels 103 are respectively a first red sub-pixel R1, a first green sub-pixel G1, a first blue sub-pixel B1, a second red sub-pixel R2, a second green sub-pixel R2, and a second green sub-pixel.
  • the number of sub-pixels 103 can be adjusted according to actual display effect requirements.
  • K can be 2, 3, 4, 5, 7, 8, etc., and is not limited thereto.
  • the light-emitting element EM1 in the first red sub-pixel R1 is used to emit red light; the light-emitting element EM2 in the first green sub-pixel G1 is used to emit green light; the light-emitting element EM3 in the first blue sub-pixel B1 is used to emit blue
  • the light-emitting element EM4 in the second red sub-pixel R2 is used to emit red light; the light-emitting element EM5 in the second green sub-pixel G2 is used to emit green light; the light-emitting element EM6 in the second blue sub-pixel B2 is used Blue light is emitted.
  • two of the sub-pixels emit light of the same color, and the six sub-pixels 103 emit light of three colors in total.
  • the sub-scanning display period Ts of each sub-pixel 103 includes a data writing period Ha and a light emitting period He.
  • the six sub-pixels 103 at least six sub-scanning display periods Ts1 to Ts6 are included.
  • the six sub-pixels 103 receive the driving current Idrv corresponding to the image data signal in a time-sharing manner through the six sub-scanning periods Ts of the scanning signal Gi in one scanning period T to display image data by emitting light.
  • 6 selection signals WT1 to WT6 are provided respectively, and the 6 selection signals WT1 to WT6 and the six sub-scanning periods corresponding to the 6 sub-pixels 103 are one-to-one.
  • the six selection signals WT1 to WT6 the first red sub-pixel R1, the first green sub-pixel G1, the first blue sub-pixel B1, the second red sub-pixel R2, the second green sub-pixel G2, and the second The blue sub-pixel B2 performs image display.
  • a selection signal WT1 is provided to the first red sub-pixel R1, and the selection signal WT1 controls the selection switch Tw1 in the first red sub-pixel R1 to be turned on, thereby turning on the selection switch Tw1 in the first red sub-pixel R1 according to the image data signal.
  • the driving current Idrv is applied to the light emitting element EM1, so that the light emitting element EM1 emits red light according to the signal carrying the red image data.
  • the selection signals WT2 to WT6 are respectively provided to select the first green sub-pixel G1, the first blue sub-pixel B1, the second red sub-pixel R2, the second green sub-pixel G2, and the second blue sub-pixel. Color sub-pixel B2.
  • At least two adjacent sub-pixels 103 in this embodiment are not selected in the adjacent sub-scanning period Ts.
  • the selection signal WT5 is provided to select the second green sub-pixel G2.
  • the selection signal WT3 is provided to select the first blue sub-pixel B1.
  • the selection signal WT4 is provided to select the second red sub-pixel R2.
  • the selection signal WT2 is provided to select the first green sub-pixel G1.
  • the selection signal WT6 is provided to select the second blue sub-pixel B2.
  • the scan signal Gj controls the analog image data signal Vdata to be loaded to the data output node Ncst during the high potential period, and the data output node Ncst is charged through the storage capacitor Cst1. Until the data output node Ncst reaches a stable voltage value and is the same as the voltage value of the image data signal Vdata, at this time, the data writing period Ha ends.
  • the data writing period Ha ends and enters the display period He.
  • the first phase input terminal Vin1 of the comparator CP1 receives the analog image data signal Vdata
  • the second phase input terminal Vin2 of the comparator CP1 receives
  • the first reference signal Vsweep is a ramp signal in the form of a triangular wave.
  • the first reference signal Vsweep is reduced from a high potential based on a first speed to a low potential at a constant speed, and then from a low potential based on the first speed. Rising at a constant speed to a high potential, that is, the waveform of the first reference signal Vsweep is in the shape of an isosceles triangle.
  • the comparator CP1 outputs a digital pulse signal Vout by comparing the first reference signal Vsweep of the second phase input terminal Vin2 with the analog image data signal Vdata.
  • the duty ratio of the pulse signal Vout is compared with the image data signal Vdata.
  • the voltage value of the data signal Vdata is in an inverse relationship, that is, the larger the voltage value of the image data signal Vdata, the smaller the duty cycle of the pulse signal Vout, and the smaller the voltage value of the image data signal Vdata, the smaller the voltage value of the pulse signal Vout. The larger the duty cycle.
  • the pulse signal Vout charges the drive control terminal Ndrv through the drive capacitor Cd1 during the low level period and controls the conduction of the drive transistor Td1 in the drive execution circuit 102.
  • the drive transistor Td1 provides a drive current Idrv to the drive voltage VDD during the on period. Drive the output terminal Ncon.
  • the selection signal WT1 in the first red sub-pixel R1 is at a low level and the selection switch Tw1 is controlled to be in an on state. Therefore, the driving current Idar is transmitted through the driving output terminal Ncon to the emission of red light. Element EM1.
  • the driving transistor Td1 When the voltage charged by the driving capacitor Cd1 to the driving control terminal Ndrv rises above the threshold voltage of the driving transistor Td1, the driving transistor Td1 is turned off, the driving current Idrv stops outputting to the driving output terminal Ncon, and the first red sub-pixel R1 stops emitting light , The light-emitting period He ends, and at the same time, the sub-scanning period Ts1 ends, and the sub-scanning period Ts2 is entered.
  • the second green sub-pixel G2 the first blue sub-pixel B1, the second red sub-pixel R2, the first green sub-pixel G1, and the two blue sub-pixels B2 are driven in sequence.
  • the light is emitted to perform image display corresponding to the image data signal, and the corresponding specific working process and principle are not repeated in this embodiment.
  • FIG. 11 is a schematic diagram of the specific circuit structure of the pixel circuit 300 shown in FIG. 4 in the third embodiment of the application.
  • the pixel circuit 300 is basically the same as the pixel circuit 100 in the embodiment corresponding to FIG. 9, except that K in the number of sub-pixel units 103 is 3, and other circuit structures and working modes are the same.
  • the pixel circuit 100 includes three sub-pixels 103, that is, K is 3.
  • the three sub-pixels 103 are respectively a first red sub-pixel R1, a first green sub-pixel G1, and a first blue sub-pixel B1 in an order from left to right.
  • FIG. 12 is a working timing diagram of the pixel circuit 300 shown in FIG. 11.
  • the sub-scanning display period Ts of each sub-pixel 103 includes data writing time periods Ha and Luminous time period He. Therefore, for the three sub-pixels 103, at least three sub-scanning display periods Ts1 to Ts3 are included.
  • the three sub-pixels 103 use three different sub-scanning periods Ts in one scanning period T of the scanning signal Gi to time-divisionally receive the driving current Idrv corresponding to the image data signal to display image data by emitting light. .
  • three selection signals WT1 to WT3 are respectively provided to select the first red sub-pixel R1, the first green sub-pixel G1, and the first blue sub-pixel B1.
  • the selection signal WT1 is provided to the first red sub-pixel R1, so that the selection signal WT1 controls the selection switch Tw1 in the first red sub-pixel R1 to be turned on, so that the selection signal WT1 is turned on according to the image data signal.
  • the driving current Idrv is applied to the light-emitting element EM1, so that the light-emitting element EM1 emits red light according to the signal carrying red image data.
  • the selection signals WT2 to WT3 are respectively provided to select the first green sub-pixel G1 and the first blue sub-pixel B1.
  • the scan signal Gj controls the analog image data signal to be loaded to the data output node Ncst during the high potential period and charges the data node Ncst through the storage capacitor Cst1 until the data The output node Ncst reaches a stable voltage value and is the same as the voltage value of the image data signal Vdata.
  • the data writing period Ha ends.
  • the data writing period Ha ends and enters the display period He.
  • the first phase input terminal Vin1 of the comparator CP1 and the second phase input terminal Vin2 of the comparator CP1 receive the first reference signal Vsweep as a triangular wave.
  • the form of ramp signal is the first reference signal Vsweep as a triangular wave.
  • the first reference signal Vsweep is reduced from the high potential to the low potential at the second speed at a uniform speed, and then rises from the low potential to the high potential at the second speed at the same speed, that is, the first reference signal Vsweep
  • the waveform of is in the shape of an isosceles triangle.
  • the first speed is the same as the second speed.
  • the first speed may also be different from the second speed.
  • the comparator CP1 compares the first reference signal Vsweep of the second phase input terminal Vin2 with the analog image data signal Vdata to output a digital pulse signal Vout.
  • the duty cycle of the pulse signal Vout has a positive relationship with the voltage value of the image data signal Vdata, that is, the larger the voltage value of the image data signal Vdata, the larger the duty cycle of the pulse signal Vout, and the image The smaller the voltage value of the data signal Vdata, the smaller the duty cycle of the pulse signal Vout.
  • the pulse signal Vout charges the drive control terminal Ndrv through the drive capacitor Cd1 during the low level period and controls the conduction of the drive transistor Td1 in the drive execution circuit 102 at the same time.
  • the drive transistor Td1 provides a drive current Idrv in conjunction with the drive voltage VDD during the on period. To the drive output terminal Ncon.
  • the selection signal WT1 in the first red sub-pixel R1 is at a low level and the selection switch Tw1 is controlled to be in an on state. Therefore, the driving current Idar is transmitted through the driving output terminal Ncon to the emission of red light. Element EM1.
  • the driving transistor Td1 When the voltage charged by the driving capacitor Cd1 to the driving control terminal Ndrv rises above the threshold voltage of the driving transistor Td1, the driving transistor Td1 is turned off, the driving current Idrv stops outputting to the driving output terminal Ncon, and the first red sub-pixel R1 stops emitting light , The light-emitting period He ends, and at the same time, the sub-scanning period Ts1 ends, and the sub-scanning period Ts2 is entered.
  • the second green sub-pixel G2 the first blue sub-pixel B1, the second red sub-pixel R2, the first green sub-pixel G1, and the two blue sub-pixels B2 are driven in sequence.
  • the light is emitted to perform image display corresponding to the image data signal, and the corresponding specific working process and principle are not repeated in this embodiment.
  • FIG. 13 is a schematic diagram of a specific circuit structure of the pixel circuit 400 shown in FIG. 4 in the fourth embodiment of the application.
  • the pixel circuit 400 is basically the same as the pixel circuit 100 in the embodiment corresponding to FIG. 9, except that the driving execution circuit 102 further includes a pulse receiving switch Tps1, a compensation unit 1024, and a second reset switch Tr2, and other circuits
  • the driving execution circuit 102 further includes a pulse receiving switch Tps1, a compensation unit 1024, and a second reset switch Tr2, and other circuits
  • Tps1 pulse receiving switch
  • Tr2 second reset switch
  • the pulse receiving switch Tps1 is electrically connected to the pulse output terminal Vout of the comparator CP1, the first driving voltage terminal VDD1 and the driving input terminal Ny.
  • the pulse receiving switch Tps1 is used for selectively loading the driving voltage VDD provided by the first driving voltage terminal VDD1 to the driving input terminal Ny under the control of the pulse signal Vout output from the pulse output terminal Vout.
  • the turn-on and turn-off time of the pulse receiving switch Tps1 corresponds to the high and low potential duration of the pulse signal Vout. That is, when the pulse receiving switch Tps1 is turned on under the low level control of the pulse signal Vout, the driving voltage VDD is loaded to the driving input terminal Ny; it is turned off under the high level control of the pulse signal Vout, and the driving voltage VDD stops loading To the drive input terminal Ny.
  • the pulse receiving switch Tps1 is a P-type thin film transistor, and the gate of the thin film transistor serving as the pulse receiving switch Tps1 is electrically connected to the pulse signal output terminal Vout to receive the pulse signal Vout output by the comparator CP1; as a pulse
  • the source of the thin film transistor of the receiving switch Tps1 is electrically connected to the first driving voltage terminal VDD1; the drain of the thin film transistor as the pulse receiving switch Tps1 is electrically connected to the driving output terminal.
  • the compensation unit 1024 includes a first compensation transistor Tcv1 and a second compensation transistor Tcv2.
  • the first compensation transistor Tcv1 is electrically connected between the driving control terminal Ndrv and the driving output terminal Ncon, and is used to pre-store the threshold voltage Vth of the first driving transistor Td1 to the driving control terminal Ndrv, and then when the first driving transistor Td1 outputs
  • the threshold voltage Vth factor in the driving current Idrv can be offset, so as to compensate the threshold voltage Vth of the first driving transistor Td1 to prevent the first driving transistor Td1 from being caused by the driving current Idrv.
  • the first compensation transistor Tcv1 is a P-type thin film transistor, wherein the gate of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the first compensation transistor Tcv1 is electrically connected The driving output terminal Ncon; the drain of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the driving control terminal Ndrv.
  • the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny, and is used to synchronously load the auxiliary voltage VD3 to the driving control terminal Ndrv when the threshold voltage Vth of the first driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the voltage value of the auxiliary voltage VD3 can be set according to the parameter characteristics of the first driving transistor Td1.
  • the second compensation transistor Tcv2 is a P-type thin film transistor, wherein the gate of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the second compensation transistor Tcv2 receives the auxiliary voltage VD3; the drain of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny.
  • the second reset switch Tr2 is electrically and electrically connected to the drive control terminal Ndrv, and is used to provide a reset voltage to the drive control terminal Ndrv when the sub-pixel 103 stops displaying images (reset time period) to ensure that the drive control terminal Ndrv is maintained in a reset state. It is ensured that the sub-image pixel 103 accurately receives the image data signal.
  • FIG. 14 is a working timing diagram of the pixel circuit 400 shown in FIG. 13.
  • a sub-pixel 103 in the pixel circuit 400 corresponds to a sub-scanning display period Ts during the display period of one frame of image.
  • the sub-scanning display period Ts of each sub-pixel 103 includes a data writing period Ha and a compensation period Hc. And the luminous time period He.
  • the six sub-pixels 103 at least six sub-scanning display periods Ts1 to Ts6 are included.
  • the selection signal WT1 is provided to the first red sub-pixel R1, so that the selection signal WT1 controls the selection switch Tw1 in the first red sub-pixel R1 to be turned on, so that the selection signal WT1 is turned on according to the image data signal.
  • the driving current Idrv is applied to the light-emitting element EM1, so that the light-emitting element EM1 emits red light according to the signal carrying red image data.
  • the selection signals WT2 to WT6 are respectively provided to select the first green sub-pixel G1, the first blue sub-pixel B1, the second red sub-pixel R2, the second green sub-pixel G2, and the second blue sub-pixel. Color sub-pixel B2.
  • At least two adjacent sub-pixels 103 are not selected in the adjacent sub-scanning period Ts.
  • WT5 is provided to select the second green sub-pixel G2; in the sub-scan period Ts3, WT3 is provided to select the first blue sub-pixel B1; in the sub-scan period Ts4, WT4 is provided to select the second red sub-pixel R2; In the sub-scanning period Ts5, WT2 is provided to select the first green sub-pixel G1; in the sub-scanning period Ts6, WT6 is provided to select the second blue sub-pixel B2.
  • the scan signal Gj controls the analog image data signal to be loaded to the data output node Ncst during the high potential period and charges the data node Ncst through the storage capacitor Cst1 until the data The output node Ncst reaches a stable voltage value and is the same as the voltage value of the image data signal Vdata.
  • the data writing period Ha ends.
  • the data writing period Ha ends and enters the compensation phase Hc.
  • the comparison reset switch Tcp1 the first reset switch Tr1 and the second reset switch Tr2 are controlled to be in the conducting state, and the reset signal Vret is turned on. They are respectively loaded to the comparison intermediate node Nmid, the drive control terminal Ndrv and the drive output terminal Ncon.
  • the first reset transistor Tcv1 and the second reset transistor Tcv2 are controlled to be turned on.
  • the auxiliary voltage VD3 is applied to the driving input terminal Ny through the second reset transistor Tcv2.
  • the drive control terminal Ndrv is directly electrically connected to the drive output terminal Ncon, and the gate and drain of the first drive transistor Td1 are directly electrically connected to form a diode connection, thus, the drive control terminal Ndrv gets the voltage of (VD3-Vth).
  • the compensation/setting signal WD jumps to a high level
  • the first reset transistor Tcv1 and the second reset transistor Tcv2 are turned off, and the compensation phase Hc ends.
  • the first reference signal Vsweep received by the first phase input terminal Vin1 of the comparator CP1 and the second phase input terminal Vin2 of the comparator CP1 is a ramp signal in the form of a triangular wave.
  • the first reference signal Vsweep is reduced from a high potential to a low potential at a uniform speed, and then increased from a low potential to a high potential at a uniform speed at the same speed, that is, the waveform of the first reference signal Vsweep is an isosceles triangle shape.
  • the comparator CP1 outputs a digital pulse signal Vout by comparing the first reference signal Vsweep of the second phase input terminal Vin2 with the analog image data signal Vdata.
  • the duty ratio of the pulse signal Vout is compared with the image data signal Vdata.
  • the voltage value of the data signal Vdata has a positive relationship, that is, the larger the voltage value of the image data signal Vdata, the larger the duty cycle of the pulse signal Vout, and the smaller the voltage value of the image data signal Vdata, the larger the pulse signal Vout The smaller the space ratio.
  • the pulse signal Vout charges the drive control terminal Ndrv through the drive capacitor Cd1 during the low level period and controls the conduction of the drive transistor Td1 in the drive execution circuit 102.
  • the drive transistor Td1 provides a drive current Idrv to the drive voltage VDD during the on period. Drive the output terminal Ncon.
  • the threshold voltage Vth contained in the driving current Idrv is offset by the threshold voltage Vth pre-written in the compensation period Hc, so the driving current Idrv is not affected by the threshold voltage Vth of the first driving transistor Td1.
  • the selection signal WT1 in the first red sub-pixel R1 is at a low level and the selection switch Tw1 is controlled to be in an on state. Therefore, the driving current Idrv is transmitted through the driving output terminal Ncon to the emission of red light. Element EM1.
  • the driving transistor Td1 When the voltage charged by the driving capacitor Cd1 to the driving control terminal Ndrv rises above the threshold voltage of the driving transistor Td1, the driving transistor Td1 is turned off, the driving current Idrv stops outputting to the driving output terminal Ncon, and the first red sub-pixel R1 stops emitting light , The light-emitting period He ends, and at the same time, the sub-scanning period Ts1 ends, and the sub-scanning period Ts2 is entered.
  • the second green sub-pixel G2 the first blue sub-pixel B1, the second red sub-pixel R2, the first green sub-pixel G1, and the two blue sub-pixels B2 are driven in sequence.
  • the light is emitted to perform image display corresponding to the image data signal, and the corresponding specific working process and principle are not repeated in this embodiment.
  • FIG. 15 is a schematic diagram of the specific circuit structure of the pixel circuit 500 shown in FIG. 4 in the fifth embodiment of the application.
  • the pixel circuit 500 is basically the same as the pixel circuit 400 in the embodiment corresponding to FIG. 13, except that K in the number of sub-pixel units 103 is 3, and other circuit structures and working modes are the same.
  • the pixel circuit 100 includes three sub-pixels 103, that is, K is 3.
  • the three sub-pixels 103 are respectively a first red sub-pixel R1, a first green sub-pixel G1, and a first blue sub-pixel B1 in an order from left to right.
  • FIG. 16 is a schematic diagram of the specific circuit structure of the pixel circuit 600 shown in FIG. 4 in the sixth embodiment of the application.
  • the pixel circuit 600 is basically the same as the pixel circuit 100 in the embodiment corresponding to FIG. 9.
  • the difference lies only in the conversion circuit 101, the drive execution circuit 102, and the pixel 103.
  • the N-type switching elements are all replaced with P-type switching elements, and the P-type switching elements in the conversion circuit 101, the drive execution circuit 102, and the pixel 103 are all replaced with N-type switching elements.
  • the scan switch T1 in the conversion circuit 101 is an N-type thin film transistor.
  • the gate of the scan switch T1 receives the scan signal Gj
  • the source receives the image data signal Vdata
  • the drain is electrically connected to the data input node Ncst.
  • the storage capacitor Cst1 is electrically connected between the first driving voltage terminal VDD1 and the data input node Ncst.
  • the first input switch Tin1, the second input switch Tin2, the first reference switch Trf1, the comparison reset switch Trc, and the second output switch Tou2 are N-type thin film transistors, the first mirror switch Tmi1, the second mirror switch Tmi2 And the first output switch Tou1 is a P-type thin film transistor.
  • the gate of the first input switch Tin1 is electrically connected to the first phase input terminal Vin1
  • the source of the first input switch Tin1 is electrically connected to the first reference switch Trf1
  • the drain of the first input switch Tin1 is electrically connected to the comparison middle node Nmid Switch Tmi1 with the first mirror image.
  • the gate of the second input switch Tin2 is electrically connected to the second phase input terminal Vin2, the source of the second input switch Tin2 is electrically connected to the first reference switch Trf1, and the drain of the second input switch Tin2 is electrically connected to the second mirror switch Tmi2.
  • the gate and drain of the first mirror switch Tmi1 are directly and electrically connected to the drain of the first input switch Tin1, the gate of the first mirror switch Tmi1 is electrically connected to the gate of the second mirror switch Tmi2, The source of the first mirror switch Tmi1 is electrically connected to the first driving voltage terminal VDD1.
  • the drain of the second mirror switch Tmi2 is electrically connected to the drain of the second input switch Tin2, the source of the second mirror switch Tmi2 is electrically connected to the first driving voltage terminal VDD1, and the drain of the second mirror switch Tmi2 is electrically connected To the comparison middle node Nmid, that is, the drain of the second mirror switch Tmi2 and the drain of the second input switch Tin2 are electrically connected to the comparison middle node Nmid.
  • the gate of the first reference switch Trf1 receives the reference voltage Vref
  • the drain of the first reference switch Trf1 is electrically connected to the first input switch Tin1 and the second input switch Tin2
  • the source of the first reference switch Trf1 is electrically connected to the first low The reference voltage terminal Vss1.
  • the reference voltage Vref controls the first reference switch Trf1 to be in a normally open state, that is, the reference voltage Vref outputs a high-level voltage signal after the display device 10 is powered on to control the first reference switch Trf1 to be always on.
  • the gate of the first output switch Tou1 is electrically connected to the comparison intermediate node Nmid, the source of the first output switch Tou1 is electrically connected to the first driving voltage terminal VDD1, and the drain of the first output switch Tou1 is electrically connected to the pulse output terminal Vout.
  • the gate of the second output switch Tou2 is electrically connected to the comparison intermediate node Nmid, the source of the second output switch Tou2 is electrically connected to the first low voltage terminal Vss1, and the drain of the second output switch Tou2 is electrically connected to the pulse output terminal Vout.
  • the first driving transistor Td1 in the driving execution circuit 102 is an N-type thin film transistor, and the driving execution circuit 102 is electrically connected between the pulse signal output terminal Vout, the driving output terminal Ncon and the first low voltage terminal Vss1 of the comparator CP1. Specifically, the gate of the first driving transistor Td1 is electrically connected to the pulse signal output terminal Vout, the drain of the first driving transistor Td1 is electrically connected to the driving output terminal Ncon, and the source of the first driving transistor Td1 is electrically connected to the first low Voltage terminal Vss1.
  • the first reset switch Tr1 is a P-type thin film transistor. Specifically, the gate of the first reset switch Tr1 receives the reset signal Vrst, the drain of the first reset switch Tr1 is electrically connected to the driving output terminal Ncon, and the source of the first reset switch Tr1 is electrically connected to the first driving voltage terminal VDD1.
  • the light emitting element EM1 is electrically connected between the driving output terminal Ncon1 and the second driving power supply VDD2 through the selection switch TW1.
  • the selection switches Tw1 to -Tw6 are N-type thin film transistors.
  • the display element EM in each sub-pixel 103 is electrically connected between the second driving power supply VDD2 and the driving output terminal Ncon through the selection switch Tw.
  • FIG. 17 is a schematic diagram of the specific circuit structure of the pixel circuit 700 shown in FIG. 4 in the seventh embodiment of the application.
  • the pixel circuit 700 is basically the same as the pixel circuit 600 in the embodiment corresponding to FIG. 16, except that the driving execution circuit 102 further includes a pulse receiving switch Tps1, a compensation unit 1024, and a second reset switch Tr2, and other circuits
  • the structure is the same.
  • the compensation unit 1024 is electrically connected to the driving control terminal Ndrv, the driving output terminal Ncon, and the driving input terminal Ny, and is used to compensate for the drift of the threshold voltage (Vth) of the first driving transistor Td1
  • the pulse receiving switch Tps1 is electrically connected between the pulse output terminal Vout of the comparator CP1, the first low voltage terminal Vss1 and the driving input terminal Ny.
  • the pulse receiving switch Tps1 is used for selectively electrically connecting the driving input terminal Ny to the first low voltage terminal Vss1 under the control of the pulse signal Vout output by the pulse output terminal Vout.
  • the turn-on and turn-off time of the pulse receiving switch Tps1 corresponds to the high and low potential duration of the pulse signal Vout. That is, when the pulse receiving switch Tps1 is turned on under the low level control of the pulse signal Vout, the low reference voltage Vss is applied to the driving input terminal Ny; it is turned off under the high level control of the pulse signal Vout, and the low reference voltage Vss Stop loading to the drive input terminal Ny.
  • the pulse receiving switch Tps1 is an N-type thin film transistor, wherein the gate of the thin film transistor serving as the pulse receiving switch Tps1 is electrically connected to the pulse signal output terminal Vout to receive the pulse signal Vout output by the comparator CP1; as a pulse
  • the source of the thin film transistor of the receiving switch Tps1 is electrically connected to the first low voltage terminal Vss1; the drain of the thin film transistor serving as the pulse receiving switch Tps1 is electrically connected to the driving output terminal Ny.
  • the compensation unit 1024 includes a first compensation transistor Tcv1 and a second compensation transistor Tcv2, wherein the first compensation transistor Tcv1 is electrically connected between the drive control terminal Ndrv and the drive output terminal Ncon, and is used to pre-load the first compensation transistor Tcv1 and Tcv2.
  • the threshold voltage Vth of the driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the first compensation transistor Tcv1 is an N-type thin film transistor, wherein the gate of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the first compensation transistor Tcv1 is electrically connected The drive output terminal Ncon; the source of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the drive control terminal Ndrv.
  • the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny, and is used to synchronously load the auxiliary voltage VD3 to the driving control terminal Ndrv when the threshold voltage Vth of the first driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the voltage value of the auxiliary voltage VD3 can be set according to the parameter characteristics of the first driving transistor Td1.
  • the second compensation transistor Tcv2 is an N-type thin film transistor, wherein the gate of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the second compensation transistor Tcv2 receives the auxiliary voltage VD3; the drain of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny.
  • the second reset switch Tr2 is electrically and electrically connected to the drive control terminal Ndrv, and is used to provide a reset signal to the drive control terminal Ndrv when the sub-pixel 103 stops displaying images (reset time period) to ensure that the drive control terminal Ndrv is maintained in a reset state. It is ensured that the sub-image pixel 103 accurately receives the image data signal.
  • the second reset switch Tr2 is a P-type thin film transistor, and the gate of the thin film transistor serving as the second reset switch Tr2 receives the reset signal Vrst; the source of the thin film transistor serving as the second reset switch Tr2 is electrically connected to the first driving voltage terminal VDD1; The drain of the thin film transistor serving as the second reset switch Tr2 is electrically connected to the driving control terminal Ndrv.
  • the driving capacitor Cd1 is electrically connected between the driving control terminal Ndrv and the first low voltage terminal Vss1.
  • FIG. 18 is a circuit block diagram of the pixel circuit 800 shown in FIG. 4 in the eighth embodiment of this application.
  • the pixel circuit 800 is basically the same as the pixel circuit 100 in the embodiment corresponding to FIG. 6, except that the first phase input terminal Vin1 in the comparator CP1 is a non-inverting input terminal, and the second phase input terminal Vin2 is an inverting input terminal. Input terminal.
  • FIG. 19 is a schematic diagram of a specific circuit structure of the pixel circuit 800 shown in FIG. 18.
  • the gate of the first input switch Tin1 is electrically connected to the second phase input terminal Vin2
  • the source of the first input switch Tin1 is electrically connected to the first reference switch Trf1
  • the first input switch The drain of the switch Tin1 is electrically connected to the first mirror switch Tmi1.
  • the gate of the second input switch Tin2 is electrically connected to the first phase input terminal Vin1
  • the source of the second input switch Tin2 is electrically connected to the first reference switch Trf1
  • the drain of the second input switch Tin2 is electrically connected to the second mirror switch Tmi2.
  • the gate and drain of the first mirror switch Tmi1 are directly and electrically connected to the drain of the first input switch Tin1, the gate of the first mirror switch Tmi1 is electrically connected to the gate of the second mirror switch Tmi2, The source of the first mirror switch Tmi1 is electrically connected to the first low voltage terminal Vss1.
  • the drain of the second mirror switch Tmi2 is electrically connected to the drain of the second input switch Tin2, and the source of the second mirror switch Tmi2 is electrically connected to the second low voltage terminal Vss1.
  • drain of the second mirror switch Tmi2 and the drain of the second input switch Tin2 are both electrically connected to the comparison intermediate node Nmin.
  • the gate of the first reference switch Trf1 receives the reference voltage Vref
  • the drain of the first reference switch Trf1 is electrically connected to the first input switch Tin1 and the second input switch Tin2
  • the source of the first reference switch Trf1 is electrically connected to the first driver Voltage terminal VDD1.
  • the reference voltage Vref controls the first reference switch Trf1 to be in a normally open state, that is, the reference voltage Vref outputs a low-level voltage signal after the display device 10 is powered on to control the first reference switch Trf1 to be always on.
  • the gate of the first output switch Tou1 is electrically connected to the comparison intermediate node Nmid, the source of the first output switch Tou1 is electrically connected to the first driving voltage terminal VDD1, and the drain of the first output switch Tou1 is electrically connected to the pulse output terminal Vout.
  • the gate of the second output switch Tou2 is electrically connected to the comparison intermediate node Nmid, the source of the second output switch Tou2 is electrically connected to the first low voltage terminal Vss1, and the drain of the second output switch Tou2 is electrically connected to the pulse output terminal Vout.
  • FIG. 20 is a timing diagram when the comparator CP1 shown in FIG. 19 is working.
  • the first phase input terminal Vin1 is a non-inverting input terminal
  • the second phase input terminal Vin2 is an inverting input terminal. Therefore, the first reference signal Vsweep is similar to the first embodiment.
  • the phase of the first reference signal Vsweep in the comparator CP1 in the middle pixel circuit 100 is opposite.
  • the scanning line Gj provides the scanning signal to the pixel circuit 100, and the scanning switch T1 is at a high level. It is turned on under the control of the scanning signal, and the image data signal Vdata in the analog form transmits the data output node Ncst.
  • the image data signal Vdata gradually increases the voltage of the data output node Ncst by charging the storage capacitor Cst.
  • the scan line Gj stops providing the scan signal
  • the scan switch T1 is turned off, and the voltage of the data output node Ncst rises to the same value through the charging of the storage capacitor Cst.
  • the data writing period Ha ends and the light emitting period He enters.
  • the first reference signal Vsweep enters the ramp signal phase, that is, the first reference signal Vsweep gradually decreases and changes from a high potential at a uniform speed and a uniform amplitude.
  • the first reference signal Vsweep gradually decreases from a high potential to a bottom potential as an example to illustrate the principle of the comparator CP1 outputting the pulse signal Vout according to the magnitude of the first reference signal Vsweep and the image data signal Vdata.
  • the driving currents of the second input switch Tin2 and the second mirror switch Tmi2 in the comparator CP1 are dominant, so the driving voltage VDD passes through the normally open first reference switch Trf1, the second input switch Tin2 are transmitted to the comparison intermediate node Nmin, so that the comparison intermediate node Nmin is at a high potential (VDD), and the second output switch Tou2 is turned on under the high potential control, and then the driving voltage VDD is passed through the second output switch Tou2 is loaded to the pulse signal output terminal Vout. As a result, the pulse signal output terminal Vout is at a low potential.
  • the driving currents of the first input switch Tin1 and the first mirror switch Tmi1 in the comparator CP1 are dominant, so the first driving voltage passes through the normally open first reference
  • the switch Trf1 and the second input switch Tin1 are transmitted to the gates of the first mirror switch Tmi1 and the second mirror switch Tmi2, so that the first mirror switch Tmi1 and the second mirror switch Tmi2 are turned on, so that the low reference voltage Vss passes through the second mirror.
  • the switch Tmi2 is loaded to the comparison intermediate node Nmin, so that the comparison intermediate node Nmin is at a low potential (Vss), and the first output switch Tou1 is turned on under the low potential control, and then the low reference voltage Vss is applied to the pulse through the first output switch Tou1 The signal output terminal Vout. As a result, the pulse signal output terminal Vout is at a high potential.
  • the comparator CP1 outputs the corresponding pulse signal Vout according to the comparison result of the magnitude of the first reference signal Vsweep and the image data signal Vdata. Since the pulse signal Vout is in a digital form, the analog image data signal Vdata is converted into Digital form. In addition, the duty ratio of the pulse signal Vout is determined by the image data signal Vdata. Since the drive current Idrv provided by the drive execution circuit 102 is determined by the duty ratio of the pulse signal Vout, the pulse signal Vout can be accurate Characterize the size of the image data signal Vdata.
  • FIG. 21 is a timing circuit diagram of the pixel circuit 800 shown in FIG. 18.
  • the sub-scanning display period Ts of each sub-pixel 103 includes a data writing period Ha and a light emitting period He.
  • the six sub-pixels 103 at least six sub-scanning display periods Ts1 to Ts6 are included.
  • the six sub-pixels 103 receive the driving current Idrv corresponding to the image data signal in a time-sharing manner through the six sub-scanning periods Ts of the scanning signal Gi in one scanning period T to display image data by emitting light.
  • six selection signals WT1 to WT6 are respectively provided to select the first red sub-pixel R1, the first green sub-pixel G1, the first blue sub-pixel B1, and the second red sub-pixel R2 ,
  • the second green sub-pixel G2 and the second blue sub-pixel B2 perform image display.
  • a selection signal WT1 is provided to the first red sub-pixel R1, and the selection signal WT1 controls the selection switch Tw1 in the first red sub-pixel R1 to be turned on, thereby turning on the selection switch Tw1 in the first red sub-pixel R1 according to the image data signal.
  • the driving current Idrv is applied to the light emitting element EM1, so that the light emitting element EM1 emits red light according to the signal carrying the red image data.
  • the selection signals WT2 to WT6 are respectively provided to select the first green sub-pixel G1, the first blue sub-pixel B1, the second red sub-pixel R2, the second green sub-pixel G2, and the second blue sub-pixel. Color sub-pixel B2.
  • At least two adjacent sub-pixels 103 are not selected in the adjacent sub-scanning period Ts.
  • WT5 is provided to select the second green sub-pixel G2; in the sub-scan period Ts3, WT3 is provided to select the first blue sub-pixel B1; in the sub-scan period Ts4, WT4 is provided to select the second red sub-pixel R2; In the sub-scanning period Ts5, WT2 is provided to select the first green sub-pixel G1; in the sub-scanning period Ts6, WT6 is provided to select the second blue sub-pixel B2.
  • the scan signal Gj controls the analog image data signal Vdata to be loaded to the data output node Ncst during the high potential period, and the data output node Ncst is charged through the storage capacitor Cst1. Until the data output node Ncst reaches a stable voltage value and is the same as the voltage value of the image data signal Vdata, at this time, the data writing period Ha ends.
  • the first phase input terminal Vin1 of the comparator CP1 and the second phase input terminal Vin2 of the comparator CP1 receive the first reference signal Vsweep as Ramp signal in the form of a triangle wave.
  • the first reference signal Vsweep rises from a low potential at a first speed to a high potential at a uniform speed, and then decreases from a high potential at a first speed to a low potential at a uniform speed, that is, the waveform of the first reference signal Vsweep is an isosceles triangle. shape.
  • the comparator CP1 outputs a digital pulse signal Vout by comparing the first reference signal Vsweep of the second phase input terminal Vin2 with the analog image data signal Vdata.
  • the duty ratio of the pulse signal Vout is compared with the image data signal Vdata.
  • the voltage value of the data signal Vdata is in an inverse relationship, that is, the larger the voltage value of the image data signal Vdata, the smaller the duty cycle of the pulse signal Vout, and the smaller the voltage value of the image data signal Vdata, the smaller the voltage value of the pulse signal Vout. The larger the duty cycle.
  • the pulse signal Vout charges the drive control terminal Ndrv through the drive capacitor Cd1 during the low level period and controls the conduction of the drive transistor Td1 in the drive execution circuit 102.
  • the drive transistor Td1 provides a drive current Idrv to the drive voltage VDD during the on period. Drive the output terminal Ncon.
  • the selection signal WT1 in the first red sub-pixel R1 is at a low level and the selection switch Tw1 is controlled to be in an on state. Therefore, the driving current Idar is transmitted through the driving output terminal Ncon to the emission of red light. Element EM1.
  • the driving transistor Td1 When the voltage charged by the driving capacitor Cd1 to the driving control terminal Ndrv rises above the threshold voltage of the driving transistor Td1, the driving transistor Td1 is turned off, the driving current Idrv stops outputting to the driving output terminal Ncon, and the first red sub-pixel R1 stops emitting light , The light-emitting period He ends, and at the same time, the sub-scanning period Ts1 ends, and the sub-scanning period Ts2 is entered.
  • the second green sub-pixel G2 the first blue sub-pixel B1, the second red sub-pixel R2, the first green sub-pixel G1, and the two blue sub-pixels B2 are driven in sequence.
  • the light is emitted to perform image display corresponding to the image data signal, and the corresponding specific working process and principle are not repeated in this embodiment.
  • FIG. 22 is a schematic diagram of the specific circuit structure of the pixel circuit 900 shown in FIG. 4 in the ninth embodiment of the application.
  • the pixel circuit 900 is basically the same as the pixel circuit 800 in the embodiment corresponding to FIG. 18.
  • the driving execution circuit 102 also includes a pulse receiving switch Tps1, a compensation unit 1024, and a second reset switch Tr2.
  • Other circuit structures the same.
  • the pulse receiving switch Tps1 is electrically connected between the pulse output terminal Vout of the comparator CP1, the first driving voltage terminal VDD1 and the driving input terminal Ny.
  • the pulse receiving switch Tps1 is used to selectively load the driving voltage VDD to the driving input terminal Ny under the control of the pulse signal Vout output from the pulse output terminal Vout.
  • the turn-on and turn-off time of the pulse receiving switch Tps1 corresponds to the high and low potential duration of the pulse signal Vout. That is, when the pulse receiving switch Tps1 is turned on under the low level control of the pulse signal Vout, the driving voltage VDD is loaded to the driving input terminal Ny; it is turned off under the high level control of the pulse signal Vout, and the driving voltage VDD stops loading To the drive input terminal Ny.
  • the pulse receiving switch Tps1 is a P-type thin film transistor, and the gate of the thin film transistor serving as the pulse receiving switch Tps1 is electrically connected to the pulse signal output terminal Vout to receive the pulse signal Vout output by the comparator CP1; as a pulse
  • the source of the thin film transistor of the receiving switch Tps1 is electrically connected to the first driving voltage terminal VDD1; the drain of the thin film transistor as the pulse receiving switch Tps1 is electrically connected to the driving output terminal.
  • the compensation unit 1024 is electrically connected to the driving control terminal Ndrv, the driving output terminal Ncon, and the driving input terminal Ny, and is used to compensate the drift of the threshold voltage (Vth) of the first driving transistor Td1.
  • the compensation unit 1024 includes a first compensation transistor Tcv1 and a second compensation transistor Tcv2, wherein the first compensation transistor Tcv1 is electrically connected between the drive control terminal Ndrv and the drive output terminal Ncon, and is used to pre-load the first compensation transistor Tcv1 and Tcv2.
  • the threshold voltage Vth of the driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the first compensation transistor Tcv1 is a P-type thin film transistor, wherein the gate of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the first compensation transistor Tcv1 is electrically connected The drive output terminal Ncon; the source of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the drive control terminal Ndrv.
  • the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny, and is used to synchronously load the auxiliary voltage VD3 to the driving control terminal Ndrv when the threshold voltage Vth of the first driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the voltage value of the auxiliary voltage VD3 can be set according to the parameter characteristics of the first driving transistor Td1.
  • the second compensation transistor Tcv2 is a P-type thin film transistor, wherein the gate of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the second compensation transistor Tcv2 receives the auxiliary voltage VD3; the drain of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny.
  • the second reset switch Tr2 is electrically and electrically connected to the drive control terminal Ndrv, and is used to provide a reset voltage to the drive control terminal Ndrv when the sub-pixel 103 stops displaying images (reset period) under the control of the reset signal Vrst to ensure the drive control terminal
  • the Ndrv is maintained in the reset state to ensure that the sub-image pixel 103 accurately receives the image data signal.
  • FIG. 23 is a schematic diagram of the specific circuit structure of the pixel circuit 1000 shown in FIG. 4 in the tenth embodiment of the application.
  • the pixel circuit 1000 is basically the same as the pixel circuit 400 in the embodiment corresponding to FIG. 13, except that the comparator CP1 further includes a hysteresis unit 105, and the other circuit structures are the same.
  • FIG. 24 is a timing diagram of the input and output signals of the hysteresis unit 105 as shown in FIG. 23.
  • the hysteresis unit 105 is electrically connected to the pulse signal output terminal Vout and the first phase.
  • the input terminal Vin1 and the data output node Ncst are used to control Vitl when the voltage difference between the signals received by the first phase input terminal Vin1 and the second phase input terminal Vin2 is greater than the first threshold or Vith is less than the second threshold,
  • the potential of the pulse signal Vout changes (as shown in FIG. 24), and the first threshold Vith is different from the second threshold Vitl.
  • the first threshold Vith is smaller than the second threshold Vitl.
  • the first threshold Vith is +0.5V
  • the second threshold Vitl is -0.5V.
  • the hysteresis unit 105 electrically includes a first hysteresis resistor R1 and a second hysteresis resistor R2.
  • the first hysteresis resistor R1 is electrically connected between the first phase input terminal Vin1 and the data output node Ncst
  • the second hysteresis resistor R2 is electrically connected between the first phase input terminal Vin1 and the pulse signal output terminal Vout.
  • the pulse signal Vout is not affected and a stable output is maintained.
  • FIG. 25 is a schematic diagram of the specific circuit structure of the pixel circuit 1100 shown in FIG. 4 in the eleventh embodiment of this application.
  • the pixel circuit 1100 is basically the same as the pixel circuit 1000 in the embodiment corresponding to FIG. 23, except that the N-type thin film transistors and the P-type switching elements in the switching circuit 101, the drive execution circuit 102, and the sub-pixel 103 are basically the same.
  • the types of thin film transistors are different.
  • the scan switch T1 in the conversion circuit 101 is an N-type thin film transistor.
  • the storage capacitor Cst1 is electrically connected between the first driving voltage terminal VDD1 and the data input node Ncst.
  • the first input switch Tin1, the second input switch Tin2, the first reference switch Trf1, the comparison reset switch Tcr, and the second output switch Tou2 are N-type thin film transistors, the first mirror switch Tmi1, the second mirror switch Tmi2 , The first output switch Tou1 is a P-type thin film transistor.
  • the gate of the first input switch Tin1 is electrically connected to the first phase input terminal Vin1
  • the source of the first input switch Tin1 is electrically connected to the first reference switch Trf1
  • the drain of the first input switch Tin1 is electrically connected to the first mirror switch Tmi1.
  • the gate of the second input switch Tin2 is electrically connected to the second phase input terminal Vin2, the source of the second input switch Tin2 is electrically connected to the first reference switch Trf1, and the drain of the second input switch Tin2 is electrically connected to the second mirror switch Tmi2.
  • the gate and drain of the first mirror switch Tmi1 are directly and electrically connected to the drain of the first input switch Tin1, the gate of the first mirror switch Tmi1 is electrically connected to the gate of the second mirror switch Tmi2, The source of the first mirror switch Tmi1 is electrically connected to the first driving voltage terminal VDD1.
  • the drain of the second mirror switch Tmi2 is electrically connected to the drain of the second input switch Tin2, and the source of the second mirror switch Tmi2 is electrically connected to the first driving voltage terminal VDD1.
  • drain of the second mirror switch Tmi2 and the drain of the second input switch Tin2 are both electrically connected to the comparison intermediate node Nmin.
  • the gate of the first reference switch Trf1 receives the reference voltage Vref
  • the drain of the first reference switch Trf1 is electrically connected to the first input switch Tin1 and the second input switch Tin2
  • the source of the first reference switch Trf1 is electrically connected to the first low The reference voltage terminal Vss1.
  • the reference voltage Vref controls the first reference switch Trf1 to be in a normally open state, that is, the reference voltage Vref outputs a high-level voltage signal after the display device 10 is powered on to control the first reference switch Trf1 to be always on.
  • the gate of the first output switch Tou1 is electrically connected to the comparison intermediate node Nmid, the source of the first output switch Tou1 is electrically connected to the first driving voltage terminal VDD1, and the drain of the first output switch Tou1 is electrically connected to the pulse output terminal Vout.
  • the gate of the second output switch Tou2 is electrically connected to the comparison intermediate node Nmid, the source of the second output switch Tou2 is electrically connected to the first low voltage terminal Vss1, and the drain of the second output switch Tou2 is electrically connected to the pulse output terminal Vout.
  • the first driving transistor Td1 in the driving execution circuit 102 is an N-type thin film transistor, and the driving execution circuit 102 is electrically connected between the pulse signal output terminal Vout, the driving output terminal Ncon and the first low voltage terminal Vss1 of the comparator CP1. Specifically, the gate of the first driving transistor Td1 is electrically connected to the pulse signal output terminal Vout, the drain of the first driving transistor Td1 is electrically connected to the driving output terminal Ncon, and the source of the first driving transistor Td1 is electrically connected to the first low Voltage terminal Vss1.
  • the first reset switch Tr1 is a P-type thin film transistor.
  • the selection switches Tw1 to -Tw6 are N-type thin film transistors. Specifically, the gate of the first reset switch Tr1 receives the reset signal Vrst, the drain of the first reset switch Tr1 is electrically connected to the driving output terminal Ncon, and the source of the first reset switch Tr1 is electrically connected to the first driving voltage terminal VDD1.
  • the compensation unit 1024 is electrically connected to the driving control terminal Ndrv, the driving output terminal Ncon, and the driving input terminal Ny, and is used to compensate the drift of the threshold voltage (Vth) of the first driving transistor Td1.
  • the pulse receiving switch Tps1 is electrically connected between the pulse output terminal Vout of the comparator CP1, the first low voltage terminal Vss1 and the driving input terminal Ny.
  • the pulse receiving switch Tps1 is used for selectively electrically connecting the driving input terminal Ny to the first low voltage terminal Vss1 under the control of the pulse signal Vout output by the pulse output terminal Vout.
  • the turn-on and turn-off time of the pulse receiving switch Tps1 corresponds to the high and low potential duration of the pulse signal Vout. That is, when the pulse receiving switch Tps1 is turned on under the low level control of the pulse signal Vout, the drive input terminal Ny is electrically connected to the first low voltage terminal Vss1; it is turned off under the high level control of the pulse signal Vout, The driving input terminal Ny is electrically disconnected from the first low voltage terminal Vss1.
  • the pulse receiving switch Tps1 is an N-type thin film transistor, and the gate of the thin film transistor serving as the pulse receiving switch Tps1 is electrically connected to the pulse signal output terminal Vout to receive the pulse signal Vout output by the comparator CP1; as a pulse
  • the source of the thin film transistor of the receiving switch Tps1 is electrically connected to the first low voltage terminal Vss1; the drain of the thin film transistor as the pulse receiving switch Tps1 is electrically connected to the driving output terminal Ny.
  • the compensation unit 1024 includes a first compensation transistor Tcv1 and a second compensation transistor Tcv2, wherein the first compensation transistor Tcv1 is electrically connected between the drive control terminal Ndrv and the drive output terminal Ncon, and is used to pre-load the first compensation transistor Tcv1 and Tcv2.
  • the threshold voltage Vth of the driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the first compensation transistor Tcv1 is an N-type thin film transistor, wherein the gate of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the first compensation transistor Tcv1 is electrically connected The driving output terminal Ncon; the drain of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the driving control terminal Ndrv.
  • the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny, and is used to synchronously load the auxiliary voltage VD3 to the driving control terminal Ndrv when the threshold voltage Vth of the first driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the voltage value of the auxiliary voltage VD3 can be set according to the parameter characteristics of the first driving transistor Td1.
  • the second compensation transistor Tcv2 is an N-type thin film transistor, wherein the gate of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the second compensation transistor Tcv2 receives the auxiliary voltage VD3; the drain of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny.
  • the second reset switch Tr2 is electrically and electrically connected to the drive control terminal Ndrv, and is used to provide a reset signal Vrst when the sub-pixel 103 stops displaying images (reset time period) to ensure that the drive control terminal Ndrv is maintained in the reset state and to ensure that the sub-pixel 103 The image data signal is accurately received.
  • the second reset switch Tr2 is a P-type thin film transistor, and the gate of the thin film transistor serving as the second reset switch Tr2 receives the reset signal Vrst; the source of the thin film transistor serving as the second reset switch Tr2 is electrically connected to the first driving voltage terminal VDD1; The drain of the thin film transistor serving as the second reset switch Tr2 is electrically connected to the driving control terminal Ndrv.
  • the driving capacitor Cd1 is electrically connected between the driving control terminal Ndrv and the first low voltage terminal Vss1.
  • the light emitting element EM1 is electrically connected between the driving output terminal Ncon1 and the second driving power supply VDD2 through the selection switch TW1.
  • the selection switches Tw1 to -Tw6 are N-type thin film transistors.
  • the display element EM in each sub-pixel 103 is electrically connected between the second driving power supply VDD2 and the driving output terminal Ncon through the selection switch Tw.
  • FIG. 26 is a schematic diagram of the specific circuit structure of the pixel circuit 1200 shown in FIG. 4 in the twelfth embodiment of the application.
  • the conversion circuit 101 includes a storage capacitor Cst1, a first preset switch Tpe1, a second preset switch Tpe2, and a conversion transistor Ttr.
  • the storage capacitor Cst1 is electrically connected between the data line Di and the data output node Ncst for storing the image data signal Vdata received from the data line Di and charging the data output node Ncst to the same potential as the image data signal Vdata.
  • the conversion transistor Ttr is electrically connected to the data output node Ncst, the first driving voltage terminal VDD1 and the pulse signal output terminal Vout, and is used to turn on or off under the voltage control of the data output node Ncst to selectively transmit the driving voltage VDD To the pulse signal output terminal Vout for the pulse signal Vout.
  • the conversion transistor Ttr is a P-type thin film transistor.
  • the transistor gate of the conversion transistor Ttr is electrically connected to the data output contact Ncst, and the transistor drain of the conversion transistor Ttr is electrically connected to the pulse signal output terminal Vout.
  • the transistor source of the transistor Ttr is electrically connected to the first driving voltage terminal VDD1.
  • the driving voltage VDD is transmitted to the pulse signal output terminal Vout through the switching transistor Ttr, and the high potential is used as the potential of the pulse signal Vout.
  • the driving voltage VDD stops the pulse signal output terminal Vout.
  • the first preset switch Tpe1 is electrically connected between the data output node Ncst and the pulse signal output terminal Vout, and is used to directly electrically conduct the data output node Ncst and the pulse signal output terminal Vout under the control of the first preset signal WS1 , So that the gate and drain of the conversion transistor are directly electrically connected in a diode connection.
  • the first preset switch Tpe1 is a P-type thin film transistor, the gate of the first preset switch Tpe1 receives the first preset signal WS1, and the source of the first preset switch Tpe1 is electrically connected to the data output node Ncst , The drain of the first preset switch Tpe1 is electrically connected to the pulse signal output terminal Vout.
  • the second preset switch Tpe2 is electrically connected between the pulse signal output terminal Vout and the first low voltage terminal Vss1, and is used to electrically connect the first low voltage terminal Vss1 and the pulse signal output terminal Vout under the control of the second preset signal WS2.
  • the electrical conduction makes the pulse signal Vout output by the pulse signal output terminal Vout have a low potential.
  • the second preset switch Tpe2 is a P-type thin film transistor, the gate of the second preset switch Tpe2 receives the second preset signal WS2, and the source of the second preset switch Tpe2 is electrically connected to the first low voltage The terminal Vss1, the drain of the second preset switch Tpe2 is electrically connected to the pulse signal output terminal Vout.
  • the first preset signal WS1 and the second preset signal WS2 are both the scan signal Gj provided by the scan line Gaj, that is, the first preset signal WS1 and the second preset signal WS2 are provided by the scan line Gaj
  • the gates of the first preset switch Tpe1 and the second preset switch Tpe2 are electrically connected to the scan line Gaj.
  • the driving execution circuit 102 includes a pulse receiving switch Tps1, a first driving transistor Td1, a preset reset switch Tpr1, a first reset switch Tre1, a second reset switch Tre2, and a driving capacitor Cd1.
  • the pulse receiving switch Tps1 is electrically connected between the pulse output terminal Vout, the second driving voltage terminal VDD2 and the driving input terminal Ny.
  • the pulse receiving switch Tps1 is used to selectively load the driving voltage VDD to the driving input terminal Ny under the control of the pulse signal Vout output from the pulse output terminal Vout.
  • the turn-on and turn-off time of the pulse receiving switch Tps1 corresponds to the high and low potential duration of the pulse signal Vout. That is, when the pulse receiving switch Tps1 is turned on under the low level control of the pulse signal Vout, the driving voltage VDD is loaded to the driving input terminal Ny; it is turned off under the high level control of the pulse signal Vout, and the driving voltage VDD stops loading To the drive input terminal Ny.
  • the pulse receiving switch Tps1 is a P-type thin film transistor, and the gate of the thin film transistor serving as the pulse receiving switch Tps1 is electrically connected to the pulse signal output terminal Vout to receive the pulse signal Vout output by the comparator CP1; as a pulse
  • the source of the thin film transistor of the receiving switch Tps1 is electrically connected to the first driving voltage terminal VDD1; the drain of the thin film transistor as the pulse receiving switch Tps1 is electrically connected to the driving output terminal.
  • the first driving transistor Td1 is electrically connected to the driving control terminal Ndrv, the driving input terminal Ny, and the driving output terminal Ncon, and is used to provide a driving current Idrv to the driving output terminal Ncon under the control of a signal loaded by the driving control terminal Ndrv.
  • the driving transistor Td1 is a P-type thin film transistor, wherein the gate of the thin film transistor as the first driving transistor Td1 is electrically connected to the driving control terminal Ndrv; the source of the thin film transistor as the first driving transistor Td1 is electrically connected The driving input terminal Ny is connected; the drain of the thin film transistor as the first driving transistor Td1 is electrically connected to the driving output terminal Ncon.
  • the driving capacitor Cd1 is electrically connected to the second driving voltage terminal VDD2 and the driving control terminal Ndrv, and is used for storing and maintaining the driving control terminal Ndrv at a stable potential within a preset time period, so as to control the first driving transistor Td1 at the preset time Maintain the conduction within.
  • the preset reset switch Tpr1 is electrically connected to the driving control terminal Ndrv, and is used to provide the auxiliary voltage VD3 to the driving control terminal Ndrv during the reset period before the sub-pixel 103 emits light.
  • the auxiliary voltage VD3 can control the first driving transistor Td1 to turn on.
  • the preset reset switch Tpr1 is a P-type thin film transistor, where the gate of the thin film transistor serving as the preset reset switch Tpr1 receives the compensation/setting signal WD; the source of the thin film transistor serving as the preset reset switch Tpr1 The auxiliary voltage VD3 is received; the drain of the thin film transistor as the preset reset switch Tpr1 is electrically connected to the driving control terminal Ndrv.
  • the first reset switch Tre1 and the second reset switch Tre2 are respectively electrically connected to the drive control terminal Ndrv and the drive output terminal Vcon, and are used to provide a low reference under the control of the reset signal Vrst when the sub-pixel 103 stops displaying images (reset period)
  • the voltage Vss is applied to the driving control terminal Ndrv and the driving output terminal Ncon, and the driving control terminal Ndrv and the driving output terminal Ncon are controlled to be reset and maintained in the reset state.
  • the first reset switch Tre1 is a P-type thin film transistor, wherein the gate of the thin film transistor serving as the first reset switch Tre1 receives the reset signal Vrst; the source of the thin film transistor serving as the first reset switch Tre1 is electrically connected The first low voltage terminal Vss1; the drain of the thin film transistor as the first reset switch Tre1 is electrically connected to the driving control terminal Ndrv.
  • the second reset switch Tre2 is a P-type thin film transistor, wherein the gate of the thin film transistor serving as the second reset switch Tre2 receives the reset signal Vrst; the source of the thin film transistor serving as the second reset switch Tre2 is electrically connected The first low voltage terminal Vss1; the drain of the thin film transistor as the second reset switch Tre2 is electrically connected to the driving output terminal Ncon.
  • each sub-pixel 103 includes a selection switch Tw and a light-emitting element EM.
  • the selection switch Tw and the light-emitting element EM of the plurality of sub-pixels 103 are passed through the position
  • the sequence number of the arrangement is distinguished, for example, the selection switch Tw1 and the light-emitting element EM1 in the sub-pixel 103 in the first position on the left, and so on, the selection switch Tw6 and the light-emitting element EM6 in the sub-pixel 103 in the last position on the right.
  • Each light emitting element EM is electrically connected between the driving output terminal Ncon and the second low voltage terminal Vss2 through a selection switch EM.
  • FIG. 27 is a working timing diagram of one sub-pixel 103 in the pixel circuit 1200 shown in FIG. 26.
  • the sub-scanning display period Ts of each sub-pixel 103 includes a data writing period Ha, a reset period Hc, a preparation period Hp, and light emission. Time period He.
  • a sub-scanning period Ts by providing a scanning signal and a selection signal WT, the sub-pixel 103 is controlled to perform image display
  • the data writing period Ha is first entered.
  • the data writing period Ha further includes 5 sub-periods Ha1 to Ha5 that are continuous in time and have no interval in sequence.
  • the pixel circuit 100 and the sub-pixel 103 to be displayed enter a waiting state.
  • the second preset signal WS2 jumps from a high potential to a low potential, triggering the second preset switch Tpe2 to turn on, and the low voltage Vss of the first low voltage terminal Vss1 is applied to the second preset switch Tpe2 through the second preset switch Tpe2. Pulse signal output terminal Vout.
  • the first preset signal WS1 jumps from a high potential to a low potential, triggering the first preset switch Tpe1 to turn on, and the voltages of the data output node Ncst and the pulse signal output terminal Vout are both approximately the low voltage Vss.
  • the first preset switch Tpe1 since the first preset switch Tpe1 is turned on, the gate and drain of the first driving transistor T1 are directly electrically connected to form a diode connection, and the first driving transistor Td1 is turned on under the control of the low-potential data output node Ncst Therefore, the voltages of the data output node Ncst and the pulse signal output terminal Vout can both be expressed as "VDD1-Vth1".
  • the second preset signal WS2 jumps to a high level, the second threshold switch Tp2 is turned off, the low potential Vss stops being applied to the pulse signal output terminal Vout, and the image data signal Vdata is loaded through the first storage capacitor Cst1 To the data output node Ncst, at this time, the voltage stored in the first storage capacitor Cst1 is: Vdata-(VDD1-Vth1).
  • the first preset signal WS1 jumps to a high level, the first threshold switch Tp1 is turned off, and the data writing period Ha.
  • the data writing period Ha After the data writing period Ha ends, it enters the reset period Hc, in which the signal of the previous frame remaining in the sub-pixel 103 is mainly released to facilitate the correctness of the image data signal data display of the current frame.
  • the reset period Hc includes three sub-periods Hc1 to Hc3.
  • the reset signal Vret and the selection signal WT both jump from a high level to a low level. Therefore, the reset signal Vret controls the first reset switch Tre1 and the second reset switch Tre2 to be turned on, so that the drive control terminal Ndrv and The drive output terminals Ncon are all at the low potential Vss and reset.
  • the selection signal WT controls the selection switch Tw to be turned on, so that the drive output terminal Ncon and all remaining signals in the circuit are released.
  • the reset signal Vret and the selection signal WT both jump from a low potential to a high potential
  • the compensation/setting signal WD jumps from a high potential to a low potential
  • the preset reset switch Tpr1 is turned on
  • the auxiliary voltage VD3 is loaded
  • the first driving transistor Td1 is controlled to be turned on
  • the driving control terminal Ndrv stores the auxiliary voltage VD3 through the driving capacitor Cd1.
  • the compensation/setting signal WD jumps from a low potential to a high potential, the preset reset switch Tpr1 is turned off, and the reset period Hc ends.
  • the reset period Hc After the reset period Hc ends, it enters the preparation period Hp, which includes two sub-periods Hp1 to Hp2.
  • the second preset signal WS2 jumps from a high potential to a low potential, triggering the second preset switch Tpe2 to turn on, and the low voltage Vss of the first low voltage terminal Vss1 is loaded through the second preset switch Tpe2
  • the pulse receiving switch Tps1 is controlled to be turned on, and the second driving voltage VDD2 is applied to the driving input node Ny through the pulse receiving switch Tps1.
  • the second preset signal WS2 jumps from a low level to a high level, the second preset switch Tpe2 is turned off, and the preparation period Hp ends
  • the data line Di in the sub-period Hp1 outputs a high-level signal.
  • the display period He is entered, and the display period He includes two sub-periods He1 to He2.
  • the selection signal WT decreases from a high potential to a low potential, and the selection switch Tw is turned on.
  • the first driving transistor Td1 cooperates with the second driving voltage VDD2 to provide a driving current Idrv to the driving output terminal Ncon to be loaded onto the light-emitting element EM through the selection switch Tw, thereby controlling the light-emitting element EM to perform image display of the image data signal Vdata.
  • the high-level signal output by the data line Di gradually decreases.
  • the first driving transistor Td1 is turned on to enter the sub-period He2.
  • the pulse signal output terminal Vout jumps from a low potential to a high potential.
  • the pulse receiving switch Tps1 is turned off under the control of a high-potential pulse signal, and the driving current Idrv is also turned off and reduced to a low current, and the light-emitting element EM stops emitting light.
  • the display period He ends, and at the same time one sub-scanning period Ts of one sub-pixel 103 ends.
  • FIG. 28 is a working timing diagram of the pixel circuit 1200 shown in FIG. 26 in this application during the display of one frame of image.
  • the pixel circuit 100 since the pixel circuit 100 includes six sub-pixels 103, the pixel circuit 100
  • the one-frame image display period includes at least six sub-scanning display periods Ts1 to Ts6.
  • the six sub-pixels 103 receive the driving current Idrv corresponding to the image data signal in a time sharing manner through six selection signals WT1 to WT6 in six sub-scanning periods Ts in one scanning period T to display image data by emitting light.
  • the six selection signals WT1 to WT6 respectively select the first red sub-pixel R1, the first green sub-pixel G1, the first blue sub-pixel B1, the second red sub-pixel R2, and the second green sub-pixel. G2 and the second blue sub-pixel B2 perform image display.
  • FIG. 29 is a schematic diagram of the specific circuit structure of the pixel circuit 1300 shown in FIG. 4 in the thirteenth embodiment of this application.
  • the pixel circuit 1300 is the same as the pixel circuit 1200 in the embodiment shown in FIG. 26, except that the driving execution circuit 102 in the pixel circuit 1300 does not have the preset reset switch Tpr1 shown in FIG. 26, and additionally includes compensation.
  • the unit 1024, the compensation unit 1024 is electrically connected to the drive control terminal Ndrv, the drive output terminal Ncon, and the drive input terminal Ny, and is used to compensate for the drift of the threshold voltage (Vth) of the first drive transistor Td1.
  • the compensation unit 1024 includes a first compensation transistor Tcv1 and a second compensation transistor Tcv2, wherein the first compensation transistor Tcv1 is electrically connected between the drive control terminal Ndrv and the drive output terminal Ncon, and is used to pre-load the first compensation transistor Tcv1 and Tcv2.
  • the threshold voltage Vth of the driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the first compensation transistor Tcv1 is a P-type thin film transistor, wherein the gate of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the first compensation transistor Tcv1 is electrically connected The driving output terminal Ncon; the drain of the thin film transistor as the first compensation transistor Tcv1 is electrically connected to the driving control terminal Ndrv.
  • the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny, and is used to synchronously load the auxiliary voltage VD3 to the driving control terminal Ndrv when the threshold voltage Vth of the first driving transistor Td1 is stored in the driving control terminal Ndrv.
  • the voltage value of the auxiliary voltage VD3 can be set according to the parameter characteristics of the first driving transistor Td1.
  • the second compensation transistor Tcv2 is a P-type thin film transistor, wherein the gate of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the compensation/setting signal WD; the source of the thin film transistor as the second compensation transistor Tcv2 receives the auxiliary voltage VD3; the drain of the thin film transistor as the second compensation transistor Tcv2 is electrically connected to the driving input terminal Ny.
  • the compensation/setting signal WD jumps from a high level to a low level, and the first compensation transistor Tcv1 and the second compensation transistor Tcv2 are turned on.
  • the gate and drain of the first driving transistor Td1 are directly electrically connected to form a diode connection, so that the voltage of the driving control terminal Vdrv is the voltage of the driving voltage input terminal Ny minus the threshold voltage Vth2 of the first driving transistor Td1.
  • the auxiliary voltage VD3 is applied to the driving input terminal Ny through the second compensation transistor Tcv2.
  • the drive control terminal Vdrv is (Vd3-Vth2), so that the threshold voltage Vth of the second compensation transistor Tcv2 is written to the drive control terminal Vdrv in advance, so that the pulse signal corresponding to the subsequent image data signal is loaded to the drive
  • the terminal Vdrv is controlled, the influence of the drift band of the threshold voltage Vth of the first driving transistor Td1 on the driving current Idrv can be eliminated.
  • FIG. 30 is a schematic diagram of the specific circuit structure of the pixel circuit 1400 shown in FIG. 4 in the fourteenth embodiment of this application.
  • the pixel circuit 1400 is basically the same as the pixel circuit 1300 corresponding to 29 in the figure, except that K in the number of sub-pixel units 103 is 3, and other circuit structures and working modes are the same.
  • the pixel circuit 1400 includes three sub-pixels 103, that is, K is 3.
  • the three sub-pixels 103 are respectively the first red sub-pixel R1, the first green sub-pixel G1, and the first blue sub-pixel B1 in the order from left to right. Therefore, the pixel circuit 1400 corresponds to one frame
  • the scanning period T of the image includes three sub-scanning periods Ts corresponding to the three sub-pixels 103.
  • FIG. 31 is a schematic diagram of a specific circuit structure of the pixel circuit 1500 shown in FIG. 4 in the fifteenth embodiment of this application.
  • the pixel circuit 1500 is basically the same as the pixel circuit 1300 in the embodiment corresponding to FIG. 29. The only difference is that the types of switching elements in the conversion circuit 101, the drive execution circuit 102, and the sub-pixel 103 are different.
  • the pixel circuit 1300 circuit All switching elements and transistors in are N-type thin film transistors.
  • the conversion circuit 101 includes a storage capacitor Cst1, a first preset switch Tpe1, a second preset switch Tpe2, and a conversion transistor Ttr.
  • the first storage capacitor Cst1 is electrically connected between the data line Di and the data output node Ncst, for storing the image data signal Vdata received from the data line Di, and charging the data output node Ncst to the same potential as the image data signal Vdata .
  • the conversion transistor Ttr is electrically connected to the data output node Ncst, the first driving voltage terminal VDD1 and the pulse signal output terminal Vout, and is used to turn on or off under the voltage control of the data output node Ncst to selectively transmit the driving voltage VDD To the pulse signal output terminal for the pulse signal Vout.
  • the conversion transistor Ttr is an N-type thin film transistor, the gate is electrically connected to the data conversion contact Ncst, the drain is electrically connected to the pulse signal output terminal Vout, and the source is electrically connected to the first driving voltage terminal VDD1.
  • the driving voltage VDD is transmitted to the pulse signal output terminal Vout through the switching transistor Ttr, and the high potential is used as the potential of the pulse signal Vout.
  • the driving voltage VDD stops the pulse signal output terminal Vout.
  • the first preset switch Tpe1 is electrically connected between the data output node Ncst and the pulse signal output terminal Vout, and is used to directly electrically conduct the data output node Ncst and the pulse signal output terminal Vout under the control of the first preset signal WS1 , So that the gate and drain of the conversion transistor are directly electrically connected in a diode connection.
  • the first preset switch Tpe1 is an N-type thin film transistor, the gate of which receives the first preset signal WS1, the source is electrically connected to the data output node Ncst, and the drain is electrically connected to the pulse signal output terminal Vout.
  • the second preset switch Tpe2 is electrically connected between the pulse signal output terminal Vout and the first low voltage terminal Vss1, and is used to electrically connect the first low voltage terminal Vss1 and the pulse signal output terminal Vout under the control of the second preset signal WS2.
  • the electrical conduction makes the pulse signal Vout output by the pulse signal output terminal Vout have a low potential.
  • the second preset switch Tpe2 is an N-type thin film transistor, the gate receives the second preset signal WS2, the source is electrically connected to the first low voltage terminal Vss1, and the drain is electrically connected to the pulse signal output terminal Vout.
  • the driving execution circuit 102 includes a pulse receiving switch Tps1, a first driving transistor Td1, a preset reset switch Tpr1, a first reset switch Tre1, a second reset switch Tre2, and a driving capacitor Cd1.
  • the pulse receiving switch Tps1 is electrically connected between the pulse output terminal Vout of the comparator CP1, the second driving voltage terminal VDD2 and the driving input terminal Ny.
  • the pulse receiving switch Tps1 is used to selectively load the driving voltage VDD to the driving input terminal Ny under the control of the pulse signal Vout output from the pulse output terminal Vout.
  • both the first driving voltage terminal VDD1 and the second driving voltage terminal VDD2 are used to provide a driving voltage VDD
  • the driving voltage VDD is used to cooperate with the first driving transistor Td1 to provide a driving current Idrv.
  • the turn-on and turn-off time of the pulse receiving switch Tps1 corresponds to the high and low potential duration of the pulse signal Vout. That is, when the pulse receiving switch Tps1 is turned on under the low level control of the pulse signal Vout, the driving voltage VDD is loaded to the driving input terminal Ny; it is turned off under the high level control of the pulse signal Vout, and the driving voltage VDD stops loading To the drive input terminal Ny.
  • the pulse receiving switch Tps1 is an N-type thin film transistor, wherein the gate of the thin film transistor serving as the pulse receiving switch Tps1 is electrically connected to the pulse signal output terminal Vout to receive the pulse signal Vout output by the comparator CP1; as a pulse
  • the source of the thin film transistor of the receiving switch Tps1 is electrically connected to the first driving voltage terminal VDD1; the drain of the thin film transistor as the pulse receiving switch Tps1 is electrically connected to the driving output terminal.
  • the first driving transistor Td1 is electrically connected to the driving control terminal Ndrv, the driving input terminal Ny, and the driving output terminal Ncon, and is used to provide a driving current Idrv to the driving output terminal Ncon under the control of a signal loaded by the driving control terminal Ndrv.
  • the first driving transistor Td1 is an N-type thin film transistor, wherein the gate of the thin film transistor serving as the first driving transistor Td1 is electrically connected to the driving control terminal Ndrv; and the source of the thin film transistor serving as the first driving transistor Td1
  • the driving input terminal Ny is electrically connected; the drain of the thin film transistor as the first driving transistor Td1 is electrically connected to the driving output terminal Ncon.
  • the driving capacitor Cd1 is electrically connected to the second driving voltage terminal VDD2 and the driving control terminal Ndrv, and is used for storing and maintaining the driving control terminal Ndrv at a stable potential within a preset time period, so as to control the first driving transistor Td1 at the preset time Maintain the conduction within.
  • the first reset switch Tre1 and the second reset switch Tre2 are respectively electrically connected to the drive control terminal Ndrv and the drive output terminal Vcon, and are used to provide a reset signal Vrst when the sub-pixel 103 stops displaying images (reset period) to ensure that the drive control terminal Ndrv and the drive output terminal Ncon are maintained in a reset state.
  • the first reset switch Tre1 is an N-type thin film transistor, wherein the gate of the thin film transistor serving as the first reset switch Tre1 receives the reset signal Vrst; the source of the thin film transistor serving as the first reset switch Tre1 is electrically connected The first low voltage terminal Vss1; the drain of the thin film transistor as the first reset switch Tre1 is electrically connected to the driving control terminal Ndrv.
  • the second reset switch Tre2 is an N-type thin film transistor, wherein the gate of the thin film transistor serving as the second reset switch Tre2 receives the reset signal Vrst; the source of the thin film transistor serving as the second reset switch Tre2 is electrically connected The first low voltage terminal Vss1; the drain of the thin film transistor as the second reset switch Tre2 is electrically connected to the driving output terminal Ncon.
  • each sub-pixel 103 includes a selection switch Tw and a light-emitting element EM.
  • the selection switch Tw and the light-emitting element EM of the plurality of sub-pixels 103 are passed through the position
  • the sequence number of the arrangement is distinguished, for example, the selection switch Tw1 and the light-emitting element EM1 in the sub-pixel 103 in the first position on the left, and so on, the selection switch Tw6 and the light-emitting element EM6 in the sub-pixel 103 in the last position on the right.
  • Each light emitting element EM is electrically connected between the driving output terminal Ncon and the second low voltage terminal Vss2 through a selection switch EM.
  • the selection switch Tw1 is an N-type thin film transistor, and the light-emitting element EM is electrically connected between the drive output terminal Ncon and the second low voltage terminal Vss2 through the selection switch Tw.
  • all the switching elements and transistors are N-type thin film transistors, so that the leakage current of the switching elements and transistors in the pixel circuit 1500 is small, which further reduces power consumption.

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Abstract

一种像素电路（100）以及包括像素电路（100）的阵列基板与显示装置，像素电路（100）包括驱动电路和多个子像素（103），驱动电路包括一个转换电路（101）和一个或多个驱动执行电路（102）。转换电路（101）用于接收模拟形态的图像数据信号，并且将模拟形态的图像数据信号转换为数字形态的图像数据信号。在驱动电路包括一个驱动执行电路（102）时，驱动执行电路（102）电性连接转换电路（101），用于接收数字形态的图像数据信号，并依据数字形态的图像数据信号分时提供驱动电流至多个子像素（103），驱动多个子像素（103）执行图像显示。在驱动电路包括多个驱动执行电路（102）时，多个驱动执行电路（102）与多个子像素（103）是一对一的，每一驱动执行电路（102）电性连接于转换电路（101）以及对应的子像素（103）之间。

Description

像素电路、阵列基板与显示装置 技术领域
本申请涉及显示驱动领域，特别是涉及一种像素电路、阵列基板与显示装置。
背景技术
在自发光显示面板显示图像的过程中，需要扫描驱动电路提供栅极扫描信号，用于配合数据驱动电路提供图像数据信号驱动设置在图像显示区的像素单元阵列执行图像显示。
每个像素单元中包括执行图像显示的红、绿和蓝三个子像素以及分别用于驱动这三个子像素的三个驱动电路，每个驱动元件均包括薄膜晶体管和电容。目前而言，每个子像素需要一个完整的驱动电路来驱动其发光，由此将会导致每个像素单元中的三个驱动电路占用的空间大，进而导致该显示面板无法满足高图像分辨率中高像素密度(Pixels Per Inch,PPI)的需求且功耗较大。
发明内容
本申请实施例提供一种功耗较小且显示效果较佳的像素电路。
在本申请一实施例中，提供一种像素电路，像素电路包括驱动电路和多个子像素，所述驱动电路包括一个转换电路和一个或多个驱动执行电路，所述转换电路用于接收模拟形态的图像数据信号，并且将所述模拟形态的图像数据信号转换为数字形态的图像数据信号。在所述驱动电路包括一个所述驱动执行电路时，所述驱动执行电路电性连接所述转换电路，用于接收所述数字形态的图像数据信号，并依据所述数字形态的图像数据信号分时提供驱动电流至所述多个子像素，驱动所述多个子像素(103)执行图像显示。在所述驱动电路包括多个所述驱动执行电路时，多个所述驱动执行电路与多个所述子像素是一对一的，每一所述驱动执行电路电性连接于所述转换电路以及对应的所述子像素之间。由于一个驱动电路能够同时驱动多个子像素发光以执行图像显示，从而有效降低了像素电路占用的面积以及像素电路电子元件的数量，有效降低了像素电路的面积以及执行图像显示时功耗，进而满足图像显示分辨率的而需求，使得图像显示较佳。
在本申请一实施例中，所述转换电路包括扫描开关、存储电容(以及比较器。所述扫描开关在接收到扫描信号时处于导通状态以将所述模拟形态的图像数据信号传输至所述存储电容。所述存储电容电性连接所述比较器的第一相位输入端，用于接收与存储所述模拟形态的图像数据信号并加载至所述比较器。所述比较器的第二相位输入端接收第一参考信号，所述第一参考信号为斜坡信号。所述比较器依据所述模拟形态的图像数据信号与所述第一参考信号中电压值的比较结果，自所述比较器的脉冲信号输出端输出数字形态的脉冲信号，所述数字形态的脉冲信号表征所述数字形态的图像数据信号。
比较器通过将图像数据信号与作为斜坡信号的第一参考信号进行比较，就能够准确以及图像数据信号输出对应占空比的脉冲信号，进而准确将模拟形态的图像数据信号转换为数字形态的对应图像数据信号的脉冲信号。
在本申请一实施例中，所述第一参考信号为三角波信号，以便于准确依据图像数据信 号输出不同占空比的脉冲信号。
在本申请一实施例中，所述扫描开关为P型薄膜晶体管，所述P型薄膜晶体管的栅极用于接收所述扫描信号，所述P型薄膜晶体管的源极用于接收图像数据信号，所述P型薄膜晶体管的漏极通过数据输出节点电性连接于所述第一相位输入端，所述存储电容电性连接于所述数据输出节点和接地端之间。扫描开关为P型薄膜晶体管的制作工艺较为简便，且阈值电压较为稳定。
在本申请一实施例中，所述扫描开关为N型薄膜晶体管，所述N型薄膜晶体管的栅极用于接收所述扫描信号；所述N型薄膜晶体管的源极用于接收图像数据信号；所述N型薄膜晶体管的漏极通过数据输出节点电性连接于所述第一相位输入端，所述存储电容电性连接于第一驱动电压端与所述数据输出节点之间。扫描开关为N型薄膜晶体管的漏电流较小使得功耗较低，并且能够准确维持数据输出节点(Ncst)的电压稳定。
在本申请一实施例中，所述第一相位输入端为反相输入端，所述第二相位输入端为同相输入，所述第一参考信号的电压值逐渐减小再逐渐增大，且所述电压值增大与减小的速度相同。
在本申请一实施例中，当所述第一参考信号的电压值小于所述模拟形态的图像数据信号时，所述脉冲信号为低电位；当所述第一参考信号的电压值大于所述模拟形态的图像数据信号时，所述脉冲信号为高电位。对称的三角形波形的第一参考信号能够更加准确地依据图像数据信号输出对应占空比的脉冲信号。
在本申请一实施例中，所述比较器包括第一输入开关、第二输入开关、第一镜像开关、第二镜像开关、第一输出开关、以及第二输出开关以及第一参考开关。第一输入开关、第二输入开关、第一参考开关(以及第一输出开关为P型薄膜晶体管，第一镜像开关、第二镜像开关以及第二输出开关为N型薄膜晶体管。所述第一输入开关的栅极电性连接所述第一相位输入端，所述第一输入开关的源极电性连接所述第一参考开关，所述第一输入开关的漏极电性连接第一镜像开关。所述第二输入开关的栅极电性连接所述第二相位输入端，所述第二输入开关的源极电性连接所述第一参考开关，所述第二输入开关的漏极电性连接所述第二镜像开关。所述第一镜像开关的栅极与漏极直接电性连接并且电性连接于所述第一输入开关的漏极，所述第一镜像开关的栅极与所述第二镜像开关的栅极电性连接，所述第一镜像开关的源极电性连接第一低电压端。所述第二镜像开关的漏极电性连接于所述第二输入开关的漏极，所述第二镜像开关的源极电性连接所述第一低电压端，所述第二镜像开关的漏极与所述第二输入开关的漏极同时电性连接至比较中间节点。所述第一参考开关的栅极接收参考电压，所述第一参考开关的漏极电性连接所述第一输入开关与所述第二输入开关，所述第一参考开关的源极电性连接所述第一驱动电压端，所述参考电压控制所述第一参考开关处于常开状态。所述第一输出开关的栅极电性连接所述比较中间节点，所述第一输出开关的源极电性连接所述第一驱动电压端，所述第一输出开关的漏极电性连接所述脉冲输出端。所述第二输出开关的栅极电性连接所述比较中间节点，所述第二输出开关的源极电性连接所述第一低电压端，所述第二输出开关的漏极电性连接所述脉冲信号输出端。
在本申请一实施例中，所述比较器还包括比较复位开关，所述比较复位开关电性连接 于所述脉冲信号输出端与第一低电压端，当所述比较复位开关在复位信号控制下导通时控制所述脉冲信号输出端停止输出所述脉冲信号。比较复位开关能够准确控制比较器输出脉冲信号的时间。
在本申请一实施例中，所述比较器包括第一输入开关、第二输入开关、第一镜像开关、第二镜像开关以及第一输出开关、第二输出开关以及第一参考开关。第一输入开关、第二输入开关、第一参考开关以及第一输出开关为N型薄膜晶体管，第一镜像开关、第二镜像开关以及第二输出开关为P型薄膜晶体管。所述第一输入开关的栅极电性连接所述第一相位输入端，所述第一输入开关的源极电性连接所述第一参考开关，所述第一输入开关的漏极电性连接第一镜像开关。所述第二输入开关的栅极电性连接所述第二相位输入端，所述第二输入开关的源极电性连接所述第一参考开关，所述第二输入开关的漏极电性连接比较中间节点。所述第一镜像开关的栅极与漏极直接电性连接并且同时电性连接于所述第一输入开关的漏极，所述第一镜像开关的栅极与所述第二镜像开关的栅极电性连接，所述第一镜像开关的源极电性连接所述第一驱动电压端。所述第二镜像开关的漏极电性连接于所述第二输入开关的漏极，所述第二镜像开关的源极电性连接所述第一驱动电压端，所述第二镜像开关的漏极与所述第二输入开关的漏极同时电性连接至所述比较中间节点。所述第一参考开关的栅极接收参考电压，所述第一参考开关的漏极电性连接所述第一输入开关与所述第二输入开关，所述第一参考开关的源极电性连接所述第一低电压端，所述参考电压控制所述第一参考开关处于常开状态。所述第一输出开关的栅极电性连接所述比较中间节点，所述第一输出开关的源极电性连接所述第一驱动电压端，所述第一输出开关的漏极电性连接所述脉冲输出端。所述第二输出开关的栅极电性连接所述比较中间节点，所述第二输出开关的源极电性连接所述第一低电压端，所述第二输出开关的漏极电性连接所述脉冲信号输出端。
在本申请一实施例中，所述比较器还包括比较复位开关，所述比较复位开关电性连接于所述脉冲信号输出端与所述第一驱动电压端，当所述比较复位开关在复位信号控制下导通时控制所述脉冲信号输出端停止输出所述脉冲信号。
在本申请一实施例中，所述第一相位输入端为同相输入端，所述第二相位输入端为反相输入端，所述第一参考信号的电压自低电位逐渐增大到高电位再自高电位逐渐减小至低电位，且所述电压值减小与增加的速度相同。
在本申请一实施例中，所述比较器包括第一输入开关、第二输出开关、第一参考开关以及第一输出开关、第一镜像开关、第二镜像开关以及第二输出开关。第一输入开关、第二输入开关、第一参考开关以及第一输出开关为P型薄膜晶体管，第一镜像开关、第二镜像开关以及第二输出开关为N型薄膜晶体管。所述第一输入开关的栅极电性连接所述第二相位输入端，所述第一输入开关的源极电性连接所述第一参考开关，所述第一输入开关的漏极电性连接第一镜像开关。所述第二输入开关的栅极电性连接所述第一相位输入端，所述第二输入开关的源极电性连接所述第一参考开关，所述第二输入开关的漏极电性连接所述第二镜像开关。所述第一镜像开关的栅极与漏极直接电性连接并且同时电性连接于所述第一输入开关的漏极，所述第一镜像开关的栅极与所述第二镜像开关的栅极电性连接，所述第一镜像开关的源极电性连接第一低电压端。所述第二镜像开关的漏极电性连接于所述 第二输入开关的漏极，所述第二镜像开关的源极电性连接所述第一低电压端，所述第二镜像开关的漏极与所述第二输入开关的漏极同时电性连接至比较中间节点。所述第一参考开关的栅极接收参考电压，所述第一参考开关的漏极电性连接所述第一输入开关与所述第二输入开关，所述第一参考开关的源极电性连接所述第一驱动电压端，所述参考电压控制所述第一参考开关处于常开状态。所述第一输出开关的栅极电性连接所述比较中间节点，所述第一输出开关的源极电性连接所述第一驱动电压端，所述第一输出开关的漏极电性连接所述脉冲输出端。所述第二输出开关的栅极电性连接所述比较中间节点，所述第二输出开关的源极电性连接所述第一低电压端，所述第二输出开关的漏极电性连接所述脉冲信号输出端。
在本申请一实施例中，所述比较器还包括迟滞单元，所述迟滞单元电性连所述脉冲信号输出端、所述第一相位输入端与所述数据输出节点，所述迟滞单元用于控制所述第一相位输入端与所述第二相位输入端接收的信号的电压差值大于第一阈值或者小于第二阈值时，所述脉冲信号的电位发生变化，且所述第一阈值小于所述第二阈值。
具体地，所述迟滞单元电性包括第一迟滞电阻与第二迟滞电阻，所述第一迟滞电阻电性连接于所述第一相位输入端与所述数据输出节点)之间，所述第二迟滞电阻电性连接于所述第一相位输入端与所述脉冲信号输出端之间。
迟滞单元通过延迟图像数据信号比较时输出脉冲信号的时间，从而有效消除图像数据信号具有噪音时对输出的脉冲信号的影响，保证脉冲信号输出的准确性与稳定性。
在本申请一实施例中，所述驱动执行电路包括驱动控制端、第一驱动晶体管、驱动电容、第一复位开关与驱动输出端。所述驱动电容电性连接于所述第一驱动电压端与驱动控制端之间，所述驱动电容用于在预设时间段内逐渐存储或者释放脉冲信号，并维持驱动控制端的电压与所述脉冲信号电压值相同。所述第一驱动晶体管电性连接于所述第一驱动电压端、所述驱动控制端以及所述驱动输出端，所述第一驱动晶体管在所述驱动控制端提供的所述脉冲信号控制下导通或者关断，当所述第一驱动晶体管导通时，所述第一驱动晶体管配合所述第一驱动电压端提供的驱动电压自所述驱动输出端输出所述驱动电流。所述第一复位开关电性连接于所述驱动输出端，用于在所述子像素(停止图像显示时提供复位电压至所述驱动输出端。驱动执行电路能够依据脉冲信号准确提供驱动电流至各个子像素，以驱动子像素准确出射光线显示图像。
在本申请一实施例中，所述驱动执行电路还包括补偿单元，所述补偿单元电性连接于所述驱动控制端，用于补偿所述第一驱动晶体管阈值电压漂移，所述补偿单元包括第一补偿晶体管，所述第一补偿晶体管电性连接于所述驱动控制端与所述驱动输出端之间，用于预先将所述第一驱动晶体管的阈值电压存储到所述驱动控制端，当所述第一驱动晶体管输出所述驱动电流时所述驱动控制端(Ndrv)存储的所述阈值电压抵消驱动电流中所述阈值电压。
所述补偿单元还包括第二补偿晶体管，所述第二补偿晶体管电性连接于驱动输入端，用于在所述第一驱动晶体管的阈值电压存储到所述驱动控制端时，将辅助电压与所述阈值电压同步加载至所述驱动控制端。
补偿单元能够有效消除第一驱动晶体管本身的阈值电压漂移对驱动电流的影响，也即 是能够使得驱动电流能够准确地驱动子像素准确出射光线，保证显示的图像的准确性。
在本申请一实施例中，所述驱动执行电路还包括第二复位开关，所述第二复位开关电性连接于所述驱动控制端与所述第一低电压端之间，用于在接收到复位信号时将所述第一低电压端(提供的低电压加载至所述驱动控制端对所述驱动控制端复位。第二复位开关能够准确针对驱动控制端进行复位，从而保证在子像素图像显示时间段中驱动电流输出的准确性。
在本申请一实施例中，所述驱动执行电路还包括脉冲接收开关，所述脉冲接收开关电性连接所述转换电路用于接收所述脉冲信号，并且依据所述脉冲信号的控制选择性将所述驱动电压提供至所述第一驱动晶体管，当所述脉冲接收开关在所述脉冲信号控制下导通时，所述第一驱动电压通过所述脉冲接收开关传输至所述第一驱动晶体管，当所述脉冲接收开关在所述脉冲信号控制下关断时，所述驱动电压停止传输至所述第一驱动晶体管。脉冲接收开关能够准确地依据脉冲信号提供驱动电压至第一驱动晶体管，以便于第一驱动晶体管准确提供驱动电流。
在本申请一实施例中，所述第一驱动晶体管、所述脉冲接收开关、第一补偿晶体管与第二补偿晶体管为P型薄膜晶体管，所述第一复位开关与所述第二复位开关为N型薄膜晶体管，每个子像素包括选择开关与发光元件，所述发光元件通过所述选择开关电性连接所述驱动执行电路的驱动输出端，当所述选择开关在选择信号控制下导通时，所述驱动电流通过所述选择开关传输至所述发光元件，驱动所述发光元件发光并显示所述图像数据，所述选择开关为P型薄膜晶体管，所述发光元件电性通过所述选择开关电性连接所述驱动输出端与第二低电压端之间。处于驱动回路上的述第一驱动晶体管、所述脉冲接收开关、第一补偿晶体管与第二补偿晶体管以及选择开关Tw为P型薄膜晶体管均为P型薄膜晶体管，从而使得驱动执行电路与子像素中的阈值电压漂移较小。而处于其他支路上的第一复位开关与所述第二复位开关为N型薄膜晶体管，漏电流较小且控制反应速度较快。
在本申请一实施例中，所述第一驱动晶体管、所述脉冲接收开关、第一补偿晶体管与第二补偿晶体管为N型薄膜晶体管，所述第一复位开关与所述第二复位开关为P型薄膜晶体管，每个子像素包括选择开关与发光元件，所述发光元件通过所述选择开关电性连接所述驱动执行电路的驱动输出端，当所述选择开关在选择信号控制下导通时，所述驱动电流通过所述选择开关传输至所述发光元件，驱动所述发光元件发光并显示所述图像数据，所述选择开关为N型薄膜晶体管，所述发光元件通过所述选择开关电性连接所述驱动输出端与第二驱动电压端之间，所述第二驱动电压端用于提供驱动电压配合所述第一驱动晶体管提供所述驱动电流。
在本申请一实施例中，所述像素电路包括三个子像素，所述三个子像素接收同一个数据线提供的所述图像数据信号以及接收同一个扫描线提供的扫描信号，所述扫描信号包括三个子扫描周期；或者，
所述像素电路包括六个子像素，所述六个子像素接收同一个数据线提供的所述图像数据信号且接收同一个扫描线提供的扫描信号，所述扫描信号包括六个子扫描周期。
在本申请一实施例中，当所述像素电路包括三个子像素时，所述三个子像素分别出射不同颜色的光线；当所述像素电路包括六个子像素时，每两个像素发射相同颜色的光线， 所述六个子像素分别出射三种不同颜色光线，且任意相邻的两个子像素出射不同颜色的光线。
在本申请一实施例中，当所述像素电路包括六个子像素时，至少两个相邻的子像素不在相邻的子扫描周期出射光线，从而保证像素电路中出射的光线较为均匀。
在本申请一实施例中，所述转换电路包括存储电容、第一预置开关、第二预置开关以及转换晶体管。
具体地，所述存储电容电性连接于数据输出节点，用于将接收到的图像数据信号对所述数据输出节点充电至与所述图像数据信号相同的电位。所述转换晶体管电性连接所述数据输出节点、第一驱动电压端以及脉冲信号输出端，用于在所述数据输出节点的电压控制下导通或者关断，当所述转换晶体管在所述数据输出节点的电压控制下导通时，所述第一驱动电压通过所述转换晶体管传输至脉冲信号输出端并且将高电位作为所述脉冲信号的电位。所述第一预置开关电性连接于所述数据输出节点与所述脉冲信号输出端之间，用于在第一预置信号控制下将所述数据输出节点与所述脉冲信号输出端直接电性导通，使得所述转换晶体管的栅极与漏极直接电性连接呈二极管连接。所述第二预置开关(Tpe2)电性连接于脉冲信号输出端与第一低电压端之间，用于在第二预置信号控制下将第一低电压端与脉冲信号输出端电性导通，使得脉冲信号输出端输出的脉冲信号为低电位。所述驱动执行电路包括脉冲接收开关、第一驱动晶体管与驱动电容，
所述脉冲接收开关电性连接脉冲输出端、第二驱动电压端与驱动输入端之间，用于在脉冲输出端输出的所述脉冲信号控制下选择性将所述驱动电压加载至驱动输入端。所述第一驱动晶体管电性连接于所述第一驱动电压端、所述驱动控制端以及所述驱动输出端，所述第一驱动晶体管在所述驱动控制端提供的所述脉冲信号控制下导通或者关断，当所述第一驱动晶体管导通时，所述第一驱动晶体管配合第一驱动电压端提供的驱动电压自所述驱动输出端输出所述驱动电流。所述驱动电容电性连接于所述第二驱动电压端与所述驱动控制端，用于存储并在预设时间段内维持驱动控制端处于稳定的电位以控制第一驱动晶体管在预设时间内维持导通。
转换电路直接将模拟形态的图像数据信号转换为对应占空比的脉冲信号，并提供至驱动执行电路，使得驱动电路的电路元件较少且结构较为简单，能够进一步降低像素电路所占用的空间。
在本申请一实施例中，所述驱动执行电路还包括第一复位开关与第二复位开关，所述第一复位开关与所述第二复位开关分别电性连接于所述驱动控制端与驱动输出端，用于在所述子像素停止图像显示时控制所述驱动控制端与驱动输出端复位。
在本申请一实施例中，每个子像素包括选择开关与发光元件，所述发光元件通过所述选择开关电性连接所述驱动执行电路，当选择开关在显示选择信号控制下导通时，所述驱动电流通过所述选择开关传输至所述发光元件，驱动所述发光元件发光并显示所述图像数据。
在本申请一实施例中，所述驱动执行电路还包括预置复位开关，所述预置复位开关电性连接于所述驱动控制端，用于在所述子像素出射光线之前的复位时间段加载辅助电压至所述驱动控制端，所述辅助电压用于控制所述第一驱动晶体管处于导通。
在本申请一实施例中，所述驱动执行电路还包括补偿单元，所述补偿单元电性连接于所述驱动控制端，用于补偿所述第一驱动晶体管阈值电压漂移，所述补偿单元包括第一补偿晶体管与第二补偿晶体管，所述第一补偿晶体管电性连接于所述驱动控制端与所述驱动输出端之间，用于预先将所述第一驱动晶体管的阈值电压存储到所述驱动控制端，当所述第一驱动晶体管输出所述驱动电流时，所述驱动控制端存储的所述阈值电压抵消驱动电流中阈值电压。所述第二补偿晶体管电性连接于驱动输入端，用于在所述第一驱动晶体管的阈值电压存储到所述驱动控制端时，将辅助电压与所述阈值电压同步加载至所述驱动控制端。
在本申请一实施例中，所述像素电路包括三个子像素或者六个子像素，所述三个像素单元或者所述六个显示单元接收同一个数据线提供的所述图像数据信号且接收同一个扫描线提供的扫描信号，所述扫描信号包括三个子扫描周期或者六个子扫描周期。
在本申请一实施例中，当所述像素电路包括三个子像素时，所述三个子像素分别出射不同颜色的光线；当所述像素电路包括六个子像素时，每两个子像素发射相同颜色的光线，所述六个子像素分别出射三种不同颜色光线，任意相邻的两个子像素出射不同颜色的光线，且至少两个相邻的子像素不在相邻的子扫描周期出射光线。
在本申请一实施例中，第一预置开关、第二预置开关、转换晶体管、脉冲接收开关、第一驱动晶体管、第一复位开关、第一复位开关、第二复位开关、多个选择开关以及第二补偿开关为P型薄膜晶体管，且每个子像素中所述发光元件电性通过所述选择开关电性连接所述驱动输出端与第二低电压端之间。P型薄膜晶体管的制作工艺较为简便，且阈值电压较为稳定。
在本申请一实施例中，第一预置开关、第二预置开关、转换晶体管、脉冲接收开关、第一驱动晶体管、第一复位开关、第一复位开关、第二复位开关、多个选择开关以及第二补偿开关为N型薄膜晶体管，且每个子像素中所述发光元件电性通过所述选择开关电性连接所述驱动输出端与第二驱动电压端之间，所述第二驱动电压端用于提供驱动电压且配合所述第一驱动晶体管提供所述驱动电流。N型薄膜晶体管的漏电流较小使得功耗较低，并且能够准确维持数据输出节点的电压稳定。
在本申请一实施例中，所述子像素为Micro-LED显示单元。
在本申请一实施例中，提供一种阵列基板，阵列基板包括位于显示区内的多个用于执行图像显示的前述的像素电路、多条数据线与多条扫描线，所述扫描线沿第一方向延伸并沿着第二方向间隔预设距离绝缘设置，所述数据线沿着所述第二方向延伸并且沿着第一方向间隔预设距离绝缘设置，所述第一方向垂直于所述第二方向，所述数据线用于提供所述图像数据信号，所述扫描线用于提供所述扫描信号，任意相邻的两条所述数据线与任意相邻的两条扫描线定义一个像素单元，所述像素单元设置一个所述像素电路。
在本申请一实施例中，提供一种显示装置，包括前述的阵列基板。
附图说明
图1为本申请一实施例中显示面板的平面结构示意图；
图2为图1所示显示面板的侧面结构示意图；
图3为图2所示显示面板中阵列基板的平面结构示意图。；
图4为本申请第一实施例中如图3所示多个像素电路中任意一个像素电路的电路框图；
图5为本申请第二实施例中如图3所示多个像素电路中任意一个像素电路的电路框图；
图6为本申请第一施例中如图4所示像素电路中的电路结构示意图；
图7为如图6所示像素电路中比较器的电路结构示意图；
图8为本申请第一实施例中如图7所示比较器工作时的时序图；
图9为本申请第一实施例中如图4所示像素电路的具体电路结构示意图；
图10为如图9所示像素电路工作时序图；
图11为本申请第三实施例中如图4所示像素电路的具体电路结构示意图；
图12为如图11所示像素电路工作时序图；
图13为本申请第四实施例中如图4所示像素电路的具体电路结构示意图；
图14为图13所示像素电路工作时序图；
图15为本申请第五实施例中如图4所示像素电路的具体电路结构示意图；
图16为本申请第六实施例中如图4所示像素电路的具体电路结构示意图；
图17为本申请第七实施例中如图4所示像素电路的具体电路结构示意图；
图18为本申请第八实施例中如图4所示像素电路的电路框图；
图19为图18所示所示像素电路的具体电路结构示意图；
图20为如图19所示比较器工作时的时序图；
图21为如图18所示像素电路的时序电路图；
图22为本申请第九实施例中如图4所示像素电路的具体电路结构示意图；
图23为本申请第十实施例中如图4所示像素电路的具体电路结构示意图；
图24为如图23所示迟滞单元输入输出信号时序图；
图25为本申请第十一实施例中如图4所示像素电路的具体电路结构示意图；
图26为本申请第十二实施例中如图4所示像素电路的具体电路结构示意图；
图27为如图26所示像素电路中一个子像素的工作时序图；
图28为如图26所示的像素电路在1帧图像显示期间的工作时序图；
图29为本申请第十三实施例中如图4所示像素电路的具体电路结构示意图；
图30为本申请第十四实施例中如图4所示像素电路的具体电路结构示意图；
图31为本申请第十五实施例中如图4所示像素电路的具体电路结构示意图。
具体实施方式
下面结合附图，对本发明的实施例进行描述。
图1为本申请一实施例中显示面板11的平面结构示意图。该显示面板11用于执行图像显示。具体的，显示面板11其中一侧面包括显示区11a与非显示区11b。显示区11a用于执行图像显示，非显示区11b环绕设置于显示区11a周围以设置其他辅助部件或者模组，本实施例中，显示面板11可以被应用在增强显示(Augmented Reality,AR)或者虚拟显示(Virtual Reality,VR)、电视、移动智能终端或平板电脑等电子产品中。
图2为图1所示显示面板11的侧面结构示意图。具体地，显示面板11包括有阵列基 板11c与对向基板11d，以及夹设于阵列基板11c与对向基板11d的显示介质层11e。本实施例中，显示介质层中的显示介质为微型-发光二极管材料(Micro-Light Emitting Diode，Micro-LED/u-LED)。
请参阅图3，其为图2所示显示面板11中阵列基板11c的平面结构示意图。如图3所示，阵列基板11c中对应图像显示区11a的区域包括多个呈矩阵排列的n*m个像素单元(Pixel)P、m条数据线(Data Line)120与n条扫描线(Scan Line)130，m和n均为大于1的自然数。
其中，该多条数据线120沿第二方向Y平行排列，且该多条数据线120中每相邻两根数据线120之间间隔第一预定距离。该多条扫描线130沿第一方向X平行排列，且该多条扫描线130中每相邻两根扫描线130之间间隔第二预定距离。进一步地，该多条数据线120之间相互绝缘，该多条扫描线130之间相互绝缘，并且多条扫描线130与多条数据线120相互绝缘。值得注意的是，所述第一方向X与第二方向Y相互垂直。
为便于说明，所述m条数据线120按照位置顺序分别定义为Da1、Da2、……、Dam；所述n条扫描线130按照位置顺序分别定义为Ga1、Ga2、……，Gan。
任意相邻两条扫描线130与任意相邻两条数据线120定义一个像素单元P的区域，在该像素单元P的区域内设置一个像素电路(Pixel Circuit,PC)，每一个像素电路PC电性连接一条沿着第一方向X延伸设置的扫描线130以及沿着第二方向Y延伸设置的数据线120。
非显示区11b设置有用于驱动像素电路PC进行图像显示的时序控制电路101、数据驱动(Data Driver)电路102与扫描驱动(Scan Driver)电路103。其中，时序控制电路101、数据驱动执行电路102与扫描驱动电路103均设置于阵列基板11c上。
数据驱动执行电路102与该多条数据线120电性连接，用于将待显示用的图像数据(Data)通过该多条数据线120以模拟形态的图像数据信号传输至该多个像素单元P。扫描驱动电路103用于与该多条扫描线130电性连接，用于通过该多条扫描线130输出扫描信号，该扫描信号用于控制像素电路PC何时接收图像数据。其中，扫描驱动电路103按照该多条扫描线130的位置排列顺序依次自扫描线Ga1、Ga2、……，Gan输出扫描信号G1、G2、……，Gn。j为大于或等于1且小于或等于n的自然数。
时序控制电路101分别与数据驱动执行电路102与扫描驱动电路103电性连接，用于控制数据驱动执行电路102以及扫描驱动电路103的工作时序，也即是分别输出对应的时序控制信号至数据驱动执行电路102和扫描驱动电路103，以控制何时输出对应的扫描信号以及图像数据。
本实施例中，扫描驱动电路103中的电路元件与显示面板11中的像素单元P使用相同的工艺制作于显示面板11中，该工艺例如可以是GOA(Gate Driver on Array)工艺。
请参阅图4，其为本申请第一实施例中如图3所示多个像素电路PC中任意一个像素电路100的电路框图。
如图4所示，像素电路100包括驱动电路DC(Driving Execution Circuit)以及K个子像 素103。驱动电路DC包括一个转换电路101和一个驱动执行电路102，。本实施例中，K为自然数，大于或等于2。
转换电路101电性连接数据线Di与扫描线Gaj，用于自扫描线Gaj接收扫描信号Gj，并在扫描信号Gj控制下工作，同时自数据线Di接收模拟形态的图像数据信号Vdata，且将所述模拟形态的图像数据信号Vdata转换为数字形态的脉冲信号Vout。i为大或等于1且小于或等于m的自然数。本实施例中，脉冲信号Vout的脉冲宽度(占空比)与图像数据信号Vdata的电压大小是对应。
驱动执行电路102电性连接于转换电路101与K个子像素103，用于接收所述数字形态的脉冲信号Vout，并依据所述脉冲信号Vout分时提供驱动电流Idrv至所述多个子像素103。
K个子像素103依据接收的驱动电流Idrv出射光线，从而对应所述图像数据信号Vdata执行图像显示。
本实施例中，模拟形态的信号为连续变化的电压或者电流，数字形态的信号为仅具有固定的至少2个值的电压或者电流，例如仅具有高电位与低电位的电压的数字形态的信号，仅具有1A驱动电流或者0A电流值的电流的数字形态的信号。
本实施例中，一个像素电路100包含有多个子像素103，也即是一个转换电路101能够同时为多个子像素103提供对应模拟形态的图像数据信号的脉冲信号Vout，进而分时依据脉冲信号Vout提供驱动电流Idrv至子像素103驱动其发射对应的光线。有效降低了阵列基板11c中需设置的转换电路101的数量，降低布线难度的同时提高了显示面板的分辨率，有效降低了各像素单元P的功耗。
请参阅图5，其为本申请第二实施例中如图3所示多个像素电路PC中任意一个像素电路200的电路框图。
如图5所示，像素电路200包括驱动电路DC(Drive Circuit,DC)以及K个子像素103。本实施例中，驱动电路DC包括一个转换电路101和K个驱动执行电路102。本实施例中，K为自然数且大于或等于2。
转换电路101电性连接数据线Dai与扫描线Gaj，用于自扫描线Gaj接收扫描信号Gj，并在扫描信号Gj控制下工作，均自数据线Dai接收模拟形态的图像数据信号Vdata，且将所述模拟形态的图像数据信号Vdata转换为数字形态的脉冲信号Vout。i为大于或等于1且小于或等于m的自然数。本实施例中，脉冲信号Vout的脉冲宽度(占空比)与图像数据信号Vdata的电压大小是对应的。
本实施例中，K个驱动执行电路102与K个子像素103按照一对一的方式电性连接，同时，每个驱动执行电路102还分别电性连接于转换电路101，即一个驱动执行电路102对应电性连接于转换电路101与一个子像素103之间。
K个驱动执行电路102分时接收所述数字形态的脉冲信号Vou，并依据所述脉冲信号Vou提供驱动电流Idrv至各自对应的子像素103。
K个子像素103依据接收的驱动电流出射光线，从而对应所述图像数据信号执行图像显示。
请参阅图6，其为本申请第一施例中如图4所示像素电路100中的电路结构示意图。
如图6所示，转换电路101包括扫描开关T1、存储电容Cst1以及比较器CP1。
扫描开关T1在接收到扫描信号Gj时处于导通状态以将所述模拟形态的图像数据信号传输至所述第一存储电容Cst1。本实施例中，扫描开关T1为P型薄膜晶体管(Thin Film Transistor，TFT)。具体地，该P型薄膜晶体管的栅极g电性连接扫描线Gaj，用于接收扫描信号Gj；该P型薄膜晶体管的源极s电性连接数据线Di，用于接收所述模拟形态的图像数据信号Vdata；该P型薄膜晶体管的漏极d电性连接数据输出节点Ncst，以用于将接收到的图像数据信号Vdata提供至比较器CP1。
第一存储电容Cst1电性连接于数据输出节点Ncst与接地端GND之间，并通过数据输出节点Ncst电性连接所述比较器CP1的第一相位输入端Vin1，用于接收与存储所述模拟形态的图像数据信号Vdata并加载至所述比较器CP1。
比较器CP1的第二相位输入端Vin2用于接收第一参考信号Vsweep，所述第一参考信号号Vsweep为斜坡信号。本实施例中，第一相位输入端Vin1为反相输入端，第二相位输入端Vin2为同相输入端。
比较器CP1依据该模拟形态的图像数据信号Vdata与所述第一参考信号Vsweep中电压值的比较结果，自比较器CP1的脉冲信号输出端Vout输出数字形态的脉冲信号Vout。所述脉冲信号Vout表征所述数字形态的图像数据信号，即脉冲信号Vout的波形与图像数据信号Vdata在高低电位上相互对应的。需要说明的是，在本申请中，该模拟形态的图像数据信号Vdata也是用电压值表示的，因此比较器CP1比较的是该模拟形态的图像数据信号Vdata与所述第一参考信号Vsweep两个电压值的大小。
驱动执行电路102包括驱动控制端Ndrv、第一驱动晶体管Td1、驱动电容Cd1与第一复位开关Tr1以及驱动输出端Ncon。驱动控制端Ndrv电性连接于脉冲信号输出端Vout，用于接收脉冲信号Vout。驱动执行电路102依据脉冲信号Vout占空比的大小自驱动输出端Ncon输出对应的驱动电流Idrv至子像素103。
具体地，驱动电容Cd1电性连接于第一驱动电压端VDD1与驱动控制端Ndrv之间。驱动电容Cd1用于在预设时间段内逐渐存储或者释放脉冲信号Vout，并维持驱动控制端Ndrv的电压与脉冲信号Vout电压值相同。
第一驱动晶体管Td1电性连接于第一驱动电压端VDD1、驱动控制端Ndrv以及驱动输出端Ncon。第一驱动晶体管Td1在驱动控制端Ndrv提供的脉冲信号Vout控制下导通(turn on)或者关断(turn off)。当第一驱动晶体管Td1导通时，第一驱动晶体管Td1配合第一驱动电压端VDD1提供的驱动电压VDD自驱动输出端Ncon输出驱动电流Idrv。当第一驱动晶体管Td1关断时，第一驱动晶体管Td1停止自驱动输出端Ncon输出驱动电流Idrv。
本实施例中，第一驱动晶体管Td1为P型薄膜晶体管。该P型薄膜晶体管的栅极用于电性连接驱动控制端Ndrv以接收脉冲信号Vout；该P型薄膜晶体管的源极电性连接第一驱动电压端VDD1，用于接收驱动电压VDD；该P型薄膜晶体管TFT的漏极(图未示)电性连接于驱动输出端Ncon。
第一复位开关Tr1电性连接于驱动输出端Ncon，用于在子像素103停止图像显示时(复位时间段)依据复位信号Vrst将复位电压提供至驱动输出端Ncon，保证驱动输出端Ncon 维持在复位状态，以在图像数据信号Vdata输入时间段保证子像素103准确接收到图像数据信号Vdata。本实施例中，复位电压用于驱动输出端Ncon维持在复位状态，例如复位电压可以为低参考电压Vss。
本实施例中，第一复位开关Tr1为N型的薄膜晶体管(TFT)，作为第一复位开关Tr1的薄膜晶体管的栅极(图未示)用于接收复位信号Vrst；作为第一复位开关Tr1的薄膜晶体管的源极(图未示)电性连接第一低电压端Vss1，用于接收低参考电压Vss；作为第一复位开关Tr1的薄膜晶体管的漏极(图未示)电性连接于驱动输出端Ncon，用于在复位时间段输出复位电压至驱动输出端Ncon。本实施例中，复位电压即为低参考电压Vss.
子像素103在接收到选择信号WT时自驱动输出端Ncon接收驱动电流Idrv并进行发光执行图像显示。
每个子像素103包括均选择开关Tw与发光元件(Emitting element,EM)，为了便于区分K个子像素103，将多个子像素103中的选择开关Tw按照Tw1,Tw2,…,Twk的顺序依次进行标记，并且将多个子像素103中发光元件按照EM1,EM2,…,EMK的顺序依次进行标记。值得注意的是，K为大于或等于2的整数。其中，选择开关Twi和发光元件EMi位于同一子像素103内，i为1至K之间的任意一个整数。例如，如图6所示，选择开关Tw1与发光元件EM1位于同一个子像素103内，依次类推，选择开关Twn与发光元件EMn位于同一个子像素103内。本实施例中，各子像素103区别仅在于发光元件EM发射的光线颜色不同，其余电路结构与工作原理均相同。
本实施例中，以图6中左边第一个子像素103为例具体说明其电路结构。
子像素103包括选择开关Tw1与发光元件EM1。发光元件EM1位于选择开关TW1与第二低电压端Vss2之间，且通过选择开关TW1电性连接于驱动输出端Ncon。第二低电压端Vss2用于提供低参考电压Vss。本实施例中，第一低电压端Vss1与第二低电压端Vss2提供的低参考电压Vss相同，例如为-3V。
选择开关Tw1在选择信号WT1的控制下导通或者关断，当选择开关Tw1导通时，驱动电流Idrv通过选择开关Tw1加载至发光元件EM1中，从而驱动发光元件EM1出射光线并显示所述图像数据信号Vdata。选择开关Tw1可由图3所示的时序控制电路101提供。
本实施例中，选择开关Tw1为P型薄膜晶体管，该P型薄膜晶体管的栅极接收选择信号WT1，该P型薄膜晶体管的源极电性连接驱动输出端Ncon，该P型薄膜晶体管的漏极电性连接发光元件EM1。发光元件EM1的阳极电性连接于作为选择开关Tw1的薄膜晶体管的漏极，发光元件EM1的阳极电性连接第二低电压端Vss2。
请参阅图7，其为如图6所示像素电路100中比较器CP1的电路结构示意图。
如图7所示，比较器CP1包括第一输入开关Tin1、第二输入开关Tin2，第一镜像开关Tmi1、第二镜像开关Tmi2、第一参考开关Trf1、第一输出开关Tou1、第二输出开关Tou2。
本实施例中，第一输入开关Tin1、第二输入开关Tin2，第一参考开关Trf1以及第一输出开关Tou1为P型薄膜晶体管。第一镜像开关Tmi1、第二镜像开关Tmi2以及第二输出开关Tou2为N型薄膜晶体管。
第一输入开关Tin1的栅极电性连接第一相位输入端Vin1，第一输入开关Tin1的源极 电性连接第一参考开关Trf1，第一输入开关Tin1的漏极电性连接第一镜像开关Tmi1。
第二输入开关Tin2的栅极电性连接第二相位输入端Vin2，第二输入开关Tin2的源极电性连接第一参考开关Trf1，第二输入开关Tin2的漏极电性连接第二镜像开关Tmi2。
第一镜像开关Tmi1的栅极与漏极直接电性连接并且均电性连接于第一输入开关Tin1的漏极，第一镜像开关Tmi1的栅极与第二镜像开关Tmi2的栅极电性连接，第一镜像开关Tmi1的源极电性连接第一低电压端Vss1。
第二镜像开关Tmi2的漏极电性连接于第二输入开关Tin2的漏极，第二镜像开关Tmi2的源极电性连接第一低电压端Vss1。另外，第二镜像开关Tmi2的漏极与第二输入开关Tin2的漏极均电性连接至比较中间节点Nmin。
第一参考开关Trf1的栅极接收参考电压Vrf，第一参考开关Trf1的漏极电性连接第一输入开关Tin1与第二输入开关Tin2，第一参考开关Trf1的源极电性连接第一驱动电压端VDD1。本实施例中，参考电压Vref控制所述第一参考开关Trf1处于常开状态，也即是参考电压Vref在显示面板11上电后输出低电位的电压信号控制第一参考开关Trf1一直导通。
第一输出开关Tou1的栅极电性连接比较中间节点Nmid，第一输出开关Tou1的源极电性连接第一驱动电压端VDD1，第一输出开关Tou1的漏极电性连接脉冲输出端Vout。
第二输出开关Tou2的栅极电性连接比较中间节点Nmid，第二输出开关Tou2的源极电性连接第一低电压端Vss1，第二输出开关Tou2的漏极电性连接脉冲信号输出端Vout。
请参阅图8，其为本申请第一实施例中如图7所示比较器CP1工作时的时序图。
需要说明的是，每个像素电路100在一帧(1Frame)图像显示时间段，具有一个扫描周期T(图8未示出，但是图10中示出了扫描周期T，因此请参考图10所示进行理解)。而对于像素电路100中的任意一个子像素103对应一个扫描周期T的子扫描周期Ts，子扫描周期Ts进一步包括在时间上连续且无间隔的数据写入时间段Ha与发光时间段He。
那么，对于比较器CP1而言，先结合图6-图8具体说明在对应于一个子像素的子扫描周期Ts内，比较器CP1在数据写入时间段Ha与发光时间段He两个时间段的具体工作过程与工作原理。
在数据写入时间段Ha中，当扫描信号Gj自高电位跳变为低电位时，扫描线Gaj提供扫描信号Gj至像素电路100，扫描开关T1在该扫描信号(该扫描信号为低电位)的控制下导通，模拟形态的图像数据信号Vdata传输数据输出节点Ncst。
图像数据信号Vdata通过存储电容Cst1的充电而使得数据输出节点Ncst的电压Vcst逐渐上升。
当扫描信号Gj的电压自低电位跳变为高电位时，也即是表征扫描线Gaj停止提供扫描信号，扫描开关T1关断，数据输出节点Ncst的电压由于存储电容Cst1的充电而上升至与图像数据信号Vdata相同的电压值，数据写入时间段Ha结束而进入发光时间段He。
在发光时间段He，第一参考信号Vsweep进入斜坡信号阶段，即第一参考信号Vsweep从低电位匀速以及匀幅逐渐变化。本实例中，以第一参考信号Vsweep从低电位逐渐升高至高电位为例，来说明比较器CP1依据第一参考信号Vsweep与图像数据信号Vdata的大小输出脉冲信号Vout的原理。
当第一参考信号Vsweep逐渐增加但仍然小于图像数据信号Vdata时，比较器CP1中第二输入开关Tin2与第二镜像开关Tmi2的驱动电流占主导位置，故而驱动电压VDD通过常开的第一参考开关Trf1并经过第二输入开关Tin2传输至比较中间节点Nmin，使得比较中间节点Nmin处于高电位(VDD1)，第二输出开关Tou2则在高电位控制下导通，进而将低参考电压Vss通过第二输出开关Tou2加载至脉冲信号输出端Vout。从而使得脉冲信号输出端Vout处于低电位。
当第一参考信号Vsweep逐渐增加并大于图像数据信号Vdata时，比较器CP1中第一输入开关Tin1与第一镜像开关Tmi1的驱动电流占主导位置，故而驱动电压VDD通过常开的第一参考开关Trf1并经过第一输入开关Tin1传输至第一镜像开关Tmi1与第二镜像开关Tmi2的栅极，第一镜像开关Tmi1与第二镜像开关Tmi2导通，进而使得低参考电压Vss通过第二镜像开关Tmi2加载至比较中间节点Nmin，使得比较中间节点Nmin为低参考电压Vss，第一输出开关Tou1则在低电位的低参考电压Vss控制下导通，进而将驱动电压VDD通过第一输出开关Tou1加载至脉冲信号输出端Vout。从而使得脉冲信号输出端Vout处于高电位。
由此，比较器CP1根据第一参考信号Vsweep与图像数据信号Vdata的大小的比较结果，来输出对应的脉冲信号Vout，由于脉冲信号Vout为数字形态，从而将模拟形态的图像数据信号Vdata转换为数字形态。并且，脉冲信号Vout占空比的大小由图像数据信号Vdata确定，由于驱动执行电路102提供的驱动电流Idrv的大小是由脉冲信号Vout占空比的大小确定的，由此，脉冲信号Vout能够准确表征图像数据信号Vdata的大小。
请一并参阅图9与图10，图9为本申请第一实施例中如图4所示像素电路100的具体电路结构示意图，图10为如图9所示像素电路100工作时序图。
如图9所示，本实施例中，比较器CP1除与图7所示的具体电路结构相同之外，还包括比较复位开关Trc，用于在比较器CP1执行比较输出脉冲信号Vout之外的其他时间段，控制比较中间节点Nmid处于低电位，进而使得脉冲信号输出端Vout处于高电位而停止输出脉冲信号Vout。本实施例中，脉冲信号Vout为低电位表征驱动执行电路102提供驱动电流Idrv至显示单元103执行图像显示。
本实施例中，比较复位开关Trc为N型薄膜晶体管，比较复位开关Trc的栅极接收复位信号Vrst；比较复位开关Trc的源极电性连接第一低参考电压端Vss1；比较复位开关Trc的漏极电性连接比较中间节点Nmid。当复位信号Vrst为高电平时，控制比较复位开关Trc导通，低参考电压Vss加载至比较中间节点Nmid，进而控制脉冲信号输出端Vout停止输出脉冲信号Vout。
如图9所示，像素电路100包括六个子像素103，即K为6。其中，所述六个子像素103按照从左到右位置排列顺序分别为第一红色子像素R1、第一绿色子像素G1、第一蓝色子像素B1、第二红色子像素R2、第二绿色子像素G2以及第二蓝色子像素B2。在本申请其他实施例中，子像素103的个数可以依据实际的显示效果需求进行调整，例如K可以为2、3、4、5、7、8等，并不以此为限。
第一红色子像素R1中发光元件EM1用于出射红色的光线；第一绿色子像素G1中发 光元件EM2用于出射绿色的光线；第一蓝色子像素B1中发光元件EM3用于出射蓝色的光线；第二红色子像素R2中发光元件EM4用于出射红色的光线；第二绿色子像素G2中发光元件EM5用于出射绿色的光线；第二蓝色子像素B2中发光元件EM6用于出射蓝色的光线。本实施例中，所述六个子像素103中，其中两个子像素发射相同颜色的光线，所述六个子像素103则共出射三种颜色的光线。
如图10所示，本实施例中，像素电路100在1帧图像显示期间，每个子像素103的子扫描显示周期Ts中均包括数据写入时间段Ha与发光时间段He。由此，对于六个子像素103，至少包括6个子扫描显示周期Ts1～Ts6。
本实施例中，该六个子像素103是通过扫描信号Gi在一个扫描周期T中的6个子扫描周期Ts来分时接收对应图像数据信号的驱动电流Idrv以出射光线显示图像数据。
对应6个子像素105的六个子扫描周期，分别提供6个选择信号WT1～WT6，该6个选择信号WT1～WT6与对应于6个子像素103的六个子扫描周期是一对一的。根据这6个选择信号WT1～WT6分别来选择第一红色子像素R1、第一绿色子像素G1、第一蓝色子像素B1、第二红色子像素R2、第二绿色子像素G2以及第二蓝色子像素B2进行图像显示。
具体地，如图10所示，对于子扫描周期Ts1，提供选择信号WT1至第一红色子像素R1，选择信号WT1控制第一红色子像素R1中选择开关Tw1导通，从而依据图像数据信号将驱动电流Idrv加载至发光元件EM1，使得发光元件EM1依据携带红色图像数据信号发射红色光线。
同理，在扫描周期Ts2～Ts6，分别提供选择信号WT2～WT6选择第一绿色子像素G1、第一蓝色子像素B1、第二红色子像素R2、第二绿色子像素G2以及第二蓝色子像素B2。
为了保证像素单元P中整体发光亮度的均匀性，本实施例中至少两个相邻位置的子像素103并不在相邻的子扫描周期Ts被选择。
具体地，如图10所示，在子扫描周期Ts2，提供选择信号WT5选择第二绿色子像素G2。在子扫描周期Ts3，提供选择信号WT3选择第一蓝色子像素B1。在子扫描周期Ts4，提供选择信号WT4选择第二红色子像素R2。在子扫描周期Ts5，提供选择信号WT2选择第一绿色子像素G1。在子扫描周期Ts6，提供选择信号WT6选择第二蓝色子像素B2。
以在子扫描周期Ts1内提供选择信号WT1至第一红色子像素R1执行图像显示为例具体说明转换电路101、驱动执行电路102以及子像素103的工作过程。
在子扫描周期Ts1中，首先进入数据写入时间段Ha，扫描信号Gj在高电位期间控制模拟形态的图像数据信号Vdata加载至数据输出节点Ncst并通过存储电容Cst1对数据输出节点Ncst进行充电，直至数据输出节点Ncst达到稳定的电压值并且与图像数据信号Vdata的电压值相同，此时，数据写入时间段Ha结束。
数据写入时间段Ha结束并进入显示时间段He，在显示时间段He，比较器CP1的第一相位输入端Vin1接收模拟形态的图像数据信号Vdata，比较器CP1的第二相位输入端Vin2接收的第一参考信号Vsweep为三角波形式的斜坡信号。
具体地，在显示时间段数据写入时间段Ha结束并进入显示时间段He，第一参考信号 Vsweep为自高电位基于第一速度匀速降低至低电位，然后再自低电位基于该第一速度匀速上升至高电位，即第一参考信号Vsweep的波形为等腰三角形的形状。
比较器CP1通过将第二相位输入端Vin2的第一参考信号Vsweep与模拟形态的图像数据信号Vdata进行比较而输出数字形态的脉冲信号Vout，本实施例中，脉冲信号Vout的占空比与图像数据信号Vdata的电压值大小呈反向关系，也即是图像数据信号Vdata的电压值越大，脉冲信号Vout的占空比越小，而图像数据信号Vdata的电压值越小，脉冲信号Vout的占空比越大。
脉冲信号Vout在低电平期间通过驱动电容Cd1对驱动控制端Ndrv进行充电并控制控制驱动执行电路102中驱动晶体管Td1的导通，驱动晶体管Td1在导通期间配合驱动电压VDD提供驱动电流Idrv至驱动输出端Ncon。
在进入显示时间段He时，第一红色子像素R1中选择信号WT1处于低电平而控制选择开关Tw1处于导通状态，由此，驱动电流Idar通过驱动输出端Ncon传输至出射红色光线的发光元件EM1。
当驱动电容Cd1对驱动控制端Ndrv充电的电压升高到驱动晶体管Td1的阈值电压之上时，驱动晶体管Td1关断，驱动电流Idrv停止输出至驱动输出端Ncon，第一红色子像素R1停止发光，发光时间段He结束，同时，子扫描周期Ts1结束，并进入子扫描周期Ts2。
以此类推，对于子扫描周期Ts2～Ts6对应依次驱动第二绿色子像素G2、第一蓝色子像素B1、第二红色子像素R2、第一绿色子像素G1以及二蓝色子像素B2执行出射光线以执行对应图像数据信号的图像显示，而对应的具体工作过程与原理本实施例不再赘述。
请参阅图11，其为本申请第三实施例中如图4所示像素电路300的具体电路结构示意图。本实施例中，像素电路300与图9对应实施例中像素电路100的基本相同，区别仅在于子像素单元103的个数中K为3，其他的电路结构与工作方式均相同。
如图11所示，本实施例中，像素电路100包括三个子像素103，即K为3。其中，所述三个子像素103按照从左到右位置排列顺序分别为第一红色子像素R1、第一绿色子像素G1、第一蓝色子像素B1。
请一并参阅图11与图12，其中图12为如图11所示像素电路300工作时序图。如图12所示，本实施例中，像素电路300在1帧图像显示期间(或在一个扫描周期T内)，每个子像素103的子扫描显示周期Ts中均包括数据写入时间段Ha与发光时间段He。由此，对于三个子像素103，至少包括3个子扫描显示周期Ts1～Ts3。
本实施例中，该三个子像素103是通过扫描信号Gi的在一个扫描周期T中的3个不同的子扫描周期Ts，来分时接收对应图像数据信号的驱动电流Idrv以出射光线显示图像数据。
对应3个子像素105的3个子扫描周期Ts1-Ts3，分别提供3个选择信号WT1～WT3来选择第一红色子像素R1、第一绿色子像素G1以及第一蓝色子像素B1。
具体地，如图12所示，对于子扫描周期Ts1，提供选择信号WT1至第一红色子像素R1，使得选择信号WT1控制第一红色子像素R1中选择开关Tw1导通，从而依据图像数据信号将驱动电流Idrv加载至发光元件EM1，使得发光元件EM1依据携带红色图像数据信 号发射红色光线。
同理，在扫描周期Ts2～Ts3，分别提供选择信号WT2～WT3选择第一绿色子像素G1、第一蓝色子像素B1。
以在子扫描周期Ts1内提供选择信号WT1至第一红色子像素R1执行图像显示为例具体说明转换电路101、驱动执行电路102以及子像素103的工作过程。
在子扫描周期Ts1中，首先进入数据写入时间段Ha，扫描信号Gj在高电位期间控制模拟形态的图像数据信号加载至数据输出节点Ncst并通过存储电容Cst1对数据节点Ncst进行充电，直至数据输出节点Ncst达到稳定的电压值并且与图像数据信号Vdata的电压值相同，此时，数据写入时间段Ha结束。
数据写入时间段Ha结束并进入显示时间段He，在显示时间段He，比较器CP1的第一相位输入端Vin1，比较器CP1的第二相位输入端Vin2接收的第一参考信号Vsweep为三角波形式的斜坡信号。
具体地，在显示时间段He，第一参考信号Vsweep为自高电位按照第二速度匀速降低至低电位，然后再自低电位按照该第二速度匀速升高至高电位，即第一参考信号Vsweep的波形为等腰三角形的形状。本实施例中，第一速度与第二速度相同，当然，在本申请其他实施例中，第一速度也可以不同于第二速度。
比较器CP1通过将第二相位输入端Vin2的第一参考信号Vsweep与模拟形态的图像数据信号Vdata进行比较而输出数字形态的脉冲信号Vout。本实施例中，脉冲信号Vout的占空比与图像数据信号Vdata的电压值大小呈正向关系，也即是图像数据信号Vdata的电压值越大，脉冲信号Vout的占空比越大，而图像数据信号Vdata的电压值越小，脉冲信号Vout的占空比越小。
脉冲信号Vout在低电平期间通过驱动电容Cd1对驱动控制端Ndrv进行充电并同时控制控制驱动执行电路102中驱动晶体管Td1的导通，驱动晶体管Td1在导通期间配合驱动电压VDD提供驱动电流Idrv至驱动输出端Ncon。
在进入显示时间段He时，第一红色子像素R1中选择信号WT1处于低电平而控制选择开关Tw1处于导通状态，由此，驱动电流Idar通过驱动输出端Ncon传输至出射红色光线的发光元件EM1。
当驱动电容Cd1对驱动控制端Ndrv充电的电压升高到驱动晶体管Td1的阈值电压之上时，驱动晶体管Td1关断，驱动电流Idrv停止输出至驱动输出端Ncon，第一红色子像素R1停止发光，发光时间段He结束，同时，子扫描周期Ts1结束，并进入子扫描周期Ts2。
以此类推，对于子扫描周期Ts2～Ts6对应依次驱动第二绿色子像素G2、第一蓝色子像素B1、第二红色子像素R2、第一绿色子像素G1以及二蓝色子像素B2执行出射光线以执行对应图像数据信号的图像显示，而对应的具体工作过程与原理本实施例不再赘述。
请参阅图13，其为本申请第四实施例中如图4所示像素电路400的具体电路结构示意图。本实施例中，像素电路400与图9对应的实施例中像素电路100的基本相同，区别仅在于驱动执行电路102还包括脉冲接收开关Tps1、补偿单元1024与第二复位开关Tr2，其他的电路结构相同。
脉冲接收开关Tps1电性连接比较器CP1的脉冲输出端Vout、第一驱动电压端VDD1与驱动输入端Ny。脉冲接收开关Tps1用于在脉冲输出端Vout输出的脉冲信号Vout控制下选择性将第一驱动电压端VDD1提供的驱动电压VDD加载至驱动输入端Ny。
脉冲接收开关Tps1导通与关断的时间与脉冲信号Vout的高、低电位时长对应。也即是当脉冲接收开关Tps1在脉冲信号Vout的低电平控制下导通，使得驱动电压VDD加载至驱动输入端Ny；在脉冲信号Vout的高电平控制下关断，驱动电压VDD停止加载至驱动输入端Ny。
本实施例中，脉冲接收开关Tps1为P型薄膜晶体管，其中，作为脉冲接收开关Tps1的薄膜晶体管的栅极电性连接脉冲信号输出端Vout，以接收比较器CP1输出的脉冲信号Vout；作为脉冲接收开关Tps1的薄膜晶体管的源极电性连接第一驱动电压端VDD1；作为脉冲接收开关Tps1的薄膜晶体管的漏极电性连接驱动输出端。
本实施例中，补偿单元1024包括第一补偿晶体管Tcv1与第二补偿晶体管Tcv2。其中第一补偿晶体管Tcv1电性连接于驱动控制端Ndrv与驱动输出端Ncon之间，用于预先将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv，进而当第一驱动晶体管Td1输出驱动电流Idrv时即可抵消驱动电流Idrv中阈值电压Vth因素，从而针对第一驱动晶体管Td1的阈值电压Vth进行补偿，防止第一驱动晶体管Td1的本身的因素而音响驱动电流Idrv。
第一补偿晶体管Tcv1为P型薄膜晶体管，其中，作为第一补偿晶体管Tcv1的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第一补偿晶体管Tcv1的薄膜晶体管的源极电性连接驱动输出端Ncon；作为第一补偿晶体管Tcv1的薄膜晶体管的漏极电性连接驱动控制端Ndrv。
第二补偿晶体管Tcv2电性连接于驱动输入端Ny，用于当将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv时，同步向驱动控制端Ndrv加载辅助电压VD3。其中，辅助电压VD3的电压值可以依据第一驱动晶体管Td1的参数特性进行设置。
第二补偿晶体管Tcv2为P型薄膜晶体管，其中，作为第二补偿晶体管Tcv2的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第二补偿晶体管Tcv2的薄膜晶体管的源极接收辅助电压VD3；作为第二补偿晶体管Tcv2的薄膜晶体管的漏极电性连接驱动输入端Ny。
第二复位开Tr2电性电性连接于驱动控制端Ndrv，用于在子像素103停止图像显示时(复位时间段)提供复位电压至驱动控制端Ndrv，保证驱动控制端Ndrv维持在复位状态，保证子图像像素103准确接收到图像数据信号。
请参阅图14，图14为图13所示像素电路400工作时序图。本实施例中，像素电路400中一个子像素103在1帧图像显示期间对应的子扫描显示周期Ts，每个子像素103的子扫描显示周期Ts中均包括数据写入时间段Ha、补偿阶段Hc与发光时间段He。由此，对于六个子像素103，至少包括6个子扫描显示周期Ts1～Ts6。
具体地，如图14所示，对于子扫描周期Ts1，提供选择信号WT1至第一红色子像素R1，使得选择信号WT1控制第一红色子像素R1中选择开关Tw1导通，从而依据图像数据信号将驱动电流Idrv加载至发光元件EM1，使得发光元件EM1依据携带红色图像数据信号发射红色光线。
同理，在扫描周期Ts2～Ts6，分别提供选择信号WT2～WT6选择第一绿色子像素G1、第一蓝色子像素B1、第二红色子像素R2、第二绿色子像素G2以及第二蓝色子像素B2。
为了保证像素单元P中整体发光亮度的均匀性，本实施中至少两个相邻位置的子像素103并不在相邻的子扫描周期Ts被选择。
具体地，在子扫描周期Ts2，提供WT5选择第二绿色子像素G2；在子扫描周期Ts3，提供WT3选择第一蓝色子像素B1；在子扫描周期Ts4，提供WT4选择第二红色子像素R2；在子扫描周期Ts5，提供WT2选择第一绿色子像素G1；在子扫描周期Ts6，提供WT6选择第二蓝色子像素B2。
以在子扫描周期Ts1内提供选择信号WT1至第一红色子像素R1执行图像显示为例具体说明转换电路101、驱动执行电路102以及子像素103的工作过程。
在子扫描周期Ts1中，首先进入数据写入时间段Ha，扫描信号Gj在高电位期间控制模拟形态的图像数据信号加载至数据输出节点Ncst并通过存储电容Cst1对数据节点Ncst进行充电，直至数据输出节点Ncst达到稳定的电压值并且与图像数据信号Vdata的电压值相同，此时，数据写入时间段Ha结束。
数据写入时间段Ha结束并进入补偿阶段Hc，复位信号Vrst自高电位降低至低电位时控制比较复位开关Tcp1、第一复位开关Tr1与第二复位开关Tr2处于导通状态，将复位信号Vret分别加载至比较中间节点Nmid、驱动控制端Ndrv以及驱动输出端Ncon。
当复位信号Vrst跳变至高电位时，补偿/设定信号WD自高电位降低至低电位时控制第一复位晶体管Tcv1与第二复位晶体管Tcv2导通。辅助电压VD3通过第二复位晶体管Tcv2加载至驱动输入端Ny。由于第一复位晶体管Tcv1导通后，驱动控制端Ndrv与驱动输出端Ncon直接电性连接，第一驱动晶体管Td1的栅极与漏极直接电性连接而成二极管连接，由此，驱动控制端Ndrv则获得(VD3-Vth)的电压。当补偿/设定信号WD跳变至高电位时第一复位晶体管Tcv1与第二复位晶体管Tcv2关断，补偿阶段Hc结束。
补偿阶段Hc结束后进入显示时间段He，比较器CP1的第一相位输入端Vin1，比较器CP1的第二相位输入端Vin2接收的第一参考信号Vsweep为三角波形式的斜坡信号。
具体地，第一参考信号Vsweep为自高电位匀速降低至低电位，然后再自低电位在采用相同的速度匀速升高至高电位，即第一参考信号Vsweep的波形为等腰三角形的形状。
比较器CP1通过将第二相位输入端Vin2的第一参考信号Vsweep与模拟形态的图像数据信号Vdata进行比较而输出数字形态的脉冲信号Vout，本实施例中，脉冲信号Vout的占空比与图像数据信号Vdata的电压值大小呈正向关系，也即是图像数据信号Vdata的电压值越大，脉冲信号Vout的占空比越大，而图像数据信号Vdata的电压值越小，脉冲信号Vout的占空比越小。
脉冲信号Vout在低电平期间通过驱动电容Cd1对驱动控制端Ndrv进行充电并控制控制驱动执行电路102中驱动晶体管Td1的导通，驱动晶体管Td1在导通期间配合驱动电压VDD提供驱动电流Idrv至驱动输出端Ncon。此时，驱动电流Idrv中含有的阈值电压Vth则被补偿时间段Hc预先写入的阈值电压Vth抵消掉，故而驱动电流Idrv并不会受到第一驱动晶体管Td1阈值电压Vth的影响。
在进入显示时间段He时，第一红色子像素R1中选择信号WT1处于低电平而控制选 择开关Tw1处于导通状态，由此，驱动电流Idrv通过驱动输出端Ncon传输至出射红色光线的发光元件EM1。
当驱动电容Cd1对驱动控制端Ndrv充电的电压升高到驱动晶体管Td1的阈值电压之上时，驱动晶体管Td1关断，驱动电流Idrv停止输出至驱动输出端Ncon，第一红色子像素R1停止发光，发光时间段He结束，同时，子扫描周期Ts1结束，并进入子扫描周期Ts2。
以此类推，对于子扫描周期Ts2～Ts6对应依次驱动第二绿色子像素G2、第一蓝色子像素B1、第二红色子像素R2、第一绿色子像素G1以及二蓝色子像素B2执行出射光线以执行对应图像数据信号的图像显示，而对应的具体工作过程与原理本实施例不再赘述。
请参阅图15，其为本申请第五实施例中如图4所示像素电路500的具体电路结构示意图。
本实施例中，像素电路500与图13对应的实施例中像素电路400的基本相同，区别仅在于子像素单元103的个数中K为3，其他的电路结构与工作方式均相同。
如图15所示，本实施例中，像素电路100包括三个子像素103，即K为3。其中，所述三个子像素103按照从左到右位置排列顺序分别为第一红色子像素R1、第一绿色子像素G1、第一蓝色子像素B1。
请参阅图16，其为本申请第六实施例中如图4所示像素电路600的具体电路结构示意图。本实施例中，像素电路600与图9对应的实施例中像素电路100的基本相同，相对于图9对应的实施例来说，区别仅在于转换电路101、驱动执行电路102、像素103中的N型开关元件均被换为P型开关元件，以及转换电路101、驱动执行电路102、像素103中的P型开关元件均被换为N型开关元件。
在本实施例中，转换电路101中扫描开关T1为N型薄膜晶体管。其中，扫描开关T1的栅极接收扫描信号Gj，源极接收图像数据信号Vdata，漏极电性连接数据输入节点Ncst。
存储电容Cst1电性连接于第一驱动电压端VDD1与数据输入节点Ncst之间。
比较器CP1中，第一输入开关Tin1、第二输入开关Tin2、第一参考开关Trf1以及比较复位开关Trc以及第二输出开关Tou2为N型薄膜晶体管，第一镜像开关Tmi1、第二镜像开关Tmi2以及第一输出开关Tou1为P型薄膜晶体管。
第一输入开关Tin1的栅极电性连接第一相位输入端Vin1，第一输入开关Tin1的源极电性连接第一参考开关Trf1，第一输入开关Tin1的漏极电性连接比较中间节点Nmid与第一镜像开关Tmi1。
第二输入开关Tin2的栅极电性连接第二相位输入端Vin2，第二输入开关Tin2的源极电性连接第一参考开关Trf1，第二输入开关Tin2的漏极电性连接第二镜像开关Tmi2。
第一镜像开关Tmi1的栅极与漏极直接电性连接并且电性连接于第一输入开关Tin1的漏极，第一镜像开关Tmi1的栅极与第二镜像开关Tmi2的栅极电性连接，第一镜像开关Tmi1的源极电性连接第一驱动电压端VDD1。
第二镜像开关Tmi2的漏极电性连接于第二输入开关Tin2的漏极，第二镜像开关Tmi2的源极电性连接第一驱动电压端VDD1，第二镜像开关Tmi2的漏极电性连接至比较中间节 点Nmid，也即是第二镜像开关Tmi2的漏极与第二输入开关Tin2的漏极一并电性连接于比较中间节点Nmid。
第一参考开关Trf1的栅极接收参考电压Vref，第一参考开关Trf1的漏极电性连接第一输入开关Tin1与第二输入开关Tin2，第一参考开关Trf1的源极电性连接第一低参考电压端Vss1。
本实施例中，参考电压Vref控制所述第一参考开关Trf1处于常开状态，也即是参考电压Vref在显示装置10上电后输出高电位的电压信号控制第一参考开关Trf1一直导通。
第一输出开关Tou1的栅极电性连接比较中间节点Nmid，第一输出开关Tou1的源极电性连接第一驱动电压端VDD1，第一输出开关Tou1的漏极电性连接脉冲输出端Vout。
第二输出开关Tou2的栅极电性连接比较中间节点Nmid，第二输出开关Tou2的源极电性连接第一低电压端Vss1，第二输出开关Tou2的漏极电性连接脉冲输出端Vout。
驱动执行电路102中第一驱动晶体管Td1为N型薄膜晶体管，驱动执行电路102电性连接于比较器CP1的脉冲信号输出端Vout、驱动输出端Ncon与第一低电压端Vss1之间。具体地，第一驱动晶体管Td1的栅极电性连接脉冲信号输出端Vout，第一驱动晶体管Td1的漏极电性连接驱动输出端Ncon，第一驱动晶体管Td1的源极电性连接第一低电压端Vss1。
第一复位开关Tr1为P型薄膜晶体管。具体地，第一复位开关Tr1的栅极接收复位信号Vrst，第一复位开关Tr1的漏极电性连接驱动输出端Ncon，第一复位开关Tr1的源极电性连接第一驱动电压端VDD1。
发光元件EM1通过选择开关TW1电性连接于驱动输出端Ncon1与第二驱动电源VDD2之间。每个子像素103中，选择开关Tw1～-Tw6为N型薄膜晶体管。每个子像素103中的显示元件EM通过选择开关Tw电性连接于第二驱动电源VDD2与驱动输出端Ncon之间。
请参阅图17，其为本申请第七实施例中如图4所示像素电路700的具体电路结构示意图。本实施例中，像素电路700与图16对应的实施例中像素电路600的基本相同，区别仅在于驱动执行电路102还包括脉冲接收开关Tps1、补偿单元1024与第二复位开Tr2，其他的电路结构相同。补偿单元1024电性连接于驱动控制端Ndrv、驱动输出端Ncon以及驱动输入端Ny，用于补偿所述第一驱动晶体管Td1的阈值电压(Vth)的漂移
具体地，脉冲接收开关Tps1电性连接比较器CP1的脉冲输出端Vout、第一低电压端Vss1与驱动输入端Ny之间。脉冲接收开关Tps1用于在脉冲输出端Vout输出的脉冲信号Vout控制下选择性将驱动输入端Ny电性连接至第一低电压端Vss1。
脉冲接收开关Tps1导通与关断的时间与脉冲信号Vout中高、低电位时长对应。也即是当脉冲接收开关Tps1在脉冲信号Vout的低电平控制下导通，使得低参考电压Vss加载至驱动输入端Ny；在脉冲信号Vout的高电平控制下关断，低参考电压Vss停止加载至驱动输入端Ny。
本实施例中，脉冲接收开关Tps1为N型薄膜晶体管，其中，作为脉冲接收开关Tps1 的薄膜晶体管的栅极电性连接脉冲信号输出端Vout，以接收比较器CP1输出的脉冲信号Vout；作为脉冲接收开关Tps1的薄膜晶体管的源极电性连接第一低电压端Vss1；作为脉冲接收开关Tps1的薄膜晶体管的漏极电性连接驱动输出端Ny。
本实施例中，补偿单元1024包括第一补偿晶体管Tcv1与第二补偿晶体管Tcv2，其中第一补偿晶体管Tcv1电性连接于驱动控制端Ndrv与驱动输出端Ncon之间，用于将预先将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv。
第一补偿晶体管Tcv1为N型薄膜晶体管，其中，作为第一补偿晶体管Tcv1的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第一补偿晶体管Tcv1的薄膜晶体管的源极电性连接驱动输出端Ncon；作为第一补偿晶体管Tcv1的薄膜晶体管的源极电性连接驱动控制端Ndrv。
第二补偿晶体管Tcv2电性连接于驱动输入端Ny，用于当将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv时，同步向驱动控制端Ndrv加载辅助电压VD3。其中，辅助电压VD3的电压值可以依据第一驱动晶体管Td1的参数特性进行设置。
第二补偿晶体管Tcv2为N型薄膜晶体管，其中，作为第二补偿晶体管Tcv2的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第二补偿晶体管Tcv2的薄膜晶体管的源极接收辅助电压VD3；作为第二补偿晶体管Tcv2的薄膜晶体管的漏极电性连接驱动输入端Ny。
第二复位开Tr2电性电性连接于驱动控制端Ndrv，用于在子像素103停止图像显示时(复位时间段)提供复位信号至驱动控制端Ndrv，保证驱动控制端Ndrv维持在复位状态，保证子图像像素103准确接收到图像数据信号。
第二复位开Tr2为P型薄膜晶体管，作为第二复位开Tr2的薄膜晶体管的栅极接收复位信号Vrst；作为第二复位开Tr2的薄膜晶体管的源极电性连接第一驱动电压端VDD1；作为第二复位开Tr2的薄膜晶体管的漏极电性连接驱动控制端Ndrv。
驱动执行电路102中，驱动电容Cd1电性连接于驱动控制端Ndrv与第一低电压端Vss1之间。
请参阅图18，其为本申请第八实施例中如图4所示像素电路800的电路框图。本实施例中，像素电路800与图6对应的实施例中像素电路100的基本相同，区别仅在于比较器CP1中第一相位输入端Vin1为同相输入端，第二相位输入端Vin2为反相输入端。
请参阅图19，其为图18所示所示像素电路800的具体电路结构示意图。如图19所示，在比较器CP1中，第一输入开关Tin1的栅极电性连接第二相位输入端Vin2，第一输入开关Tin1的源极电性连接第一参考开关Trf1，第一输入开关Tin1的漏极电性连接第一镜像开关Tmi1。
第二输入开关Tin2的栅极电性连接第一相位输入端Vin1，第二输入开关Tin2的源极电性连接第一参考开关Trf1，第二输入开关Tin2的漏极电性连接第二镜像开关Tmi2。
第一镜像开关Tmi1的栅极与漏极直接电性连接并且电性连接于第一输入开关Tin1的漏极，第一镜像开关Tmi1的栅极与第二镜像开关Tmi2的栅极电性连接，第一镜像开关Tmi1的源极电性连接第一低电压端Vss1。
第二镜像开关Tmi2的漏极电性连接于第二输入开关Tin2的漏极，第二镜像开关Tmi2的源极电性连接第二低电压端Vss1。
另外，第二镜像开关Tmi2的漏极与第二输入开关Tin2的漏极均电性连接至比较中间节点Nmin。
第一参考开关Trf1的栅极接收参考电压Vref，第一参考开关Trf1的漏极电性连接第一输入开关Tin1与第二输入开关Tin2，第一参考开关Trf1的源极电性连接第一驱动电压端VDD1。本实施例中，参考电压Vref控制所述第一参考开关Trf1处于常开状态，也即是参考电压Vref在显示装置10上电后输出低电位的电压信号控制第一参考开关Trf1一直导通。
第一输出开关Tou1的栅极电性连接比较中间节点Nmid，第一输出开关Tou1的源极电性连接第一驱动电压端VDD1，第一输出开关Tou1的漏极电性连接脉冲输出端Vout。
第二输出开关Tou2的栅极电性连接比较中间节点Nmid，第二输出开关Tou2的源极电性连接第一低电压端Vss1，第二输出开关Tou2的漏极电性连接脉冲输出端Vout。
请参阅图20，其为如图19所示比较器CP1工作时的时序图。本实施例中像素电路800中的比较器CP1中由于第一相位输入端Vin1为同相输入端，第二相位输入端Vin2为反相输入端，由此，第一参考信号Vsweep与第一实施例中像素电路100中的比较器CP1中第一参考信号Vsweep相位相反。
具体地，在数据写入时间段Ha在写入阶段中，当扫描信号Gj的电压自高电位跳变为低电位时表征扫描线Gaj提供扫描信号至像素电路100，扫描开关T1在高电平的扫描信号控制下导通，模拟形态的图像数据信号Vdata传输数据输出节点Ncst。
图像数据信号Vdata通过存储电容Cst的充电而使得数据输出节点Ncst的电压逐渐上升。
当扫描信号Gj的电压自低电位跳变为高电位时，也即是表征扫描线Gaj停止提供扫描信号，扫描开关T1关断,数据输出节点Ncst的电压通过存储电容Cst的充电而上升至与图像数据信号Vdata相同的电压值，数据写入时间段Ha结束而进入发光时间段He。
在发光时间段He，第一参考信号Vsweep进入斜坡信号阶段，即第一参考信号Vsweep从高电位匀速、匀幅逐渐降低变化。本实例中，第一参考信号Vsweep以从高电位逐渐降低至底电位为例来说明比较器CP1依据第一参考信号Vsweep与图像数据信号Vdata的大小输出脉冲信号Vout的原理。
当第一参考信号Vsweep逐渐减小并大于图像数据信号Vdata，比较器CP1中第二输入开关Tin2与第二镜像开关Tmi2的驱动电流占主导位置，故而驱动电压VDD通过常开的第一参考开关Trf1、第二输入开关Tin2传输至比较中间节点Nmin，使得比较中间节点Nmin处于高电位(VDD)，第二输出开关Tou2则在高电位控制下导通，进而将驱动电压VDD通过第二输出开关Tou2加载至脉冲信号输出端Vout。从而使得脉冲信号输出端Vout处于低电位。
当第一参考信号Vsweep逐渐减小并小于图像数据信号Vdata，比较器CP1中第一输入开关Tin1与第一镜像开关Tmi1的驱动电流占主导位置，故而第一驱动电压通过常开的第一参考开关Trf1、第二输入开关Tin1传输至第一镜像开关Tmi1与第二镜像开关Tmi2的栅 极，使得第一镜像开关Tmi1与第二镜像开关Tmi2导通，进而使得低参考电压Vss通过第二镜像开关Tmi2加载至比较中间节点Nmin，使得比较中间节点Nmin处于低电位(Vss)，第一输出开关Tou1则在低电位控制下导通，进而将低参考电压Vss通过第一输出开关Tou1加载至脉冲信号输出端Vout。从而使得脉冲信号输出端Vout处于高电位。
由此，比较器CP1根据第一参考信号Vsweep与图像数据信号Vdata的大小的比较结果，来输出对应的脉冲信号Vout，由于脉冲信号Vout为数字形态，从而将模拟形态的图像数据信号Vdata转换为数字形态。并且，脉冲信号Vout占空比的大小由图像数据信号Vdata确定，由于驱动执行电路102提供的驱动电流Idrv的大小是由脉冲信号Vout占空比的大小确定的，由此，脉冲信号Vout能够准确表征图像数据信号Vdata的大小。
请参阅图21，其为如图18所示像素电路800的时序电路图。如图21所示，本实施例中，像素电路800在1帧图像显示期间，每个子像素103的子扫描显示周期Ts中均包括数据写入时间段Ha与发光时间段He。由此，对于六个子像素103，至少包括6个子扫描显示周期Ts1～Ts6。
本实施例中，该六个子像素103是通过扫描信号Gi在一个扫描周期T中的6个子扫描周期Ts来分时接收对应图像数据信号的驱动电流Idrv以出射光线显示图像数据。
对应6个子像素105的六个子扫描周期，分别提供6个选择信号WT1～WT6来选择第一红色子像素R1、第一绿色子像素G1、第一蓝色子像素B1、第二红色子像素R2、第二绿色子像素G2以及第二蓝色子像素B2进行图像显示。
具体地，如图10所示，对于子扫描周期Ts1，提供选择信号WT1至第一红色子像素R1，选择信号WT1控制第一红色子像素R1中选择开关Tw1导通，从而依据图像数据信号将驱动电流Idrv加载至发光元件EM1，使得发光元件EM1依据携带红色图像数据信号发射红色光线。
同理，在扫描周期Ts2～Ts6，分别提供选择信号WT2～WT6选择第一绿色子像素G1、第一蓝色子像素B1、第二红色子像素R2、第二绿色子像素G2以及第二蓝色子像素B2。
为了保证像素单元P中整体发光亮度的均匀性，本实施中至少两个相邻位置的子像素103并不在相邻的子扫描周期Ts被选择。
具体地，在子扫描周期Ts2，提供WT5选择第二绿色子像素G2；在子扫描周期Ts3，提供WT3选择第一蓝色子像素B1；在子扫描周期Ts4，提供WT4选择第二红色子像素R2；在子扫描周期Ts5，提供WT2选择第一绿色子像素G1；在子扫描周期Ts6，提供WT6选择第二蓝色子像素B2。
以在子扫描周期Ts1内提供选择信号WT1至第一红色子像素R1执行图像显示为例具体说明转换电路101、驱动执行电路102以及子像素103的工作过程。
在子扫描周期Ts1中，首先进入数据写入时间段Ha，扫描信号Gj在高电位期间控制模拟形态的图像数据信号Vdata加载至数据输出节点Ncst并通过存储电容Cst1对数据输出节点Ncst进行充电，直至数据输出节点Ncst达到稳定的电压值并且与图像数据信号Vdata的电压值相同，此时，数据写入时间段Ha结束。
在数据写入时间段Ha结束而进入显示时间段He，在显示时间段He，比较器CP1的第一相位输入端Vin1，比较器CP1的第二相位输入端Vin2接收的第一参考信号Vsweep为三角波形式的斜坡信号。
具体地，第一参考信号Vsweep为自低电位以第一速度匀速升高至高电位，然后再自高电位以第一速度匀速降低至低电位，即第一参考信号Vsweep的波形为等腰三角形的形状。
比较器CP1通过将第二相位输入端Vin2的第一参考信号Vsweep与模拟形态的图像数据信号Vdata进行比较而输出数字形态的脉冲信号Vout，本实施例中，脉冲信号Vout的占空比与图像数据信号Vdata的电压值大小呈反向关系，也即是图像数据信号Vdata的电压值越大，脉冲信号Vout的占空比越小，而图像数据信号Vdata的电压值越小，脉冲信号Vout的占空比越大。
脉冲信号Vout在低电平期间通过驱动电容Cd1对驱动控制端Ndrv进行充电并控制控制驱动执行电路102中驱动晶体管Td1的导通，驱动晶体管Td1在导通期间配合驱动电压VDD提供驱动电流Idrv至驱动输出端Ncon。
在进入显示时间段He时，第一红色子像素R1中选择信号WT1处于低电平而控制选择开关Tw1处于导通状态，由此，驱动电流Idar通过驱动输出端Ncon传输至出射红色光线的发光元件EM1。
当驱动电容Cd1对驱动控制端Ndrv充电的电压升高到驱动晶体管Td1的阈值电压之上时，驱动晶体管Td1关断，驱动电流Idrv停止输出至驱动输出端Ncon，第一红色子像素R1停止发光，发光时间段He结束，同时，子扫描周期Ts1结束，并进入子扫描周期Ts2。
以此类推，对于子扫描周期Ts2～Ts6对应依次驱动第二绿色子像素G2、第一蓝色子像素B1、第二红色子像素R2、第一绿色子像素G1以及二蓝色子像素B2执行出射光线以执行对应图像数据信号的图像显示，而对应的具体工作过程与原理本实施例不再赘述。
请参阅图22，其为本申请第九实施例中如图4所示像素电路900的具体电路结构示意图。本实施例中，像素电路900与图18对应实施例中的像素电路800基本相同，区别仅在于驱动执行电路102还包括脉冲接收开关Tps1、补偿单元1024与第二复位开Tr2，其他的电路结构相同。
脉冲接收开关Tps1电性连接比较器CP1的脉冲输出端Vout、第一驱动电压端VDD1与驱动输入端Ny之间。脉冲接收开关Tps1用于在脉冲输出端Vout输出的脉冲信号Vout控制下选择性将驱动电压VDD加载至驱动输入端Ny。
脉冲接收开关Tps1导通与关断的时间与脉冲信号Vout中高、低电位时长对应。也即是当脉冲接收开关Tps1在脉冲信号Vout的低电平控制下导通，使得驱动电压VDD加载至驱动输入端Ny；在脉冲信号Vout的高电平控制下关断，驱动电压VDD停止加载至驱动输入端Ny。
本实施例中，脉冲接收开关Tps1为P型薄膜晶体管，其中，作为脉冲接收开关Tps1的薄膜晶体管的栅极电性连接脉冲信号输出端Vout，以接收比较器CP1输出的脉冲信号Vout；作为脉冲接收开关Tps1的薄膜晶体管的源极电性连接第一驱动电压端VDD1；作为 脉冲接收开关Tps1的薄膜晶体管的漏极电性连接驱动输出端。
补偿单元1024电性连接于驱动控制端Ndrv、驱动输出端Ncon以及驱动输入端Ny，用于补偿所述第一驱动晶体管Td1的阈值电压(Vth)的漂移。
本实施例中，补偿单元1024包括第一补偿晶体管Tcv1与第二补偿晶体管Tcv2，其中第一补偿晶体管Tcv1电性连接于驱动控制端Ndrv与驱动输出端Ncon之间，用于将预先将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv。
第一补偿晶体管Tcv1为P型薄膜晶体管，其中，作为第一补偿晶体管Tcv1的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第一补偿晶体管Tcv1的薄膜晶体管的源极电性连接驱动输出端Ncon；作为第一补偿晶体管Tcv1的薄膜晶体管的源极电性连接驱动控制端Ndrv。
第二补偿晶体管Tcv2电性连接于驱动输入端Ny，用于当将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv时，同步向驱动控制端Ndrv加载辅助电压VD3。其中，辅助电压VD3的电压值可以依据第一驱动晶体管Td1的参数特性进行设置。
第二补偿晶体管Tcv2为P型薄膜晶体管，其中，作为第二补偿晶体管Tcv2的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第二补偿晶体管Tcv2的薄膜晶体管的源极接收辅助电压VD3；作为第二补偿晶体管Tcv2的薄膜晶体管的漏极电性连接驱动输入端Ny。
第二复位开Tr2电性电性连接于驱动控制端Ndrv，用于在复位信号Vrst控制下在子像素103停止图像显示时(复位时间段)提供复位电压至驱动控制端Ndrv，保证驱动控制端Ndrv维持在复位状态，保证子图像像素103准确接收到图像数据信号。
请参阅图23，其为本申请第十实施例中如图4所示像素电路1000的具体电路结构示意图。本实施例中，像素电路1000与图13对应的实施例中像素电路400基本相同，区别仅在于比较器CP1还包括迟滞单元105，其他的电路结构相同。
请结合图24一并参阅图23，其中，图24为如图23所示迟滞单元105输入输出信号时序图，如图23所示，迟滞单元105电性连脉冲信号输出端Vout、第一相位输入端Vin1与数据输出节点Ncst，用于控制所述第一相位输入端Vin1与所述第二相位输入端Vin2接收的信号的电压差值大于第一阈值或Vith者小于第二阈值时Vitl，所述脉冲信号Vout的电位发生变化(如图24所示)，且所述第一阈值Vith与所述第二阈值Vitl不同，具体的，第一阈值Vith小于第二阈值Vitl。例如，第一阈值Vith为+0.5V，所述第二阈值Vitl为-0.5V。
如图23所示，迟滞单元105电性包括第一迟滞电阻R1与第二迟滞电阻R2。第一迟滞电阻R1电性连接于所述第一相位输入端Vin1与数据输出节点Ncst之间，第二迟滞电阻R2电性连接于第一相位输入端Vin1与脉冲信号输出端Vout之间。
通过迟滞单元105的设置，当图像数据信号Vdata具有不稳定具有波动或者具有噪音时，使得脉冲信号Vout不会受到影响而保持稳定的输出。
请参阅图25，其为本申请第十一实施例中如图4所示像素电路1100的具体电路结构示意图。本实施例中，像素电路1100与图23对应的实施例中像素电路1000的基本相同，区别仅在于转换电路101、驱动执行电路102、子像素103中的开关元件的N型薄膜晶体管 与P型薄膜晶体管的类型不同。
本实施例中，转换电路101中扫描开关T1为N型薄膜晶体管。存储电容Cst1电性连接于第一驱动电压端VDD1与数据输入节点Ncst之间。
比较器CP1中，第一输入开关Tin1、第二输入开关Tin2、第一参考开关Trf1以及比较复位开关Tcr以及第二输出开关Tou2为N型薄膜晶体管，第一镜像开关Tmi1、第二镜像开关Tmi2、第一输出开关Tou1为P型薄膜晶体管。
第一输入开关Tin1的栅极电性连接第一相位输入端Vin1，第一输入开关Tin1的源极电性连接第一参考开关Trf1，第一输入开关Tin1的漏极电性连接第一镜像开关Tmi1。
第二输入开关Tin2的栅极电性连接第二相位输入端Vin2，第二输入开关Tin2的源极电性连接第一参考开关Trf1，第二输入开关Tin2的漏极电性连接第二镜像开关Tmi2。
第一镜像开关Tmi1的栅极与漏极直接电性连接并且电性连接于第一输入开关Tin1的漏极，第一镜像开关Tmi1的栅极与第二镜像开关Tmi2的栅极电性连接，第一镜像开关Tmi1的源极电性连接第一驱动电压端VDD1。
第二镜像开关Tmi2的漏极电性连接于第二输入开关Tin2的漏极，第二镜像开关Tmi2的源极电性连接第一驱动电压端VDD1。
另外，第二镜像开关Tmi2的漏极与第二输入开关Tin2的漏极均电性连接至比较中间节点Nmin。
第一参考开关Trf1的栅极接收参考电压Vref，第一参考开关Trf1的漏极电性连接第一输入开关Tin1与第二输入开关Tin2，第一参考开关Trf1的源极电性连接第一低参考电压端Vss1。
本实施例中，参考电压Vref控制所述第一参考开关Trf1处于常开状态，也即是参考电压Vref在显示装置10上电后输出高电位的电压信号控制第一参考开关Trf1一直导通。
第一输出开关Tou1的栅极电性连接比较中间节点Nmid，第一输出开关Tou1的源极电性连接第一驱动电压端VDD1，第一输出开关Tou1的漏极电性连接脉冲输出端Vout。
第二输出开关Tou2的栅极电性连接比较中间节点Nmid，第二输出开关Tou2的源极电性连接第一低电压端Vss1，第二输出开关Tou2的漏极电性连接脉冲输出端Vout。
驱动执行电路102中第一驱动晶体管Td1为N型薄膜晶体管，驱动执行电路102电性连接于比较器CP1的脉冲信号输出端Vout、驱动输出端Ncon与第一低电压端Vss1之间。具体地，第一驱动晶体管Td1的栅极电性连接脉冲信号输出端Vout，第一驱动晶体管Td1的漏极电性连接驱动输出端Ncon，第一驱动晶体管Td1的源极电性连接第一低电压端Vss1。
第一复位开关Tr1为P型薄膜晶体管。每个子像素103中，选择开关Tw1～-Tw6为N型薄膜晶体管。具体地，第一复位开关Tr1的栅极接收复位信号Vrst，第一复位开关Tr1的漏极电性连接驱动输出端Ncon，第一复位开关Tr1的源极电性连接第一驱动电压端VDD1。
补偿单元1024电性连接于驱动控制端Ndrv、驱动输出端Ncon以及驱动输入端Ny，用于补偿所述第一驱动晶体管Td1的阈值电压(Vth)的漂移。
脉冲接收开关Tps1电性连接比较器CP1的脉冲输出端Vout、第一低电压端Vss1与驱 动输入端Ny之间。脉冲接收开关Tps1用于在脉冲输出端Vout输出的脉冲信号Vout控制下，选择性将驱动输入端Ny电性连接至第一低电压端Vss1。
脉冲接收开关Tps1导通与关断的时间与脉冲信号Vout中高、低电位时长对应。也即是当脉冲接收开关Tps1在脉冲信号Vout的低电平控制下导通，使得驱动输入端Ny电性连接至第一低电压端Vss1；在脉冲信号Vout的高电平控制下关断，驱动输入端Ny与第一低电压端Vss1电性断开。
本实施例中，脉冲接收开关Tps1为N型薄膜晶体管，其中，作为脉冲接收开关Tps1的薄膜晶体管的栅极电性连接脉冲信号输出端Vout，以接收比较器CP1输出的脉冲信号Vout；作为脉冲接收开关Tps1的薄膜晶体管的源极电性连接第一低电压端Vss1；作为脉冲接收开关Tps1的薄膜晶体管的漏极电性连接驱动输出端Ny。
本实施例中，补偿单元1024包括第一补偿晶体管Tcv1与第二补偿晶体管Tcv2，其中第一补偿晶体管Tcv1电性连接于驱动控制端Ndrv与驱动输出端Ncon之间，用于将预先将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv。
第一补偿晶体管Tcv1为N型薄膜晶体管，其中，作为第一补偿晶体管Tcv1的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第一补偿晶体管Tcv1的薄膜晶体管的源极电性连接驱动输出端Ncon；作为第一补偿晶体管Tcv1的薄膜晶体管的漏极电性连接驱动控制端Ndrv。
第二补偿晶体管Tcv2电性连接于驱动输入端Ny，用于当将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv时，同步向驱动控制端Ndrv加载辅助电压VD3。其中，辅助电压VD3的电压值可以依据第一驱动晶体管Td1的参数特性进行设置。
第二补偿晶体管Tcv2为N型薄膜晶体管，其中，作为第二补偿晶体管Tcv2的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第二补偿晶体管Tcv2的薄膜晶体管的源极接收辅助电压VD3；作为第二补偿晶体管Tcv2的薄膜晶体管的漏极电性连接驱动输入端Ny。
第二复位开Tr2电性电性连接于驱动控制端Ndrv，用于在子像素103停止图像显示时(复位时间段)提供复位信号Vrst，保证驱动控制端Ndrv维持在复位状态，保证子像素103准确接收到图像数据信号。
第二复位开Tr2为P型薄膜晶体管，作为第二复位开Tr2的薄膜晶体管的栅极接收复位信号Vrst；作为第二复位开Tr2的薄膜晶体管的源极电性连接第一驱动电压端VDD1；作为第二复位开Tr2的薄膜晶体管的漏极电性连接驱动控制端Ndrv。
驱动执行电路102中，驱动电容Cd1电性连接于驱动控制端Ndrv与第一低电压端Vss1之间。
发光元件EM1通过选择开关TW1电性连接于驱动输出端Ncon1与第二驱动电源VDD2之间。每个子像素103中，选择开关Tw1～-Tw6为N型薄膜晶体管。每个子像素103中的显示元件EM通过选择开关Tw电性连接于第二驱动电源VDD2与驱动输出端Ncon之间。
请参阅图26，其为本申请第十二实施例中如图4所示像素电路1200的具体电路结构示意图。
如图26所示，转换电路101包括存储电容Cst1、第一预置开关Tpe1、第二预置开关Tpe2以及转换晶体管Ttr。
存储电容Cst1电性连接于数据线Di与数据输出节点Ncst之间，用于存储自数据线Di接收到的图像数据信号Vdata，并将数据输出节点Ncst充电至于图像数据信号Vdata相同的电位。
转换晶体管Ttr电性连接数据输出节点Ncst、第一驱动电压端VDD1以及脉冲信号输出端Vout，用于在数据输出节点Ncst的电压控制下导通或者关断，以选择性地将驱动电压VDD传输至脉冲信号输出端Vout，以作脉冲信号Vout。
本实施例中，转换晶体管Ttr为P型的薄膜晶体管，作为转换晶体管Ttr的晶体管栅极电性连接数据输出接点Ncst，作为转换晶体管Ttr的晶体管漏极电性连接脉冲信号输出端Vout，作为转换晶体管Ttr的晶体管源极电性连接第一驱动电压端VDD1。
当转换晶体管Ttr在数据输出节点Ncst的电压控制下导通时，驱动电压VDD通过转换晶体管Ttr传输至脉冲信号输出端Vout，并且将高电位作为脉冲信号Vout的电位。当转换晶体管Ttr在数据输出节点Ncst的电压控制下关断时，驱动电压VDD停止脉冲信号输出端Vout。
第一预置开关Tpe1电性连接于数据输出节点Ncst与脉冲信号输出端Vout之间，用于在第一预置信号WS1控制下将数据输出节点Ncst与脉冲信号输出端Vout直接电性导通，使得转换晶体管的栅极与漏极直接电性连接呈二极管连接。
本实施例中，第一预置开关Tpe1为P型薄膜晶体管，第一预置开关Tpe1的栅极接收第一预置信号WS1，第一预置开关Tpe1的源极电性连接数据输出节点Ncst，第一预置开关Tpe1的漏极电性连接脉冲信号输出端Vout。
第二预置开关Tpe2电性连接于脉冲信号输出端Vout与第一低电压端Vss1之间，用于在第二预置信号WS2控制下将第一低电压端Vss1与脉冲信号输出端Vout电性导通，使得脉冲信号输出端Vout输出的脉冲信号Vout为低电位。
本实施例中，第二预置开关Tpe2为P型薄膜晶体管，第二预置开关Tpe2的栅极接收第二预置信号WS2，第二预置开关Tpe2的源极电性连接第一低电压端Vss1，第二预置开关Tpe2的漏极电性连接脉冲信号输出端Vout。
本实施例中，第一预置信号WS1与第二预置信号WS2均为扫描线Gaj提供的扫描信号Gj，也是说，第一预置信号WS1与第二预置信号WS2为扫描线Gaj提供的扫描信号，第一预置开关Tpe1与第二预置开关Tpe2的栅极均电性连接于扫描线Gaj。
驱动执行电路102包括脉冲接收开关Tps1、第一驱动晶体管Td1、预置复位开关Tpr1、第一复位开关Tre1、第二复位开关Tre2与驱动电容Cd1。
脉冲接收开关Tps1电性连脉冲输出端Vout、第二驱动电压端VDD2与驱动输入端Ny之间。脉冲接收开关Tps1用于在脉冲输出端Vout输出的脉冲信号Vout控制下选择性将驱动电压VDD加载至驱动输入端Ny。
脉冲接收开关Tps1导通与关断的时间与脉冲信号Vout中高、低电位时长对应。也即是当脉冲接收开关Tps1在脉冲信号Vout的低电平控制下导通，使得驱动电压VDD加载至 驱动输入端Ny；在脉冲信号Vout的高电平控制下关断，驱动电压VDD停止加载至驱动输入端Ny。
本实施例中，脉冲接收开关Tps1为P型薄膜晶体管，其中，作为脉冲接收开关Tps1的薄膜晶体管的栅极电性连接脉冲信号输出端Vout，以接收比较器CP1输出的脉冲信号Vout；作为脉冲接收开关Tps1的薄膜晶体管的源极电性连接第一驱动电压端VDD1；作为脉冲接收开关Tps1的薄膜晶体管的漏极电性连接驱动输出端。第一驱动晶体管Td1电性连接于驱动控制端Ndrv、驱动输入端Ny以及驱动输出端Ncon，用于在驱动控制端Ndrv加载的信号控制下提供驱动电流Idrv至驱动输出端Ncon。
本实施例中，驱动晶体管Td1为P型薄膜晶体管，其中，作为第一驱动晶体管Td1的薄膜晶体管的栅极电性连接驱动控制端Ndrv；作为第一驱动晶体管Td1的薄膜晶体管的源极电性连接驱动输入端Ny；作为第一驱动晶体管Td1的薄膜晶体管的漏极电性连接驱动输出端Ncon。
驱动电容Cd1电性连接于第二驱动电压端VDD2与驱动控制端Ndrv，用于存储并在预设时间段内维持驱动控制端Ndrv处于稳定的电位，以控制第一驱动晶体管Td1在预设时间内维持导通。
预置复位开关Tpr1电性连接于驱动控制端Ndrv，用于在子像素103在出射光线之前的复位时间段为驱动控制端Ndrv提供辅助电压VD3。本实施例中，辅助电压VD3为能够控制第一驱动晶体管Td1导通。
本实施例中，预置复位开关Tpr1为P型薄膜晶体管，其中，作为预置复位开关Tpr1的薄膜晶体管的栅极接收补偿/设定信号WD；作为预置复位开关Tpr1的薄膜晶体管的源极接收辅助电压VD3；作为预置复位开关Tpr1的薄膜晶体管的漏极电性连接驱动控制端Ndrv。
第一复位开关Tre1与第二复位开关Tre2分别电性连接于驱动控制端Ndrv、驱动输出端Vcon，用于在子像素103停止图像显示时(复位时间段)在复位信号Vrst控制下提供低参考电压Vss至驱动控制端Ndrv以及驱动输出端Ncon，控制驱动控制端Ndrv以及驱动输出端Ncon复位并维持在复位状态。
本实施例中，第一复位开关Tre1为P型薄膜晶体管，其中，作为第一复位开关Tre1的薄膜晶体管的栅极接收复位信号Vrst；作为第一复位开关Tre1的薄膜晶体管的源极电性连接第一低电压端Vss1；作为第一复位开关Tre1的薄膜晶体管的漏极电性连接驱动控制端Ndrv。
本实施例中，第二复位开关Tre2为P型薄膜晶体管，其中，作为第二复位开关Tre2的薄膜晶体管的栅极接收复位信号Vrst；作为第二复位开关Tre2的薄膜晶体管的源极电性连接第一低电压端Vss1；作为第二复位开关Tre2的薄膜晶体管的漏极电性连接驱动输出端Ncon。
本实施例中，包括六个子像素103，每个子像素103包括均选择开关Tw与发光元件EM，为了便于区分六个子像素103，将多个子像素103的中的选择开关Tw与发光元件EM通过位置排列的顺序的序号来进行区分，例如处于左边第一位置的子像素103中的选择开 关Tw1与发光元件EM1，依次类推，最右边最后位置的子像素103中的选择开关Tw6与发光元件EM6。
每个发光元件EM均通过一个选择开关EM电性连接于驱动输出端Ncon与第二低电压端Vss2之间。
请参阅图27，图27为如图26所示像素电路1200中一个子像素103的工作时序图。如27所示，本实施例中，像素103在1帧图像显示期间，每个子像素103的子扫描显示周期Ts中均包括数据写入时间段Ha、复位时间段Hc以及准备时间段Hp以及发光时间段He。
在一个子扫描周期Ts内通过提供一个扫描信号中以及一个选择信号WT配合，控制子像素103执行图像显示
在子扫描周期Ts中，首先进入数据写入时间段Ha，本实施例中，数据写入时间段Ha，还进一步依次包括5个在时间上连续且无间隔的子时间段Ha1～Ha5。
在子时间段Ha1，像素电路100与其待显示的子像素103进入等待状态。
在时间段Ha2，第二预置信号WS2自高电位跳变为低电位，触发第二预置开关Tpe2导通，第一低电压端Vss1的低电压Vss则通过第二预置开关Tpe2加载至脉冲信号输出端Vout。
在子时间段Ha3，第一预置信号WS1自高电位跳变为低电位，触发第一预置开关Tpe1导通，数据输出节点Ncst与脉冲信号输出端Vout的电压均近似为低电压Vss。同时，由于第一预置开关Tpe1导通，使得第一驱动晶体管T1的栅极与漏极直接电性连接而呈二极管连接，第一驱动晶体管Td1在低电位的数据输出节点Ncst控制下导通，由此，数据输出节点Ncst与脉冲信号输出端Vout的电压均可以表示为“VDD1-Vth1”。
在子时间段Ha4，第二预置信号WS2跳变为高电平，第二阈值开关Tp2关断，低电位Vss停止加载至脉冲信号输出端Vout，图像数据信号Vdata通过第一存储电容Cst1加载至数据输出节点Ncst，此时，第一存储电容Cst1中存储的电压为：Vdata-(VDD1-Vth1)。
在子时间段Ha5，第一预置信号WS1跳变为高电平，第一阈值开关Tp1关断，数据写入时间段Ha。
数据写入时间段Ha结束后进入复位时间段Hc，在该时间段内主要是针对子像素103残存的前一帧的讯号进行释放，以便于当前帧图像数据信号数据显示的正确性。
复位时间段Hc包括3个子时间段Hc1～Hc3。
在子时间段Hc1复位信号Vret与选择信号WT均自高电位跳变为低电位，由此，复位信号Vret控制第一复位开关Tre1与第二复位开关Tre2均导通，使得驱动控制端Ndrv以及驱动输出端Ncon均处于低电位Vss而复位。
另外，选择信号WT控制选择开关Tw导通，使得驱动输出端Ncon以及电路中所有残留的信号进行释放。
在子时间段Hc2，复位信号Vret与选择信号WT均自低电位跳变为高电位，补偿/设定信号WD自高电位跳变为低电位，预置复位开关Tpr1导通，辅助电压VD3加载至驱动控制端Ndrv，从而控制第一驱动晶体管Td1导通，驱动控制端Ndrv通过驱动电容Cd1对辅 助电压VD3进行存储。
在子时间段Hc3，补偿/设定信号WD自低电位跳变为高电位，预置复位开关Tpr1关断，复位时间段Hc结束。
复位时间段Hc结束后进入准备时间段Hp，包括2个子时间段Hp1～Hp2。
在子时间段Hp1，第二预置信号WS2自高电位跳变为低电位，触发第二预置开关Tpe2导通，第一低电压端Vss1的低电压Vss则通过第二预置开关Tpe2加载至脉冲信号输出端Vout，进而控制脉冲接收开关Tps1导通，第二驱动电压VDD2通过脉冲接收开关Tps1加载至驱动输入节点Ny。
在子时间段Hp2，第二预置信号WS2自低电位跳变为高电位，第二预置开关Tpe2关断，准备时间段Hp结束
另外，在子时间段Hp1数据线Di输出高电位的信号。
在准备时间段Hp结束而进入显示时间段He，显示时间段He包括2个子时间段He1～He2。
在子时间段He1，选择信号WT自高电位降低至低电位，选择开关Tw导通。由此，第一驱动晶体管Td1配合第二驱动电压VDD2提供驱动电流Idrv至驱动输出端Ncon通过选择开关Tw加载至发光元件EM上，从而控制发光元件EM执行图像数据信号Vdata的图像显示。
同时在子时间段He1，数据线Di输出高电位的信号逐渐降低，当降低至第一驱动晶体管Td1的阈值电压Vth1时，第一驱动晶体管Td1导通从而进入子时间段He2。
在子时间段He2，由于第一驱动晶体管Td1导通，脉冲信号输出端Vout自低电位跳变为高电位。脉冲接收开关Tps1在高电位的脉冲信号控制下关断，驱动电流Idrv也被关断而降低至低电流，发光元件EM停止发光。
当选择信号WT自低电位降低至高电位显示时间段He结束，同时一个子像素103的一个子扫描周期Ts结束。
请参阅图28，为本申请如图26所示的像素电路1200在1帧图像显示期间的工作时序图，如图28所示，由于像素电路100包括六个子像素103，由此，像素电路100在1帧图像显示期间至少包括6个子扫描显示周期Ts1～Ts6。
本实施例中，该六个子像素103是通过六个选择信号WT1～WT6在一个扫描周期T中的6个子扫描周期Ts来分时接收对应图像数据信号的驱动电流Idrv以出射光线显示图像数据。
本实施例中，所述六个选择信号WT1～WT6分别选择第一红色子像素R1、第一绿色子像素G1、第一蓝色子像素B1、第二红色子像素R2、第二绿色子像素G2以及第二蓝色子像素B2进行图像显示。
请参阅图29，其为本申请第十三实施例中如图4所示像素电路1300的具体电路结构 示意图。
本实施例中，像素电路1300与图26所示实施例中像素电路1200相同，区别仅在于像素电路1300中驱动执行电路102未设置图26所示的预置复位开关Tpr1，而另外还包括补偿单元1024，补偿单元1024电性连接于驱动控制端Ndrv、驱动输出端Ncon以及驱动输入端Ny，用于补偿所述第一驱动晶体管Td1的阈值电压(Vth)的漂移。
本实施例中，补偿单元1024包括第一补偿晶体管Tcv1与第二补偿晶体管Tcv2，其中第一补偿晶体管Tcv1电性连接于驱动控制端Ndrv与驱动输出端Ncon之间，用于将预先将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv。
第一补偿晶体管Tcv1为P型薄膜晶体管，其中，作为第一补偿晶体管Tcv1的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第一补偿晶体管Tcv1的薄膜晶体管的源极电性连接驱动输出端Ncon；作为第一补偿晶体管Tcv1的薄膜晶体管的漏极电性连接驱动控制端Ndrv。
第二补偿晶体管Tcv2电性连接于驱动输入端Ny，用于当将第一驱动晶体管Td1的阈值电压Vth存储到驱动控制端Ndrv时，同步向驱动控制端Ndrv加载辅助电压VD3。其中，辅助电压VD3的电压值可以依据第一驱动晶体管Td1的参数特性进行设置。
第二补偿晶体管Tcv2为P型薄膜晶体管，其中，作为第二补偿晶体管Tcv2的薄膜晶体管的栅极电性连接补偿/设定信号WD；作为第二补偿晶体管Tcv2的薄膜晶体管的源极接收辅助电压VD3；作为第二补偿晶体管Tcv2的薄膜晶体管的漏极电性连接驱动输入端Ny。
当像素电路100在工作过程中复位时间的子时间段Hc2内，补偿/设定信号WD自高电位跳变为低电位，第一补偿晶体管Tcv1与第二补偿晶体管Tcv2导通。第一驱动晶体管Td1的栅极与漏极直接电性连接而呈二极管连接，使得驱动控制端Vdrv的电压为驱动电压输入端Ny的电压减去第一驱动晶体管Td1的阈值电压Vth2。而辅助电压VD3通过第二补偿晶体管Tcv2加载至驱动输入端Ny。由此，驱动控制端Vdrv则为(Vd3-Vth2)，由此预先将第二补偿晶体管Tcv2的阈值电压Vth写入到驱动控制端Vdrv上，从而在后续图像数据信号对应的脉冲信号加载至驱动控制端Vdrv时能够消除第一驱动晶体管Td1的阈值电压Vth的漂移带对驱动电流Idrv的影响。
请参阅图30，其为本申请第十四实施例中如图4所示像素电路1400的具体电路结构示意图。本实施例中，像素电路1400与图中29对应的像素电路1300的基本相同，区别仅在于子像素单元103的个数中K为3，其他的电路结构与工作方式均相同。
如图30所示，本实施例中，像素电路1400包括三个子像素103，即K为3。其中，所述三个子像素103按照从左到右位置排列顺序分别为第一红色子像素R1、第一绿色子像素G1、第一蓝色子像素B1，由此，在像素电路1400对应一帧图像的扫描周期T内包括对应三个子像素103的三个子扫描周期Ts。
请参阅图31，其为本申请第十五实施例中如图4所示像素电路1500的具体电路结构示意图。
本实施例中，像素电路1500与图29对应的实施例中像素电路1300的基本相同，区别 仅在于转换电路101、驱动执行电路102、子像素103中的开关元件的类型不同，像素电路1300电路中的全部开关元件与晶体管均为N型薄膜晶体管。
具体地，如图31所示，转换电路101包括存储电容Cst1、第一预置开关Tpe1、第二预置开关Tpe2以及转换晶体管Ttr。
第一存储电容Cst1电性连接于数据线Di与数据输出节点Ncst之间，用于存储自数据线Di接收到的图像数据信号Vdata，并将数据输出节点Ncst充电至于图像数据信号Vdata相同的电位。
转换晶体管Ttr电性连接数据输出节点Ncst、第一驱动电压端VDD1以及脉冲信号输出端Vout，用于在数据输出节点Ncst的电压控制下导通或者关断，以选择性地将驱动电压VDD传输至脉冲信号输出端，以作脉冲信号Vout。
本实施例中，转换晶体管Ttr为N型的薄膜晶体管，栅极电性连接数据转换接点Ncst，漏极电性连接脉冲信号输出端Vout，源极电性连接第一驱动电压端VDD1。
当转换晶体管Ttr在数据输出节点Ncst的电压控制下导通时，驱动电压VDD通过转换晶体管Ttr传输至脉冲信号输出端Vout，并且将高电位作为脉冲信号Vout的电位。当转换晶体管Ttr在数据输出节点Ncst的电压控制下关断时，驱动电压VDD停止脉冲信号输出端Vout。
第一预置开关Tpe1电性连接于数据输出节点Ncst与脉冲信号输出端Vout之间，用于在第一预置信号WS1控制下将数据输出节点Ncst与脉冲信号输出端Vout直接电性导通，使得转换晶体管的栅极与漏极直接电性连接呈二极管连接。
本实施例中，第一预置开关Tpe1为N型薄膜晶体管，其栅极接收第一预置信号WS1，源极电性连接数据输出节点Ncst，漏极电性连接脉冲信号输出端Vout。
第二预置开关Tpe2电性连接于脉冲信号输出端Vout与第一低电压端Vss1之间，用于在第二预置信号WS2控制下将第一低电压端Vss1与脉冲信号输出端Vout电性导通，使得脉冲信号输出端Vout输出的脉冲信号Vout为低电位。
本实施例中，第二预置开关Tpe2为N型薄膜晶体管，栅极接收第二预置信号WS2，源极电性连接第一低电压端Vss1，漏极电性连接脉冲信号输出端Vout。
驱动执行电路102包括脉冲接收开关Tps1、第一驱动晶体管Td1、预置复位开关Tpr1、第一复位开关Tre1、第二复位开关Tre2与驱动电容Cd1。
脉冲接收开关Tps1电性连接比较器CP1的脉冲输出端Vout、第二驱动电压端VDD2与驱动输入端Ny之间。脉冲接收开关Tps1用于在脉冲输出端Vout输出的脉冲信号Vout控制下选择性将驱动电压VDD加载至驱动输入端Ny。本实施例中，第一驱动电压端VDD1与第二驱动电压端VDD2均用于提供驱动电压VDD，驱动电压VDD用于配合第一驱动晶体管Td1提供驱动电流Idrv。
脉冲接收开关Tps1导通与关断的时间与脉冲信号Vout中高、低电位时长对应。也即是当脉冲接收开关Tps1在脉冲信号Vout的低电平控制下导通，使得驱动电压VDD加载至驱动输入端Ny；在脉冲信号Vout的高电平控制下关断，驱动电压VDD停止加载至驱动输入端Ny。
本实施例中，脉冲接收开关Tps1为N型薄膜晶体管，其中，作为脉冲接收开关Tps1 的薄膜晶体管的栅极电性连接脉冲信号输出端Vout，以接收比较器CP1输出的脉冲信号Vout；作为脉冲接收开关Tps1的薄膜晶体管的源极电性连接第一驱动电压端VDD1；作为脉冲接收开关Tps1的薄膜晶体管的漏极电性连接驱动输出端。第一驱动晶体管Td1电性连接于驱动控制端Ndrv、驱动输入端Ny以及驱动输出端Ncon，用于在驱动控制端Ndrv加载的信号控制下提供驱动电流Idrv至驱动输出端Ncon。
本实施例中，第一驱动晶体管Td1为N型薄膜晶体管，其中，作为第一驱动晶体管Td1的薄膜晶体管的栅极电性连接驱动控制端Ndrv；作为第一驱动晶体管Td1的薄膜晶体管的源极电性连接驱动输入端Ny；作为第一驱动晶体管Td1的薄膜晶体管的漏极电性连接驱动输出端Ncon。
驱动电容Cd1电性连接于第二驱动电压端VDD2与驱动控制端Ndrv，用于存储并在预设时间段内维持驱动控制端Ndrv处于稳定的电位，以控制第一驱动晶体管Td1在预设时间内维持导通。
第一复位开关Tre1与第二复位开关Tre2分别电性连接于驱动控制端Ndrv、驱动输出端Vcon，用于在子像素103停止图像显示时(复位时间段)提供复位信号Vrst，保证驱动控制端Ndrv以及驱动输出端Ncon维持在复位状态。
本实施例中，第一复位开关Tre1为N型薄膜晶体管，其中，作为第一复位开关Tre1的薄膜晶体管的栅极接收复位信号Vrst；作为第一复位开关Tre1的薄膜晶体管的源极电性连接第一低电压端Vss1；作为第一复位开关Tre1的薄膜晶体管的漏极电性连接驱动控制端Ndrv。
本实施例中，第二复位开关Tre2为N型薄膜晶体管，其中，作为第二复位开关Tre2的薄膜晶体管的栅极接收复位信号Vrst；作为第二复位开关Tre2的薄膜晶体管的源极电性连接第一低电压端Vss1；作为第二复位开关Tre2的薄膜晶体管的漏极电性连接驱动输出端Ncon。
本实施例中，包括六个子像素103，每个子像素103包括均选择开关Tw与发光元件EM，为了便于区分六个子像素103，将多个子像素103的中的选择开关Tw与发光元件EM通过位置排列的顺序的序号来进行区分，例如处于左边第一位置的子像素103中的选择开关Tw1与发光元件EM1，依次类推，最右边最后位置的子像素103中的选择开关Tw6与发光元件EM6。
每个发光元件EM均通过一个选择开关EM电性连接于驱动输出端Ncon与第二低电压端Vss2之间。本实施例中，选择开关Tw1为N型薄膜晶体管，发光元件EM通过选择开关Tw电性连接于驱动输出端Ncon与第二低电压端Vss2之间。
本实施例中，全部开关元件于晶体管均为N型薄膜晶体管，使得像素电路1500中开关元件于晶体管的漏电流较小，进一步降低功耗。
以上对本申请实施例所提供的一种像素电路进行了详细介绍，本文中应用了具体个例对本申请的原理及实施例进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施例及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

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  1. 一种像素电路，其特征在于，包括驱动电路和多个子像素，所述驱动电路包括一个转换电路和一个或多个驱动执行电路，
    所述转换电路用于接收模拟形态的图像数据信号，并且将所述模拟形态的图像数据信号转换为数字形态的图像数据信号；
    在所述驱动电路包括一个所述驱动执行电路时，所述驱动执行电路电性连接所述转换电路，用于接收所述数字形态的图像数据信号，并依据所述数字形态的图像数据信号分时提供驱动电流至所述多个子像素，驱动所述多个子像素执行图像显示；
    在所述驱动电路包括多个所述驱动执行电路时，多个所述驱动执行电路与多个所述子像素是一对一的，每一所述驱动执行电路电性连接于所述转换电路以及对应的所述子像素之间。
  2. 根据权利要求1所述的像素电路，其特征在于，所述转换电路包括扫描开关、存储电容以及比较器，
    所述扫描开关在接收到扫描信号时处于导通状态以将所述模拟形态的图像数据信号传输至所述存储电容；
    所述存储电容电性连接所述比较器的第一相位输入端，用于接收与存储所述模拟形态的图像数据信号并加载至所述比较器；
    所述比较器的第二相位输入端接收第一参考信号，所述第一参考信号为斜坡信号；
    所述比较器依据所述模拟形态的图像数据信号与所述第一参考信号中电压值的比较结果，自所述比较器的脉冲信号输出端输出所述数字形态的图像数据信号。
  3. 根据权利要求2所述的像素电路，其特征在于，所述第一参考信号为三角波信号。
  4. 根据权利要求3所述的像素电路，其特征在于，所述扫描开关为P型薄膜晶体管，所述P型薄膜晶体管的栅极用于接收所述扫描信号，所述P型薄膜晶体管的源极用于接收图像数据信号，所述P型薄膜晶体管的漏极通过数据输出节点电性连接于所述第一相位输入端，所述存储电容电性连接于所述数据输出节点和接地端之间。
  5. 根据权利要求3所述的像素电路，其特征在于，所述扫描开关为N型薄膜晶体管，所述N型薄膜晶体管的栅极用于接收所述扫描信号；所述N型薄膜晶体管的源极用于接收图像数据信号；所述N型薄膜晶体管的漏极通过数据输出节点电性连接于所述第一相位输入端，所述存储电容电性连接于第一驱动电压端与所述数据输出节点之间。
  6. 根据权利要求2至5任意一项所述的像素电路，其特征在于，所述第一相位输入端为反相输入端，所述第二相位输入端为同相输入端，所述第一参考信号的电压值逐渐减小再逐渐增大，且所述电压值增大与减小的速度相同。
  7. 根据权利要求6所述的像素电路，其特征在于，当所述第一参考信号的电压值小于所述模拟形态的图像数据信号时，所述脉冲信号为低电位；当所述第一参考信号的电压值大于所述模拟形态的图像数据信号时，所述脉冲信号为高电位。
  8. 根据权利要求7所述的像素电路，其特征在于，所述比较器包括第一输入开关、第二输入开关、第一镜像开关、第二镜像开关、第一输出开关、以及第二输出开关以及第一参考开关；
    第一输入开关、第二输入开关、第一参考开关以及第一输出开关为P型薄膜晶体管，第一镜像开关、第二镜像开关以及第二输出开关为N型薄膜晶体管；
    所述第一输入开关的栅极电性连接所述第一相位输入端，所述第一输入开关的源极电性连接所述第一参考开关，所述第一输入开关的漏极电性连接第一镜像开关；
    所述第二输入开关的栅极电性连接所述第二相位输入端，所述第二输入开关的源极电性连接所述第一参考开关，所述第二输入开关的漏极电性连接所述第二镜像开关；
    所述第一镜像开关的栅极与漏极直接电性连接并且电性连接于所述第一输入开关的漏极，所述第一镜像开关的栅极与所述第二镜像开关的栅极电性连接，所述第一镜像开关的源极电性连接第一低电压端；
    所述第二镜像开关的漏极电性连接于所述第二输入开关的漏极，所述第二镜像开关的源极电性连接所述第一低电压端，所述第二镜像开关的漏极与所述第二输入开关的漏极均电性连接至比较中间节点；
    所述第一参考开关的栅极接收参考电压，所述第一参考开关的漏极电性连接所述第一输入开关与所述第二输入开关，所述第一参考开关的源极电性连接第一驱动电压端，所述第一驱动电压端用于提供驱动高电压，所述参考电压控制所述第一参考开关处于常开状态；
    所述第一输出开关的栅极电性连接所述比较中间节点，所述第一输出开关的源极电性连接所述第一驱动电压端，所述第一输出开关的漏极电性连接所述脉冲输出端；
    所述第二输出开关的栅极电性连接所述比较中间节点，所述第二输出开关的源极电性连接所述第一低电压端，所述第二输出开关的漏极电性连接所述脉冲信号输出端。
  9. 根据权利要求8所述的像素电路，其特征在于，所述比较器还包括比较复位开关，所述比较复位开关电性连接于所述脉冲信号输出端与第一低电压端，当所述比较复位开关在复位信号控制下导通时控制所述脉冲信号输出端停止输出所述脉冲信号。
  10. 根据权利要求7所述的像素电路，其特征在于，所述比较器包括第一输入开关、第二输入开关、第一镜像开关、第二镜像开关以及第一输出开关、第二输出开关以及第一参考开关；
    第一输入开关、第二输入开关、第一参考开关以及第一输出开关为N型薄膜晶体管，第一镜像开关、第二镜像开关以及第二输出开关为P型薄膜晶体管；
    所述第一输入开关的栅极电性连接所述第一相位输入端，所述第一输入开关的源极电 性连接所述第一参考开关，所述第一输入开关的漏极电性连接第一镜像开关；
    所述第二输入开关的栅极电性连接所述第二相位输入端，所述第二输入开关的源极电性连接所述第一参考开关，所述第二输入开关的漏极电性连接比较中间节点；
    所述第一镜像开关的栅极与漏极直接电性连接并且电性连接于所述第一输入开关的漏极，所述第一镜像开关的栅极与所述第二镜像开关的栅极电性连接，所述第一镜像开关的源极电性连接所述第一驱动电压端；
    所述第二镜像开关的漏极电性连接于所述第二输入开关的漏极，所述第二镜像开关的源极电性连接所述第一驱动电压端，所述第二镜像开关的漏极与所述第二输入开关的漏极均电性连接至所述比较中间节点；
    所述第一参考开关的栅极接收参考电压，所述第一参考开关的漏极电性连接所述第一输入开关与所述第二输入开关，所述第一参考开关的源极电性连接所述第一低电压端，所述参考电压控制所述第一参考开关处于常开状态；
    所述第一输出开关的栅极电性连接所述比较中间节点，所述第一输出开关的源极电性连接所述第一驱动电压端，所述第一输出开关的漏极电性连接所述脉冲输出端；
    所述第二输出开关的栅极电性连接所述比较中间节点，所述第二输出开关的源极电性连接所述第一低电压端，所述第二输出开关的漏极电性连接所述脉冲信号输出端。
  11. 根据权利要求10所述的像素电路，其特征在于，所述比较器还包括比较复位开关，所述比较复位开关电性连接于所述脉冲信号输出端与所述第一驱动电压端，当所述比较复位开关在复位信号控制下导通时控制所述脉冲信号输出端停止输出所述脉冲信号。
  12. 根据权利要求2至5任意一项所述的像素电路，其特征在于，所述第一相位输入端为同相输入端，所述第二相位输入端为反相输入端，所述第一参考信号的电压自低电位逐渐增大到高电位再自高电位逐渐减小至低电位，且所述电压值减小与增加的速度相同。
  13. 根据权利要求12所述的像素电路，其特征在于，所述比较器包括第一输入开关、第二输出开关、第一参考开关以及第一输出开关、第一镜像开关、第二镜像开关以及第二输出开关；
    第一输入开关、第二输入开关、第一参考开关以及第一输出开关为P型薄膜晶体管，第一镜像开关、第二镜像开关以及第二输出开关为N型薄膜晶体管；
    所述第一输入开关的栅极电性连接所述第二相位输入端，所述第一输入开关的源极电性连接所述第一参考开关，所述第一输入开关的漏极电性连接第一镜像开关；
    所述第二输入开关的栅极电性连接所述第一相位输入端，所述第二输入开关的源极电性连接所述第一参考开关，所述第二输入开关的漏极电性连接所述第二镜像开关；
    所述第一镜像开关的栅极与漏极直接电性连接并且电性连接于所述第一输入开关的漏极，所述第一镜像开关的栅极与所述第二镜像开关的栅极电性连接，所述第一镜像开关的源极电性连接第一低电压端；
    所述第二镜像开关的漏极电性连接于所述第二输入开关的漏极，所述第二镜像开关的 源极电性连接所述第一低电压端，所述第二镜像开关的漏极与所述第二输入开关的漏极均电性连接至比较中间节点；
    所述第一参考开关的栅极接收参考电压，所述第一参考开关的漏极电性连接所述第一输入开关与所述第二输入开关，所述第一参考开关的源极电性连接所述第一驱动电压端，所述参考电压控制所述第一参考开关处于常开状态；
    所述第一输出开关的栅极电性连接所述比较中间节点，所述第一输出开关的源极电性连接所述第一驱动电压端，所述第一输出开关的漏极电性连接所述脉冲输出端；
    所述第二输出开关的栅极电性连接所述比较中间节点，所述第二输出开关的源极电性连接所述第一低电压端，所述第二输出开关的漏极电性连接所述脉冲信号输出端。
  14. 根据权利要求2至13任意一项所述的像素电路，其特征在于，所述比较器还包括迟滞单元，所述迟滞单元电性连所述脉冲信号输出端、所述第一相位输入端与所述数据输出节点，所述迟滞单元用于控制所述第一相位输入端与所述第二相位输入端接收的信号的电压差值大于第一阈值或者小于第二阈值时，所述脉冲信号的电位发生变化，且所述第一阈值小于所述第二阈值。
  15. 根据权利要求14所述的像素电路，其特征在于，所述迟滞单元电性包括第一迟滞电阻与第二迟滞电阻，所述第一迟滞电阻电性连接于所述第一相位输入端(Vin1)与所述数据输出节点之间，所述第二迟滞电阻电性连接于所述第一相位输入端(Vin1)与所述脉冲信号输出端之间。
  16. 根据权利要求2至15任意一项所述的像素电路，其特征在于，所述驱动执行电路包括驱动控制端、第一驱动晶体管、驱动电容、第一复位开关与驱动输出端，
    所述驱动电容电性连接于第一驱动电压端与驱动控制端之间，所述第一驱动电压端用于提供驱动电压，所述驱动电容用于在预设时间段内逐渐存储或者释放脉冲信号，并维持驱动控制端的电压与所述脉冲信号电压值相同；
    所述第一驱动晶体管电性连接于所述第一驱动电压端、所述驱动控制端以及所述驱动输出端，所述第一驱动晶体管在所述驱动控制端提供的所述脉冲信号控制下导通或者关断，当所述第一驱动晶体管导通时，所述第一驱动晶体管配合所述第一驱动电压端提供的所述驱动电压自所述驱动输出端输出所述驱动电流；
    所述第一复位开关电性连接于所述驱动输出端，用于在所述子像素停止图像显示时提供复位电压至所述驱动输出端。
  17. 根据权利要求16所述的像素电路，其特征在于，所述驱动执行电路还包括补偿单元，所述补偿单元电性连接于所述驱动控制端，用于补偿所述第一驱动晶体管阈值电压漂移，所述补偿单元包括第一补偿晶体管，所述第一补偿晶体管电性连接于所述驱动控制端与所述驱动输出端之间，用于预先将所述第一驱动晶体管的阈值电压存储到所述驱动控制端，当所述第一驱动晶体管输出所述驱动电流时所述驱动控制端存储的所述阈值电压抵消 驱动电流中所述阈值电压。
  18. 根据权利要求17所述的像素电路，其特征在于，所述补偿单元还包括第二补偿晶体管，所述第二补偿晶体管电性连接于驱动输入端，用于在所述第一驱动晶体管的阈值电压存储到所述驱动控制端时，将辅助电压与所述阈值电压同步加载至所述驱动控制端。
  19. 根据权利要求18所述的像素电路，其特征在于，所述驱动执行电路还包括第二复位开关，所述第二复位开关电性连接于所述驱动控制端与所述第一低电压端之间，用于在接收到复位信号时将所述第一低电压端提供的低电压加载至所述驱动控制端对所述驱动控制端复位。
  20. 根据权利要求19所述的像素电路，其特征在于，所述驱动执行电路还包括脉冲接收开关，所述脉冲接收开关电性连接所述转换电路用于接收所述脉冲信号，并且依据所述脉冲信号的控制选择性将所述驱动电压提供至所述第一驱动晶体管，当所述脉冲接收开关在所述脉冲信号控制下导通时，所述驱动电压通过所述脉冲接收开关传输至所述第一驱动晶体管，当所述脉冲接收开关在所述脉冲信号控制下关断时，所述驱动电压停止传输至所述第一驱动晶体管。
  21. 根据权利要求20所述的像素电路，其特征在于，所述第一驱动晶体管、所述脉冲接收开关、第一补偿晶体管与第二补偿晶体管为P型薄膜晶体管，所述第一复位开关与所述第二复位开关为N型薄膜晶体管，每个子像素103包括选择开关与发光元件，所述发光元件通过所述选择开关电性连接所述驱动执行电路的驱动输出端，当所述选择开关在选择信号控制下导通时，所述驱动电流通过所述选择开关传输至所述发光元件，驱动所述发光元件发光并显示所述图像数据，所述选择开关为P型薄膜晶体管，所述发光元件电性通过所述选择开关电性连接所述驱动输出端与第二低电压端之间。
  22. 根据权利要求20所述的像素电路，其特征在于，所述第一驱动晶体管、所述脉冲接收开关、第一补偿晶体管与第二补偿晶体管为N型薄膜晶体管，所述第一复位开关与所述第二复位开关为P型薄膜晶体管，每个子像素包括选择开关与发光元件，所述发光元件通过所述选择开关电性连接所述驱动执行电路的驱动输出端，当所述选择开关在选择信号控制下导通时，所述驱动电流通过所述选择开关传输至所述发光元件，驱动所述发光元件发光并显示所述图像数据，所述选择开关为N型薄膜晶体管，所述发光元件通过所述选择开关电性连接所述驱动输出端与第二驱动电压端之间，所述第二驱动电压端用于提供驱动电压配合所述第一驱动晶体管提供所述驱动电流。
  23. 根据权利要求1至22任意一项所述的像素电路，其特征在于，所述像素电路包括三个子像素，所述三个子像素接收同一个数据线提供的所述图像数据信号以及接收同一个扫描线提供的扫描信号，所述扫描信号包括三个子扫描周期；或者，
    所述像素电路包括六个子像素，所述六个子像素接收同一个数据线提供的所述图像数据信号且接收同一个扫描线提供的扫描信号，所述扫描信号包括六个子扫描周期。
  24. 根据权利要求23所述的像素电路，其特征在于，当所述像素电路包括三个子像素时，所述三个子像素分别出射不同颜色的光线；当所述像素电路包括六个子像素时，每两个像素发射相同颜色的光线，所述六个子像素分别出射三种不同颜色光线，且任意相邻的两个子像素出射不同颜色的光线。
  25. 根据权利要求23所述的像素电路，其特征在于，当所述像素电路包括六个子像素时，至少两个相邻的子像素不在相邻的子扫描周期出射光线。
  26. 根据权利要求1所述的像素电路，其特征在于，所述转换电路包括存储电容、第一预置开关、第二预置开关以及转换晶体管，
    所述存储电容电性连接于数据输出节点，用于将接收到的图像数据信号对所述数据输出节点充电至与所述图像数据信号相同的电位；
    所述转换晶体管电性连接所述数据输出节点、第一驱动电压端以及脉冲信号输出端，用于在所述数据输出节点的电压控制下导通或者关断，所述第一驱动电压端用于提供驱动电压，当所述转换晶体管在所述数据输出节点的电压控制下导通时，所述驱动电压通过所述转换晶体管传输至脉冲信号输出端并且将高电位作为所述脉冲信号的电位；
    所述第一预置开关电性连接于所述数据输出节点与所述脉冲信号输出端之间，用于在第一预置信号控制下将所述数据输出节点与所述脉冲信号输出端直接电性导通，使得所述转换晶体管的栅极与漏极直接电性连接呈二极管连接；
    所述第二预置开关电性连接于脉冲信号输出端与第一低电压端之间，用于在第二预置信号控制下将第一低电压端与脉冲信号输出端电性导通，使得脉冲信号输出端输出的脉冲信号为低电位；
    所述驱动执行电路包括脉冲接收开关、第一驱动晶体管与驱动电容，
    所述脉冲接收开关电性连接脉冲输出端、第二驱动电压端与驱动输入端之间，用于在脉冲输出端输出的所述脉冲信号控制下选择性将所述驱动电压加载至驱动输入端；
    所述第一驱动晶体管电性连接于所述第一驱动电压端、所述驱动控制端以及所述驱动输出端，所述第一驱动晶体管在所述驱动控制端提供的所述脉冲信号控制下导通或者关断，当所述第一驱动晶体管导通时，所述第一驱动晶体管配合第一驱动电压端提供的所述驱动电压自所述驱动输出端输出所述驱动电流；
    所述驱动电容电性连接于所述第二驱动电压端与所述驱动控制端，用于存储并在预设时间段内维持驱动控制端处于稳定的电位以控制第一驱动晶体管在预设时间内维持导通。
  27. 根据权利要求26所述的像素电路，其特征在于，所述驱动执行电路还包括第一复位开关与第二复位开关，所述第一复位开关与所述第二复位开关分别电性连接于所述驱动控制端与驱动输出端，用于在所述子像素停止图像显示时控制所述驱动控制端与驱动输出 端复位。
  28. 根据权利要求27所述的像素电路，其特征在于，每个子像素包括选择开关与发光元件，所述发光元件通过所述选择开关电性连接所述驱动执行电路，当选择开关在显示选择信号控制下导通时，所述驱动电流通过所述选择开关传输至所述发光元件，驱动所述发光元件发光并显示所述图像数据。
  29. 根据权利要求28所述的像素电路，其特征在于，所述驱动执行电路还包括预置复位开关，所述预置复位开关电性连接于所述驱动控制端，用于在所述子像素出射光线之前的复位时间段加载辅助电压至所述驱动控制端，所述辅助电压用于控制所述第一驱动晶体管处于导通。
  30. 根据权利要求28所述的像素电路，其特征在于，所述驱动执行电路还包括补偿单元，所述补偿单元电性连接于所述驱动控制端，用于补偿所述第一驱动晶体管阈值电压漂移，所述补偿单元包括第一补偿晶体管与第二补偿晶体管，所述第一补偿晶体管电性连接于所述驱动控制端与所述驱动输出端之间，用于预先将所述第一驱动晶体管的阈值电压存储到所述驱动控制端，当所述第一驱动晶体管输出所述驱动电流时，所述驱动控制端(Ndrv)存储的所述阈值电压抵消驱动电流中阈值电压；
    所述第二补偿晶体管电性连接于驱动输入端，用于在所述第一驱动晶体管的阈值电压存储到所述驱动控制端时，将辅助电压与所述阈值电压同步加载至所述驱动控制端。
  31. 根据权利要求26至30任一项所述的像素电路，其特征在于，所述像素电路包括三个子像素或者六个子像素，所述三个子像素单元或者所述六个子像素接收同一个数据线提供的所述图像数据信号且接收同一个扫描线提供的扫描信号，所述扫描信号包括三个子扫描周期或者六个子扫描周期。
  32. 根据权利要求31所述的像素电路，其特征在于，当所述像素电路包括三个子像素时，所述三个子像素分别出射不同颜色的光线；当所述像素电路包括六个子像素时，每两个子像素发射相同颜色的光线，所述六个子像素分别出射三种不同颜色光线，任意相邻的两个子像素出射不同颜色的光线，且至少两个相邻的子像素不在相邻的子扫描周期出射光线。
  33. 根据权利要求32所述的像素电路，其特征在于，第一预置开关、第二预置开关、转换晶体管、脉冲接收开关、第一驱动晶体管、第一复位开关、第一复位开关、第二复位开关、多个选择开关以及第二补偿开关为P型薄膜晶体管，且每个子像素中所述发光元件电性通过所述选择开关电性连接所述驱动输出端与第二低电压端之间。
  34. 根据权利要求32所述的像素电路，其特征在于，第一预置开关、第二预置开关、 转换晶体管、脉冲接收开关、第一驱动晶体管、第一复位开关、第一复位开关、第二复位开关、多个选择开关以及第二补偿开关为N型薄膜晶体管，且每个子像素中所述发光元件电性通过所述选择开关电性连接所述驱动输出端与第二驱动电压端之间，所述第二驱动电压端用于提供驱动电压且配合所述第一驱动晶体管提供所述驱动电流。
  35. 据权利要求1至34任意一项所述的像素电路，其特征在于，所述子像素为Micro-LED显示单元。
  36. 一种阵列基板，其特征在于，包括位于显示区内的多个用于执行图像显示的如权利要求1-35项任意一项的像素电路、多条数据线与多条扫描线，所述扫描线沿第一方向延伸并沿着第二方向间隔预设距离绝缘设置，所述数据线沿着所述第二方向延伸并且沿着第一方向间隔预设距离绝缘设置，所述第一方向垂直于所述第二方向，所述数据线用于提供所述图像数据信号，所述扫描线用于提供所述扫描信号，任意相邻的两条所述数据线与任意相邻的两条扫描线定义一个像素单元，所述像素单元设置一个所述像素电路。
  37. 一种显示装置，其特征在于，包括权利要求36所述的阵列基板。
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