WO2021044443A1

WO2021044443A1 - In-situ etching process

Info

Publication number: WO2021044443A1
Application number: PCT/IN2020/050771
Authority: WO
Inventors: Srinivasan Raghavan; Navakanta Bhat; Rohith SOMAN
Original assignee: Indian Institute Of Science
Priority date: 2019-09-04
Filing date: 2020-09-04
Publication date: 2021-03-11

Abstract

Methods of fabricating semiconductor stacks and semiconductor stacks obtained therefrom are provided. A substrate (102) is provided in a reactor. First precursors are supplied with a carrier gas to form a first layer (104) on the substrate (102) and the supply is stopped after the first layer (104) is formed. Second precursors and third precursors are supplied with the carrier gas to form a doped layer. The second precursors correspond to precursors which form an intrinsic semiconductor and the third precursors correspond to precursors which form a dopant. Supply of the second precursors and the third precursors is stopped. The carrier gas is continued to be supplied to remove a top surface of the doped layer to form a surface etched doped layer (106) to reduce diffusion of the dopant to subsequent layers.

Description

iN-SiTU ETCHING PROCESS

TECHNICAL FIELD

[0001] The present subject matter relates to Metal Organic Chemical Vapor Deposition (MOCVD) growth and, in particular, to an in-situ etching process to prevent diffusion of dopant during the growth of designed stack. The stack can be High Electron Mobility

Transistor (HEMT) or Light Emitting Diode (LED) structures or any other device stack.

BACKGROUND

[0002] Doping is the intentional introduction of impurities into an intrinsic semiconductor for modulating its electrical, optical, and structural properties. A material used to dope the semiconductor is called a dopant and the doped material is referred to as an extrinsic semiconductor.

[0003] In gallium nitride (GaN) based electronic devices such as High Electron Mobility Transistors (HEMTs) or Light Emitting diodes (LEDs), magnesium and iron may be used as p-type dopants and silicon may be used as n-type dopant. Diffusion of the dopants into subsequent layers during Metal Organic Chemical Vapour Deposition (MOCVD) is an obstacle in realizing controlled doping in GaN HEMT architecture. Such diffusion can affect the intended electrical properties of the devices.

BRIEF DESCRIPTION OF DRAWINGS [0004] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and components.

[0005] Fig. 1 illustrates an example HEMT stack, in accordance with an implementation of the present subject matter. [0006] Fig. 2 illustrates an example method of growing an example HEMT stack, in accordance with an implementation of the present subject matter.

[0007] Figs. 3 (A) - (D) illustrate reflectivity oscillations of four growth runs with different in-situ etching times, in accordance with an implementation of the present subject matter.

[0008] Fig. 4 illustrates a Secondary Ion Mass Spectroscopy (SIMS) graph, in accordance with an implementation of the present subject matter.

[0009] Fig 5(a) illustrates variation of average contactless mobility and Fig. 5(b) illustrates variation of saturation current between two ohmic contact of the samples treated with in-situ etching for different time duration, in accordance with an implementation of the present subject matter.

DETAILED DESCRIPTION

[00010] The present subject matter provides methods of in-situ etching in GaN based electronic devices such as HEMTs or LEDs. In the present description, while the in- situ etching has been explained for reduction of p-type dopant from a surface of a doped layer for purposes of discussion, it may be understood that the method of the present subject matter may be used for reduction of n-type dopant from the surface of the doped layer as well.

[00011] Generally, HEMTs or LEDs comprise a plurality of layers of semiconductors in the form of a stack. For sake of ease in explanation, the present subject matter has been explained with respect to HEMTs. However, the principles of the present subject matter will apply to other semiconductor devices, such as Light Emitting Diodes (LEDs), also. To improve the electrical properties of semiconductors, one or more layers may be doped. Dopant used for doping may be p-type dopants or n-type dopants. In the case of GaN based HEMTs, the p-type dopants may be magnesium or iron and the n-type dopants may be silicon. The plurality of stacks is generally fabricated by deposition of one layer on another to form the semiconductor stack. [00012] During deposition, the dopant may diffuse into the subsequently formed layers forming a dopant tail in the subsequently formed layers. For example, in GaN based HEMTs, magnesium in a p-type doped layer may form a p-type dopant tail in subsequently formed layers. This diffusion can be attributed to a high concentration of the dopant on the surface of the doped layer. The diffusion can also be attributed to the dopants being adsorbed on to walls of reactors where the semiconductor stack is grown. The dopant tail is characterized by a decay rate (nanometer/decade). Ideally, the decay rate should be zero.

[00013] Conventionally, Metal Organic Chemical Vapour Deposition (MOCVD) is used for the growth of the plurality of stacks. The decay rate for MOCVD grown stacks has been found to be in the range of 150 - 200 nm/ dec. This indicates that for a drop of a decade in the dopant concentration, 200 nm of subsequent layer is needed. Thus, for optimal drop of concentration of the dopant in subsequent layers, about 400-600 nm of subsequent layers are required. [00014] There have been efforts to reduce the diffusion of the dopant into the subsequent layers in the MOCVD. A first technique for reducing the diffusion is by wet etching. Using the first technique, the dopant can be etched or removed from the surface of the doped layer to reduce or eliminate the diffusion of the dopant into the subsequent layers. For this, after forming the doped layer, the MOCVD reactor is stopped. The stack with the doped layer is removed from the MOCVD reactor and etched to remove the dopant from the surface of the doped layer to form an etched stack.

[00015] The etched stack is then placed again in the MOCVD reactor to grow the subsequent layers. While wet etching helps in reducing the decay rate as compared to MOCVD without wet etching, the technique is a low throughput technique as it involves stopping deposition and withdrawal of the partially grown stack from the MOCVD reactor. Further, MOCVD occurs at high temperatures of 1050°C. For wet etching, as the MOCVD reactor must be stopped and the stack has to be cooled, the technique is time consuming and has high power consumption associated with re heating the MOCVD reactor to high temperatures for subsequent growth of layers. [00016] A second technique for reducing diffusion of dopants includes reducing temperature in the MOCVD reactor prior to growth of the subsequent layers after the growth of the doped layer. In this technique, after the growth of the doped layer by MOCVD at 1050°C, the temperature in the MOCVD reactor is dropped to about 400 - 500 °C. This reduction in temperature reduces the amount of diffusion of the dopant into subsequently grown layers. However, the reduction in temperature for growth of the subsequent layers reduces the quality of the stack and, thereby, of the HEMT. [00017] A third technique for reducing the diffusion during MOCVD involves growing an aluminum nitride (AIN) over the doped layer. However, this could affect intended functionality of the GaN HEMT.

[00018] Further, to reduce or eliminate diffusion, other methods for fabrication or growth of the HEMT stack have been used, such as Molecular Beam Epitaxy (MBE) and Flow Modulation Epitaxy (FME). While these methods have reduced the decay rate, MOCVD is the most preferred growth technique for commercial applications because of higher growth rate.

[00019] The present subject matter addresses these and other problems of MOCVD based growth or fabrication of semiconductor stacks. The present subject matter provides a method of in-situ etching for removing a top surface of a doped layer. The in-situ etching helps in reducing availability of the dopant for diffusion without interrupting the MOCVD process.

[00020] A substrate is provided in a reactor. First precursors are supplied along with a carrier gas to form a first layer on the substrate. In one example, the first layer comprises a plurality of first sub-layers. To form the plurality of first sub-layers, the sub-layer precursors are supplied successively with the carrier gas. For example, to form a particular sub-layer, the precursors for that particular sub-layer are supplied along with the carrier gas. For forming the next sub-layer, the supply of precursor for the previous sub-layer is stopped and precursor for the next sub-layer is supplied along with the carrier gas. This is repeated till all the first sub-layers are formed.

[00021] On forming the first layer, second precursors and third precursors are supplied with the carrier gas to form a doped layer on the first later. The second precursors correspond to precursors which form an intrinsic semiconductor and the third precursors correspond to precursors of a dopant. The dopant may be a p-type dopant or an n-type dopant. Thus, the doped layer formed of the intrinsic semiconductor doped with the dopant is formed.

[00022] A top surface of the doped layer may have a high concentration of the dopant while below the top surface, the dopant concentration may be less. For in-situ etching and reducing availability of dopant for diffusion, supply of the second precursors and the third precursors is stopped and the supply of the carrier gas is continued. On supply of only the carrier gas, due to high temperatures maintained during MOCVD, the top surface of the doped layer decomposes and gets etched. Thus, the top surface is removed exposing a lower surface which has a lower amount of dopant available. The reduced availability of dopant at the surface of the dopant contributes to a reduction of diffusion of the dopant from the doped layer to subsequent layers when the subsequent layers are formed on the surface etched doped layer.

[00023] Thus, by using the teachings of the present subject matter, the dopant can be removed from the top surface of the doped later without removing a partially grown semiconductor stack from the MOCVD reactor or changing the temperature of the reactor. This helps in increasing throughput of the MOCVD process. Further, since the high concentration of dopant at the top surface is removed, the diffusion of the dopant into subsequent layers formed on the doped layer is reduced. This helps in improving saturation current of the semiconductor stack and reducing the overall stack size.

[00024] The above and other features, aspects, and advantages of the subject matter will be better explained with regard to the following description and accompanying figures. It should be noted that the description and figures merely illustrate the principles of the present subject matter along with examples described herein and, should not be construed as a limitation to the present subject matter. It is thus understood that various arrangements may be devised that, although not explicitly described or shown herein, embody the principles of the present disclosure. Moreover, all statements herein reciting principles, aspects, and examples thereof, are intended to encompass equivalents thereof. Further, for the sake of simplicity, and without limitation, the same numbers are used throughout the drawings to reference like features and components.

[00025] Fig. 1 illustrates an example semiconductor stack 100, in accordance with an implementation of the present subject matter. While the present subject matter has been described with reference to GaN -based HEMTs, other materials may also be used to fabricate the semiconductor stack 100 as will be understood. The semiconductor stack 100 comprises a substrate 102. The substrate 102 may be fabricated from a material selected from silicon, silicon carbide, sapphire, and combinations thereof. In an example, a thickness of the substrate 102 is in a range of 0.5 mm to 2 mm.

[00026] A first layer 104 may be provided on the substrate 102. The first layer 104 may comprise a plurality of first sub-layers, for example, nucleation layers, transition layers, buffer layers, and the like. In the example semiconductor stack 100 as illustrated in Fig. 1, the plurality of first sub-layers may comprises an AIN layer 104-1, an AlGaN layer 104-2, and an AIN 104-3. Each of the sub-layers can further include sub-layers. For example, the AlGaN layer 104-2 can include layers of AEAEo^N, AlsoGasoN, and Al25Ga75N. The thickness of each layer can be varied based on the intended functionality of the semiconductor stack 100 as will be understood.

[00027] A surface etched doped layer 106 can be provided on the first layer 104. The surface etched doped layer 106 can be formed by removing or etching a top surface of a doped layer which can otherwise comprise high concentration of the dopant. The doped layer may be fabricated from an intrinsic semiconductor doped with a dopant. In one example, the dopant may be a p-type dopant or an n-type dopant. For example, the doped layer may have GaN layer doped with magnesium or iron.

[00028] Due to high concentration of dopant in the top surface of the doped layer, the dopant may diffuse into subsequent layers, for example, a second layer 108 as shown in Fig. 1, during MOCVD for growth of the semiconductor stack 100. To prevent this, the top surface of the doped layer, as shown by arrow 110, may be etched in-situ without interrupting MOCVD. The in-situ etching reduces the concentration of dopant available at the top surface of the doped layer. This helps in reducing the amount of dopant available for diffusion and, hence, contributes to reduction of diffusion of the dopant into the second layer 108.

[00029] The second layer 108 may be provided on the surface etched doped layer 106. The second layer 108 may include a plurality of second sub-layers. For example, the second sub-layers may include an n-doped layer 108-1, for example, silicon doped GaN; an unintentionally doped layer 108-2, an AIN layer 108-3, an AbsGaysN layer 108-4, and a GaN layer 108-5. Other materials may be used to fabricate each layer of the second layer 108 as will be understood.

[00030] Fig. 2 illustrates an example method 200 of fabricating or growing a semiconductor stack, in accordance with an implementation of the present subject matter. The semiconductor stack may be as shown in Fig. 1. However, other HEMT stacks, LED stacks, and architecture may be fabricated as well. The order in which the method 200 is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement method 200 or an alternative method. Additionally, individual blocks may be deleted from the method 200 without departing from the spirit and scope of the subject matter described herein. For discussion, the method 200 is described with reference to the implementations illustrated in Fig. 1.

[00031] With reference to method 200, as illustrated in Fig. 2, at block 202, the method 200 comprises providing a substrate. The substrate may be substrate 102 and may be selected from silicon, silicon carbide, sapphire, and combinations thereof. The substrate may be provided in a reactor, for example, an MOCVD reactor. For fabricating or growing the semiconductor stack, temperature within the reactor may be maintained in a range of 700°C to 1400°C and pressure within the reactor may be maintained in a range of 20 mbar to 500 mbar. In one example, the temperature within the reactor is maintained at 1000°C and pressure is maintained at 40 mbar.

[00032] At block 204, the method 200 comprises supplying first precursors with a carrier gas to form a first layer on the substrate and stopping supply of the first precursors after formation of the first layer. The first layer may be first layer 104 as shown in Fig. 1. The carrier gas may be selected from hydrogen, nitrogen, or combination thereof.

[00033] In one example, the first layer 104 comprises a plurality of first sub-layers, for example, sub-layers 104-1, 104-2... 104n. In said example, for each sub-layer, the method can comprise supplying sub-layer precursors with the carrier gas to form that sub-layer. For example, to form a particular sub-layer, the precursors for that particular sub-layer are supplied along with the carrier gas. For forming the next sub-layer, the supply of precursor for the previous sub-layer is stopped and precursor for the next sub-layer is supplied along with the carrier gas. This is repeated till all the first sub layers are formed. For example, with reference to AIN layer 104-1, precursors for aluminium, such as tri-methyl aluminium (TMA), and nitrogen, such as ammonia, may be supplied with the carrier gas while supply of precursors for previous layers, such as precursors for gallium, may be stopped. Similarly, with reference to AlGaN layer 104- 2, precursors of aluminium, such as TMA, precursors of gallium, such as trimethylgallium, and precursors of nitrogen, such as ammonia, may be supplied to grow the AlGaN layer.

[00034] In one example, since each sub-layer of the plurality of sub-layers includes nitride, ammonia may be continuously supplied as a nitrogen precursor while forming each layer of the first plurality of layers. However, as previously explained, based on the composition of the layer to be grown, the precursors may be accordingly supplied. [00035] At block 206, the method comprises supplying second precursors and third precursors with the carrier gas to form a doped layer. The doped layer can be formed over the first layer 104. As explained previously, the doped layer comprises an intrinsic semiconductor doped with a dopant. The second precursors can correspond to precursors which form the intrinsic semiconductor and the third precursors correspond to precursors which form the dopant. For example, the intrinsic semiconductor may be GaN and the precursors for GaN may be trimethyl gallium (for gallium) and ammonia (for nitrogen). The dopant may be n-type dopant or a p-type dopant. In one example, the dopant is a p-type dopant and may be magnesium or iron. In said example, the precursor of magnesium may be bis(cyclopentadienyl) magnesium (Cp2Mg), and the precursor for iron may be ferrocene. On forming the doped layer, a top surface of the doped layer may have a high concentration of the dopant which contributes to diffusion into subsequent layers formed on the doped layer while below the top surface, the dopant concentration may be less.

[00036] At block 208, the method comprises stopping supply of the second precursors and the third precursors. At block 210, the method comprises continuing supply of the carrier gas to remove or etch the top surface of the doped layer to form a surface etched doped layer. The time for which the etching may be performed may vary based on the amount of dopant to be removed and the depth to which etching is to be performed. [00037] On supplying the carrier gas in the absence of any precursors, the top surface of the doped layer decomposes leading to in-situ etching of the surface of the doped layer and removal of the dopant. By etching, the top surface of the doped layer gets decomposed and gets removed in the gaseous form with the carrier gas. Thus, the dopant available for diffusion may be removed without removing the partially formed semiconductor stack from the reactor or reducing the temperature of the reactor. The in-situ etching may be done on the top surface as shown by arrow 110 in Fig. 1. The in-situ etching, thus, may be performed without reducing the temperature of the MOCVD reactor or removing the partially grown stack from the MOCVD reactor, thereby, providing high throughput and also reducing or eliminating diffusion of the dopant into the subsequent layers. The surface etched doped layer may be, for example, the surface etched doped layer 106.

[00038] In one example, a second layer may be formed on the surface etched doped layer 106. The second layer may be, for example, the second layer 108. The second layer 108 may be formed by supplying fourth precursors with the carrier gas to obtain the semiconductor stack. In one example, the second layer may comprise a plurality of second sub-layers, for example, the second sub-layers may include the n-doped GaN layer 108-1, for example, silicon doped GaN; the unintentionally doped layer 108-2, the AIN layer 108-3, the AhsGaysN layer 108-4, and the GaN layer 108-5.

[00039] In said example, for each sub-layer, the method can comprise supplying sub layer precursors with the carrier gas to form that sub-layer. For example, to form a particular sub-layer, the precursors for that particular sub-layer are supplied along with the carrier gas. For forming the next sub-layer, the supply of precursor for the previous sub-layer is stopped and precursor for the next sub-layer is supplied along with the carrier gas. This is repeated till all the second sub-layers are formed. For example, to form the n-doped GaN layer where the n-dopant is silicon, precursors for silicon, such as silane, precursors for gallium, such as trimethylgallium, and precursors of nitrogen, such as ammonia may be supplied along with the carrier gas. Similarly, to form AIN layer 108-3, the supply of precursor for silicon and gallium may be stopped, while precursors of aluminium, such as TMA, and precursors of nitrogen, such as ammonia, may be supplied. However, as previously explained, based on the composition of the layer to be grown, the precursors may be accordingly supplied.

[00040] The semiconductor stack obtained using the method 200 may be used, for example, in HEMTs, LEDs, and other semiconductor-based devices. The semiconductor stack obtained using the method 200 provides reduced diffusion of the dopant from the doped layer to the second layer 108.

[00041] The present subject matter will now be illustrated with working examples, which are intended to illustrate the working of disclosure and not intended to be taken restrictively to imply any limitations on the scope of the present disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood to one of ordinary skill in the art to which this disclosure belongs. It is to be understood that this disclosure is not limited to the particular methods and experimental conditions described, as such methods and conditions may vary depending on the process and inputs used as will be easily understood by a person skilled in the art.

EXAMPLES

EXAMPLE 1 : PREPARATION OF THE SEMICONDUCTOR STACK [00042] A semiconductor stack was grown by using the method 200. The semiconductor stack was grown by MOCVD. The substrate used was silicon wafer. The first layer comprised an AIN layer, Af_/5Ga25N, AlsoGasoN, AbsGaysN layers, and AIN layer stacked. Each sub-layer of the first layer was grown by supplying precursors for forming that layer with hydrogen as carrier gas and stopping supply of precursors of other layers.

[00043] The doped layer was grown from magnesium doped GaN by supplying precursors of magnesium, gallium, and nitrogen, i.e., bis(cyclopentadienyl) magnesium (Cp2Mg), trimethyl gallium, and ammonia, respectively. Surface of the doped layer was etched in-situ by stopping supply of all precursors after formation of the doped layer and continuing supply of hydrogen to obtain the surface etched doped layer.

[00044] The second layer was formed on the surface etched doped layer. The second layer comprised silicon doped GaN; the unintentionally doped layer, the AIN layer, the Ab5Ga75N layer, and the GaN layer stacked. Each sub-layer of the second layer was grown by supplying precursors for forming that layer with hydrogen as carrier gas and stopping supply of precursors of other layers.

[00045] The temperature within the MOCVD reactor was maintained at 1000°C and the pressure within the MOCVD reactor was maintained at 40 mbar during the growth process.

EXAMPLE 2: REFLECTIVITY OSCILLATION STUDY

[00046] Figs. 3 (A) - (D) illustrate reflectivity oscillations of four growth runs with different in-situ etching times during growth of stack as described with reference to Example 1. Fig. 3 (A) depicts reflectivity oscillation of a first growth run where no in- situ etching was performed, in accordance with an implementation of the present subject matter. As can be seen, the reflectivity oscillation shows a sinusoidal graph indicating a normal growth.

[00047] Fig. 3 (B) depicts reflectivity oscillation of a second growth run where in-situ etching of the doped layer was performed for 25 seconds, in accordance with an implementation of the present subject matter. Portion 302 marked by dotted lines 304a and 304b indicates the in-situ etching of the doped layer. Similarly, Fig. 3 (C) depicts reflectivity oscillation of a third growth run where in-situ etching of the doped layer was performed for 50 seconds, in accordance with an implementation of the present subject matter. Portion 306 marked by dotted lines 308a and 308b indicates the in-situ etching of the doped layer. Fig. 3 (D) depicts reflectivity oscillation of a fourth growth run where in-situ etching of the doped layer was performed for 75 seconds, in accordance with an implementation of the present subject matter. Portion 310 marked by dotted lines 312a and 312b indicates the in-situ etching of the doped layer. Portions 302, 306, and 310 confirm etching of the doped layer. Thus, from Fig. 3(A)-(D) in-situ etching in the presence of the carrier gas was confirmed. EXAMPLE 3: STRUCTURED ION MASS SPECTROSCOPY (SIMS) STUDY [00048] Structured Ion Mass Spectroscopy (SIMS) plot with no in-situ etching and 50 seconds in-situ hydrogen etching were obtained as shown in Fig. 4. The inverse of slope obtained from line 402 (without in-situ etching) and line 404 (with 50 seconds in-situ hydrogen etching) indicate that the dopant concentration decay rate dropped from 160 nm/dec (line 402) to 24 nm/dec (line 404).

EXAMPLE 4: MOBILITY AND CURRENT OUTPUT STUDY

[00049] Fig 5(a) illustrates variation of average contactless mobility and Fig. 5(b) illustrates variation of saturation current between two ohmic contacts of the samples treated with in-situ etching for different time duration, in accordance with an implementation of the present subject matter. Sample 1, 2, 3, and 4 in Fig. 5(a) and Fig. 5(b) indicate samples with in-situ hydrogen etching performed for 0, 25 seconds, 50 seconds, and 75 seconds, respectively.

[00050] From Fig. 5(a), it was observed that mobility of two-dimensional electron gas (2DEG) of the stack increased gradually with the in-situ etching. The low mobility for sample 1 was, therefore, believed to be because of diffusion of the p-type dopant. With in-situ hydrogen treatment, the p-type dopant on the surface of the doped layer is etched off and diffusion of the p-type dopant to the subsequent layers (second plurality of layers 108) is reduced, thereby increasing 2DEG mobility. The increase in 2DEG mobility resulted in higher current. Thus, saturation current was also observed to increase with increase in in-situ etching time as shown in Fig. 5(b).

[00051] The present subject matter, thus, provides an in-situ etching process to remove p-type dopant from a doped layer during MOCVD based growth of HEMT stacks. By using the process, the diffusion of p-type dopant is reduced which contributes to mobility of 2DEG and also improves saturation current of the stack. The in-situ etching process increases throughput of the MOCVD process while also decreasing the decay rate of the p-type dopant into subsequent layers. [00052] Although the subject matter has been described in considerable detail with reference to certain examples and implementations thereof, other implementations are possible. As such, the scope of the present subject matter should not be limited to the description of the preferred examples and implementations contained therein.

Claims

1/ We claim:

1. A method of growing a semiconductor stack (100), the method comprising: providing a substrate (102) in a reactor; supplying first precursors with a carrier gas to form a first layer (104) on the substrate ( 102) and stopping supply of the first precursors after formation of the first layer (104); supplying second precursors and third precursors with the carrier gas to form a doped layer, wherein the second precursors correspond to precursors which form an intrinsic semiconductor and the third precursors correspond to precursors of a dopant; stopping supply of the second precursors and the third precursors; and continuing supply of the carrier gas to remove a top surface of the doped layer to form a surface etched doped layer (106) to reduce diffusion of the dopant to subsequent layers.

2. The method as claimed in claim 1, wherein the method comprises supplying fourth precursors with the carrier gas to form a second layer (108) to obtain the semiconductor stack (100).

3. The method as claimed in claim 1, wherein the first layer (104) comprises a plurality of first sub-layers, wherein the method comprises: for each sub-layer, supplying sub-layer precursors with the carrier gas to form that sub-layer.

4. The method as claimed in claim 1, wherein the second layer (108) comprises a plurality of second sub-layers, wherein the method comprises: for each sub-layer, supplying sub-layer precursors with the carrier gas to form that sub-layer.

5. The method as claimed in claim 1, wherein the carrier gas is selected from hydrogen, nitrogen, or combination thereof.

6. The method as claimed in claim 3, wherein the plurality of first sub -layers are

AIN layer, an AlGaN layer, and an AIN.

7. The method as claimed in claim 4, wherein the plurality of second sub-layers are silicon doped GaN, unintentionally doped layer, AIN, AhsGaysN, and GaN.

8. The method as claimed in claim 1, wherein the method comprises maintaining temperature in the reactor during fabrication of the stack in a range of 700 - 1400°C.

9. The method as claimed in claim 1, wherein the dopant is a p-type dopant or an n-type dopant.

10. The method as claimed in claim 9, wherein the p-type dopant is magnesium or iron.

11. The method as claimed in claim 1, wherein the intrinsic semiconductor is gallium nitride.

12. The method as claimed in claim 1, wherein the method comprises maintaining pressure in the reactor during fabrication of the stack in a range of 20 mbar to 500 mbar.

13. A semiconductor stack (100) fabricated by the method as claimed in any one of the preceding claims, the semiconductor stack (100) comprising: a substrate (102); a first layer (104) provided on the substrate (102); a surface etched doped layer (106) provided on the first layer (104), wherein the surface etched doped layer (106) is formed by removing a top surface of a doped layer; and a second layer (108) provided on the surface etched doped layer.