WO2021042377A1

WO2021042377A1 - Integrated device and manufacturing method therefor

Info

Publication number: WO2021042377A1
Application number: PCT/CN2019/104733
Authority: WO
Inventors: 陆斌; 沈健
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2019-09-06
Filing date: 2019-09-06
Publication date: 2021-03-11
Also published as: CN111095544B; CN111095544A

Abstract

Provided are an integrated device and a manufacturing method therefor. The integrated device comprises: a substrate, the upper surface of the substrate being provided with at least one first bonding pad; a silicon layer, the silicon layer being provided above the substrate, the silicon layer being provided with at least one conductive structure, and the at least one conductive structure separately corresponding to the at least one first bonding pad; and a first insulating layer, the first insulating layer being provided above the silicon layer, a first wiring layer being provided in the first insulating layer, and the at least one first bonding pad being connected to the first wiring layer separately by means of the at least one conductive structure. On the basis of the technical solution, the thickness and the cost of the integrated device can be effectively reduced.

Description

Integrated device and preparation method thereof

Technical field

The embodiments of the present application relate to the field of chip packaging, and more specifically, to an integrated device and a manufacturing method thereof.

Background technique

At present, the 2.5-dimensional (Dimensions, D) silicon/glass interposer is an important advanced packaging structure in the post-Moore era.

Specifically, as shown in FIG. 1, the 2.5D interposer 120 selects silicon wafer or glass as the substrate, and first uses a wafer process to fabricate a redistribution layer (RDL) on both surfaces of the substrate 121, and then plating Copper through silicon vias (Through Si Vias, TSV) or through glass vias (Through Glass Via, TGV) 122 realize the vertical transmission of electrical signals from the wiring layer 123 on the front side of the interposer to the wiring layer 124 on the back side.

During the packaging process, the chip 130 is packaged on the substrate 110 through the 2.5D interposer 120 in the form of an inverted pile. For example, the 2.5D interposer board 120 and the chip 130 are connected by micro bumps or solder balls with a smaller pitch; at the same time, the 2.5D interposer board 120 and the substrate 110 are connected by bumps or solder balls with a larger pitch. The ball is connected.

However, because the 2.5D transfer board 120 not only needs to integrate TSV/TGV, copper plating, metal planarization, wafer thinning, rewiring, fine-pitch copper bumps, high-precision chip bonding and other complete sets of manufacturing processes, but also installation The process is complicated, which increases the cost. Moreover, the thickness of the product 100 formed based on the 2.5D adapter plate 120 is too large.

Summary of the invention

An integrated device and a preparation method thereof are provided, which can reduce the cost and thickness of the integrated device.

In the first aspect, an integrated device is provided, including:

A substrate, the upper surface of the substrate is provided with at least one first pad;

A silicon layer, the silicon layer is provided above the substrate, the silicon layer is provided with at least one conductive structure, and the at least one conductive structure respectively corresponds to the at least one first pad;

A first insulating layer, the first insulating layer is disposed above the silicon layer, a first wiring layer is disposed in the first insulating layer, and the at least one first pad passes through the at least one conductive structure respectively Connected to the first wiring layer.

By disposing a silicon layer on the upper surface of the substrate and disposing at least one conductive structure corresponding to the at least one first pad in the silicon layer, not only can vertical and horizontal high-density metal interconnections be realized, And can avoid the use of 2.5D adapter board. Compared with the 2.5D interposer board, the preparation process of the integrated device and the integration process of integrating the chip to be integrated into the integrated device are simple, which can not only reduce the cost of the integrated device, but also reduce the overall size of the integrated device. thickness.

At the same time, supporting the first wiring layer by the silicon layer can alleviate the thermal expansion coefficient difference between the substrate and the chip to be integrated as much as possible, thereby improving the performance of the integrated device.

In addition, by supporting the first wiring layer by the silicon layer, passive devices such as capacitors can be integrated in the silicon layer to improve the performance of the integrated device.

In some possible implementation manners, the silicon layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, and a microcrystalline silicon layer.

In some possible implementation manners, the silicon layer is a deposition layer deposited on the substrate.

In some possible implementation manners, the silicon layer is formed with at least one through hole corresponding to the at least one first pad, wherein the first wiring layer extends into the at least one through hole, and Are respectively connected to the at least one first pad to form the at least one conductive structure.

In some possible implementation manners, the first insulating layer and the first wiring layer both extend into the first through hole in the at least one through hole, and the first wiring in the first through hole The layer is located outside the first insulating layer in the first through hole.

In some possible implementation manners, a conductive pillar is provided in a second through hole of the at least one through hole, and the first wiring layer is connected to the conductive pillar.

In some possible implementation manners, the aperture of each through hole of the at least one through hole close to the first insulating layer is larger than the aperture of the same through hole close to the substrate.

In some possible implementation manners, the integrated device further includes:

Second insulating layer

Wherein, the second insulating layer is disposed between the silicon layer and the first insulating layer, and extends to the inner wall of each through hole of the at least one through hole.

In some possible implementation manners, the silicon layer is formed with at least one conductive region corresponding to the at least one first pad, wherein the resistivity of each conductive region in the at least one conductive region is less than or equal to a predetermined value. A threshold is set to form the at least one conductive structure.

The third insulating layer;

Wherein, the silicon layer is formed with a concave ring penetrating the silicon layer around the at least one conductive area, and the third insulating layer is disposed between the silicon layer and the first insulating layer and extends Into the concave ring, the third insulating layer is formed with a through hole corresponding to each conductive area in the at least one conductive area, and each conductive area in the at least one conductive area passes through the third insulating layer The through holes corresponding to the same conductive area on the upper side are connected to the first wiring layer.

The fourth insulating layer;

Wherein, the fourth insulating layer is disposed between the substrate and the silicon layer, and the fourth insulating layer is formed with a through hole corresponding to each first pad of the at least one first pad, Each first pad of the at least one first pad is connected to a conductive structure corresponding to the same first pad through a through hole corresponding to the same first pad on the fourth insulating layer.

The fifth insulating layer;

Wherein, the fifth insulating layer is disposed between the silicon layer and the substrate, a second wiring layer is disposed in the fifth insulating layer, and at least one conductive structure of the silicon layer passes through the second The wiring layer is connected to the at least one first pad.

In some possible implementation manners, the line width of the wiring in the second wiring layer is greater than the line width of the wiring in the first wiring layer, and/or the spacing of the wiring in the second wiring layer is greater than that of the first wiring layer. The pitch of wiring in a wiring layer.

In some possible implementation manners, the silicon layer includes a plurality of silicon layer units, and the first insulating layer extends to a surrounding area of each silicon layer unit of the plurality of silicon layer units.

In some possible implementation manners, each silicon layer unit of the plurality of silicon layer units is provided with at least one conductive structure.

In some possible implementation manners, passive devices are formed in the silicon layer.

In some possible implementations, the passive device includes a capacitor.

A chip, the chip is arranged above the first insulating layer, at least one second pad is arranged on a side of the chip close to the first wiring layer, and the at least one second pad is respectively connected to the Mentioned first wiring layer.

In some possible implementation manners, the first wiring layer is provided with at least one link pad corresponding to the at least one second pad on a side close to the chip, and the first wiring layer is close to the chip. One side of the silicon layer is provided with at least one link pad corresponding to the at least one first pad, wherein the distance between the connection pads provided on the side close to the chip of the first wiring layer is smaller than the distance between the connection pads. The pitch of the connection pads provided on the side of the first wiring layer close to the silicon layer.

In the second aspect, a method for preparing an integrated device is provided, including:

Forming a silicon layer on the upper surface of the substrate, and at least one first pad is provided on the upper surface of the substrate;

Forming at least one conductive structure of the silicon layer, the at least one conductive structure respectively corresponding to the at least one first pad;

Forming a first insulating layer above the silicon layer;

Wherein, a first wiring layer is provided in the first insulating layer, and the at least one first pad is respectively connected to the first wiring layer through the at least one conductive structure.

In some possible implementation manners, the forming a silicon layer on the upper surface of the substrate includes:

The silicon layer is deposited on the substrate.

In some possible implementation manners, the at least one conductive structure forming the silicon layer includes:

Forming at least one through hole of the silicon layer, the at least one through hole respectively corresponding to the at least one first pad; wherein the forming a first insulating layer above the silicon layer includes:

A first insulating layer is formed above the silicon layer, and the first wiring layer respectively extends into the at least one through hole and is respectively connected to the at least one first pad to form the at least one conductive pad. structure.

In some possible implementation manners, the forming a first insulating layer on the silicon layer includes:

Forming a second insulating layer above the silicon layer and the inner wall of each of the at least one through hole;

The first insulating layer is formed on the second insulating layer.

At least one conductive region of the silicon layer is formed, and the at least one conductive region respectively corresponds to the at least one first pad, wherein the resistivity of each conductive region in the at least one conductive region is less than or equal to a preset threshold , To form the at least one conductive structure.

Forming a concave ring penetrating the silicon layer around each of the at least one conductive area;

Forming a third insulating layer between the silicon layer and the first insulating layer and in the concave ring;

Forming a through hole corresponding to each conductive region of the at least one conductive region of the third insulating layer;

The first insulating layer is formed on the third insulating layer, and each conductive area of the at least one conductive area is connected to the first insulating layer through a through hole corresponding to the same conductive area on the third insulating layer. Wiring layer.

Forming a fourth insulating layer above the substrate;

Forming a through hole corresponding to each first pad of the at least one first pad of the fourth insulating layer;

The silicon layer is formed above the fourth insulating layer, and each first pad of the at least one first pad is connected through a through hole corresponding to the same first pad on the fourth insulating layer To the conductive structure corresponding to the same first pad.

Forming a fifth insulating layer on the substrate, and a second wiring layer is provided in the fifth insulating layer;

The silicon layer is provided on the fifth insulating layer, and at least one conductive structure of the silicon layer is respectively connected to the at least one first pad through the second wiring layer.

Dividing the silicon layer into a plurality of silicon layer units;

The first insulating layer is formed above the plurality of silicon layer units and a surrounding area of each silicon layer unit of the plurality of silicon layer units.

In some possible implementations, the passive device includes a capacitor.

In some possible implementation manners, the method further includes:

Disposing a chip above the first insulating layer;

Wherein, at least one second pad is provided on a side of the chip close to the first wiring layer, and the at least one second pad is respectively connected to the first wiring layer.

In a third aspect, an integrated device is provided, including:

An integrated device prepared according to the method described in the second aspect and any possible implementation manner in the second aspect.

Description of the drawings

Figure 1 is an example of an existing chip mounting solution.

Fig. 2 is a schematic structural diagram of an integrated device according to an embodiment of the present application.

3 to 6 are schematic diagrams of the deformed structure of the integrated device shown in FIG. 2.

Fig. 7 is a schematic flow chart of preparing an integrated device according to an embodiment of the present application.

8 to 14 are respectively schematic diagrams of structures formed in various stages in the process of preparing the integrated device shown in FIG. 2 in an embodiment of the present application.

15 to 18 are schematic diagrams of the structures formed at various stages in the process of preparing the integrated device shown in FIG. 3 according to the embodiments of the present application.

detailed description

The integrated device of the present application and its preparation method will be described in detail below with reference to the drawings.

It should be understood that the integrated device involved in this application can be applied to various electronic devices. For example, portable or mobile computing devices such as smartphones, notebook computers, tablet computers, and gaming devices, as well as other electronic devices such as electronic databases, automobiles, and bank automated teller machines (ATM).

It should be noted that, for ease of description, in the embodiments of the present application, the same reference numerals denote the same components, and for brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length and width of the various components in the embodiments of the application shown in the drawings, as well as the overall thickness, length and width of the integrated device, are only exemplary descriptions, and should not constitute any limitation to the application. .

In addition, for ease of understanding, in the embodiments shown below, for the structures shown in different embodiments, the same structures are given the same reference numerals, and for the sake of brevity, detailed descriptions of the same structures are omitted.

As shown in FIG. 2, the integrated device 200 may include a substrate 210, a silicon layer 220 located above the substrate 210, and a first insulating layer 230 located above the silicon layer 220.

Wherein, the upper surface of the substrate 210 may be provided with at least one first pad, and the silicon layer 220 may be provided with at least one conductive structure, and the at least one conductive structure corresponds to the at least one first pad. A first wiring layer 231 is provided in the first insulating layer 230, and the at least one first pad is respectively connected to the first wiring layer through the at least one conductive structure.

In other words, the integrated device 200 may include a substrate 210, a silicon layer 220 located above the substrate 210, a first insulating layer 230 located above the silicon layer 220, and a first wiring layer 231 located in the first insulating layer 230, The silicon layer 220 is used to support the first wiring layer 231, and the first insulating layer 230 is used to protect and insulate the first wiring layer 231. The first wiring layer 231 is respectively connected to at least one first pad of the substrate 210 through at least one conductive structure in the silicon layer 220, so as to realize electrical signals from the first wiring layer 231 to the substrate. Vertical transfer between at least one first pad on 210.

By disposing the silicon layer 220 on the upper surface of the substrate 210 and disposing at least one conductive structure corresponding to the at least one first pad in the silicon layer 220, it is not only possible to realize high-density metal in the vertical and horizontal directions. Interconnect, and can avoid the use of 2.5D transfer board. Compared with the 2.5D interposer board, the preparation process of the integrated device and the integration process of integrating the chip to be integrated into the integrated device are simple, which not only can reduce the cost of the integrated device 200, but also can reduce the integrated device 200 The overall thickness.

At the same time, the first wiring layer 231 is supported by the silicon layer 220, which can alleviate the thermal expansion coefficient difference between the substrate 210 and the chip to be integrated as much as possible, thereby improving the performance of the integrated device 200.

In addition, the first wiring layer 231 is supported by the silicon layer 220, and passive devices such as capacitors can be integrated in the silicon layer 220 to improve the performance of the integrated device 200.

It should be understood that the substrate 210 can provide electrical connection, protection, support, heat dissipation, assembly and other functions for various chips, so as to achieve multi-pin, reduce the size of packaged products, improve electrical performance and heat dissipation, ultra-high density or more. The purpose of chip modularization.

For example, the substrate 210 may be various types of flexible or rigid, organic or inorganic substrates used in various packaging technologies. The material of the substrate 210 includes, but is not limited to, organic materials such as quartz, glass, ceramics, and various resins. The organic substrate may also include fillers such as glass fibers and silicon oxide balls, such as FR4 substrates, and Bismaleimide-Triazine (BT) resin substrates. Among them, FR4 is a code for the grade of flame-resistant materials.

The at least one first pad of the substrate 210 may be a pad (Pad) that may have been prepared on one surface before entering the integration process flow, or may be a pad prepared after entering the integration process flow. The upper surface of the substrate 210 may be the surface on which the pads have been prepared, or in other words, the surface opposite to the lower surface of the silicon layer 220 is the upper surface of the substrate 210.

With reference to FIG. 2, the substrate 210 may include three pads 211, and each pad 211 may be connected to an internal circuit in the substrate 210.

The silicon layer 220 may be a polycrystalline silicon layer, an amorphous silicon layer or a microcrystalline silicon layer, or a material layer formed of a mixed material including silicon. The silicon layer 220 may be deposited on the substrate 210. Floor. For example, the symmetry 220 may be a deposition layer formed of a mixed material including polysilicon or amorphous silicon.

The first insulating layer 230 may be a material layer or a deposited layer formed of any material having insulating properties. For example, the material of the first insulating layer 230 may include, but is not limited to, silicon oxide, silicon nitride, silicon glass, spin-on glass (SOG), polyimide (PI) , Parylene, benzocyclobutene (BCB) and so on. Wherein, the silicon glass includes, but is not limited to, Undoped Silicon Glass (USG), Boro-silicate glass (BSG), phospho-silicate glass (PSG), and borophosphosilicate glass (PSG). Glass (Boro-phospho-silicate glass, BPSG). For another example, the material of the first insulating layer 230 may also be some inorganic materials, such as silicon oxide synthesized from Tetraethyl Orth Silicate (TEOS), silicon oxide, nitride, and ceramic. For another example, the first insulating layer 230 may be a stacked layer of the above-mentioned materials, or the first insulating layer may be a material layer formed of a mixed material of the above-mentioned materials.

The first wiring layer 231 may include a connection pad for at least one pad of the substrate 210, a wiring connected with a connection pad for at least one pad of the substrate 210, and a connection pad for a chip to be integrated . Wherein, the lower surface of the first insulating layer 230 exposes connection pads respectively directed to at least one pad of the substrate 210, and the upper surface of the first insulating layer 230 exposes at least one contact pad respectively directed to the substrate 210. The connection pad of the pad.

Optionally, in some embodiments of the present application, the first wiring layer 231 may pass through the silicon layer 220 and be connected to at least one first pad of the substrate 210.

For example, as shown in FIG. 2, the silicon layer 220 may be formed with at least one through hole corresponding to the at least one first pad, wherein the first wiring layer 231 extends to the at least one through hole, respectively , And are respectively connected to at least one first pad on the substrate 210 to form at least one conductive structure of the silicon layer 220.

In other words, the silicon layer 220 respectively forms at least one through hole above the at least one first pad, and the at least one through hole is used to provide a receiving space for the first wiring layer 231 so that the first The wiring layer 231 can be connected to the at least one first pad. The at least one through hole and the first wiring layer 231 in the through hole may be used to form the at least one conductive structure, and the at least one conductive structure is used to connect the first wiring layer 231 to the substrate 210 Of at least one first pad.

As an example, the first insulating layer 230 and the first wiring layer 231 both extend into the first through hole in the at least one through hole, and the first wiring layer 231 in the first through hole The outer side of the first insulating layer 230 located in the first through hole.

In other words, the first wiring layer 231 is located on the inner wall of the first through hole and is connected to at least one first pad of the substrate 210, and the first insulating layer 230 fills the first through hole The area surrounded by the first wiring layer 231.

With reference to FIG. 2, the first through hole may be the leftmost through hole on the silicon layer 220.

As another example, a conductive pillar is disposed in the second through hole of the at least one through hole, and the first wiring layer 231 is connected to the conductive pillar.

In other words, the second through hole can be filled with the same conductive material as the first wiring layer 231, and the first wiring layer 231 is connected to the conductive material in the second through hole, thereby forming the The conductive structure of the silicon layer 220 is described.

With reference to FIG. 2, the second through hole may be the rightmost through hole on the silicon layer 220.

Of course, it is also possible to extend the first wiring layer 231 into the second through hole of the at least one through hole and fill the second through hole to form the conductive structure of the silicon layer 220. The application does not make specific restrictions on this.

It should be understood that the at least one through hole may include at least one first through hole and/or at least one second through hole, which is not specifically limited in this application.

Optionally, in some embodiments of the present application, each of the at least one through hole is an axisymmetric through hole. For example, the hole diameter of each of the at least one through hole close to the first insulating layer is larger than the hole diameter of the same through hole close to the substrate, so that the first insulating layer 230 or The first wiring layer 231 extends into the through hole.

With reference to FIG. 2, each of the at least one through hole may be a topped inverted cone structure. It should be understood that in other alternative embodiments, each of the at least one through hole may also be a through hole of other shapes, such as an inverted trapezoidal through hole.

As shown in FIG. 2, in some embodiments of the present application, the integrated device 200 may further include a second insulating layer 240 to protect and insulate the first wiring layer 231.

For example, the second insulating layer 240 is disposed between the silicon layer 220 and the first insulating layer 230 and extends to the inner wall of each through hole of the at least one through hole.

In other words, the second insulating layer 240 only covers the upper surface of the silicon layer 220 and the inner wall of each of the at least one through hole, so that the first wiring layer 231 can pass through the second The insulating layer 230 is connected to at least one first pad on the substrate 210.

It should be understood that the material of the second insulating layer 240 may be the same as or different from the material of the first insulating layer 230, which is not specifically limited in this application.

As shown in FIG. 2, in some embodiments of the present application, the integrated device 200 may further include a fourth insulating layer 250 to protect and insulate the substrate 210.

For example, the fourth insulating layer 250 may be disposed between the substrate 210 and the silicon layer 220, and the fourth insulating layer 250 may be formed with each of the at least one first pad. The through hole corresponding to the disk, so that each first pad of the at least one first pad is connected to the corresponding first pad through the through hole corresponding to the same first pad on the fourth insulating layer 250 The conductive structure.

In other words, the fourth insulating layer 250 may be disposed between the substrate 210 and the silicon layer 220, and through holes are respectively formed above at least one first pad of the base 210, so that the The first wiring layer 231 can pass through the fourth insulating layer 250 and be connected to the at least one first pad.

It should be understood that the material of the fourth insulating layer 250 may be the same as or different from the material of the first insulating layer 230, which is not specifically limited in this application.

As shown in FIG. 2, in some embodiments of the present application, the integrated device 200 may further include a chip 260, and the chip 260 may be used to process and/or transmit and receive signals.

For example, the chip 260 may be disposed above the first insulating layer 230, at least one second pad is disposed on the side of the chip 260 close to the first wiring layer 231, and the at least one second solder The pads are connected to the first wiring layer 231, respectively.

In other words, the chip 260 can be connected to the substrate 210 through the first wiring layer 231, avoiding the use of an interposer, which not only reduces the process complexity, but also reduces the thickness of the integrated device 200.

It should be understood that the chip 260 may be a chip of any type or specification. For example, the chip 260 may be a special chip or a security chip for executing complex encryption and decryption algorithms. Wherein, the security chip may be a chip provided with a circuit (such as a processor), various types of chips in the Internet of Things field, and so on. For example, the chip 260 may include elements such as transistors, resistors, capacitors, and inductors, and wiring devices or components. For example, the chip 260 may be a micro electronic device or component carrying an integrated circuit.

Optionally, in some embodiments of the present application, the first wiring layer 231 is provided with at least one link pad corresponding to the at least one second pad on a side close to the chip 260, and the The first wiring layer 231 is provided with at least one link pad corresponding to the at least one first pad on the side close to the silicon layer 220, wherein the first wiring layer 231 is close to the chip 260 The pitch of the connection pads provided on one side is smaller than the pitch of the connection pads provided on the side of the first wiring layer 231 close to the silicon layer 220.

Wherein, at least one second pad of the chip 260 may be connected to the connection pad of the first wiring layer 231 through a solder ball or other connecting components. At least one chip 260 may be disposed above the first insulating layer 230.

With reference to FIG. 2, three chips 260 are provided above the first insulating layer, and a total of 9 pads 261 are provided on the three chips 260. At this time, the first wiring layer 231 is provided with nine connection pads on the side close to the three chips 260 to connect to the nine pads 261 respectively, and the first wiring layer 231 is close to Three connection pads are provided on one side of the silicon layer 220 to connect to the three pads 211 of the substrate 210 respectively.

Of course, in other alternative embodiments, the distance between the connecting pads of the first wiring layer 231 on the side close to the chip 260 may also be greater than or equal to that of the first wiring layer 231 close to the silicon. The pitch of the connection pads provided on one side of the layer 220.

FIG. 3 is a schematic diagram of a modified structure of the integrated device 200 shown in FIG. 2.

As shown in FIG. 3, in some embodiments of the present application, the silicon layer 220 may be formed with at least one conductive region corresponding to the at least one first pad, wherein each of the at least one conductive region The resistivity of the conductive region is less than or equal to a preset threshold to form the at least one conductive structure. For example, each conductive region in the at least one conductive region may be a columnar conductive region 225.

In other words, the silicon layer 220 may respectively form at least one conductive area above the at least one first pad of the substrate 210, and the at least one conductive area is used as the at least one conductive structure. The at least one first pad may be electrically connected to the first wiring layer 231 through the silicon layer 220.

It should be understood that in other alternative implementation manners, each conductive region in the at least one conductive region may also be a conductive region of other shapes, which is not specifically limited in this application.

As shown in FIG. 3, in some embodiments of the present application, the integrated device 200 further includes a third insulating layer 241 to protect and insulate the first wiring layer 231.

For example, the silicon layer 220 is formed with a concave ring penetrating through the silicon layer 220 around the at least one conductive region, and the third insulating layer 241 is disposed on the silicon layer 220 and the first insulating layer 230 Between and extending into the concave ring, the third insulating layer 241 is formed with a through hole corresponding to each conductive region in the at least one conductive region, and each conductive region in the at least one conductive region passes through The through holes corresponding to the same conductive area on the third insulating layer 241 are connected to the first wiring layer 231.

In other words, the third insulating layer 241 is formed with a through hole above each of the at least one conductive area, so that the first wiring layer 231 can pass through the third insulating layer 241 to connect to The at least one conductive area.

FIG. 4 is a schematic diagram of another modified structure of the integrated device 200 shown in FIG. 2.

As shown in FIG. 4, in some embodiments of the present application, the integrated device 200 may further include a fifth insulating layer, so as to be provided on the substrate 210 for connecting the first wiring layer 231 to the substrate. The second wiring layer of at least one pad of 210.

For example, the fifth insulating layer may be disposed between the silicon layer 220 and the substrate 210, a second wiring layer is disposed in the fifth insulating layer, and at least one conductive structure of the silicon layer 220 may pass through The second wiring layer is connected to the at least one first pad.

Optionally, in some embodiments of the present application, the line width of the wiring in the second wiring layer 271 is greater than the line width of the wiring in the first wiring layer 231, and/or, the second wiring layer 271 The pitch of the middle wiring is greater than the pitch of the wiring in the first wiring layer 231 to increase the utilization rate of the wiring in the second wiring layer 271.

In other words, the RDL layer is located on the upper surface and the lower surface of the silicon layer 220. Wherein, the line width and/or line pitch of the first wiring layer on the upper surface is relatively large, which is used to match the thick-pitch metal wiring on the substrate 210; the line width and/or line pitch of the second wiring layer on the lower surface is relatively large. Small, used to match the fine pitch metal traces on the chip 260.

FIG. 5 is a schematic diagram of another modified structure of the integrated device 200 described in FIG. 2.

As shown in FIG. 5, in some embodiments of the present application, the silicon layer 220 may be divided into a plurality of independent silicon layer units, so as to avoid that the silicon layer 220 is in a higher temperature process due to The problem of cracking of the silicon layer caused by the mismatch of thermal expansion coefficient.

In other words, the silicon layer 220 may include a plurality of silicon layer units, and the first insulating layer 230 extends to a surrounding area of each of the plurality of silicon layer units. Optionally, each silicon layer unit of the plurality of silicon layer units is provided with at least one conductive structure, so as to realize the transmission of electrical signals in the vertical direction of each silicon layer unit.

Wherein, the plurality of silicon layer units may be distributed at equal intervals, or may be distributed at unequal intervals. The sizes of the multiple silicon layer units may be partly the same, or all of them may be the same, which is not specifically limited in this application. For example, the size of each silicon layer unit and the number of conductive structures can be set according to actual requirements.

With reference to FIG. 5, the multiple silicon layer units may include two silicon layer units 221. Among them, the silicon layer unit 221 on the left is provided with two conductive structures, and the silicon layer unit 221 on the right is provided with one conductive structure.

FIG. 6 is another schematic diagram of a modified structure of the integrated device 200 shown in FIG. 2.

As shown in FIG. 6, in some embodiments of the present application, a passive device 280 may be formed in the silicon layer 220 to shorten the distance between the passive device and the chip integrated on the integrated device 200 , Thereby improving the performance of the integrated device 200. For example, the passive device 280 includes a capacitor. Optionally, the capacitors may be arranged in a layered manner, so as to arrange a plurality of capacitors connected in parallel, thereby increasing the capacitance of the capacitors. Further, the dielectric layer or the conductive layer in the capacitor may be formed with a groove structure to increase the capacitance of the capacitor.

It should be understood that FIG. 2 to FIG. 6 are only examples of the present application, and should not be construed as a limitation to the present application.

For example, in other alternative embodiments, the second insulating layer 240 or the third insulating layer 241 may be directly omitted. That is, the first insulating layer 230 can be directly disposed on the upper surface of the silicon layer 220. For another example, the fourth insulating layer 250 can be omitted directly. That is, the silicon layer 220 can be directly disposed on the upper surface of the substrate 210.

For another example, under the premise of no conflict, the various embodiments described in this application and/or the technical features in each embodiment can be combined with each other arbitrarily, and the technical solutions obtained after the combination should also fall within the protection scope of this application. For example, passive devices may also be provided in the silicon layer 220 in the integrated device 200 shown in FIG. 3.

For another example, a connecting cable may also be provided in each of the at least one through hole of the silicon layer 220 to connect the first wiring layer 231 to the pad of the substrate 210.

FIG. 7 is a schematic flowchart of a method 300 for preparing an integrated device according to an embodiment of the present application.

As shown in FIG. 7, the method 300 may include:

S310: A silicon layer is formed on the upper surface of the substrate, and at least one first pad is provided on the upper surface of the substrate.

S320, forming at least one conductive structure of the silicon layer, the at least one conductive structure respectively corresponding to the at least one first pad.

S330, forming a first insulating layer on the silicon layer. Wherein, a first wiring layer is provided in the first insulating layer, and the at least one first pad is respectively connected to the first wiring layer through the at least one conductive structure.

In short, after the silicon layer is formed on the substrate, the first insulating layer is formed on the silicon layer. Wherein, a first wiring layer is provided in the first insulating layer, and the silicon layer is used to support the first wiring layer. The silicon layer is provided with at least one conductive structure, whereby the first wiring layer can be connected to at least one first pad of the substrate through the at least one conductive structure, thereby realizing the transmission of electrical signals in the vertical direction .

In some embodiments of the present application, the silicon layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, and a microcrystalline silicon layer.

In some embodiments of the present application, the S310 may include:

The silicon layer is deposited on the substrate.

In some embodiments of the present application, the S320 may include:

Forming at least one through hole of the silicon layer, the at least one through hole respectively corresponding to the at least one first pad; wherein, the S330 may include:

The first insulating layer is formed above the silicon layer, and the first wiring layer respectively extends into the at least one through hole and is respectively connected to the at least one first pad to form the at least one A conductive structure.

In some embodiments of the present application, both the first insulating layer and the first wiring layer extend into the first through hole in the at least one through hole, and the first through hole in the first through hole The wiring layer is located outside the first insulating layer in the first through hole.

In some embodiments of the present application, a conductive pillar is provided in a second through hole of the at least one through hole, and the first wiring layer is connected to the conductive pillar.

In some embodiments of the present application, the hole diameter of each of the at least one through hole close to the first insulating layer is larger than the hole diameter of the same through hole close to the substrate.

In some embodiments of the present application, the S330 may include:

A second insulating layer is formed above the silicon layer and the inner wall of each of the at least one through hole; and the first insulating layer is formed above the second insulating layer.

In some embodiments of the present application, the S320 may include:

In some embodiments of the present application, the S330 may include:

A concave ring penetrating through the silicon layer is formed around each of the at least one conductive area; a third insulation is formed between the silicon layer and the first insulating layer and in the concave ring Layer; forming a through hole corresponding to each conductive region in the at least one conductive region of the third insulating layer; forming the first insulating layer on the third insulating layer, in the at least one conductive region Each conductive area of is connected to the first wiring layer through a through hole corresponding to the same conductive area on the third insulating layer.

In some embodiments of the present application, the S320 may include:

A fourth insulating layer is formed above the substrate; a through hole corresponding to each first pad of the at least one first pad forming the fourth insulating layer; above the fourth insulating layer The silicon layer is formed, and each first pad of the at least one first pad is connected to a conductive pad corresponding to the same first pad through a through hole corresponding to the same first pad on the fourth insulating layer. structure.

In some embodiments of the present application, the S320 may include:

A fifth insulating layer is formed on the substrate, and a second wiring layer is arranged in the fifth insulating layer; the silicon layer is arranged on the fifth insulating layer, and at least one conductive structure of the silicon layer passes through The second wiring layer is connected to the at least one first pad.

In some embodiments of the present application, the line width of the wiring in the second wiring layer is greater than the line width of the wiring in the first wiring layer, and/or the spacing of the wiring in the second wiring layer is greater than the line width of the wiring in the second wiring layer. The pitch of the wiring in the first wiring layer.

In some embodiments of the present application, the S330 may include:

The silicon layer is divided into a plurality of silicon layer units; the first insulating layer is formed above the plurality of silicon layer units and the surrounding area of each of the plurality of silicon layer units.

In some embodiments of the present application, each silicon layer unit of the plurality of silicon layer units is provided with at least one conductive structure.

In some embodiments of the present application, passive devices are formed in the silicon layer.

In some embodiments of the present application, the passive device includes a capacitor.

In some embodiments of the present application, the method 300 may further include:

A chip is provided above the first insulating layer; wherein at least one second pad is provided on a side of the chip close to the first wiring layer, and the at least one second pad is respectively connected to the first A wiring layer.

In some embodiments of the present application, the first wiring layer is provided with at least one link pad corresponding to the at least one second pad on a side close to the chip, and the first wiring layer is close to the chip. One side of the silicon layer is provided with at least one link pad corresponding to the at least one first pad, wherein the distance between the connection pads provided on the side close to the chip of the first wiring layer is smaller than The pitch of the connection pads provided on the side of the first wiring layer close to the silicon layer.

It should be understood that the method embodiment and the product embodiment may correspond to each other, and similar descriptions may refer to the product embodiment. For the sake of brevity, I will not repeat them here.

It should also be understood that the method 300 may be executed by a robot or a numerical control processing method, and the device software or process used to execute the method 300 may execute the method 300 by executing computer program codes stored in a memory.

It should also be understood that, in the various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not be implemented in this application. The implementation process of the example constitutes any limitation.

8 to 14 are respectively schematic diagrams of structures formed in various stages in the process of preparing the integrated device shown in FIG. 2 in an embodiment of the present application. The preparation method of the integrated device 200 shown in FIG. 2 will be described below in conjunction with FIG. 8 to FIG. 14.

step one:

Select the substrate where the chip needs to be soldered. For example, the substrate 210 shown in FIG. 8.

Wherein, the substrate 210 may be a glass, ceramic or organic substrate. The organic substrate may include fillers such as resin, glass fiber, and silica balls. At least one pad 211 is provided on the upper surface of the substrate 210.

Step two:

Using a deposition process, a fourth insulating layer 250 is deposited on the upper surface of the substrate 210 (that is, the side where the pads are provided), and then a silicon layer 220 is deposited on the upper surface of the fourth insulating layer 250 to form a pattern. 9 shows the structure.

Wherein, the insulating layer can be made of silicon oxide, silicon nitride, silicon glass (such as USG, BSG, PSG or BPSG), or can be coated spin-on-glass (SOG), polyimide ( PI), Parylene, benzocyclobutene (BCB), etc.

It should be noted that the fourth insulating layer 250 can also be omitted. That is, the silicon layer 220 is directly deposited on the upper surface of the substrate 210 by using a deposition process.

Step three:

Using a photolithography process combined with a dry etching process (or a laser drilling process), at least one through hole is formed on the silicon layer 220. The bottom of the at least one through hole stays on the upper surface of the fourth insulating layer 250 to form the structure shown in FIG. 10.

Of course, the bottom of the at least one through hole can also stay on the at least one pad of the substrate 210.

Step 4:

Using a deposition process, a second insulating layer 240 is first deposited on the inner sidewall of the at least one through hole of the silicon layer 220 and the upper surface of the silicon layer 220. Then, an etching process is used to remove the second insulating layer 240 (and the fourth insulating layer 250) at the bottom of the at least one through hole to expose the pad 211 of the substrate 210. Finally, a deposition process is used to A metal layer 232 is deposited on the upper surface of the second insulating layer 240 and the bottom of the at least one through hole (that is, on the at least one first pad of the substrate 210, for example, the two through holes on the leftmost side in FIG. 11) , To form the structure shown in Figure 11.

Of course, it is also possible to use a deposition process to fill the at least one through hole with conductive materials such as Cu and W, and then on the upper surface of the second insulating layer 240 and the upper surface of the conductive material (for example, FIG. 11 The metal layer 232 is deposited on the right-most via hole in ).

Step Five:

Using photolithography combined with an etching (or etching) process, the metal layer 232 above the second insulating layer 240 is patterned to form a connection pad 233 in the first wiring layer for the substrate 210, thereby forming FIG. 12 The structure shown.

Step Six:

On the second insulating layer 240 and the connection pad 233, a wiring connected to the connection pad 233 of the substrate 210, a connection pad for a chip and a first insulating layer connected to the wiring are made 230. The first wiring layer 231 is formed for the connection pads 233 of the substrate 210, the connection pads for the chip, and the wiring between the connection pads 233 of the substrate 210 and the connection pads for the chip. The wiring layer 231 is disposed inside the first insulating layer 230 to form the structure described in FIG. 13.

Step Seven:

The chip 260 with the micro bumps is soldered to the connection pad of the first wiring layer 231 for the chip 260. For example, the chip 260 with long micro bumps is soldered to the connection pad of the first wiring layer 231 for the chip 260 through a solder ball to form the structure shown in FIG. 14.

15 to 18 are schematic diagrams of the structures formed at various stages in the process of preparing the integrated device shown in FIG. 3 according to the embodiments of the present application. The preparation method of the integrated device 200 shown in FIG. 3 will be described below in conjunction with FIG. 15 to FIG. 18.

step one:

After the substrate 210 is selected, a deposition process is used to deposit a silicon layer 220 on the upper surface of the substrate 210, and then doped by local ion implantation and laser annealing to form a conductive area above each pad 211 of the substrate 210 225, further forming the structure shown in FIG. 15.

Step two:

Using a photolithography process combined with an etching process, a concave ring (or gap) penetrating through the silicon layer 220 is formed around each conductive area 225, and then a deposition process is used to form the upper surface of the silicon layer 220 and the concave ring A third insulating layer 241 is deposited in the ring to form the structure described in FIG. 16.

Step three:

Then, an etching process is used to form an opening of the third insulating layer 241 above each conductive area 225, and a connection pad for the substrate 210 and a connection pad for the substrate 210 are formed on the pad 211 of the substrate 210. The wiring connected to the connection pad 233 of the substrate 210 and the connection pad for the chip connected to the wiring, and a first insulating layer 230 is prepared on the third insulating layer 241. The first wiring layer 231 is formed for the connection pads of the substrate 210, the connection pads for the chip, and the wiring between the connection pads of the substrate 210 and the connection pads for the chip. 231 is disposed inside the first insulating layer 230 to form the structure described in FIG. 17.

Step 4:

The chip 260 with the micro bumps is soldered to the connection pad of the first wiring layer 231 for the chip 260. For example, the chip 260 with long micro bumps is soldered to the connection pad of the first wiring layer 231 for the chip 260 through a solder ball to form the structure shown in FIG. 18.

It should be understood that the etching process mentioned above may include at least one of the following processes:

Dry etching process, wet etching process and laser etching process.

Further, the dry etching process may include at least one of the following etching processes: reactive ion etching, ion beam etching, and the like. The chemical raw materials of the wet etching process may include, but are not limited to, an etching solution containing hydrofluoric acid. In some embodiments of the present application, the combination of dry etching and wet etching, or the combination of laser etching and wet etching, can effectively ensure the shape of the etching and the flatness of the bottom surface. Wait.

It should also be understood that the deposition processes mentioned above include but are not limited to:

Physical Vapor Deposition (PVD) process and/or Chemical Vapor Deposition (CVD) process. For example, thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.), atomic layer deposition (ALD) ), electroplating, spin coating or spraying.

It should also be understood that the preparation process (such as a deposition process or an etching process) involved in the embodiments of the present application is only an example, and should not be construed as a limitation of the present application. In other words, the processes capable of preparing integrated devices with the same or similar structure are all within the scope of protection of the present application.

A person of ordinary skill in the art may be aware that the preparation methods of the examples described in the embodiments disclosed in this specification can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In the several embodiments provided in this application, it should be understood that the disclosed integrated device, the components in the integrated device, and the method for preparing the integrated device may be implemented in other ways. For example, the integrated device embodiment described above is only exemplary. For example, the division of the layers is only a logical function division, and there may be other division methods in actual implementation. For example, multiple layers or devices can be combined or can be integrated. For another example, some features (such as the second insulating layer 240 or the third insulating layer 241) can be ignored or not prepared.

For example, in other alternative embodiments, the first insulating layer 230 and the second insulating layer 240 (or the third insulating layer 241) may be combined into one layer.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

An integrated device, characterized in that it comprises:

A substrate, the upper surface of the substrate is provided with at least one first pad;

A silicon layer, the silicon layer is provided above the substrate, the silicon layer is provided with at least one conductive structure, and the at least one conductive structure respectively corresponds to the at least one first pad;

A first insulating layer, the first insulating layer is disposed above the silicon layer, a first wiring layer is disposed in the first insulating layer, and the at least one first pad passes through the at least one conductive structure respectively Connected to the first wiring layer.
The integrated device according to claim 1, wherein the silicon layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, and a microcrystalline silicon layer.
The integrated device according to claim 1 or 2, wherein the silicon layer is a deposition layer deposited on the substrate.
The integrated device according to any one of claims 1 to 3, wherein the silicon layer is formed with at least one through hole corresponding to the at least one first pad, wherein the first wiring layer Respectively extend into the at least one through hole and respectively connect to the at least one first pad to form the at least one conductive structure.
The integrated device according to claim 4, wherein the first insulating layer and the first wiring layer both extend into the first through hole of the at least one through hole, and the first through hole The first wiring layer in the hole is located outside the first insulating layer in the first through hole.
The integrated device according to claim 4 or 5, wherein a conductive pillar is provided in a second through hole of the at least one through hole, and the first wiring layer is connected to the conductive pillar.
The integrated device according to any one of claims 4 to 6, wherein the aperture of each of the at least one through hole close to the opening of the first insulating layer is larger than that of the same through hole. The aperture of the opening of the substrate.
The integrated device according to any one of claims 4 to 7, wherein the integrated device further comprises:

Second insulating layer

Wherein, the second insulating layer is disposed between the silicon layer and the first insulating layer, and extends to the inner wall of each through hole of the at least one through hole.
The integrated device according to any one of claims 1 to 3, wherein the silicon layer is formed with at least one conductive area corresponding to the at least one first pad, wherein the at least one conductive area The resistivity of each conductive region is less than or equal to a preset threshold to form the at least one conductive structure.
The integrated device according to claim 9, wherein the integrated device further comprises:

The third insulating layer;

Wherein, the silicon layer is formed with a concave ring penetrating the silicon layer around the at least one conductive area, and the third insulating layer is disposed between the silicon layer and the first insulating layer and extends Into the concave ring, the third insulating layer is formed with a through hole corresponding to each conductive area in the at least one conductive area, and each conductive area in the at least one conductive area passes through the third insulating layer The through holes corresponding to the same conductive area on the upper side are connected to the first wiring layer.
The integrated device according to any one of claims 1 to 10, wherein the integrated device further comprises:

The fourth insulating layer;

Wherein, the fourth insulating layer is disposed between the substrate and the silicon layer, and the fourth insulating layer is formed with a through hole corresponding to each first pad of the at least one first pad, Each first pad of the at least one first pad is connected to a conductive structure corresponding to the same first pad through a through hole corresponding to the same first pad on the fourth insulating layer.
The integrated device according to any one of claims 1 to 11, wherein the integrated device further comprises:

The fifth insulating layer;

Wherein, the fifth insulating layer is disposed between the silicon layer and the substrate, a second wiring layer is disposed in the fifth insulating layer, and at least one conductive structure of the silicon layer passes through the second The wiring layer is connected to the at least one first pad.
The integrated device according to claim 12, wherein the line width of the wiring in the second wiring layer is greater than the line width of the wiring in the first wiring layer, and/or the wiring in the second wiring layer The pitch of is greater than the pitch of the wiring in the first wiring layer.
The integrated device according to any one of claims 1 to 13, wherein the silicon layer comprises a plurality of silicon layer units, and the first insulating layer extends to each of the plurality of silicon layer units The surrounding area of the silicon layer unit.
The integrated device according to claim 14, wherein each silicon layer unit of the plurality of silicon layer units is provided with at least one conductive structure.
The integrated device according to any one of claims 1 to 15, wherein a passive device is formed in the silicon layer.
The integrated device of claim 16, wherein the passive device comprises a capacitor.
The integrated device according to any one of claims 1 to 17, wherein the integrated device further comprises:

A chip, the chip is arranged above the first insulating layer, at least one second pad is arranged on a side of the chip close to the first wiring layer, and the at least one second pad is respectively connected to the Mentioned first wiring layer.
The integrated device according to claim 18, wherein the first wiring layer is provided with at least one link pad corresponding to the at least one second pad on a side close to the chip, and the first wiring layer is A wiring layer is provided with at least one link pad corresponding to the at least one first pad on the side close to the silicon layer, wherein the first wiring layer is connected to the side close to the chip. The pitch of the pads is smaller than the pitch of the connection pads provided on the side of the first wiring layer close to the silicon layer.
A method for preparing an integrated device, characterized in that it comprises:

Forming a silicon layer on the upper surface of the substrate, and at least one first pad is provided on the upper surface of the substrate;

Forming at least one conductive structure of the silicon layer, the at least one conductive structure respectively corresponding to the at least one first pad;

Forming a first insulating layer above the silicon layer;

Wherein, a first wiring layer is provided in the first insulating layer, and the at least one first pad is respectively connected to the first wiring layer through the at least one conductive structure.
The method according to claim 1, wherein the silicon layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, and a microcrystalline silicon layer.
The method according to claim 1 or 2, wherein the forming a silicon layer on the upper surface of the substrate comprises:

The silicon layer is deposited on the substrate.
The method according to any one of claims 20 to 22, wherein the forming at least one conductive structure of the silicon layer comprises:

Forming at least one through hole of the silicon layer, the at least one through hole respectively corresponding to the at least one first pad; wherein the forming a first insulating layer above the silicon layer includes:

The first insulating layer is formed above the silicon layer, and the first wiring layer respectively extends into the at least one through hole and is respectively connected to the at least one first pad to form the at least one A conductive structure.
22. The method of claim 23, wherein the first insulating layer and the first wiring layer both extend into a first through hole of the at least one through hole, and the first through hole The first wiring layer inside is located outside the first insulating layer inside the first through hole.
The method according to claim 23 or 24, wherein a conductive pillar is provided in a second through hole of the at least one through hole, and the first wiring layer is connected to the conductive pillar.
The method according to any one of claims 23 to 25, wherein the aperture of each through hole of the at least one through hole close to the first insulating layer is larger than that of the same through hole. The aperture of the opening of the substrate.
The method according to any one of claims 23 to 26, wherein the forming a first insulating layer on the silicon layer comprises:

Forming a second insulating layer above the silicon layer and the inner wall of each of the at least one through hole;

The first insulating layer is formed on the second insulating layer.
The method of claim 27, wherein the forming at least one conductive structure of the silicon layer comprises:

At least one conductive region of the silicon layer is formed, and the at least one conductive region respectively corresponds to the at least one first pad, wherein the resistivity of each conductive region in the at least one conductive region is less than or equal to a preset threshold , To form the at least one conductive structure.
The method of claim 28, wherein the forming a first insulating layer on the silicon layer comprises:

Forming a concave ring penetrating the silicon layer around each of the at least one conductive area;

Forming a third insulating layer between the silicon layer and the first insulating layer and in the concave ring;

Forming a through hole corresponding to each conductive region of the at least one conductive region of the third insulating layer;

The first insulating layer is formed on the third insulating layer, and each conductive area of the at least one conductive area is connected to the first insulating layer through a through hole corresponding to the same conductive area on the third insulating layer. Wiring layer.
The method according to any one of claims 20 to 29, wherein the forming a silicon layer on the upper surface of the substrate comprises:

Forming a fourth insulating layer above the substrate;

Forming a through hole corresponding to each first pad of the at least one first pad of the fourth insulating layer;

The silicon layer is formed above the fourth insulating layer, and each first pad of the at least one first pad is connected through a through hole corresponding to the same first pad on the fourth insulating layer To the conductive structure corresponding to the same first pad.
The method according to any one of claims 20 to 30, wherein the forming a silicon layer on the upper surface of the substrate comprises:

Forming a fifth insulating layer on the substrate, and a second wiring layer is provided in the fifth insulating layer;

The silicon layer is provided on the fifth insulating layer, and at least one conductive structure of the silicon layer is respectively connected to the at least one first pad through the second wiring layer.
The method according to claim 31, wherein the line width of the wiring in the second wiring layer is greater than the line width of the wiring in the first wiring layer, and/or the line width of the wiring in the second wiring layer The pitch is greater than the pitch of the wiring in the first wiring layer.
The method according to any one of claims 20 to 32, wherein the forming a first insulating layer on the silicon layer comprises:

Dividing the silicon layer into a plurality of silicon layer units;

The first insulating layer is formed above the plurality of silicon layer units and a surrounding area of each silicon layer unit of the plurality of silicon layer units.
The method according to claim 33, wherein each silicon layer unit of the plurality of silicon layer units is provided with at least one conductive structure.
The method according to any one of claims 20 to 34, wherein a passive device is formed in the silicon layer.
The method of claim 35, wherein the passive device comprises a capacitor.
The method according to any one of claims 20 to 36, wherein the method further comprises:

Disposing a chip above the first insulating layer;

Wherein, at least one second pad is provided on a side of the chip close to the first wiring layer, and the at least one second pad is respectively connected to the first wiring layer.
The method according to claim 37, wherein the first wiring layer is provided with at least one link pad corresponding to the at least one second pad on a side close to the chip, and the first wiring layer is The wiring layer is provided with at least one link pad corresponding to the at least one first pad on the side close to the silicon layer, wherein the first wiring layer is provided with a connection pad on the side close to the chip. The pitch of the pads is smaller than the pitch of the connection pads provided on the side of the first wiring layer close to the silicon layer.
An integrated device, characterized in that it comprises:

An integrated device prepared according to the method of any one of claims 20 to 38.