CN109075141B - Chip packaging structure, method and terminal equipment - Google Patents

Chip packaging structure, method and terminal equipment Download PDF

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Publication number
CN109075141B
CN109075141B CN201880001314.XA CN201880001314A CN109075141B CN 109075141 B CN109075141 B CN 109075141B CN 201880001314 A CN201880001314 A CN 201880001314A CN 109075141 B CN109075141 B CN 109075141B
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chip
fingerprint identification
identification chip
conductive layer
package structure
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CN109075141A (en
Inventor
冷寒剑
张胜斌
吴宝全
龙卫
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Huiding Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Image Input (AREA)
  • Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)

Abstract

A chip packaging structure, a chip packaging method and terminal equipment are provided. The chip packaging structure comprises: the upper surface of the substrate is provided with a groove structure; the fingerprint identification chip is positioned in the groove structure and is provided with a first bonding pad; and the first bonding pad is electrically connected to a connecting end of the chip packaging structure through the conductive layer and is used for being electrically connected with the outside. In the embodiment of the application, embed the fingerprint identification chip in the base plate through groove structure for the upper surface of the chip after the encapsulation can be for leveling the surface, effectively reduced the deformation volume and the image distance tolerance of fingerprint identification chip and base plate, reached the definition of optimizing optics fingerprint formation of image, promoted recognition speed and used the purpose of experiencing.

Description

Chip packaging structure, method and terminal equipment
Technical Field
The embodiment of the application relates to the field of chip packaging, in particular to a chip packaging structure, a chip packaging method and terminal equipment.
Background
With the development of the mobile phone industry, the traditional capacitive fingerprint identification technology cannot meet the requirements of the emerging mobile phone market gradually due to the defects of limited penetration capacity, complex chip structure, thicker module size, limited placement position and the like, and the optical fingerprint identification technology becomes the mainstream of the fingerprint identification technology gradually due to the characteristics of strong penetration capacity, full screen placement support and the like.
However, the optical fingerprint identification technology has extremely high requirements on key optical path parameters such as object distance, image distance and the like, and the allowable tolerance range is extremely small. The existing optical fingerprint identification product has the defects of fuzzy imaging effect due to too many design laminated layers and large accumulative tolerance, and greatly influences the identification speed and the use experience of the product, thereby limiting the large-scale popularization and application of the product. For example, Chip On Board (COB) or one-package schemes, in which a holder for mounting a lens is attached to a substrate for mounting a chip, are both laminated, and have a large and unstable image distance tolerance under the influence of the holder, the substrate, an adhesive, and deformation and tolerance values of the chip.
Therefore, how to reduce the image distance tolerance, so as to achieve the purposes of optimizing the definition of optical fingerprint imaging, improving the recognition speed and using experience is an urgent problem to be solved in the field of chip packaging.
Disclosure of Invention
The chip packaging structure, the chip packaging method and the terminal equipment are provided, so that the image distance tolerance can be effectively reduced, the definition of optical fingerprint imaging is further optimized, the identification speed is increased, and the use experience is improved.
In a first aspect, a chip package structure is provided, including: the device comprises a substrate, wherein a groove structure is formed on the upper surface of the substrate; the fingerprint identification chip is positioned in the groove structure and is provided with a first bonding pad; the conductive layer is positioned above the substrate, and the first bonding pad is electrically connected to a connecting end of the chip packaging structure through the conductive layer and used for being electrically connected with the outside.
In the embodiment of the application, inlay in the base plate with the fingerprint identification chip through groove structure for the upper surface of the chip after the encapsulation can be for leveling the surface, and then the support of carrying the camera lens can directly paste on leveling the surface, has effectively subtracted base plate, chip, laminating glue to the influence of image distance tolerance, has reached the purpose of optimizing the definition of optics fingerprint formation of image, promotion discernment speed and use experience. Furthermore, the first bonding pad of the fingerprint identification chip is pulled to the edge position of the substrate through the conducting layer, and the purpose of packaging the fingerprint identification chip is achieved.
In some possible implementations, the fingerprint identification chip is provided with a plurality of the first pads, the chip packaging structure is provided with a plurality of the connection terminals, and the conductive layer is formed with an opening directly above the fingerprint identification chip, so that the conductive layer is divided into a plurality of conductive units, and each of the one or more first pads is connected to one or more of the connection terminals through one or more of the conductive units.
In some possible implementations, the chip packaging structure further includes: the protective layer is formed on the upper surface of the conductive layer, a window is formed in the protective layer, and the connecting end is arranged in the window on the conductive layer.
In some possible implementations, the protective layer is formed with an opening directly above the fingerprint identification chip, so that reflected light formed by reflection of a finger passes through the opening of the protective layer and is received by the fingerprint identification chip.
In some possible implementations, a through silicon via TSV is formed between the conductive layer and the lower surface of the substrate, the connection end is disposed at a TSV opening of the lower surface of the substrate, and the conductive layer is electrically connected to the connection end through the TSV.
In some possible implementations, the chip packaging structure further includes: the insulating layer is arranged between the substrate and the conducting layer, and an opening is formed right above the fingerprint identification chip, so that reflected light formed by reflection of a finger penetrates through the opening of the insulating layer and is received by the fingerprint identification chip.
In some possible implementations, the fingerprint identification chip is fixed in the groove structure by liquid or solid glue, and the depth of the groove structure is the sum of the thickness of the fingerprint identification chip and the thickness of the glue.
In some possible implementations, the chip packaging structure further includes: and the optical filter is attached to the upper surface of the fingerprint identification chip.
In some possible implementations, the connecting terminal is a second bonding pad or a solder ball.
In some possible implementations, the fingerprint identification chip includes a plurality of chips arranged in a parallel direction and/or a perpendicular direction of the upper surface of the substrate.
In some possible implementations, the chip packaging structure further includes: a holder and a lens; the camera lens passes through the support is fixed the top of fingerprint identification chip, just the camera lens with the fingerprint identification chip aligns the setting.
In some possible implementations, the lens and the holder are integrally or separately disposed.
In a second aspect, a chip package structure is provided, including:
the fingerprint identification chip, the upper surface of fingerprint identification chip is provided with first pad, be provided with through-silicon via TSV between the upper surface of fingerprint identification chip and the lower surface, the lower surface of fingerprint identification chip is provided with the conducting layer, first pad passes through-silicon via TSV electricity is connected to the one end of conducting layer, the other end of conducting layer with chip package structure's the link that is used for being connected with external electricity is connected.
In the embodiment of the application, draw the first pad of fingerprint identification chip extremely through TSV the lower surface of fingerprint identification photo for the upper surface of the chip after the encapsulation can be for leveling the surface, and then the support of carrying the camera lens can directly paste on leveling the surface, has effectively subtracted base plate, chip, laminating and has glued the influence to the image distance tolerance, has reached the purpose of optimizing the definition of optics fingerprint formation of image, promotion discernment speed and use experience. Furthermore, the TSV hole of the lower surface of the fingerprint identification chip is pulled to the edge position of the fingerprint identification chip 201 through the conducting layer, and the purpose of packaging the fingerprint identification chip is achieved.
In some possible implementations, the chip package structure is provided with a plurality of the first pads, the chip package structure is provided with a plurality of the connection terminals, a plurality of TSVs are disposed between an upper surface and a lower surface of the chip, the conductive layer is formed with an opening such that the conductive layer is divided into a plurality of conductive units, and each or a plurality of the first pads are electrically connected to one of the connection terminals through one or a plurality of the TSVs and one or a plurality of the conductive units.
In some possible implementations, the lower surface of the fingerprint identification chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection end is disposed on the lower surface of the inverted trapezoid or the multi-step inverted trapezoid.
In some possible implementations, the chip packaging structure further includes: and the optical filter is attached to the upper surface of the fingerprint identification chip.
In a third aspect, a method of packaging a chip is provided, including: forming a groove structure in a substrate; fixing a fingerprint identification chip in the groove structure; and a conductive layer is formed above the substrate by adopting a coating process, and the first bonding pad of the fingerprint identification chip is electrically connected to the connecting end of the chip packaging structure for being electrically connected with the outside through the conductive layer.
In some possible implementations, the fingerprint identification chip is provided with a plurality of the first pads, the chip packaging structure is provided with a plurality of the connection terminals, and the method further includes: removing the conductive layer directly above the fingerprint identification chip to divide the conductive layer into a plurality of conductive units, wherein each one or more first bonding pads are connected to one or more connecting terminals through one or more conductive units.
In some possible implementations, the method further includes: forming a protective layer on the upper surface of the conductive layer by adopting a coating process; forming a window in the protective layer and forming the connection terminal in the window on the conductive layer.
In some possible implementations, the method further includes: and removing the protective layer right above the fingerprint identification chip to form an opening, so that the reflected light formed by the reflection of the finger passes through the opening of the protective layer and is received by the fingerprint identification chip.
In some possible implementations, the method further includes: arranging a TSV between the conductive layer and the lower surface of the substrate by adopting a TSV process; and generating the connecting end at the TSV hole of the lower surface of the substrate.
In some possible implementations, before forming the conductive layer over the substrate by using the plating process, the method further includes: forming an insulating layer on the upper surface of the substrate by adopting a coating process so as to form the conductive layer on the upper surface of the insulating layer; and removing the insulating layer right above the fingerprint identification chip to form an opening, so that the reflected light formed by the reflection of the finger passes through the opening of the insulating layer and is received by the fingerprint identification chip.
In some possible implementations, the fixing the fingerprint identification chip in the groove structure includes: fixing the fingerprint identification chip in the groove structure through liquid or solid glue; the depth of the groove structure is the sum of the thickness of the fingerprint identification chip and the thickness of the glue.
In some possible implementations, the method further includes: and an optical filter is attached to the upper surface of the fingerprint identification chip.
In some possible implementations, the connecting terminal is a second bonding pad or a solder ball.
In some possible implementations, the fingerprint identification chip includes a plurality of chips arranged in a parallel direction and/or a perpendicular direction of the upper surface of the substrate.
In some possible implementations, the method further includes: arranging a bracket and a lens above the substrate; the lens is fixed above the fingerprint identification chip through the support, and the lens is aligned with the fingerprint identification chip.
In some possible implementations, the lens and the holder are integrally or separately disposed.
In a fourth aspect, a method of packaging a chip is provided, comprising:
arranging a Through Silicon Via (TSV) between the upper surface and the lower surface of the fingerprint identification chip by adopting a TSV process; forming a conductive layer on the lower surface of the fingerprint identification chip by adopting a coating process, wherein a first bonding pad of the fingerprint identification chip is electrically connected to one end of the conductive layer through a TSV; and generating a connecting end for electrically connecting with the outside at the other end of the conducting layer.
In some possible implementations, the fingerprint identification chip is provided with a plurality of the first pads, the chip packaging structure is provided with a plurality of the connection terminals, and a plurality of TSVs are provided between an upper surface and a lower surface of the fingerprint identification chip, and the method further includes: dividing the conductive layer into a plurality of conductive units by forming openings in the conductive layer, each of the one or more first pads being electrically connected to one or more of the connection terminals through one or more of the TSVs and one or more of the conductive units.
In some possible implementations, the lower surface of the fingerprint identification chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection end is disposed on the lower surface of the inverted trapezoid or the step inverted trapezoid.
In some possible implementations, the method further includes: and an optical filter is attached to the upper surface of the fingerprint identification chip.
In a fifth aspect, a terminal device is provided, which includes: a chip package structure prepared according to the method of packaging a chip of the second aspect.
In some possible implementation manners, the terminal device further includes a screen, and the chip package structure is disposed below the screen.
In a sixth aspect, a terminal device is provided, which includes: a chip packaging structure prepared according to the method of packaging a chip of the third aspect.
In some possible implementation manners, the terminal device further includes a screen, and the chip package structure is disposed below the screen.
In the embodiment of the application, the fingerprint identification chip avoids adopting a traditional routing mode to package, and the first bonding pad of the fingerprint identification chip is pulled to the edge position of the chip packaging structure through the metal layer and/or the TSV, so that the upper surface of the packaged chip can be a smooth surface, and the image distance tolerance is reduced. And further can directly paste the support that carries the camera lens on leveling the surface, effectively subtract base plate, chip, laminating and glued the influence to the image distance tolerance, greatly optimized the definition of optics fingerprint formation of image, promote recognition speed and use and experience.
Drawings
Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present application.
Fig. 2 is a schematic block diagram of a chip packaging structure integrated with a protective layer and an insulating layer.
Fig. 3 is a schematic block diagram of a chip package structure integrated with a filter.
Fig. 4 is a schematic structural view of a connection terminal disposed on a lower surface of a chip package structure.
Fig. 5 is a schematic block diagram of a chip package structure integrated with a lens and a holder.
Fig. 6 is another schematic structural view of a chip packaging structure of an embodiment of the present application.
Fig. 7 is another schematic block diagram of a chip package structure integrated with a filter.
Fig. 8 is another schematic block diagram of a chip package structure integrated with a lens and a holder.
Fig. 9 is a schematic flow chart diagram of a method of packaging a chip of an embodiment of the present application.
Fig. 10 is another schematic flow chart diagram of a method of packaging a chip of an embodiment of the present application.
Fig. 11 is a schematic block diagram of a terminal device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application.
Hereinafter, the chip package structure according to the embodiment of the present application will be described in detail with reference to fig. 1 to 8.
It should be noted that, for convenience of description, like reference numerals denote like parts in the embodiments of the present application, and a detailed description of the like parts is omitted in different embodiments for the sake of brevity.
It should be understood that the thickness, length, width and other dimensions of the various components in the embodiments of the present application and the overall thickness, length, width and other dimensions of the chip packaging structure shown in the drawings are only exemplary and should not limit the present application in any way.
Fig. 1 is a schematic structural diagram of a chip package structure 100 of one embodiment of the present application. As shown in fig. 1, the chip package structure 100 includes: the fingerprint identification chip comprises a fingerprint identification chip 101, a substrate 102 and a conducting layer 104, wherein a groove structure is formed on the upper surface of the substrate 102; the fingerprint identification chip 101 is positioned in the groove structure, and the fingerprint identification chip 101 is provided with a first bonding pad 106; the conductive layer 104 is located over the substrate 102.
In the embodiment of the application, through groove structure with fingerprint identification chip 101 embedded in base plate 102 for the upper surface of the chip after the encapsulation can be for leveling the surface, and then the support of carrying the camera lens can directly paste on leveling the surface, has effectively subtracted base plate 102, fingerprint identification chip 101 and laminating and has glued the influence to the image distance tolerance, has reached the purpose of optimizing the definition of optics fingerprint formation of image, promotion discernment speed and use experience. And furthermore, the first bonding pad 106 of the fingerprint identification chip is pulled to the surface position of the substrate 102 through the conductive layer 104 by the conductive layer 104, so as to achieve the purpose of packaging the fingerprint identification chip 101.
It should be noted that before the fingerprint identification chip 101 enters the packaging factory, a Pad (Pad) is prepared on one surface thereof, for example, a first Pad 106 as shown in fig. 1, and the first Pad 106 is electrically connected to a connection terminal 107 of the chip packaging structure for electrically connecting with the outside through the conductive layer 104. The first bonding pad 106 can be understood as a pin for connecting the fingerprint identification chip 101 with the outside. In this embodiment, the upper surface of the fingerprint identification chip 101 is the surface that has been prepared with the pad before entering the packaging factory, and the one side opposite to the fingerprint identification chip 101 is the lower surface of the fingerprint identification chip 101, the lower surface of the fingerprint identification chip 101 is not prepared with the pad before entering the packaging factory for laminating with the upper surface of the groove in the substrate 102.
The fingerprint identification chip 101 may be, for example, an optical fingerprint identification chip, and may specifically include an optical biometric sensor having an optical sensing array, such as an optical fingerprint sensor; the optical sensing array may include a plurality of optical sensing units for performing a biometric sensing operation. The optical sensing array of the fingerprint identification chip 101 may also be specifically a Photo detector (Photo detector) array, which includes a plurality of Photo detectors distributed in an array, where the Photo detectors may be used as the optical sensing units as described above.
Taking the technology of fingerprint identification under the screen as an example, the area where the optical sensing array is located is the sensing area of the fingerprint identification chip 101. The sensing area can be located below the display area of the display screen, so that when a user needs to unlock the terminal device or verify other biological characteristics, the user only needs to press a finger on the display screen, and the optical sensing array located in the sensing area can perform fingerprint sensing operation.
It should be understood that the optical fingerprint sensor is used as the fingerprint identification chip 101 for example only, and in other alternative embodiments, the fingerprint identification chip 101 may also use ultrasonic waves or other types of fingerprint identification modules, for example, the optical biometric sensor may be replaced by an ultrasonic fingerprint sensor or other types of fingerprint sensors. The present application does not specifically limit the type and specific structure of the fingerprint identification chip 101, as long as the fingerprint identification chip 101 can meet the performance requirement for fingerprint identification.
The fingerprint recognition chip 101 may also include a plurality of chips arranged in a parallel direction and/or a vertical direction along the upper surface of the substrate 102. That is, a plurality of chips arranged in a parallel direction and/or a vertical direction of the upper surface of the substrate 102 may be packaged in a package structure, and the plurality of chips may be electrically connected to each other to transmit signals.
The connecting terminal 107 may be a second bonding pad or a solder ball, or other connecting members for achieving an electrical connection with the outside, which is not limited in the embodiment of the present application. For example, the connection terminals 107 may be solder pads or any other type of connection terminals for electrically connecting with a Flexible Printed Circuit (FPC), and the fingerprint recognition chip 101 may be electrically connected to the FPC through the connection terminals 107. For example, when the connecting terminal 107 is a second bonding pad, the fingerprint identification chip 101 may be soldered to the FPC through the second bonding pad. Therefore, the fingerprint identification chip 101 can realize electrical interconnection and signal transmission with other peripheral circuits or other elements of the device to which the fingerprint identification chip 101 belongs through the FPC. For example, the fingerprint identification chip 101 may receive a control signal from a processing unit of the device to which the fingerprint identification chip 101 belongs through the FPC, and may output the fingerprint image to a processing unit or a control unit of the device to which the fingerprint identification chip 101 belongs through the FPC.
The fingerprint identification chip 101 may be fixed in the groove structure by liquid or solid glue, for example, the depth of the groove structure may be the sum of the thickness of the fingerprint identification chip 101 and the thickness of the glue. However, the embodiments of the present application are not limited thereto, for example, in other embodiments, the depth of the groove structure may be greater than or less than the sum of the thickness of the fingerprint recognition chip 101 and the thickness of the glue. The glue may be realized as, for example, a water glue. The water gel may comprise a single component or multiple components. In a specific implementation, the lower surface of the fingerprint identification chip 101 and the upper surface in the groove structure may be fixedly connected based on a physical process and/or a chemical process of glue.
It should be understood that the number and location of the first pads 106 in the chip package structure shown in fig. 1 are merely examples and are not limiting.
For example, the upper surface of the fingerprint recognition chip 101 may include a plurality of first pads 106, and the first pads 106 may be uniformly or non-uniformly distributed on the upper surface of the fingerprint recognition chip 101. Accordingly, the chip package structure 100 may include a plurality of connection terminals 107, and the conductive layer 104 may be configured to electrically connect one or more first pads 106 of the plurality of first pads 106 with one or more connection terminals 107 of the plurality of connection terminals 107.
For another example, the first pad 106 shown in fig. 1 directly protrudes from the surface of the fingerprint identification chip 101 by the same thickness as the conductive layer 104, and is located at the edge of the conductive layer 104, and the side surface of the first pad 106 is exposed. The embodiments of the present application are not limited thereto. For example, in other alternative embodiments, the first bonding pad 106 is disposed on the fingerprint recognition chip 101, and the upper surface of the fingerprint recognition chip 101 is a flat surface.
For example, the fingerprint identification chip 101 is provided with a plurality of first bonding pads 106, and the chip package structure 100 is provided with a plurality of connecting terminals 107. In one implementation, the conductive layer 104 may be formed with an opening directly above the fingerprint identification chip 101, so that the conductive layer 104 may be divided into a plurality of conductive units, wherein the one or more first pads 106 are connected to the one or more connection terminals 107 through the one or more conductive units, thereby ensuring that the plurality of first pads 106 are electrically connected to the plurality of connection terminals 107 of the chip packaging structure 100, respectively. In another implementation, the conductive Layer 104 may be designed as a Redistribution Layer (RDL), so that Redistribution of the first pads 106 on the fingerprint identification chip 101 to the edge of the substrate is not only achieved, but also the layout structure of the first pads 106 of the fingerprint identification chip 101 is not changed. Accordingly, when the fingerprint recognition chip 101 includes a plurality of chips, the first pad of each chip may be electrically connected to the connection terminal 107 of the chip package structure 100 through a respective conductive element.
Fig. 2 is a schematic block diagram of the chip packaging structure 100 integrated with the protective layer 105 and the insulating layer 103. As shown in fig. 2, the chip package structure 101 may further include a protection layer 105, where the protection layer 105 is formed on an upper surface of the conductive layer 104, and is used to prevent the fingerprint identification chip 101 from being damaged during the transportation and installation processes, when the chip package structure 100 according to the embodiment of the present application is used to perform underscreen fingerprint identification, a finger presses the display screen, and reflected light emitted by the display screen and reflected by the finger needs to pass through the protection layer 105 to reach the fingerprint identification chip 101, that is, an optical signal actually received by the fingerprint identification chip 101 is an optical signal reflected by the finger and passing through the protection layer 105. Therefore, in order to avoid excessive consumption of the optical signal reflected by the finger when passing through the protection layer 105, in the embodiment of the present application, an opening may be formed in the protection layer 105 directly above the fingerprint identification chip 101, so that the reflected light formed by the reflection of the finger passes through the opening of the protection layer 105 and is received by the fingerprint identification chip 101.
Since the protective layer may use any protective type material, for example, an insulating material. In order to ensure that the connection end 107 of the chip package structure 100 can be electrically connected to the outside, in this embodiment, a window may be further formed in the protection layer 105, and the connection end 107 may be disposed in the window on the conductive layer 104.
Referring to fig. 2, the chip package structure 101 may further include an insulating layer 103, where the insulating layer 103 is disposed between the substrate 102 and the conductive layer 104, and the insulating layer 103 may reduce an influence of the substrate 102 on an electrical signal in the conductive layer 104, for example, when the fingerprint identification chip 101 and the connection terminal 107 perform signal interaction, a current of the conductive layer 104 is prevented from flowing to the substrate 102, so as to ensure reliability of the fingerprint identification chip 101 and the connection terminal 107 during signal transmission. Accordingly, in order to avoid excessive consumption of the optical signal reflected by the finger when passing through the insulating layer 103, in the embodiment of the present application, like the protective layer 105, an opening may also be formed for the insulating layer 103 directly above the fingerprint identification chip 101, so that the reflected light formed by the reflection of the finger passes through the opening of the insulating layer 103 and is received by the fingerprint identification chip 101.
It should be understood that the structure shown in fig. 2 is only an example, and the embodiment of the present application is not limited thereto.
For example, in other alternative embodiments, the chip package structure 101 may not include the insulating layer 103.
For another example, the connection manner between the conductive layer 104 and the first pad of the fingerprint identification chip 101 shown in fig. 2 is only an example, and the embodiment of the present application is not limited thereto.
For example, in other alternative embodiments, the first bonding pad 106 is disposed on the fingerprint recognition chip 101, and the upper surface of the fingerprint recognition chip 101 is a flat surface. In this case, the insulating layer 103 may be left with a conductive hole at a position opposite to the first pad 106, wherein the conductive layer 104 may be connected to the first pad 106 on the fingerprint identification chip 101 through the conductive hole of the insulating layer 103.
Fig. 3 is a schematic block diagram of the chip package structure 100 integrated with the optical filter 109. As shown in fig. 3, the chip package structure 100 may further include an optical filter 109, where the optical filter 109 is attached to the upper surface of the fingerprint identification chip 101 for reducing undesired background light in fingerprint sensing, so as to improve optical sensing of the fingerprint identification chip 101 on received light. The filter 109 may specifically be used to filter out ambient light wavelengths, such as near infrared light and portions of red light, etc. For example, a human finger absorbs most of the energy of light with wavelengths below-580 nm, and the effect of ambient light on optical detection in fingerprint sensing can be greatly reduced if one or more optical filters or optical filter coatings can be designed to filter light with wavelengths from 580nm to infrared.
The optical filter 109 may particularly comprise one or more optical filters, which may be configured, for example, as a band pass filter, to allow transmission of light emitted by the OLED pixel while blocking other light components, such as infrared light, in sunlight. Such optical filtering may be effective in reducing background light caused by sunlight when the device is used outdoors. The one or more optical filters may be implemented, for example, as an optical filter coating formed on one or more continuous interfaces, or may be implemented as one or more discrete interfaces. It should be understood that the filter 109 may be fabricated on the surface of any optical component or along the optical path to the fingerprint recognition chip 101 for reflected light via finger reflection. The embodiment of the present application only takes the upper surface of the filter 109 as an example, but the present application is not limited thereto. For example, the filter 109 may be attached to the bottom surface of the display, the surface of the prism, the inside of the fingerprint recognition chip 101, or the like.
It should be understood that the number, the position, and the specific structure of the protective layer 105 and the insulating layer 103 shown in fig. 2 and the optical filter 109 shown in fig. 3 are only exemplary descriptions, and the embodiment of the present application does not limit this. For example, whether to add one or more of the protective layer 105, the insulating layer 103, and the optical filter 109 may be determined according to actual requirements of the fingerprint recognition chip 101.
It should also be understood that the connection end 107 shown in fig. 1 to 3 is located on the upper surface of the chip package structure 100 only for example, and the embodiment of the present application is not limited thereto. For example, the connection terminal 107 may be disposed on the lower surface of the chip package structure. In the embodiment of the present invention, a so-called Fan-out (Fan-out) method is to draw a pin (i.e., the first pad 106) of the fingerprint identification chip 101 to a Via pad Through a Through Silicon Via (TSV), specifically, the first pad 106 may be drawn out a distance Through a conductive layer 104, and a TSV is formed at a drawing position of the first pad 106, where the TSV may electrically connect the conductive layer 104 to the lower surface of the substrate 102. Thereby, the first bonding pads 106 on the upper surface of the fingerprint identification chip 101 are pulled to the lower surface of the substrate 102, and the connection terminals 107 are formed. The Fan-in is to draw a pin (i.e., the first pad 106) of the fingerprint identification chip 101 to an edge position of the fingerprint identification chip 101 Through a Through Silicon Via (TSV), specifically, a TSV may be directly punched at a position of the first pad 106, and this TSV may electrically connect the first pad 106 to a lower surface of the fingerprint identification chip 101. Thereby, the first pads 106 on the upper surface of the fingerprint recognition chip 101 are pulled to the lower surface of the fingerprint recognition chip 101, and the connection terminals 107 are formed.
Fig. 4 is a schematic structural diagram of the connection terminal 107 disposed on the lower surface of the chip package structure 100 (i.e., Fan-out advanced packaging process). As shown in fig. 4, a Through Silicon Via (TSV) is formed between the conductive layer 104 and the lower surface of the substrate 102, the connection terminal 107 is disposed at the TSV opening of the lower surface of the substrate 102, and the conductive layer 104 is electrically connected to the connection terminal 107 through the TSV. In some implementations, as shown in fig. 4, the through silicon via may have a conductive material disposed therein, the conductive layer 104 may be electrically connected to the third pad 110 at the TSV via through the conductive material in the through silicon via, and the third pad 110 may have a connection terminal 107 in the form of a solder ball formed thereon.
It should be understood that the embodiments of the present application are intended to illustrate that the conductive layer 104 can be electrically connected to the connection terminal 107 disposed on the lower surface of the substrate 102 through a through-silicon via, and the number, position and specific implementation of the through-silicon vias shown in fig. 4 are merely examples and are not limited. For example, the top surface of the fingerprint recognition chip 101 may include a plurality of first pads 106, and correspondingly, the chip package structure 100 (i.e., the bottom surface of the substrate 102) may include a plurality of connection terminals 107, and the through-silicon vias may be configured to electrically connect one or more first pads 106 of the plurality of first pads 106 with one or more connection terminals 107 of the plurality of connection terminals 107.
Taking the chip package structure 100 provided with a plurality of connecting terminals 107 as an example, in one implementation, the chip package structure is provided with a plurality of TSVs, so that the one or more first pads 106 can be electrically connected with the one or more connecting terminals 107 through one TSV. In another implementation, the chip package structure may dispose a TSV at the back of each pad 106, and the conductive material in the TSV may be designed as RDL, so that redistribution of the first pad 106 on the fingerprint identification chip 101 to the lower surface of the substrate 102 is not only achieved, but also the layout structure of the first pad 106 on the fingerprint identification chip 101 is not changed.
It should also be understood that the Fan-out advanced packaging process shown in fig. 4 is only an example of drawing the first bonding pads 106 on the fingerprint identification chip 101 to the lower surface of the substrate 102, but the embodiments of the present application are not limited to this packaging process and the specific structure shown in fig. 4.
Fig. 5 is a schematic block diagram of the chip packaging structure 100 integrated with the lens 201 and the holder 202. As shown in fig. 5, the chip package structure 100 may further include a support 202 and a lens 201; the lens 201 is fixed above the fingerprint identification chip 101 through the bracket 202, and the lens 201 is aligned with the fingerprint identification chip 101.
In the embodiment of the present application, the lens 201 and the holder 202 may be integrally disposed or separately disposed. The integral arrangement is that the lens 201 and the bracket 202 are integrated. For example, the lens 201 is fixed to the holder 202 in a non-detachable manner. The separation arrangement is that the lens 201 and the bracket 202 are detachably fixed on the bracket 202. The integrated arrangement can simplify the processing and assembling and optimize the yield of the module. And the separation sets up the image distance tolerance that can make originally receive the influence of many stromatolites, only receives the deformation volume and the tolerance value influence of camera lens itself, has further reduced the image distance tolerance, has optimized the definition of optics fingerprint formation of image, promotes discernment speed and uses and experiences, has also reduced the change degree of difficulty of camera lens 201 simultaneously, can effective reduce cost.
The lens 201 may be any device or element for modulating the optical path, such as a spherical or aspherical lens of a 1P or multi-P lens. In particular, a transmission type or a reflection type lens is also possible. The lens 201 is used to achieve a desired high imaging resolution. In practice, when the chip package structure 100 is applied to fingerprint recognition under a screen, the lens 201 reflects the received reflected light formed by reflection of a finger onto the fingerprint recognition chip 101. Taking the lens 201 as an example, the effective aperture of the lens 201 can be designed to be larger than the aperture of the hole in the OLED display layer, which allows light to transmit through the OLED display layer for optical fingerprint sensing. Such a design may reduce the resulting undesirable effects of wiring structures and other scattering objects in the OLED display module.
The holder 202 may be a device or an element for supporting or fixing the lens 201, for example, the holder 202 may be a device or an element for fixing the lens 201 on a terminal device to which the chip packaging structure 100 belongs, for example, when the chip packaging structure 100 is mounted on a mobile phone capable of performing fingerprint recognition under a screen, the holder 202 may be fixedly connected with a part of the device or the element of the mobile phone, for example, the holder 202 may be fixed to a middle frame, a back cover, a main board, a battery, and other easily detachable devices of the mobile phone. Even further, the stand 202 may be fixed to a lower surface of a display screen of the cellular phone.
Fig. 6 is a schematic structural diagram of a chip package structure 300 (i.e., a connection terminal 307 is disposed on the lower surface of a fingerprint identification chip 301 by Fan-in advanced packaging process) according to another embodiment of the present application. As shown in fig. 6, the chip package structure 300 includes a fingerprint identification chip 301, a first pad 306 is disposed on an upper surface of the fingerprint identification chip 301, a TSV is disposed between the upper surface and a lower surface of the fingerprint identification chip 301, a conductive layer 304 is disposed on the lower surface of the fingerprint identification chip 301, the first pad 306 is electrically connected to one end of the conductive layer 304 through the TSV, and the other end of the conductive layer 304 is electrically connected to a connection terminal 307 of the chip package structure 300, which is used for electrically connecting with the outside. In some implementations, the through-silicon via shown in fig. 6 may have a conductive material disposed therein, the first pad 306 may be electrically connected to a third pad 310 at the TSV via through the conductive material in the through-silicon via, and a connection terminal 307 in the form of a solder ball may be generated on the third pad 310.
In the embodiment of the application, draw fingerprint identification chip 301's first pad 306 extremely through TSV the lower surface of fingerprint identification photo 301 for the upper surface of the chip after the encapsulation can be for leveling the surface, makes the support of carrying on the camera lens can directly paste on leveling the surface, has effectively subtracted base plate, chip, laminating glue to the influence of image distance tolerance, has reached the purpose of optimizing the definition of optics fingerprint formation of image, promotion recognition speed and use experience. Furthermore, the TSV hole of the lower surface of the fingerprint identification chip 301 is pulled to the edge position of the fingerprint identification chip 201 through the conductive layer 304 by the conductive layer 304, so as to package the fingerprint identification chip 301.
It should be noted that, in the embodiment of the present application, the first Pad 306 may be understood as a Pad (Pad) that is prepared on one surface of the fingerprint identification chip 301 before entering a packaging factory, for example, the first Pad 106 shown in fig. 1, and the first Pad 306 is electrically connected to the connection terminal 307 of the chip packaging structure 300 for electrically connecting with the outside through the TSV. In this embodiment, the upper surface of the fingerprint identification chip 301 is a surface on which a bonding pad is prepared before entering a packaging factory, the surface opposite to the fingerprint identification chip 301 is a lower surface of the fingerprint identification chip 301, and the connecting terminal 307 is not prepared before the lower surface of the fingerprint identification chip 301 enters the packaging factory. In other words, the connection terminal 307 of the fingerprint recognition chip 301 is prepared after the fingerprint recognition chip 301 enters the packaging factory. Specifically, the first pad 306 may be exposed from the lower surface of the fingerprint identification chip 301 by using a TSV process, and then the connection end 307 may be generated at a position where the lower surface of the fingerprint identification chip 301 is exposed, or the first pad 306 may be guided to a specific position on the lower surface of the fingerprint identification chip 301, and the connection end 307 may be generated at the specific position.
Referring to fig. 6, the lower surface of the fingerprint recognition chip 301 may be an inverted trapezoid or a multi-step inverted trapezoid, and the connection terminal 307 may be disposed on the lower surface of the inverted trapezoid or the multi-step inverted trapezoid. But the embodiments themselves are not limited thereto. For example, in other alternative embodiments, the lower surface of the fingerprint identification chip 301 may also be present as a plurality of steps, or bosses, or may be a portion of a polygon, a portion of a circle, or the like.
It should be understood that the number, location, and specific implementation of the through silicon vias shown in fig. 6 are merely exemplary and not limiting. For example, the top surface of the fingerprint recognition chip 301 may include a plurality of first pads 306, and the first pads 306 may be uniformly or non-uniformly distributed on the top surface of the fingerprint recognition chip 301. Accordingly, the chip package structure 300 (i.e., the lower surface of the fingerprint recognition chip 301) may include a plurality of connection terminals 307, and the through-silicon-vias may be configured to electrically connect one or more first pads 306 of the plurality of first pads 306 with one or more connection terminals 307 of the plurality of connection terminals 307. For another example, the connecting terminal in the embodiment of the present application may be a solder ball generated on the third pad 310 as shown in fig. 6, or may be directly the third pad 310. The embodiments of the present application are not particularly limited.
For example, the fingerprint identification chip 301 is provided with a plurality of first bonding pads 306, and the chip package structure 300 is provided with a plurality of connecting terminals 307. In one implementation, a plurality of TSVs are disposed between the upper surface and the lower surface of the fingerprint identification chip 301, the conductive layer 304 is formed with an opening such that the conductive layer 304 is divided into a plurality of conductive units, and one or more of the first pads 306 are electrically connected to one or more of the connection terminals 307 through one or more of the TSVs and one or more of the conductive units, thereby ensuring that the plurality of first pads 306 are electrically connected to the plurality of connection terminals 307, respectively.
It should also be understood that the Fan-in advanced packaging process shown in fig. 6 is only an example of pulling the first pads 106 on the fingerprint identification chip 101 to the lower surface of the fingerprint identification chip 101, but the embodiment of the present application is not limited to this packaging process and the specific structure shown in fig. 6.
Fig. 7 is a schematic block diagram of a chip package structure 300 integrated with an optical filter 309. As shown in fig. 7, the chip package structure 300 may further include an optical filter 309, and the optical filter 309 is attached to the upper surface of the fingerprint identification chip 301. As shown in fig. 7, the optical filter 309 is attached to the upper surface of the fingerprint identification chip 301 by glue 308. Fig. 8 is a schematic block diagram of a chip package structure 300 integrated with a lens 401 and a support 402. As shown in fig. 8, the lens 401 is fixed to the holder 402, which is attached to the upper surface of the filter 309.
It should be understood that the fingerprint identification chip 301, the conductive layer 304, the first pad 306, the third pad 310, the connecting terminal 307, the optical filter 309 lens 401 and the support 402 shown in fig. 6 to 8 may refer to the corresponding descriptions of the fingerprint identification chip 101, the conductive layer 104, the first pad 106, the third pad 110, the connecting terminal 107, the optical filter 109 lens 201 and the support 202 shown in fig. 1 to 5, respectively, and are not repeated here to avoid repetition.
To sum up, the fingerprint identification chip of the embodiment of the application avoids adopting the traditional routing mode for packaging, and the first bonding pad of the fingerprint identification chip is pulled to the edge position of the chip packaging structure through the metal layer and/or the TSV, so that the upper surface of the packaged chip can be a flat surface, and the image distance tolerance is reduced. And further integrate the support carrying the lens to the chip packaging structure, make originally receive the image distance tolerance that the stromatolite influences, only influenced by the deformation volume and the tolerance value of support itself to reduce the image distance tolerance, greatly optimized the definition of optical fingerprint formation of image, promoted recognition speed and use and experienced.
Specific embodiments of the chip package structure of the present application are described in detail above with reference to fig. 1 to 8, and the method for preparing the chip package structure 100 shown in fig. 1 to 5 and the chip package structure 300 shown in fig. 6 to 8 is described in detail below with reference to fig. 9 and 10.
Fig. 9 is a schematic flow chart diagram of a method 500 of packaging a chip in an embodiment of the present application. The method 500 may be used to prepare the chip package structure 100 shown in fig. 1 to 5. The method 500 includes some or all of the following:
and S510, forming a groove structure in the substrate.
S520, fixing the fingerprint identification chip in the groove structure.
And S530, forming a conductive layer above the substrate by adopting a coating process, wherein the first bonding pad of the fingerprint identification chip is electrically connected to the connecting end of the chip packaging structure, which is used for being electrically connected with the outside, through the conductive layer.
In S510, the substrate may be a component or a device formed by an inorganic material such as silicon wafer, glass or ceramic, and the fingerprint identification chip may be manufactured into a component or a device matching the groove structure by grinding or cutting.
In S520, the fingerprint identification chip may be fixed in the groove structure by using a substance having an adhesive property, such as water gel or solid state gel. The water gel may comprise a single component or multiple components. In a specific implementation, the lower surface of the fingerprint identification chip and the upper surface in the groove structure can be fixedly connected based on a physical process and/or a chemical process of water gel. In some implementations, the fingerprint identification chip may be secured within the groove structure by a liquid or solid glue; wherein, the depth of groove structure is the sum of the thickness of fingerprint identification chip and the thickness of glue.
In S530, the conductive layer may be processed by a metal plating process such as sputtering, electroplating, or evaporation, and any metal having good conductivity such as aluminum, copper, nickel, silver, or gold may be used as the material. In some implementations, the conductive layer is a micron-scale coating
It should be understood that fig. 9 is only an example of a method of manufacturing a chip package structure according to an embodiment of the present application, and the embodiment of the present application is not limited thereto.
For example, in order to reduce the influence of the substrate on the electrical signal in the conductive layer, the method shown in fig. 9 may further include: before forming the conductive layer over the substrate, an insulating layer is formed on an upper surface of the substrate using a plating process so that the conductive layer is formed on the upper surface of the insulating layer. The coating process of the insulating layer can use a mechanical coating process such as spraying, spin coating, film pasting, silk printing and the like, and the material of the insulating layer can use any insulating material. The insulating layer may be a micron-scale coating.
For another example, in order to avoid damage to the fingerprint identification chip during the transportation and installation processes, the method shown in fig. 9 may further include: and forming a protective layer on the upper surface of the conductive layer by adopting a coating process. The coating process of the protective layer can use any organic coating process such as spraying, spin coating, film pasting, silk screen printing and the like, and the material of the protective layer can use any insulating protective material. The protective layer may be a micron-scale coating. In one implementation, to achieve a design in which the connecting terminals are located on the upper surface of the conductive layer, windows may be formed in the protective layer and the connecting terminals may be formed within the windows in the conductive layer. Specifically, the window may be formed at a designated position on the substrate, and the connecting end may be formed on the upper surface of the conductive layer at the window by using a ball-planting process, a tin printing process, a tin plating process, a copper plating process, and the like, so as to be used for subsequent module assembly. In another implementation, in order to realize that the connection end is located on the lower surface of the substrate, a TSV process may be adopted to arrange a TSV between the conductive layer and the lower surface of the substrate; and at the TSV orifice of the lower surface of the substrate, a connecting end is generated. The TSV process may include, but is not limited to, etching, laser, machine drilling, and the like.
For another example, in order to avoid excessive consumption of the light signal reflected by the finger when passing through the protective layer 105 and improve the lighting effect of the fingerprint identification chip, in the embodiment of the present application, the method shown in fig. 9 may further include: and removing the insulating layer right above the fingerprint identification chip to form an opening, so that the reflected light formed by the reflection of the finger passes through the opening of the insulating layer and is received by the fingerprint identification chip. Similarly, the method shown in fig. 9 may further include: and removing the protective layer right above the fingerprint identification chip to form an opening, so that the reflected light formed by the reflection of the finger passes through the opening of the protective layer and is received by the fingerprint identification chip.
For another example, in order to reduce the undesired background light received by the fingerprint identification chip during fingerprint sensing, the optical sensing of the received light by the fingerprint identification chip is improved. For example, the method shown in fig. 9 may further include: and an optical filter is attached to the upper surface of the fingerprint identification chip. The filter may use a light transmitting material such as optical glass or sapphire sheet that filters light of a given wavelength by plating.
For another example, the method shown in fig. 9 may further include: arranging a bracket and a lens above the substrate; the lens is fixed above the fingerprint identification chip through the support, and the lens is aligned with the fingerprint identification chip. In a specific implementation, the contact surface attached to the support may be an upper surface of an RDL (e.g., a conductive layer), an upper surface of a passivation layer (e.g., a protective layer), an upper surface of a silicon material surface (e.g., a substrate), or an upper surface of an optical filter. This is not particularly limited in the embodiments of the present application. The lens and the bracket can be integrally arranged or separately arranged. The integrated arrangement can simplify the processing and assembling and optimize the yield of the module. And the separation setting can make the image distance tolerance that originally receives the influence of many stromatolites, only receives the deformation volume and the tolerance value influence of camera lens itself, has further reduced the image distance tolerance, has optimized the definition of optics fingerprint formation of image, promotes discernment speed and use and experiences. Meanwhile, the replacement difficulty of the lens is reduced, and the cost can be effectively reduced. The lens may be a spherical or aspherical lens of a 1P or multi P lens. The preparation process for arranging the bracket and the lens can select injection molding, photoetching or Wafer Level Optics (WLO) process and the like.
In addition, when the fingerprint identification chip is provided with a plurality of first bonding pads and the chip packaging structure needs to be provided with a plurality of connecting ends, the method shown in fig. 9 may further include: and removing the conductive layer right above the fingerprint identification chip to divide the conductive layer into a plurality of conductive units, wherein each of the one or more first bonding pads is connected to one or more connecting terminals through one or more conductive units.
Fig. 10 is a schematic flow chart diagram of a method 600 of packaging a chip in an embodiment of the present application. As shown in fig. 10, the method 600 includes all or part of the following:
s610, arranging TSV between the upper surface and the lower surface of the fingerprint identification chip by adopting a TSV process;
s620, forming a conductive layer on the lower surface of the fingerprint identification chip by adopting a coating process, wherein the first bonding pad of the fingerprint identification chip is electrically connected to one end of the conductive layer through a TSV;
and S630, generating a connecting end for electrically connecting with the outside at the other end of the conducting layer.
It should be understood that fig. 10 is only an example of a method of manufacturing a chip package structure according to an embodiment of the present application, and the embodiment of the present application is not limited thereto.
For example, in order to reduce the undesired background light received by the fingerprint identification chip during fingerprint sensing, the optical sensing of the received light by the fingerprint identification chip is improved. For example, the method shown in fig. 10 may further include: and an optical filter is attached to the upper surface of the fingerprint identification chip. The filter may use a light transmitting material such as optical glass or sapphire sheet that filters light of a given wavelength by plating.
For another example, the method shown in fig. 10 may further include: arranging a bracket and a lens above the substrate; the lens is fixed above the fingerprint identification chip through the support, and the lens is aligned with the fingerprint identification chip. Specifically, the first bonding pad of the fingerprint identification chip can be guided to the lower surface of the fingerprint identification chip by using a through silicon via operation mode, and finally, the optical path bracket lens is adhered to the surface of the optical filter. The lens and the bracket can be integrally arranged or separately arranged. The integrated arrangement can simplify the processing and assembling and optimize the yield of the module. And the separation setting can make the image distance tolerance that originally receives the influence of many stromatolites, only receives the deformation volume and the tolerance value influence of camera lens itself, has further reduced the image distance tolerance, has optimized the definition of optics fingerprint formation of image, promotes discernment speed and use and experiences. Meanwhile, the difficulty in replacing the lens 201 is reduced, and the cost can be effectively reduced. The lens may be a spherical or aspherical lens of a 1P or multi P lens. The process for arranging the bracket and the lens can be injection molding, photoetching or Wafer Level Optics (WLO) process.
In addition, when the fingerprint identification chip is provided with a plurality of first pads and the chip packaging structure needs to be provided with a plurality of connecting ends, the method shown in fig. 10 may further include: and a plurality of TSVs are arranged between the upper surface and the lower surface of the fingerprint identification chip, the conducting layer is divided into a plurality of conducting units by forming openings in the conducting layer, and each or a plurality of first bonding pads are electrically connected to one or a plurality of connecting terminals through one or a plurality of TSVs and one or a plurality of conducting units. In some implementations, the lower surface of the fingerprint identification chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection terminal is disposed on the lower surface of the inverted trapezoid or the multi-step inverted trapezoid.
It is understood that method embodiments and chip package structure embodiments may correspond to each other and similar descriptions may refer to specific embodiments of chip package structures. For brevity, no further description is provided herein.
It should also be understood that the above-listed embodiments of the chip packaging method may be performed by a robot or a numerical control machining method, and that the device software or processes for performing the chip packaging method may be performed by executing computer program code stored in a memory.
A terminal device is provided in an embodiment of the present application, fig. 11 is a side view of a terminal device 700 in an embodiment of the present application, and as shown in fig. 11, the terminal device may include a chip packaging structure 701 and a screen 702, where the chip packaging structure 701 is disposed below the screen 702, and the chip packaging structure 701 may be the chip packaging structure 100 or 300 described above, or a chip packaging structure prepared according to the chip packaging method 500 or 600 described above.
In some implementations, the terminal device 700 may be a mobile phone, a tablet computer, an electronic book, or other terminal devices.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (34)

1. A chip package structure, comprising:
the device comprises a substrate, wherein a groove structure is formed on the upper surface of the substrate;
the fingerprint identification chip is positioned in the groove structure and is provided with a first bonding pad;
the conductive layer is positioned above the substrate, and the first bonding pad is electrically connected to a connecting end of the chip packaging structure through the conductive layer and used for being electrically connected with the outside;
the chip packaging structure further comprises:
the insulating layer is arranged between the substrate and the conducting layer, and an opening is formed right above the fingerprint identification chip, so that reflected light formed by reflection of a finger penetrates through the opening of the insulating layer and is received by the fingerprint identification chip.
2. The chip package structure according to claim 1, wherein the fingerprint identification chip is provided with a plurality of the first pads, the chip package structure is provided with a plurality of the connection terminals, the conductive layer is formed with an opening directly above the fingerprint identification chip, so that the conductive layer is divided into a plurality of conductive units, and each of the one or more first pads is connected to one or more of the connection terminals through one or more of the conductive units.
3. The chip package structure according to claim 1, further comprising:
the protective layer is formed on the upper surface of the conductive layer, a window is formed in the protective layer, and the connecting end is arranged in the window on the conductive layer.
4. The chip package structure according to claim 3, wherein the protective layer has an opening formed directly above the fingerprint identification chip, so that reflected light formed by reflection of a finger passes through the opening of the protective layer and is received by the fingerprint identification chip.
5. The chip packaging structure according to claim 1, wherein a Through Silicon Via (TSV) is formed between the conductive layer and the lower surface of the substrate, the connecting terminal is disposed at a TSV opening of the lower surface of the substrate, and the conductive layer is electrically connected to the connecting terminal through the TSV.
6. The chip package structure according to claim 1, wherein the chip is fixed in the groove structure by a liquid or solid glue, and the depth of the groove structure is the sum of the thickness of the chip and the thickness of the glue.
7. The chip package structure according to claim 1, further comprising:
and the optical filter is attached to the upper surface of the fingerprint identification chip.
8. The chip package structure according to claim 1, wherein the connecting terminal is a second bonding pad or a solder ball.
9. The chip package structure according to claim 1, wherein the fingerprint identification chip comprises a plurality of chips arranged along a parallel direction and/or a vertical direction of the upper surface of the substrate.
10. The chip package structure according to claim 1, further comprising:
a holder and a lens;
the camera lens passes through the support is fixed the top of fingerprint identification chip, just the camera lens with the fingerprint identification chip aligns the setting.
11. The chip package structure according to claim 10, wherein the lens and the holder are integrally or separately disposed.
12. A chip package structure, comprising:
the fingerprint identification chip, the upper surface of fingerprint identification chip is provided with first pad, be provided with through-silicon via TSV between the upper surface of fingerprint identification chip and the lower surface, the lower surface of fingerprint identification chip is provided with the conducting layer, first pad passes through-silicon via TSV electricity is connected to the one end of conducting layer, the other end of conducting layer with chip package structure's the link that is used for being connected with external electricity is connected.
13. The chip package structure according to claim 12, wherein the chip is provided with a plurality of the first pads, the chip package structure is provided with a plurality of the connection terminals, a plurality of TSVs are disposed between an upper surface and a lower surface of the chip, the conductive layer is formed with an opening such that the conductive layer is divided into a plurality of conductive units, and each of the one or more first pads is electrically connected to one or more of the connection terminals through one or more of the TSVs and one or more of the conductive units.
14. The chip package structure according to claim 12, wherein the lower surface of the fingerprint identification chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection terminal is disposed on the lower surface of the inverted trapezoid or the multi-step inverted trapezoid.
15. The chip package structure according to claim 12, further comprising:
and the optical filter is attached to the upper surface of the fingerprint identification chip.
16. A method of packaging a chip, comprising:
forming a groove structure in a substrate;
fixing a fingerprint identification chip in the groove structure;
forming a conductive layer above the substrate by adopting a coating process, wherein the first bonding pad of the fingerprint identification chip is electrically connected to the connecting end of the chip packaging structure for electrically connecting with the outside through the conductive layer;
before the forming of the conductive layer over the substrate by the plating process, the method further includes:
forming an insulating layer on the upper surface of the substrate by adopting a coating process so as to form the conductive layer on the upper surface of the insulating layer;
and removing the insulating layer right above the fingerprint identification chip to form an opening, so that the reflected light formed by the reflection of the finger passes through the opening of the insulating layer and is received by the fingerprint identification chip.
17. The method of claim 16, wherein the fingerprint identification chip is provided with a plurality of the first pads, the chip package structure is provided with a plurality of the connection terminals, and the method further comprises:
removing the conductive layer directly above the fingerprint identification chip to divide the conductive layer into a plurality of conductive units, wherein each one or more first bonding pads are connected to one or more connecting terminals through one or more conductive units.
18. The method of claim 16, further comprising:
forming a protective layer on the upper surface of the conductive layer by adopting a coating process;
forming a window in the protective layer and forming the connection terminal in the window on the conductive layer.
19. The method of claim 18, further comprising:
and removing the protective layer right above the fingerprint identification chip to form an opening, so that the reflected light formed by the reflection of the finger passes through the opening of the protective layer and is received by the fingerprint identification chip.
20. The method of claim 16, further comprising:
arranging a TSV between the conductive layer and the lower surface of the substrate by adopting a TSV process;
and generating the connecting end at the TSV hole of the lower surface of the substrate.
21. The method of claim 16, wherein securing the fingerprint identification chip within the recess structure comprises:
fixing the fingerprint identification chip in the groove structure through liquid or solid glue;
the depth of the groove structure is the sum of the thickness of the fingerprint identification chip and the thickness of the glue.
22. The method of claim 16, further comprising:
and an optical filter is attached to the upper surface of the fingerprint identification chip.
23. The method of claim 16, wherein the connecting terminal is a second bonding pad or a solder ball.
24. The method of claim 16, wherein the fingerprint recognition chip comprises a plurality of chips arranged in a parallel direction and/or a perpendicular direction of the upper surface of the substrate.
25. The method of claim 16, further comprising:
arranging a bracket and a lens above the substrate;
the lens is fixed above the fingerprint identification chip through the support, and the lens is aligned with the fingerprint identification chip.
26. The method of claim 25, wherein the lens and the mount are integrally or separately disposed.
27. A method of packaging a chip, comprising:
arranging TSV between the upper surface and the lower surface of the fingerprint identification chip by adopting a TSV process;
forming a conductive layer on the lower surface of the fingerprint identification chip by adopting a coating process, wherein a first bonding pad of the fingerprint identification chip is electrically connected to one end of the conductive layer through a TSV;
and generating a connecting end for electrically connecting with the outside at the other end of the conducting layer.
28. The method of claim 27, wherein the chip is provided with a plurality of the first pads, the chip package structure is provided with a plurality of the connection terminals, and a plurality of TSVs are provided between an upper surface and a lower surface of the chip, the method further comprising:
dividing the conductive layer into a plurality of conductive units by forming openings in the conductive layer, each of the one or more first pads being electrically connected to one or more of the connection terminals through one or more of the TSVs and one or more of the conductive units.
29. The method as claimed in claim 27, wherein the lower surface of the fingerprint recognition chip is an inverted trapezoid or a multi-step inverted trapezoid, and the connection terminal is provided on the lower surface of the inverted trapezoid or the multi-step inverted trapezoid.
30. The method of claim 27, further comprising:
and an optical filter is attached to the upper surface of the fingerprint identification chip.
31. A terminal device, comprising:
a chip packaging structure prepared by the method of packaging a chip according to any one of claims 16 to 26.
32. The terminal device of claim 31, further comprising a screen, wherein the chip package structure is disposed below the screen.
33. A terminal device, comprising:
a chip packaging structure prepared according to the method of packaging a chip of any one of claims 27 to 30.
34. The terminal device of claim 33, further comprising a screen, wherein the chip package structure is disposed below the screen.
CN201880001314.XA 2018-07-26 2018-07-26 Chip packaging structure, method and terminal equipment Active CN109075141B (en)

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