WO2021037233A1 - Package body and preparation method therefor - Google Patents

Package body and preparation method therefor Download PDF

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Publication number
WO2021037233A1
WO2021037233A1 PCT/CN2020/112226 CN2020112226W WO2021037233A1 WO 2021037233 A1 WO2021037233 A1 WO 2021037233A1 CN 2020112226 W CN2020112226 W CN 2020112226W WO 2021037233 A1 WO2021037233 A1 WO 2021037233A1
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WO
WIPO (PCT)
Prior art keywords
substrate
package
plastic
semi
support plate
Prior art date
Application number
PCT/CN2020/112226
Other languages
French (fr)
Chinese (zh)
Inventor
刘建辉
郭文龙
张强波
宋关强
柳仁辉
Original Assignee
天芯互联科技有限公司
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Publication date
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Publication of WO2021037233A1 publication Critical patent/WO2021037233A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This application relates to the field of packaging technology, in particular to a packaging body and a preparation method thereof.
  • the inventor of the present application found that in the current chip-stacked packaging structure, especially for high-power modules, the current flow capacity, heat dissipation treatment and high reliability have become technical difficulties in the industry.
  • the main technical problem solved by the present application is to provide a package and a preparation method thereof, which can not only solve the alignment problem in the preparation process of the package, but also realize the miniaturization of the package.
  • a technical solution adopted by the present application is to provide a method for preparing a package body.
  • the preparation method includes: preparing a package semi-finished product, wherein the package semi-finished product includes a substrate, a first device, and a second device.
  • a first plastic encapsulated body and a second plastic encapsulated body, the substrate includes a first surface and a second surface opposed to each other, and the first device and the second device are respectively disposed on the first surface and the second surface of the substrate
  • the first plastic package body and the second plastic package body wrap the first device and the second device on the first surface and the second surface of the substrate, respectively, and the second plastic package body
  • the pins of the second device are exposed; a plurality of semi-finished products of the package are fixed on the same side of the first support board, wherein the exposed pins of the second device face the first support board
  • Place an intermediate layer support and a second support plate wherein the intermediate layer support is provided on the side of the support plate where a plurality of semi-finished products of the package are provided, and the intermediate layer support has a plurality of semi-finished products with the package
  • the semi-finished packaging products are respectively located in the corresponding through grooves
  • the second supporting plate is arranged on the side of the semi-finished packaging products
  • the package includes: a substrate, including a first surface and a second surface disposed oppositely; and a first device disposed on the The first surface of the substrate; the second device is arranged on the second surface of the substrate; the first plastic package is used to wrap the first device on the first surface of the substrate; the second plastic package is used to Wrap the second device on the second surface of the substrate, wherein the second plastic package exposes the pins of the second device; the redistribution layer is provided in the exposed area of the second plastic package On one side of the pin, the redistribution layer includes a pad connected to the pin, and the pad serves as a pin of the package body.
  • the beneficial effect of the present application is: the preparation method of the package of the present application first encapsulates a plurality of semi-finished products of the package, and then presses and fixes the semi-finished products of the plurality of packages through the first support plate, the intermediate layer support and the second support plate, and then processed to form Pads, that is, a single unit is plastic-encapsulated, and then multiple encapsulated units are fixed together before processing.
  • the substrate undergoes less stress during the plastic-encapsulation process, so that the semi-finished package that is formed has a smaller degree of deformation and warpage, and the alignment in the subsequent process of forming the pad is more It is accurate.
  • the first device and the second device are laid out in the longitudinal space of the substrate, which can realize the miniaturization of the package size.
  • FIG. 1 is a schematic flowchart of an embodiment of a method for preparing a package of the present application
  • Fig. 2 is a partial preparation process diagram corresponding to the preparation method of Fig. 1;
  • FIG. 3 is a schematic diagram of the structure of encapsulating semi-finished products in an application scenario
  • Fig. 4 is a subsequent preparation process diagram of Fig. 2 in an application scenario
  • Fig. 5 is a subsequent preparation process diagram of Fig. 2 in another application scenario
  • Fig. 6 is a schematic structural diagram of an embodiment of the package of the present application.
  • FIG. 7 is a schematic structural diagram of another embodiment of the package of the present application.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for manufacturing a package according to the present application.
  • the preparation method of the package includes:
  • the semi-finished package 1000 includes a substrate 1100, a first device 1200, a second device 1300, a first plastic package 1400, and a second plastic package 1500.
  • the substrate 1100 includes a first surface 1110 and a second opposite surface.
  • the surface 1120, the first device 1200 and the second device 1300 are respectively disposed on the first surface 1110 and the second surface 1120 of the substrate 1100.
  • the first plastic package 1400 and the second plastic package 1500 separate the first device 1200 and the second device 1300 is wrapped on the first surface 1110 and the second surface 1120 of the substrate 1100, and the second plastic package 1500 exposes the pins 1310 of the second device 1300.
  • the first device 1200 is packaged on one side of the substrate 1100
  • the second device 1300 is packaged on the other side of the substrate 1100, that is, the first device 1200 and the second device 1300 are opposed to the longitudinal space of the substrate 1100.
  • the layout can realize the miniaturization of the package size.
  • the substrate 1100 can be any supporting board such as a printed circuit board or a frame substrate.
  • the first surface 1110 and the second surface 1120 are provided with input/output ports (not shown).
  • the first device 1200 and the second surface 1120 are provided with input/output ports (not shown).
  • the input/output ports on one surface 1110 are electrically connected, and the second device 1300 is electrically connected with the input/output ports on the second surface 1120.
  • the first device 1200 is a bare chip, that is, an unpackaged chip.
  • the first device 1200 includes a functional surface 1210 and a non-functional surface 1220.
  • the functional surface 1210 is provided with input/output ports and the non-functional surface 1220 There is no input/output port on it.
  • the first device 1200 is disposed on the first surface 1110 of the substrate 1100 in a flip-chip manner to achieve electrical connection with the substrate 1100, that is, the functional surface 1210 of the first device 1200 faces
  • the first device 1200 is electrically connected to the substrate 1100 through the first conductive member 1600 disposed between the functional surface 1210 and the substrate 1100.
  • the first conductive member 1600 may be a tin ball or a copper pillar. This is not limited.
  • the first device 1200 is disposed on the first surface 1110 of the substrate 1100 in a traditional bonding manner to achieve electrical connection with the substrate 1100, that is, the functional surface of the first device 1200 1210 faces away from the substrate 1100, and the first device 1200 is electrically connected to the substrate 1100 through a bonding wire 1230 connecting the functional surface 1210 and the substrate 1100.
  • the bonding wire 1230 may be a connecting wire with conductive properties such as a copper wire or a gold wire.
  • the first device 1200 may also be provided with a heat sink 1700 on the side away from the substrate 1100.
  • the functional surface 1210 of the first device 1200 is provided with a heat sink. ⁇ 1700.
  • the heat sink 1700 may not be provided, and there is no limitation here.
  • the number of the first device 1200 may be more than one.
  • the first device 1200 may also be a packaged device.
  • the first device 1200 is a packaged resistor and capacitor. Or inductors and other devices.
  • the second device 1300 is disposed on the second surface 1120 of the substrate 1100 and is electrically connected to the substrate 1100.
  • the second device 1300 may be mounted on the second surface 1120 of the substrate 1100 in a surface mount manner.
  • the second device 1300 is provided with pins 1310 on the surface of the side away from the substrate 1100, and the second plastic package 1500 exposes the pins 1310 of the second device 1300.
  • the pins 1310 on the other surface of the second device 1300 may be exposed by the second plastic package 1500, which is not limited here.
  • the preparation process of the packaged semi-finished product 1000 is: providing a substrate 1100; arranging the first device 1200 on the first surface 1110 of the substrate 1100; plastic-sealing the side of the substrate 1100 with the first device 1200 with a plastic molding compound, and A first plastic package body 1400 that wraps the first device 1200 is formed; a second device 1300 is arranged on the second surface 1120 of the substrate 1100; the side of the substrate 1100 with the second device 1300 is plastic-encapsulated with a plastic molding compound to form a package second The second plastic package body 1500 of the device 1300; the second plastic package body 1500 is ground to expose the pins 1310 of the second device 1300.
  • the second plastic package 1500 in order to be able to subsequently draw out more input/output ports on the substrate 1100, before forming the second plastic package 1500, it further includes: forming a second conductive member 1800 on the second surface 1120 of the substrate 1100, and The two conductive members 1800 are electrically connected to the substrate 1100, and then the second plastic package body 1500 is ground to expose the other end of the second conductive member 1800 and the pins 1310 of the second device 1300 at the same time.
  • the second conductive member 1800 may be a copper pillar or a copper ball, etc., which is not limited here.
  • S120 Fix a plurality of package semi-finished products 1000 on the same side of the first support plate 2000, wherein the exposed pins 1310 of the second device 1300 face the first support plate 2000.
  • S130 Place the intermediate layer support 3000 and the second support plate 4000, wherein the intermediate layer support 3000 is arranged on the side of the support plate 2000 where a plurality of package semi-finished products 1000 are provided, and the intermediate layer support 3000 has a plurality of corresponding to the package semi-finished products 1000
  • the through grooves 3100 and the semi-finished packaging product 1000 are respectively located in the corresponding through grooves 3100, and the second supporting plate 4000 is arranged on the side of the semi-finished packaging product 1000 away from the first supporting plate 2000.
  • S150 Process the first support plate 2000 to form a pad 5200 connected to the pin 1310 of the second device 1300, where the pad 5200 serves as the pin of the package body 6000.
  • the second support plate 4000 is a support plate with a certain supporting strength such as a steel plate
  • the middle layer bracket 3000 is a frame with a certain supporting effect.
  • the first support plate 2000 is a support plate with a certain support strength such as a steel plate, and one side of the first support plate 2000 is covered with a redistribution layer 5000.
  • Step S120 specifically includes: The packaged semi-finished product 1000 is fixed on the redistribution layer 5000, the exposed pins 1310 of the second device 1300 face the redistribution layer 5000, and the exposed pins 1310 of the second device 1300 are electrically connected to the redistribution layer 5000 through the solder paste 5100, In other words, the exposed pins 1310 of the second device 1300 are soldered on the redistribution layer 5000 through the solder paste 5100.
  • the rewiring layer 5000 may be copper foil.
  • one end of the second conductive member 1800 is also soldered on the redistribution layer 5000 through the solder paste 5100.
  • a plurality of package semi-finished products 1000 are fixed on the rewiring layer 5000 through operations such as printing solder paste 5100, patching, and reflow soldering.
  • step S130 also includes: filling the gap between the intermediate layer support 3000 and the semi-finished package 1000 with an insulating material 4100 to facilitate subsequent pressing of the first support plate 2000, the second support plate 4000, and the intermediate
  • the layer bracket 3000 and a plurality of encapsulated semi-finished products 1000 can be integrated into a structure.
  • the insulating material 4100 may be a prepreg and other adhesive materials, which is not limited here.
  • step S150 specifically includes: removing the first support plate 2000 and patterning the redistribution layer 5000 to form a pad 5200 connected to the pin 1310 of the second device 1300.
  • the specific process of the patterned redistribution layer 5000 is: etching and surface treatment of the redistribution layer 5000 to form the pad 5200.
  • the first support plate 2000 is also a support plate with a certain support strength such as steel plate.
  • the difference from the first application scenario is that the first support plate 2000 is not covered with heavy weight.
  • the wiring layer 5000, at this time, step S120 specifically includes: fixing a plurality of semi-finished packaging products 1000 on the same side of the first support plate 2000 through insulating glue 2100 (in other application scenarios, it may also be an insulating film, such as a DAF film).
  • Step S150 specifically includes: removing the first support plate 2000 and the insulating glue 2100; forming a redistribution layer 5000 on the side of the pins 1310 of the second device 1300 of the plurality of packaged semi-finished products 1000; and patterning the redistribution layer 5000 to form a connection to the second device 1300 pin 1310 pad 5200.
  • the method of forming the rewiring layer 5000 may be to press the pre-prepared rewiring layer 5000 on the side of the exposed pin 1310 of the semi-finished package 1000, or use sputtering, vapor deposition, etc. to expose the lead on the semi-finished package 1000.
  • the rewiring layer 5000 is formed on one side of the pin 1310, which is not limited here.
  • the material of the redistribution layer 5000 can be conductive materials such as copper, aluminum, etc., which is not limited here.
  • the structure of the package 6000 prepared by the preparation method of the first application scenario and the second application scenario is different, specifically: the package 6000 prepared by the first application scenario includes the second plastic package 1500 and The solder paste 5100 between the rewiring layers 5000 and the insulating material 4100 surrounding the solder paste 5100.
  • the package 6000 prepared in the second application scenario does not include the solder paste 5100 and the insulating material 4100 surrounding the solder paste 5100.
  • the second The pin 1310 of the device 1300 is directly electrically connected to the redistribution layer 5000.
  • the method further includes: removing the second support plate 4000; grinding the first plastic encapsulation body 1400 of a plurality of encapsulated semi-finished products 1000 to expose the non-irregularities of the first device 1200 Functional surface 1220; cutting the intermediate layer support 3000 and the patterned redistribution layer 5000 to obtain a plurality of packages 6000.
  • the double-sided vertical heat dissipation of the package 6000 can be realized: one side is through the non-functional surface 1220 of the first device 1200 for heat dissipation, and the other side is through the electrical connection with the second device 1300.
  • the connected pad 5200 dissipates heat, and the heat dissipation effect is better.
  • the non-functional surface 1220 of the first device 1200 may be exposed without grinding the first plastic encapsulation body 1400 of the plurality of semi-finished products 1000. That is, at this time, each surface of the first device 1200 is uniform. It is wrapped by the first plastic package 1400.
  • the first device 1200 is provided with a heat sink 1700 on the side away from the substrate 1100, after grinding the first plastic package 1400, the surface of the heat sink 1700 far away from the first device 1200 is finally exposed.
  • a plurality of semi-finished packaging products 1000 are packaged first, and then the semi-finished packaging products 1000 are press-fitted and fixed on the first support plate 2000, the intermediate support 3000, and the second support plate 4000.
  • the bonding pad 5200 is formed by post-processing together, that is, a single unit is plastic-encapsulated first, and then multiple encapsulated units are fixed together before processing.
  • the substrate 1100 receives less stress during the plastic-encapsulation process, so that the resulting package semi-finished product 1000 has a smaller degree of deformation and warping, and subsequent soldering is formed.
  • the alignment of the disk 5200 is more accurate, which ensures that the formed package 6000 has a better flow capacity.
  • the pad 5200 is newly formed as the pins of the package 6000.
  • this embodiment can expand the package 6000.
  • the area of the pins so that when the package body 6000 is soldered to other components through the pins, the bonding force between the package body 6000 and other components can be increased, and the soldering reliability can be improved.
  • the first support plate 2000, the second support plate 4000, the intermediate layer support 3000 and a plurality of package semi-finished products 1000 are pressed together to form an integral structure, which can ensure the subsequent formation
  • the bonding force between the bonding pad 5200 and the second device 1300 can also ensure the reliability of subsequent welding of the package body 6000.
  • the first support plate 2000 in step S150, may also be directly etched and surface treated to obtain the pad 5200 connected to the pin 1310 of the second device 1300.
  • the first support plate 2000 The material of is a conductive material, such as copper, and it is necessary to electrically connect the exposed pin 1310 of the second device 1300 with the first support plate 2000 in step S120.
  • the intermediate layer bracket 3000 and other components may not be cut, that is, the package 6000 that is finally formed includes a plurality of package semi-finished products 1000.
  • the package 7000 includes a substrate 7100, a first device 7200, a second device 7300, a first plastic package 7400, a second plastic package 7500, and a redistribution layer 7600.
  • the substrate 7100 includes a first surface 7110 and a second surface 7120 disposed oppositely; the first device 7200 is disposed on the first surface 7110 of the substrate 7100; the second device 7300 is disposed on the second surface 7120 of the substrate 7100; the first plastic package body 7400 is used To wrap the first device 7200 on the first surface 7110 of the substrate 7100; the second plastic package 7500 is used to wrap the second device 7300 on the second surface 7120 of the substrate 7100, wherein the second plastic package 7500 exposes the second device
  • the pin 7310 of the 7300; the redistribution layer 7600 is arranged on the side of the second plastic package 7500 that exposes the pin 7310.
  • the redistribution layer 7600 includes the pad 7610 connected to the pin 7310, and the pad 7610 is used as the pin 7310 of the package 7000 .
  • the package body 7000 further includes: a soldering layer 7700.
  • the soldering layer 7700 is disposed between the second plastic package 7500 and the redistribution layer 7600.
  • the soldering layer 7700 includes a solder paste 7710 and an insulating material 7720 surrounding the solder paste 7710.
  • the solder paste 7710 is electrically connected to the pins 7310 of the second device 7300 and the rewiring layer 7600.
  • the pad 7610 of the wiring layer 7600 is electrically connected to the pins 7310 of the second device 7300 and the rewiring layer 7600.
  • the package 7000 may not include the soldering layer 7700.
  • the pins 7310 of the second device 7300 are directly connected to the pads 7610 of the redistribution layer 7600.
  • the side of the second plastic encapsulation body 7500 away from the substrate 7100 exposes the pins 7310 of the second device 7300.
  • the second plastic encapsulation body 7500 may also be the pins 7310 exposed on other surfaces of the second device 7300, which is not limited here.
  • the package body 7000 further includes: a first conductive member 7800.
  • One end of the first conductive member 7800 is disposed on the second surface 7120 of the substrate 7100 to achieve electrical connection between the first conductive member 7800 and the substrate 7100, and the other end of the first conductive member 7800 is connected to the outside of the second plastic package 7500.
  • the first device 7200 is a bare chip.
  • the first device 7200 includes a functional surface 7210 and a non-functional surface 7220 arranged oppositely.
  • the functional surface 7210 of the first device 7200 faces the substrate 7100.
  • a device 7200 is electrically connected to the substrate 7100 through a second conductive member 7900 disposed between the functional surface 7210 and the substrate 7100, wherein the first plastic encapsulation body 7400 exposes the non-functional surface 7220 of the first device 7200, wherein the first plastic package 7400 exposes the non-functional surface 7220 of the first device 7200.
  • the second conductive element 7900 is a tin ball or a copper pillar; in another application scenario, as shown in FIG.
  • the functional surface 7210 of the first device 7200 is away from the substrate 7100, and the first device 7200 connects the functional surface 7210 and the substrate 7100 by soldering Wire 7240 to achieve electrical connection with the substrate 7100.
  • the package body 7000 further includes a heat sink 7230.
  • the heat sink 7230 is disposed on the functional surface 7210 of the first device 7200, and the first plastic package body 7400 exposes the heat sink. 7230 is away from the surface on the side of the first device 7200.
  • the multiple first devices 7200 there are multiple first devices 7200.
  • the multiple first devices 7200 also include packaged devices, such as packaged resistors, capacitors, or inductors.
  • the package body in this embodiment is prepared by the method for preparing the package body in the above embodiment, and the detailed preparation method can be referred to the above embodiment, which will not be repeated here.
  • the preparation method of the package body of the present application first encapsulates a plurality of semi-finished products of the package, and then presses and fixes the semi-finished products of the plurality of packages through the first support plate, the intermediate layer support and the second support plate, and then processes them to form the bonding pads.
  • a single unit is plastic-encapsulated, and then multiple encapsulated units are fixed together before processing. Compared with the prior art, all devices are fixed on the substrate and then plastic-encapsulated to form an integrated structure.
  • the substrate receives less stress during the plastic-encapsulation process, so that the semi-finished package that is formed has a smaller degree of deformation and warpage, and the subsequent process of forming the pad is more accurate.
  • this application prepares In the package body, the first device and the second device are arranged relative to the longitudinal space of the substrate, so that the package size can be miniaturized.

Abstract

A package body (6000) and a preparation method therefor. The preparation method for the package body (6000) comprises: preparing package semi-finished products (1000), each comprising a substrate (1100), a first device (1200), a second device (1300), a first plastic package body (1400) and a second plastic package body (1500), the first device (1200) and the second device (1300) being respectively provided on a first surface (1110) and a second surface (1120) of the substrate (1100), the first plastic package body (1400) and the second plastic package body (1500) respectively wrapping the first device (1200) and the second device (1300) onto the substrate (1100); fixing the plurality of package semi-finished products (1000) on the same side of a first support plate (2000), exposed pins (1310) of the second device (1300) facing towards the first support plate (2000); placing an intermediate layer support (3000) and a second support plate (4000); pressing the first support plate (2000), the second support plate (4000), the intermediate layer support (3000) and the plurality of package semi-finished products (1000) so as to form an integral structure; and processing the first support plate (2000), so as to form a pad (5200) connecting pins of the second device (1300). The preparation method provided is able to solve the problem of alignment during the preparation of the package body (6000), and is also able to achieve the miniaturization of the size of the package body (6000).

Description

封装体及其制备方法Encapsulation body and preparation method thereof 【技术领域】【Technical Field】
本申请涉及封装技术领域，特别是涉及一种封装体及其制备方法。This application relates to the field of packaging technology, in particular to a packaging body and a preparation method thereof.
【背景技术】【Background technique】
近年来，随着芯片封装高密度、多功能、小型化的快速发展，芯片平铺的封装方式已经不能满足需求，有鉴于此，目前已经出现了芯片堆叠的封装结构。In recent years, with the rapid development of high-density, multi-function, and miniaturization of chip packaging, the packaging method of chip tile has been unable to meet the demand. In view of this, a chip-stacked packaging structure has emerged.
本申请的发明人发现，目前芯片堆叠的封装结构中，尤其对于大功率模块而言，通流能力、散热处理和高可靠性成为了业内技术难点。The inventor of the present application found that in the current chip-stacked packaging structure, especially for high-power modules, the current flow capacity, heat dissipation treatment and high reliability have become technical difficulties in the industry.
【发明内容】[Summary of the invention]
本申请主要解决的技术问题是提供一种封装体及其制备方法，既能够解决封装体制备过程中的对位问题，也能够实现封装体的尺寸小型化。The main technical problem solved by the present application is to provide a package and a preparation method thereof, which can not only solve the alignment problem in the preparation process of the package, but also realize the miniaturization of the package.
为解决上述技术问题，本申请采用的一个技术方案是：提供一种封装体的制备方法，所述制备方法包括：制备封装半成品，其中，所述封装半成品包括基板、第一器件、第二器件、第一塑封体和第二塑封体，所述基板包括相对的第一表面和第二表面，所述第一器件和所述第二器件分别设置在所述基板的第一表面和第二表面上，所述第一塑封体和所述第二塑封体分别将所述第一器件和所述第二器件包裹在所述基板的第一表面和第二表面上，且所述第二塑封体裸露出所述第二器件的引脚；将多个所述封装半成品固定在第一支撑板的同一侧上，其中，所述第二器件裸露出的所述引脚朝向所述第一支撑板；放置中间层支架和第二支撑板，其中，所述中间层支架设置在所述支撑板设置有多个所述封装半成品的一侧上，所述中间层支架具有多个与所述封装半成品对应的通槽，所述封装半成品分别位于对应的所述通槽中，所述第二支撑板设置在所述封装半成品远离所述第一支撑板的一侧；压合所述第一支撑板、所述第二支撑板、所述中间层支架以及多个所述封装半成品而使之成为整体结构；对所述第 一支撑板进行处理，以形成连接所述第二器件的所述引脚的焊盘，其中，所述焊盘作为所述封装体的引脚。In order to solve the above technical problems, a technical solution adopted by the present application is to provide a method for preparing a package body. The preparation method includes: preparing a package semi-finished product, wherein the package semi-finished product includes a substrate, a first device, and a second device. , A first plastic encapsulated body and a second plastic encapsulated body, the substrate includes a first surface and a second surface opposed to each other, and the first device and the second device are respectively disposed on the first surface and the second surface of the substrate In the above, the first plastic package body and the second plastic package body wrap the first device and the second device on the first surface and the second surface of the substrate, respectively, and the second plastic package body The pins of the second device are exposed; a plurality of semi-finished products of the package are fixed on the same side of the first support board, wherein the exposed pins of the second device face the first support board Place an intermediate layer support and a second support plate, wherein the intermediate layer support is provided on the side of the support plate where a plurality of semi-finished products of the package are provided, and the intermediate layer support has a plurality of semi-finished products with the package Corresponding through grooves, the semi-finished packaging products are respectively located in the corresponding through grooves, the second supporting plate is arranged on the side of the semi-finished packaging products away from the first supporting plate; the first supporting plate is pressed together , The second supporting board, the intermediate layer bracket, and a plurality of semi-finished products of the package to form an integral structure; processing the first supporting board to form the pins connecting the second device The pads, wherein the pads are used as pins of the package body.
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种封装体，所述封装体包括：基板，包括相对设置的第一表面以及第二表面；第一器件，设置于所述基板的第一表面；第二器件，设置于所述基板的第二表面；第一塑封体，用于将所述第一器件包裹在所述基板的第一表面；第二塑封体，用于将所述第二器件包裹在所述基板的第二表面，其中，所述第二塑封体裸露出所述第二器件的引脚；重布线层，设置于所述第二塑封体裸露出所述引脚一侧，所述重布线层包括连接所述引脚的焊盘，所述焊盘作为所述封装体的引脚。In order to solve the above technical problems, another technical solution adopted by the present application is to provide a package, the package includes: a substrate, including a first surface and a second surface disposed oppositely; and a first device disposed on the The first surface of the substrate; the second device is arranged on the second surface of the substrate; the first plastic package is used to wrap the first device on the first surface of the substrate; the second plastic package is used to Wrap the second device on the second surface of the substrate, wherein the second plastic package exposes the pins of the second device; the redistribution layer is provided in the exposed area of the second plastic package On one side of the pin, the redistribution layer includes a pad connected to the pin, and the pad serves as a pin of the package body.
本申请的有益效果是：本申请封装体的制备方法先封装多个封装半成品，而后再将多个封装半成品通过第一支撑板、中间层支架以及第二支撑板压合固定在一起后加工形成焊盘，即先对单个单元进行塑封，然后将多个封装后的单元固定在一起后再进行加工，从而相比现有技术中将所有器件固定在基板上后塑封形成整体结构再加工焊盘的方式，本实施方式由于是对单个单元进行塑封，在塑封过程中基板受到的应力较小，从而形成的封装半成品发生形变翘曲的程度较小，后续再形成焊盘的过程中对位更加准确，另外本申请制备的封装体中将第一器件以及第二器件相对基板纵向空间布局，能够实现封装尺寸小型化。The beneficial effect of the present application is: the preparation method of the package of the present application first encapsulates a plurality of semi-finished products of the package, and then presses and fixes the semi-finished products of the plurality of packages through the first support plate, the intermediate layer support and the second support plate, and then processed to form Pads, that is, a single unit is plastic-encapsulated, and then multiple encapsulated units are fixed together before processing. Compared with the prior art, all devices are fixed on the substrate and then plastic-encapsulated to form an overall structure and then the pads are processed In this embodiment, since a single unit is plastic-encapsulated, the substrate undergoes less stress during the plastic-encapsulation process, so that the semi-finished package that is formed has a smaller degree of deformation and warpage, and the alignment in the subsequent process of forming the pad is more It is accurate. In addition, in the package prepared by the present application, the first device and the second device are laid out in the longitudinal space of the substrate, which can realize the miniaturization of the package size.
【附图说明】【Explanation of the drawings】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained from these drawings without creative work. among them:
图1是本申请封装体的制备方法一实施方式的流程示意图；FIG. 1 is a schematic flowchart of an embodiment of a method for preparing a package of the present application;
图2是对应图1制备方法的部分制备过程图；Fig. 2 is a partial preparation process diagram corresponding to the preparation method of Fig. 1;
图3是一应用场景中封装半成品的结构示意图；FIG. 3 is a schematic diagram of the structure of encapsulating semi-finished products in an application scenario;
图4是一应用场景中图2的后续制备过程图；Fig. 4 is a subsequent preparation process diagram of Fig. 2 in an application scenario;
图5是另一应用场景中图2的后续制备过程图；Fig. 5 is a subsequent preparation process diagram of Fig. 2 in another application scenario;
图6是本申请封装体一实施方式的结构示意图；Fig. 6 is a schematic structural diagram of an embodiment of the package of the present application;
图7是本申请封装体另一实施方式的结构示意图。FIG. 7 is a schematic structural diagram of another embodiment of the package of the present application.
【具体实施方式】【detailed description】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by a person of ordinary skill in the art without creative work shall fall within the protection scope of this application.
参阅图1，图1是本申请封装体的制备方法一实施方式的流程示意图。结合图2，该封装体的制备方法包括：Refer to FIG. 1, which is a schematic flow chart of an embodiment of a method for manufacturing a package according to the present application. With reference to Figure 2, the preparation method of the package includes:
S110：制备封装半成品1000，其中，封装半成品1000包括基板1100、第一器件1200、第二器件1300、第一塑封体1400和第二塑封体1500，基板1100包括相对的第一表面1110和第二表面1120，第一器件1200和第二器件1300分别设置在基板1100的第一表面1110和第二表面1120上，第一塑封体1400和第二塑封体1500分别将第一器件1200和第二器件1300包裹在基板1100的第一表面1110和第二表面1120上，且第二塑封体1500裸露出第二器件1300的引脚1310。S110: Prepare the semi-finished package 1000, where the semi-finished package 1000 includes a substrate 1100, a first device 1200, a second device 1300, a first plastic package 1400, and a second plastic package 1500. The substrate 1100 includes a first surface 1110 and a second opposite surface. The surface 1120, the first device 1200 and the second device 1300 are respectively disposed on the first surface 1110 and the second surface 1120 of the substrate 1100. The first plastic package 1400 and the second plastic package 1500 separate the first device 1200 and the second device 1300 is wrapped on the first surface 1110 and the second surface 1120 of the substrate 1100, and the second plastic package 1500 exposes the pins 1310 of the second device 1300.
在本实施方式中，将第一器件1200封装在基板1100的一侧，将第二器件1300封装在基板1100的另一侧，即，将第一器件1200以及第二器件1300相对基板1100纵向空间布局，能够实现封装尺寸小型化。In this embodiment, the first device 1200 is packaged on one side of the substrate 1100, and the second device 1300 is packaged on the other side of the substrate 1100, that is, the first device 1200 and the second device 1300 are opposed to the longitudinal space of the substrate 1100. The layout can realize the miniaturization of the package size.
基板1100可以是印刷电路板、框架类基板等任何具有支撑作用的板件，其第一表面1110和第二表面1120上均设有输入/输出端口(图未示)，第一器件1200和第一表面1110上的输入/输出端口电连接，第二器件1300和第二表面1120上的输入/输出端口电连接。The substrate 1100 can be any supporting board such as a printed circuit board or a frame substrate. The first surface 1110 and the second surface 1120 are provided with input/output ports (not shown). The first device 1200 and the second surface 1120 are provided with input/output ports (not shown). The input/output ports on one surface 1110 are electrically connected, and the second device 1300 is electrically connected with the input/output ports on the second surface 1120.
在本实施方式中，第一器件1200为裸芯片，即未经过封装的芯片，第一器件1200包括功能面1210以及非功能面1220，功能面1210上设有输入/输出端口，非功能面1220上不设有输入/输出端口。在一应用场景中，如图2所示，第一器件1200以倒装的方式设置于基板1100的第一表面1110而实现与基板1100的电连接，即，第一器件1200的功能面1210朝向基板1100，且第一器件1200通过设置在功能面1210和基板1100之间的第一导电件1600而实现与基板1100的电连接，其中，第一导电件1600可以是锡球或者铜柱，在此不做限制。在另一应用场景中，如图3所示，第一器件1200以传统键合的方式设置于基板1100的第一表面1110而实现与基板1100的电连接，即，第一器件1200的功能面1210背向基板1100，且第一器件1200通过连接功能面1210与基板1100之间的焊线1230而实现与基板1100的电连接。其中，焊线1230可以是铜线、金线等具有导电性能的连接线。In this embodiment, the first device 1200 is a bare chip, that is, an unpackaged chip. The first device 1200 includes a functional surface 1210 and a non-functional surface 1220. The functional surface 1210 is provided with input/output ports and the non-functional surface 1220 There is no input/output port on it. In an application scenario, as shown in FIG. 2, the first device 1200 is disposed on the first surface 1110 of the substrate 1100 in a flip-chip manner to achieve electrical connection with the substrate 1100, that is, the functional surface 1210 of the first device 1200 faces The first device 1200 is electrically connected to the substrate 1100 through the first conductive member 1600 disposed between the functional surface 1210 and the substrate 1100. The first conductive member 1600 may be a tin ball or a copper pillar. This is not limited. In another application scenario, as shown in FIG. 3, the first device 1200 is disposed on the first surface 1110 of the substrate 1100 in a traditional bonding manner to achieve electrical connection with the substrate 1100, that is, the functional surface of the first device 1200 1210 faces away from the substrate 1100, and the first device 1200 is electrically connected to the substrate 1100 through a bonding wire 1230 connecting the functional surface 1210 and the substrate 1100. Wherein, the bonding wire 1230 may be a connecting wire with conductive properties such as a copper wire or a gold wire.
同时为了提高后续制成的封装体的散热性能，第一器件1200远离基板1100一侧还可以设有散热片1700，例如在图3应用场景中，第一器件1200的功能面1210上设有散热片1700。当然在某些应用场景中，例如图2应用场景中，也可以不设置散热片1700，在此不做限制。At the same time, in order to improve the heat dissipation performance of the subsequently manufactured package, the first device 1200 may also be provided with a heat sink 1700 on the side away from the substrate 1100. For example, in the application scenario of FIG. 3, the functional surface 1210 of the first device 1200 is provided with a heat sink.片1700. Of course, in some application scenarios, such as the application scenario in FIG. 2, the heat sink 1700 may not be provided, and there is no limitation here.
其中在其他实施方式中，第一器件1200的数量可以不止一个，其中除了裸芯片外，第一器件1200还可以是经过封装过的器件，例如，第一器件1200是经过封装过的电阻、电容或电感等器件。In other embodiments, the number of the first device 1200 may be more than one. In addition to a bare chip, the first device 1200 may also be a packaged device. For example, the first device 1200 is a packaged resistor and capacitor. Or inductors and other devices.
第二器件1300设置于基板1100的第二表面1120且与基板1100电连接，可选的，第二器件1300可以采用表面贴的方式安装于基板1100的第二表面1120。同时在本实施方式中，第二器件1300远离基板1100一侧的表面上设有引脚1310，第二塑封体1500裸露第二器件1300的引脚1310。当然在其他实施方式中，第二塑封体1500可以裸露的是第二器件1300其他表面的引脚1310，在此不做限制。The second device 1300 is disposed on the second surface 1120 of the substrate 1100 and is electrically connected to the substrate 1100. Optionally, the second device 1300 may be mounted on the second surface 1120 of the substrate 1100 in a surface mount manner. Meanwhile, in this embodiment, the second device 1300 is provided with pins 1310 on the surface of the side away from the substrate 1100, and the second plastic package 1500 exposes the pins 1310 of the second device 1300. Of course, in other embodiments, the pins 1310 on the other surface of the second device 1300 may be exposed by the second plastic package 1500, which is not limited here.
继续参阅图2，封装半成品1000的制备过程是：提供基板1100；在基板1100 的第一表面1110上设置第一器件1200；用塑封料对基板1100具有第一器件1200的一侧进行塑封，而形成包裹第一器件1200的第一塑封体1400；在基板1100的第二表面1120上设置第二器件1300；用塑封料对基板1100具有第二器件1300的一侧进行塑封，而形成包裹第二器件1300的第二塑封体1500；研磨第二塑封体1500而裸露出第二器件1300的引脚1310。Continuing to refer to FIG. 2, the preparation process of the packaged semi-finished product 1000 is: providing a substrate 1100; arranging the first device 1200 on the first surface 1110 of the substrate 1100; plastic-sealing the side of the substrate 1100 with the first device 1200 with a plastic molding compound, and A first plastic package body 1400 that wraps the first device 1200 is formed; a second device 1300 is arranged on the second surface 1120 of the substrate 1100; the side of the substrate 1100 with the second device 1300 is plastic-encapsulated with a plastic molding compound to form a package second The second plastic package body 1500 of the device 1300; the second plastic package body 1500 is ground to expose the pins 1310 of the second device 1300.
在一应用场景中，为了后续能够引出基板1100上更多的输入/输出端口，在形成第二塑封体1500之前，还包括：在基板1100的第二表面1120上形成第二导电件1800，第二导电件1800与基板1100电连接，而后研磨第二塑封体1500而同时裸露第二导电件1800的另一端以及第二器件1300的引脚1310。其中，第二导电件1800可以是铜柱或铜球等，在此不做限制。In an application scenario, in order to be able to subsequently draw out more input/output ports on the substrate 1100, before forming the second plastic package 1500, it further includes: forming a second conductive member 1800 on the second surface 1120 of the substrate 1100, and The two conductive members 1800 are electrically connected to the substrate 1100, and then the second plastic package body 1500 is ground to expose the other end of the second conductive member 1800 and the pins 1310 of the second device 1300 at the same time. Wherein, the second conductive member 1800 may be a copper pillar or a copper ball, etc., which is not limited here.
S120：将多个封装半成品1000固定在第一支撑板2000的同一侧上，其中，第二器件1300裸露出的引脚1310朝向第一支撑板2000。S120: Fix a plurality of package semi-finished products 1000 on the same side of the first support plate 2000, wherein the exposed pins 1310 of the second device 1300 face the first support plate 2000.
S130：放置中间层支架3000和第二支撑板4000，其中，中间层支架3000设置在支撑板2000设置有多个封装半成品1000的一侧上，中间层支架3000具有多个与封装半成品1000对应的通槽3100，封装半成品1000分别位于对应的通槽3100中，第二支撑板4000设置在封装半成品1000远离第一支撑板2000的一侧。S130: Place the intermediate layer support 3000 and the second support plate 4000, wherein the intermediate layer support 3000 is arranged on the side of the support plate 2000 where a plurality of package semi-finished products 1000 are provided, and the intermediate layer support 3000 has a plurality of corresponding to the package semi-finished products 1000 The through grooves 3100 and the semi-finished packaging product 1000 are respectively located in the corresponding through grooves 3100, and the second supporting plate 4000 is arranged on the side of the semi-finished packaging product 1000 away from the first supporting plate 2000.
S140：压合第一支撑板2000、第二支撑板4000、中间层支架3000以及多个封装半成品1000而使之成为整体结构。S140: Pressing the first support plate 2000, the second support plate 4000, the intermediate support 3000, and a plurality of package semi-finished products 1000 to form an integral structure.
S150：对第一支撑板2000进行处理，以形成连接第二器件1300的引脚1310的焊盘5200，其中，焊盘5200作为封装体6000的引脚。S150: Process the first support plate 2000 to form a pad 5200 connected to the pin 1310 of the second device 1300, where the pad 5200 serves as the pin of the package body 6000.
其中，第二支撑板4000为钢板等具有一定支撑强度的支撑板，中间层支架3000为具有一定支撑作用的框架。Among them, the second support plate 4000 is a support plate with a certain supporting strength such as a steel plate, and the middle layer bracket 3000 is a frame with a certain supporting effect.
结合图4，在第一应用场景中，第一支撑板2000为钢板等具有一定支撑强度的支撑板，第一支撑板2000的一侧覆盖有重布线层5000，步骤S120具体包括：将多个封装半成品1000固定于重布线层5000上，第二器件1300裸露出的 引脚1310朝向重布线层5000，且第二器件1300裸露出的引脚1310通过锡膏5100与重布线层5000电连接，也就是说，将第二器件1300裸露出的引脚1310通过锡膏5100焊接在重布线层5000上。其中，重布线层5000可以为铜箔。在一应用场景中，也将第二导电件1800的一端通过锡膏5100焊接在重布线层5000上。With reference to FIG. 4, in the first application scenario, the first support plate 2000 is a support plate with a certain support strength such as a steel plate, and one side of the first support plate 2000 is covered with a redistribution layer 5000. Step S120 specifically includes: The packaged semi-finished product 1000 is fixed on the redistribution layer 5000, the exposed pins 1310 of the second device 1300 face the redistribution layer 5000, and the exposed pins 1310 of the second device 1300 are electrically connected to the redistribution layer 5000 through the solder paste 5100, In other words, the exposed pins 1310 of the second device 1300 are soldered on the redistribution layer 5000 through the solder paste 5100. Among them, the rewiring layer 5000 may be copper foil. In an application scenario, one end of the second conductive member 1800 is also soldered on the redistribution layer 5000 through the solder paste 5100.
具体地，通过印刷锡膏5100、贴片以及回流焊等操作而将将多个封装半成品1000固定于重布线层5000上。Specifically, a plurality of package semi-finished products 1000 are fixed on the rewiring layer 5000 through operations such as printing solder paste 5100, patching, and reflow soldering.
在该应用场景中，步骤S130中还包括：在中间层支架3000与封装半成品1000之间的缝隙中填充绝缘材料4100，以便于后续在压合第一支撑板2000、第二支撑板4000、中间层支架3000以及多个封装半成品1000时能够使之成为整体结构。其中绝缘材料4100可以是半固化片等具有粘性的材料，在此不做限制。In this application scenario, step S130 also includes: filling the gap between the intermediate layer support 3000 and the semi-finished package 1000 with an insulating material 4100 to facilitate subsequent pressing of the first support plate 2000, the second support plate 4000, and the intermediate The layer bracket 3000 and a plurality of encapsulated semi-finished products 1000 can be integrated into a structure. The insulating material 4100 may be a prepreg and other adhesive materials, which is not limited here.
在该应用场景中，步骤S150具体包括：去除第一支撑板2000，图案重布线层5000而形成连接第二器件1300的引脚1310的焊盘5200。In this application scenario, step S150 specifically includes: removing the first support plate 2000 and patterning the redistribution layer 5000 to form a pad 5200 connected to the pin 1310 of the second device 1300.
其中，图案重布线层5000的具体过程为：蚀刻以及对重布线层5000进行表面处理而形成焊盘5200。Among them, the specific process of the patterned redistribution layer 5000 is: etching and surface treatment of the redistribution layer 5000 to form the pad 5200.
在第二应用场景中，如图5所示，第一支撑板2000也为钢板等具有一定支撑强度的支撑板，与第一应用场景不同的是，此时第一支撑板2000不覆盖有重布线层5000，此时步骤S120具体包括：将多个封装半成品1000通过绝缘胶2100(其他应用场景中也可以是绝缘膜，例如为DAF膜)固定在第一支撑板2000的同一侧上。In the second application scenario, as shown in FIG. 5, the first support plate 2000 is also a support plate with a certain support strength such as steel plate. The difference from the first application scenario is that the first support plate 2000 is not covered with heavy weight. The wiring layer 5000, at this time, step S120 specifically includes: fixing a plurality of semi-finished packaging products 1000 on the same side of the first support plate 2000 through insulating glue 2100 (in other application scenarios, it may also be an insulating film, such as a DAF film).
步骤S150具体包括：去除第一支撑板2000以及绝缘胶2100；在多个封装半成品1000暴露第二器件1300的引脚1310一侧形成重布线层5000；图案重布线层5000而形成连接第二器件1300的引脚1310的焊盘5200。Step S150 specifically includes: removing the first support plate 2000 and the insulating glue 2100; forming a redistribution layer 5000 on the side of the pins 1310 of the second device 1300 of the plurality of packaged semi-finished products 1000; and patterning the redistribution layer 5000 to form a connection to the second device 1300 pin 1310 pad 5200.
其中，形成重布线层5000的方式可以是将预先制备好的重布线层5000压合在封装半成品1000暴露引脚1310的一侧，或者，采用溅射、气相沉积等方式在封装半成品1000暴露引脚1310的一侧形成重布线层5000，在此不做限制。 其中，重布线层5000的材料可以是铜、铝等导电材料，在此不做限制。Wherein, the method of forming the rewiring layer 5000 may be to press the pre-prepared rewiring layer 5000 on the side of the exposed pin 1310 of the semi-finished package 1000, or use sputtering, vapor deposition, etc. to expose the lead on the semi-finished package 1000. The rewiring layer 5000 is formed on one side of the pin 1310, which is not limited here. Wherein, the material of the redistribution layer 5000 can be conductive materials such as copper, aluminum, etc., which is not limited here.
可以理解的是，分别采用上述第一应用场景和第二应用场景的制备方法制备的封装体6000结构不同，具体为：采用第一应用场景制备的封装体6000包括设置在第二塑封体1500和重布线层5000之间的锡膏5100以及围绕锡膏5100的绝缘材料4100，采用第二应用场景制备的封装体6000则不包括锡膏5100以及围绕锡膏5100的绝缘材料4100，此时第二器件1300的引脚1310直接与重布线层5000电连接。It is understandable that the structure of the package 6000 prepared by the preparation method of the first application scenario and the second application scenario is different, specifically: the package 6000 prepared by the first application scenario includes the second plastic package 1500 and The solder paste 5100 between the rewiring layers 5000 and the insulating material 4100 surrounding the solder paste 5100. The package 6000 prepared in the second application scenario does not include the solder paste 5100 and the insulating material 4100 surrounding the solder paste 5100. At this time, the second The pin 1310 of the device 1300 is directly electrically connected to the redistribution layer 5000.
结合图4和图5，在本实施方式中，在形成焊盘5200后，还包括：去除第二支撑板4000；研磨多个封装半成品1000的第一塑封体1400而暴露第一器件1200的非功能面1220；切割中间层支架3000以及图案后的重布线层5000而得到多个封装体6000。With reference to FIGS. 4 and 5, in this embodiment, after the bonding pad 5200 is formed, the method further includes: removing the second support plate 4000; grinding the first plastic encapsulation body 1400 of a plurality of encapsulated semi-finished products 1000 to expose the non-irregularities of the first device 1200 Functional surface 1220; cutting the intermediate layer support 3000 and the patterned redistribution layer 5000 to obtain a plurality of packages 6000.
具体地，通过暴露第一器件1200的非功能面1220能够实现封装体6000的双面垂直散热：一面是通过第一器件1200的非功能面1220进行散热，另一面是通过与第二器件1300电连接的焊盘5200进行散热，散热效果更佳。Specifically, by exposing the non-functional surface 1220 of the first device 1200, the double-sided vertical heat dissipation of the package 6000 can be realized: one side is through the non-functional surface 1220 of the first device 1200 for heat dissipation, and the other side is through the electrical connection with the second device 1300. The connected pad 5200 dissipates heat, and the heat dissipation effect is better.
可以理解的是，在其他实施方式中，也可以不用研磨多个封装半成品1000的第一塑封体1400而暴露第一器件1200的非功能面1220，即此时，第一器件1200的各个表面均被第一塑封体1400包裹。It is understandable that, in other embodiments, the non-functional surface 1220 of the first device 1200 may be exposed without grinding the first plastic encapsulation body 1400 of the plurality of semi-finished products 1000. That is, at this time, each surface of the first device 1200 is uniform. It is wrapped by the first plastic package 1400.
可以理解的是，当第一器件1200远离基板1100一侧设有散热片1700时，在研磨第一塑封体1400后，最终暴露的是散热片1700远离第一器件1200一侧表面。It can be understood that when the first device 1200 is provided with a heat sink 1700 on the side away from the substrate 1100, after grinding the first plastic package 1400, the surface of the heat sink 1700 far away from the first device 1200 is finally exposed.
从上述内容可以看出，在本实施方式中，先封装多个封装半成品1000，而后再将多个封装半成品1000通过第一支撑板2000、中间层支架3000以及第二支撑板4000压合固定在一起后加工形成焊盘5200，即先对单个单元进行塑封，然后将多个封装后的单元固定在一起后再进行加工，从而相比现有技术将所有器件固定在基板上后整体塑封形成整体结构再加工焊盘的方式，本实施方式由于是对单个单元进行塑封，在塑封过程中基板1100受到的应力较小，从而形成 的封装半成品1000发生形变翘曲的程度较小，后续再形成焊盘5200的过程中对位更加准确，保证形成的封装体6000通流能力更好。It can be seen from the above that, in this embodiment, a plurality of semi-finished packaging products 1000 are packaged first, and then the semi-finished packaging products 1000 are press-fitted and fixed on the first support plate 2000, the intermediate support 3000, and the second support plate 4000. The bonding pad 5200 is formed by post-processing together, that is, a single unit is plastic-encapsulated first, and then multiple encapsulated units are fixed together before processing. Compared with the prior art, all the devices are fixed on the substrate and the whole is plastic-encapsulated to form a whole In the method of reprocessing the bonding pads of the structure, in this embodiment, since a single unit is plastic-encapsulated, the substrate 1100 receives less stress during the plastic-encapsulation process, so that the resulting package semi-finished product 1000 has a smaller degree of deformation and warping, and subsequent soldering is formed. The alignment of the disk 5200 is more accurate, which ensures that the formed package 6000 has a better flow capacity.
同时在本实施方式中，通过重新形成焊盘5200而作为封装体6000的引脚，相比直接将第二器件1300的引脚1310作为封装体6000的引脚，本实施方式可以扩大封装体6000引脚的面积，从而当封装体6000通过引脚焊接于其他元件上时，可以增大封装体6000与其他元件的结合力，提高焊接可靠性。At the same time, in this embodiment, the pad 5200 is newly formed as the pins of the package 6000. Compared with directly using the pins 1310 of the second device 1300 as the pins of the package 6000, this embodiment can expand the package 6000. The area of the pins, so that when the package body 6000 is soldered to other components through the pins, the bonding force between the package body 6000 and other components can be increased, and the soldering reliability can be improved.
同时在本实施方式中，在形成焊盘5200之前，压合第一支撑板2000、第二支撑板4000、中间层支架3000以及多个封装半成品1000而使之成为整体结构，可以保证后续形成的焊盘5200与第二器件1300的结合力，也能保证后续焊接封装体6000的可靠性。At the same time, in this embodiment, before forming the pad 5200, the first support plate 2000, the second support plate 4000, the intermediate layer support 3000 and a plurality of package semi-finished products 1000 are pressed together to form an integral structure, which can ensure the subsequent formation The bonding force between the bonding pad 5200 and the second device 1300 can also ensure the reliability of subsequent welding of the package body 6000.
其中，在其他实施方式中，在步骤S150中也可以是直接对第一支撑板2000进行蚀刻、表面处理而得到连接第二器件1300的引脚1310的焊盘5200，此时第一支撑板2000的材料为导电材料，例如铜等，且在步骤S120中需要将第二器件1300裸露出的引脚1310与第一支撑板2000电连接。Wherein, in other embodiments, in step S150, the first support plate 2000 may also be directly etched and surface treated to obtain the pad 5200 connected to the pin 1310 of the second device 1300. At this time, the first support plate 2000 The material of is a conductive material, such as copper, and it is necessary to electrically connect the exposed pin 1310 of the second device 1300 with the first support plate 2000 in step S120.
其中，在其他实施方式中，在步骤S150之后还可以不对中间层支架3000等元件进行切割，也就是说，最后形成的封装体6000中包括多个封装体半成品1000。Wherein, in other embodiments, after step S150, the intermediate layer bracket 3000 and other components may not be cut, that is, the package 6000 that is finally formed includes a plurality of package semi-finished products 1000.
参阅图6，图6是本申请封装体一实施方式的结构示意图。该封装体7000包括：基板7100、第一器件7200、第二器件7300、第一塑封体7400、第二塑封体7500以及重布线层7600。Refer to FIG. 6, which is a schematic structural diagram of an embodiment of the package of the present application. The package 7000 includes a substrate 7100, a first device 7200, a second device 7300, a first plastic package 7400, a second plastic package 7500, and a redistribution layer 7600.
基板7100包括相对设置的第一表面7110以及第二表面7120；第一器件7200设置于基板7100的第一表面7110；第二器件7300设置于基板7100的第二表面7120；第一塑封体7400用于将第一器件7200包裹在基板7100的第一表面7110；第二塑封体7500用于将第二器件7300包裹在基板7100的第二表面7120，其中，第二塑封体7500裸露出第二器件7300的引脚7310；重布线层7600设置于第二塑封体7500裸露出引脚7310一侧，重布线层7600包括连接引脚7310的焊盘 7610，焊盘7610作为封装体7000的引脚7310。The substrate 7100 includes a first surface 7110 and a second surface 7120 disposed oppositely; the first device 7200 is disposed on the first surface 7110 of the substrate 7100; the second device 7300 is disposed on the second surface 7120 of the substrate 7100; the first plastic package body 7400 is used To wrap the first device 7200 on the first surface 7110 of the substrate 7100; the second plastic package 7500 is used to wrap the second device 7300 on the second surface 7120 of the substrate 7100, wherein the second plastic package 7500 exposes the second device The pin 7310 of the 7300; the redistribution layer 7600 is arranged on the side of the second plastic package 7500 that exposes the pin 7310. The redistribution layer 7600 includes the pad 7610 connected to the pin 7310, and the pad 7610 is used as the pin 7310 of the package 7000 .
在一应用场景中，继续参阅图6，封装体7000还包括：焊接层7700。In an application scenario, continuing to refer to FIG. 6, the package body 7000 further includes: a soldering layer 7700.
焊接层7700设置于第二塑封体7500与重布线层7600之间，焊接层7700包括锡膏7710以及围绕锡膏7710的绝缘材料7720，锡膏7710电连接第二器件7300的引脚7310与重布线层7600的焊盘7610。The soldering layer 7700 is disposed between the second plastic package 7500 and the redistribution layer 7600. The soldering layer 7700 includes a solder paste 7710 and an insulating material 7720 surrounding the solder paste 7710. The solder paste 7710 is electrically connected to the pins 7310 of the second device 7300 and the rewiring layer 7600. The pad 7610 of the wiring layer 7600.
在其他实施方式中，如图7所示，封装体7000也可以不包括焊接层7700，此时第二器件7300的引脚7310直接与重布线层7600的焊盘7610连接。In other embodiments, as shown in FIG. 7, the package 7000 may not include the soldering layer 7700. In this case, the pins 7310 of the second device 7300 are directly connected to the pads 7610 of the redistribution layer 7600.
继续参阅图6和图7，在一应用场景中，第二塑封体7500远离基板7100一侧裸露第二器件7300的引脚7310。当然在其他应用场景中，第二塑封体7500也可以是裸露第二器件7300其他表面的引脚7310，在此不做限制。Continuing to refer to FIGS. 6 and 7, in an application scenario, the side of the second plastic encapsulation body 7500 away from the substrate 7100 exposes the pins 7310 of the second device 7300. Of course, in other application scenarios, the second plastic encapsulation body 7500 may also be the pins 7310 exposed on other surfaces of the second device 7300, which is not limited here.
继续参阅图6和图7，封装体7000还包括：第一导电件7800。Continuing to refer to FIGS. 6 and 7, the package body 7000 further includes: a first conductive member 7800.
第一导电件7800的一端设置于基板7100的第二表面7120而实现第一导电件7800与基板7100的电连接，第一导电件7800的另一端连通至第二塑封体7500的外部。One end of the first conductive member 7800 is disposed on the second surface 7120 of the substrate 7100 to achieve electrical connection between the first conductive member 7800 and the substrate 7100, and the other end of the first conductive member 7800 is connected to the outside of the second plastic package 7500.
第一器件7200为裸芯片，第一器件7200包括相对设置的功能面7210以及非功能面7220，在一应用场景中，如图6所示，第一器件7200的功能面7210朝向基板7100，第一器件7200通过设置在功能面7210和基板7100之间的第二导电件7900而实现与基板7100的电连接，其中，第一塑封体7400暴露第一器件7200的非功能面7220，其中，第二导电件7900为锡球或铜柱；在另一应用场景中，如图7所示，第一器件7200的功能面7210背离基板7100，第一器件7200通过连接功能面7210和基板7100的焊线7240而实现与基板7100的电连接，同时在该应用场景中，封装体7000还包括散热片7230，散热片7230设置于第一器件7200的功能面7210上，第一塑封体7400暴露散热片7230远离第一器件7200一侧的表面。The first device 7200 is a bare chip. The first device 7200 includes a functional surface 7210 and a non-functional surface 7220 arranged oppositely. In an application scenario, as shown in FIG. 6, the functional surface 7210 of the first device 7200 faces the substrate 7100. A device 7200 is electrically connected to the substrate 7100 through a second conductive member 7900 disposed between the functional surface 7210 and the substrate 7100, wherein the first plastic encapsulation body 7400 exposes the non-functional surface 7220 of the first device 7200, wherein the first plastic package 7400 exposes the non-functional surface 7220 of the first device 7200. The second conductive element 7900 is a tin ball or a copper pillar; in another application scenario, as shown in FIG. 7, the functional surface 7210 of the first device 7200 is away from the substrate 7100, and the first device 7200 connects the functional surface 7210 and the substrate 7100 by soldering Wire 7240 to achieve electrical connection with the substrate 7100. At the same time, in this application scenario, the package body 7000 further includes a heat sink 7230. The heat sink 7230 is disposed on the functional surface 7210 of the first device 7200, and the first plastic package body 7400 exposes the heat sink. 7230 is away from the surface on the side of the first device 7200.
其中，在一应用场景中，第一器件7200的数量为多个，除了裸芯片外，多个第一器件7200还包括经过封装过的器件，例如经过封装过的电阻、电容或电 感等器件。In an application scenario, there are multiple first devices 7200. In addition to bare chips, the multiple first devices 7200 also include packaged devices, such as packaged resistors, capacitors, or inductors.
其中，本实施方式中的封装体采用上述实施方式中的封装体的制备方法制备，详细的制备方法可参见上述实施方式，在此不再赘述。Wherein, the package body in this embodiment is prepared by the method for preparing the package body in the above embodiment, and the detailed preparation method can be referred to the above embodiment, which will not be repeated here.
总而言之，本申请封装体的制备方法先封装多个封装半成品，而后再将多个封装半成品通过第一支撑板、中间层支架以及第二支撑板压合固定在一起后加工形成焊盘，即先对单个单元进行塑封，然后将多个封装后的单元固定在一起后再进行加工，从而相比现有技术中，将所有器件固定在基板上后塑封形成整体结构而加工的方式，本实施方式由于是对单个单元进行塑封，在塑封过程中基板受到的应力较小，从而形成的封装半成品发生形变翘曲的程度较小，后续再形成焊盘的过程中对位更加准确，另外本申请制备的封装体中将第一器件以及第二器件相对基板纵向空间布局，能够实现封装尺寸小型化。In a word, the preparation method of the package body of the present application first encapsulates a plurality of semi-finished products of the package, and then presses and fixes the semi-finished products of the plurality of packages through the first support plate, the intermediate layer support and the second support plate, and then processes them to form the bonding pads. A single unit is plastic-encapsulated, and then multiple encapsulated units are fixed together before processing. Compared with the prior art, all devices are fixed on the substrate and then plastic-encapsulated to form an integrated structure. This embodiment Since a single unit is plastic-encapsulated, the substrate receives less stress during the plastic-encapsulation process, so that the semi-finished package that is formed has a smaller degree of deformation and warpage, and the subsequent process of forming the pad is more accurate. In addition, this application prepares In the package body, the first device and the second device are arranged relative to the longitudinal space of the substrate, so that the package size can be miniaturized.
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。The above are only implementations of this application, and do not limit the scope of this application. Any equivalent structure or equivalent process transformation made using the content of the description and drawings of this application, or directly or indirectly applied to other related technologies In the same way, all fields are included in the scope of patent protection of this application.

Claims (16)

  1. 一种封装体的制备方法，其特征在于，包括：A method for preparing a package, which is characterized in that it comprises:
    制备封装半成品，其中，所述封装半成品包括基板、第一器件、第二器件、第一塑封体和第二塑封体，所述基板包括相对的第一表面和第二表面，所述第一器件和所述第二器件分别设置在所述基板的第一表面和第二表面上，所述第一塑封体和所述第二塑封体分别将所述第一器件和所述第二器件包裹在所述基板的第一表面和第二表面上，且所述第二塑封体裸露出所述第二器件的引脚；A package semi-finished product is prepared, wherein the package semi-finished product includes a substrate, a first device, a second device, a first plastic packaged body, and a second plastic packaged body, the substrate includes a first surface and a second surface opposite to each other, and the first device And the second device are respectively disposed on the first surface and the second surface of the substrate, and the first plastic package body and the second plastic package body respectively wrap the first device and the second device in On the first surface and the second surface of the substrate, and the second plastic package body exposes the pins of the second device;
    将多个所述封装半成品固定在第一支撑板的同一侧上，其中，所述第二器件裸露出的所述引脚朝向所述第一支撑板；Fixing a plurality of semi-finished packaging products on the same side of the first supporting board, wherein the exposed pins of the second device face the first supporting board;
    放置中间层支架和第二支撑板，其中，所述中间层支架设置在所述支撑板设置有多个所述封装半成品的一侧上，所述中间层支架具有多个与所述封装半成品对应的通槽，所述封装半成品分别位于对应的所述通槽中，所述第二支撑板设置在所述封装半成品远离所述第一支撑板的一侧；An intermediate layer support and a second support plate are placed, wherein the intermediate layer support is arranged on a side of the support plate where a plurality of the semi-finished products of the package are arranged, and the intermediate layer support has a plurality of corresponding to the semi-finished products of the package. The semi-finished packaging products are respectively located in the corresponding through-slots, and the second support plate is arranged on a side of the semi-finished packaging products away from the first support plate;
    压合所述第一支撑板、所述第二支撑板、所述中间层支架以及多个所述封装半成品而使之成为整体结构；Pressing the first supporting plate, the second supporting plate, the intermediate layer bracket and a plurality of semi-finished products of the packaging to form an integral structure;
    对所述第一支撑板进行处理，以形成连接所述第二器件的所述引脚的焊盘，其中，所述焊盘作为所述封装体的引脚。The first support board is processed to form a pad connected to the pin of the second device, wherein the pad serves as a pin of the package body.
  2. 根据权利要求1所述的制备方法，其特征在于，所述第一支撑板一侧覆盖有重布线层；The manufacturing method according to claim 1, wherein one side of the first support plate is covered with a redistribution layer;
    所述将多个所述封装半成品固定在第一支撑板的同一侧上的步骤，包括：The step of fixing a plurality of semi-finished packaging products on the same side of the first support plate includes:
    将多个所述封装半成品均固定于所述重布线层上，其中，所述第二器件裸露出的所述引脚朝向所述重布线层，且所述第二器件裸露出的所述引脚与所述重布线层电连接；The plurality of semi-finished products of the package are all fixed on the redistribution layer, wherein the exposed pins of the second device face the redistribution layer, and the exposed leads of the second device The feet are electrically connected to the redistribution layer;
    所述对所述第一支撑板进行处理，以形成连接所述第二器件的所述引脚的焊盘的步骤，包括：The step of processing the first support plate to form a pad connecting the pins of the second device includes:
    去除所述第一支撑板；Removing the first support plate;
    图案所述重布线层而形成连接所述第二器件的所述引脚的所述焊盘。The redistribution layer is patterned to form the pad connecting the lead of the second device.
  3. 根据权利要求1所述的制备方法，其特征在于，The preparation method according to claim 1, wherein:
    所述将多个所述封装半成品固定在第一支撑板的同一侧上的步骤，包括：The step of fixing a plurality of semi-finished packaging products on the same side of the first support plate includes:
    将多个所述封装半成品通过绝缘膜或绝缘胶固定在所述第一支撑板的同一侧上；Fixing a plurality of semi-finished products of the package on the same side of the first support plate through an insulating film or an insulating glue;
    所述对所述第一支撑板进行处理，以形成连接所述第二器件的所述引脚的焊盘的步骤，包括：The step of processing the first support plate to form a pad connecting the pins of the second device includes:
    去除所述第一支撑板以及所述绝缘膜或所述绝缘胶；Removing the first support plate and the insulating film or the insulating glue;
    在多个所述封装半成品暴露所述第二器件的所述引脚一侧形成重布线层；Forming a rewiring layer on the side of the plurality of semi-finished packaging products where the pins of the second device are exposed;
    图案所述重布线层而形成连接所述第二器件的所述引脚的所述焊盘。The redistribution layer is patterned to form the pad connecting the lead of the second device.
  4. 根据权利要求3所述的制备方法，其特征在于，所述在多个所述封装半成品暴露所述第二器件的所述引脚一侧形成重布线层的步骤，包括：3. The manufacturing method according to claim 3, wherein the step of forming a rewiring layer on the side of the plurality of semi-finished packaging products where the pins of the second device are exposed, comprises:
    采用溅射或气相沉积工艺在多个所述封装半成品暴露所述第二器件的所述引脚一侧形成所述重布线层，或，将预先制备的所述重布线层压合在多个所述封装半成品暴露所述第二器件的所述引脚一侧。Sputtering or vapor deposition process is used to form the redistribution layer on the side of a plurality of semi-finished packaging products that exposes the pins of the second device, or the redistribution layer prepared in advance is laminated on a plurality of The package semi-finished product exposes one side of the pin of the second device.
  5. 根据权利要求2或3所述的制备方法，其特征在于，所述方法还包括：The preparation method according to claim 2 or 3, wherein the method further comprises:
    去除所述第二支撑板；Removing the second support plate;
    切割所述中间层支架以及图案后的所述重布线层而得到多个所述封装体。Cutting the intermediate layer support and the patterned redistribution layer to obtain a plurality of the packages.
  6. 根据权利要求1所述的制备方法，其特征在于，所述第二塑封体远离所述基板一侧裸露出所述第二器件的所述引脚，以及，所述第一器件为裸芯片，所述第一器件包括相对设置的功能面以及非功能面，所述第一器件的所述功能面朝向所述基板，所述第一器件通过设置在所述功能面和所述基板之间的第一导电件而实现与所述基板的电连接；The manufacturing method of claim 1, wherein the second plastic package body exposes the pins of the second device on a side away from the substrate, and the first device is a bare chip, The first device includes a functional surface and a non-functional surface that are arranged oppositely, the functional surface of the first device faces the substrate, and the first device passes through the functional surface and the non-functional surface disposed between the functional surface and the substrate. The first conductive member realizes electrical connection with the substrate;
    所述方法还包括：The method also includes:
    去除所述第二支撑板；Removing the second support plate;
    研磨多个所述封装半成品的所述第一塑封体而暴露所述第一器件的所述非 功能面。Grinding the first plastic encapsulation bodies of a plurality of semi-finished products of the package to expose the non-functional surface of the first device.
  7. 根据权利要求1所述的制备方法，其特征在于，所述制备封装半成品的步骤，包括：The preparation method according to claim 1, wherein the step of preparing a semi-finished product package comprises:
    提供所述基板；Provide the substrate;
    在所述基板的所述第一表面上设置所述第一器件；Disposing the first device on the first surface of the substrate;
    用塑封料对所述基板具有所述第一器件的一侧进行塑封，而形成包裹所述第一器件的第一塑封体；Plastic-encapsulating the side of the substrate with the first device with a plastic molding compound to form a first plastic-encapsulated body that wraps the first device;
    在所述基板的所述第二表面上设置所述第二器件；Disposing the second device on the second surface of the substrate;
    用塑封料对所述基板具有所述第二器件的一侧进行塑封，而形成包裹所述第二器件的第二塑封体；Plastic-encapsulating the side of the substrate with the second device with a plastic molding compound to form a second plastic-encapsulated body that wraps the second device;
    研磨所述第二塑封体而裸露出所述第二器件的所述引脚。Grinding the second plastic package body to expose the pins of the second device.
  8. 根据权利要求7所述的制备方法，其特征在于，所述第二塑封体远离所述基板一侧裸露出所述第二器件的所述引脚，7. The manufacturing method according to claim 7, wherein the second plastic package body exposes the pins of the second device on a side away from the substrate,
    在所述用塑封料对所述基板具有所述第二器件的一侧进行塑封，而形成包裹所述第二器件的第二塑封体之前，还包括：Before the plastic molding compound is used to mold the side of the substrate with the second device to form a second plastic package that wraps the second device, the method further includes:
    在所述基板的所述第二表面上形成与所述基板电连接的第二导电件；Forming a second conductive element electrically connected to the substrate on the second surface of the substrate;
    所述研磨所述第二塑封体而裸露出所述第二器件的所述引脚的步骤，包括：The step of grinding the second plastic package body to expose the pins of the second device includes:
    研磨所述第二塑封体而裸露出所述第二器件的所述引脚以及所述第二导电件。Grinding the second plastic package body to expose the pins of the second device and the second conductive element.
  9. 根据权利要求1所述的制备方法，其特征在于，所述放置中间层支架和第二支撑板的步骤，包括：The preparation method according to claim 1, wherein the step of placing the intermediate layer support and the second support plate comprises:
    放置所述中间层支架，并在所述中间层支架与所述封装半成品之间填充绝缘材料；Placing the intermediate layer support, and filling an insulating material between the intermediate layer support and the semi-finished packaging product;
    放置所述第二支撑板。Place the second support plate.
  10. 根据权利要求1所述的制备方法，其特征在于，所述第二塑封体远离所述基板一侧裸露出所述第二器件的所述引脚，以及，所述封装半成品还包括散 热片，设置于所述第一器件远离所述基板一侧；The manufacturing method of claim 1, wherein the second plastic package body exposes the pins of the second device on a side away from the substrate, and the semi-finished package further includes a heat sink, Arranged on the side of the first device away from the substrate;
    所述方法还包括：The method also includes:
    去除所述第二支撑板；Removing the second support plate;
    研磨多个所述封装半成品的所述第一塑封体而暴露散热片。Grinding the first plastic encapsulation bodies of a plurality of semi-finished products of the package to expose the heat sink.
  11. 一种封装体，其特征在于，包括：A package is characterized in that it comprises:
    基板，包括相对设置的第一表面以及第二表面；The substrate includes a first surface and a second surface that are opposed to each other;
    第一器件，设置于所述基板的第一表面；The first device is arranged on the first surface of the substrate;
    第二器件，设置于所述基板的第二表面；The second device is arranged on the second surface of the substrate;
    第一塑封体，用于将所述第一器件包裹在所述基板的第一表面；The first plastic package is used to wrap the first device on the first surface of the substrate;
    第二塑封体，用于将所述第二器件包裹在所述基板的第二表面，其中，所述第二塑封体裸露出所述第二器件的引脚；The second plastic package is used to wrap the second device on the second surface of the substrate, wherein the second plastic package exposes the pins of the second device;
    重布线层，设置于所述第二塑封体裸露出所述引脚一侧，所述重布线层包括连接所述引脚的焊盘，所述焊盘作为所述封装体的引脚。The redistribution layer is arranged on the side of the second plastic package body that exposes the pins, and the redistribution layer includes pads connected to the pins, and the pads serve as pins of the package body.
  12. 根据权利要求11所述的封装体，其特征在于，所述封装体还包括：The package body according to claim 11, wherein the package body further comprises:
    焊接层，设置于所述第二塑封体与所述重布线层之间，所述焊接层包括锡膏以及围绕所述锡膏的绝缘材料，所述锡膏电连接所述第二器件的所述引脚与所述重布线层的所述焊盘。The soldering layer is arranged between the second plastic package and the redistribution layer. The soldering layer includes a solder paste and an insulating material surrounding the solder paste, and the solder paste is electrically connected to all of the second device. The pin and the pad of the redistribution layer.
  13. 根据权利要求11所述的封装体，其特征在于，所述第二塑封体远离所述基板一侧裸露所述第二器件的所述引脚。11. The package according to claim 11, wherein the second plastic encapsulation body exposes the pins of the second device on a side away from the substrate.
  14. 根据权利要求13所述的封装体，其特征在于，所述封装体还包括：The package body according to claim 13, wherein the package body further comprises:
    第一导电件，所述第一导电件的一端设置于所述基板的第二表面而实现所述第一导电件与所述基板的电连接，所述第一导电件的另一端连通至所述第二塑封体的外部。The first conductive member, one end of the first conductive member is disposed on the second surface of the substrate to realize the electrical connection between the first conductive member and the substrate, and the other end of the first conductive member is connected to the substrate The exterior of the second plastic packaged body.
  15. 根据权利要求13所述的封装体，其特征在于，所述第一器件为裸芯片，所述第一器件包括相对设置的功能面以及非功能面，所述第一器件的所述功能面朝向所述基板，所述第一器件通过设置在所述功能面和所述基板之间的第二 导电件而实现与所述基板的电连接，其中，所述第一塑封体暴露所述第一器件的所述非功能面。The package according to claim 13, wherein the first device is a bare chip, and the first device includes a functional surface and a non-functional surface disposed oppositely, and the functional surface of the first device faces In the substrate, the first device is electrically connected to the substrate through a second conductive member disposed between the functional surface and the substrate, wherein the first plastic package exposes the first The non-functional surface of the device.
  16. 根据权利要求13所述的封装体，其特征在于，所述第一器件为裸芯片，所述第一器件包括相对设置的功能面以及非功能面，所述第一器件的所述功能面背离所述基板，所述第一器件通过连接所述功能面和所述基板的焊线而实现与所述基板的电连接，同时所述封装体还包括：The package according to claim 13, wherein the first device is a bare chip, and the first device includes a functional surface and a non-functional surface disposed oppositely, and the functional surface of the first device is away from In the substrate, the first device is electrically connected to the substrate through a bonding wire connecting the functional surface and the substrate, and the package body further includes:
    散热片，设置于所述第一器件的所述功能面上，所述第一塑封体暴露所述散热片远离所述第一器件一侧的表面。The heat sink is arranged on the functional surface of the first device, and the first plastic package exposes the surface of the heat sink on the side away from the first device.
PCT/CN2020/112226 2019-08-30 2020-08-28 Package body and preparation method therefor WO2021037233A1 (en)

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CN107749411A (en) * 2017-09-25 2018-03-02 江苏长电科技股份有限公司 Two-sided SiP three-dimension packaging structure
CN211150513U (en) * 2019-08-30 2020-07-31 无锡天芯互联科技有限公司 Package body

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