WO2021036518A1

WO2021036518A1 - Fast-locking phase-locked loop circuit for avoiding cycle slip

Info

Publication number: WO2021036518A1
Application number: PCT/CN2020/100641
Authority: WO
Inventors: 徐志伟; 陈姜波; 刘嘉冰; 聂辉; 吕志浩
Original assignee: 浙江大学
Priority date: 2019-08-30
Filing date: 2020-07-07
Publication date: 2021-03-04
Also published as: JP7257711B2; CN110474634B; JP2022521346A; CN110474634A

Abstract

Disclosed is a fast-locking phase-locked loop circuit for avoiding a cycle slip, wherein same belongs to the technical field of integrated circuits. The fast-locking phase-locked loop circuit comprises: a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator (VCO) and a frequency divider, wherein the phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output (OUT) end of the voltage-controlled oscillator is connected to an input (IN) end of the frequency divider; and an output (OUT) end of the frequency divider is connected to an input (IN) end of the phase frequency detector to form a feedback path. According to the present invention, by means of adjusting an initial output frequency of a VCO, an output clock frequency of the VCO being too close to an expected frequency, that is, a reference clock frequency being too close to a feedback clock frequency, is prevented when a loop is enabled, such that the locking time is greatly prolonged when a cycle slip occurs in the loop.

Description

A fast-locking phase-locked loop circuit for avoiding cycle slip

Technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a fast-locking phase-locked loop circuit that avoids cycle slips.

Background technique

Phase locked loop (phase locked loop) is a frequency control system, which is widely used in circuit design, including clock generation, clock recovery, jitter and noise reduction, frequency synthesis, and so on. The operation of the PLL is based on the phase difference between the reference clock signal and the feedback of the voltage controlled oscillator (VCO) output clock signal. The cycle slip refers to when the feedback clock frequency is less than the reference clock frequency, it should be charged at this time, but because the phase of the reference clock lags behind the feedback clock, the charge pump discharges the loop filter instead. Or conversely, when the feedback clock frequency is greater than the reference clock frequency, it should be discharged at this time, but because the phase of the reference clock is ahead of the feedback clock, the charge pump instead charges the loop filter. This phenomenon often occurs when the loop starts or when the frequency jumps.

If the reference clock frequency is very close to the feedback clock frequency, then the average outflow or inflow current of the charge pump in each cycle is very small, and the corresponding VCO control voltage Vc and the VCO output frequency change very much. small. This causes the phase change between the reference clock and the feedback clock to become slow, thereby greatly increasing the loop lock time, especially in Kvco and systems with small loop bandwidths, this situation is particularly serious.

In the traditional design, in order to speed up the loop lock speed and avoid the significant extension of the loop lock time due to cycle slips, the loop bandwidth will be increased by adding extra current in the charge pump during the lock process. Reduce the loop lock time and turn off the additional charge pump after the loop locks. This not only reduces the loop bandwidth after the loop is locked, thereby reducing the output noise of the system, but also speeds up the process of loop locking. But this also increases the power consumption of the system to a certain extent and increases the complexity of the circuit.

Summary of the invention.

The purpose of the present invention is to provide a fast-locking phase-locked loop circuit that avoids cycle slips without increasing circuit complexity and system power consumption.

The present invention is different from the traditional phase-locked loop circuit that avoids cycle slip, in which no additional charge pump is added. Instead, the initial control voltage of the VCO is adjusted when the loop is started to change the initial output frequency of the VCO to make it consistent with the expectation. There is a certain gap in frequency, and 10-20 reference clock cycles are given to make the phase of the reference clock really lead or lag behind the feedback clock. This avoids the above-mentioned situation where the phase change between the reference clock frequency and the feedback clock frequency is too close during the locking process, which greatly increases the locking time.

In order to achieve the above objective, the present invention is achieved through the following technical solutions: a fast-locking phase-locked loop circuit that avoids cycle slips, the fast-locking phase-locked loop circuit includes: a frequency discriminator, a charge pump, and an intermediate circuit , Loop filter, voltage controlled oscillator, frequency divider. The output OP end of the frequency discriminator is connected to the input IP end of the charge pump, the output ON end of the frequency discriminator is connected to the input IN end of the charge pump; the output end of the charge pump is connected to the intermediate stage circuit Input IN terminal, the output terminal of the intermediate stage circuit is connected to the input terminal of the loop filter, the output terminal of the loop filter is connected to the input terminal of the voltage controlled oscillator, and the output terminal of the voltage controlled oscillator is connected to the frequency divider The output terminal of the frequency divider is connected with the input IN terminal of the frequency discriminator to form a feedback path.

Further, the intermediate stage circuit includes: a power supply, a first voltage dividing resistor R1, a second voltage dividing resistor R2, an inverter, a first transmission gate T1, a second transmission gate T2, a counter, and an NMOS switch M1. One end of the second transmission gate T2 is connected to the output end of the charge pump; one port of the intermediate stage circuit is connected to an inverter, and the inverter is connected to an input end of a counter. The output terminal is connected to the gate G terminal of the NMOS switch M1, and the source terminal S of the NMOS switch M1 is grounded; the other port of the intermediate circuit is connected to the other input terminal of the counter; the power supply is connected to the first The voltage dividing resistor R1 is connected, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series, and the second voltage dividing resistor R2 is grounded; the output terminals of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to the One end of the first transmission gate T1 is connected. The other end of the first transmission gate T1, the drain D of the NMOS switch M1, and the other end of the second transmission gate T2 are connected to the input end of the loop filter.

Further, the OPEN_LOOP control signal is input from a port of the intermediate stage circuit, and the OPEN_LOOP_N signal is obtained after passing through the inverter. The OPEN_LOOP control signal and the OPEN_LOOP_N signal jointly control the switching of the first transmission gate T1 and the second transmission gate T2, and the counter. When the control signal OPEN_LOOP is at a high level, the first transmission gate T1 is closed and the second transmission gate T2 is opened. At this time, the feedback path is in a normal locked state, and the charge pump and loop filter pass through the second transmission. The gate T2 is directly connected, and the loop filter outputs the voltage signal Vc, which is the control voltage of the voltage controlled oscillator. When OPEN_LOOP is low, the first transmission gate T1 is opened and the second transmission gate T2 is closed. At this time, the loop is in the automatic frequency calibration and cycle avoiding state. The power supply transmits the voltage signal VDD to the first voltage divider resistor. R1 and the second voltage dividing resistor R2, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 output a voltage signal of VDD/2, and the output signal PLUSE of the counter Counter is low, that is, the gate of the NMOS switch M1 The voltage of the pole G is at a low level and is in the off state, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to the loop filter through the first transmission gate T1, and the loop filter outputs The voltage signal Vc=VDD/2, which is the control voltage of the voltage controlled oscillator. When the control signal OPEN_LOOP changes from low level to high level, the counter Counter starts to work, and at the same time, the reference clock signal CLK_REF is input to the counter Counter through another port of the intermediate circuit as its clock signal. At this time, when the counter Counter counts, The output signal PLUSE of the counter Counter is high and the NMOS switch M1 is opened. At this time, the drain terminal D of the NMOS switch M1 is connected to the loop filter, and the input voltage signal LPF_IN of the loop filter is 0, that is, voltage control The control voltage of the oscillator Vc=0. When the counter Counter finishes counting, its output signal PLUSE becomes low again, and the NMOS switch M1 is turned off. At this time, the first transmission gate T1 is closed, the second transmission gate T2 is opened, and the charge pump and loop filter pass through the second The transmission gate T2 is directly connected, and the loop filter outputs the voltage signal Vc, which is the control voltage of the voltage controlled oscillator.

The beneficial effect of the present invention is that the fast-locking phase-locked loop circuit proposed by the present invention avoids cycle slips, which does not increase circuit complexity and system power consumption, between the charge pump and the loop filter. An intermediate circuit has been added. The intermediate circuit plays two roles. One is to disconnect the VCO from the loop during the automatic frequency calibration (Automatic Frequency Calibration) process, control Vc at VDD/2, and select the VCO tuning curve through the automatic frequency calibration module to make It is the closest to the desired frequency. Second, when the loop is pre-started, the loop is reconnected and a low potential Vc of 10-20 reference clock cycles is provided, and the corresponding VCO output frequency will be less than the desired frequency. At the same time, since the reference clock frequency>the feedback clock frequency, after several reference clock cycles, it is ensured that the phase of the reference clock will lead the phase of the feedback always. This ensures that when the intermediate circuit releases Vc and the loop actually starts, the frequency of the feedback clock signal is less than the reference clock signal, and its phase lags behind the reference clock, and the charge pump charges the loop filter to increase the output frequency of the VCO. This avoids the occurrence of cycle slips when the circuit is started, and on this basis, the loop lock time is greatly increased due to the inconsistent but small difference between the reference clock frequency and the feedback clock frequency. By changing the initial frequency of the VCO when the loop is started, it is ensured that the phases of the feedback clock signal CLK_DIV and the reference clock signal CLK_REF are in the correct context, so as to actively avoid the cycle slip phenomenon. And it avoids the situation that the loop falls into an abnormal locked state due to the output clock frequency being too close to the expected clock frequency when the loop is started, and the fast lock of the phase-locked loop is realized.

Description of the drawings

Figure 1 is a schematic diagram of a traditional phase-locked loop circuit;

Figure 2 is a schematic diagram of the occurrence of cycle slip phenomenon;

Figure 3 is a schematic diagram of a traditional phase-locked loop circuit that avoids cycle slips;

Figure 4 is a schematic diagram of a phase-locked loop circuit for avoiding cycle slips improved in the present invention;

Figure 5 shows the tuning curve of the VCO;

Fig. 6 is a signal schematic diagram of an improved phase-locked loop circuit for avoiding cycle slips of the present invention.

detailed description

The following describes the present invention in detail based on the accompanying drawings, so that the purpose and effects of the present invention will become clearer. It should be understood that what is described here is only used to explain the present invention and is not intended to limit the present invention.

Figure 1-3 is a traditional phase-locked loop circuit used to avoid cycle slip for acceleration lock. It increases the output current of the charge pump by adding an additional charge pump unit during lock, thereby increasing the loop bandwidth to achieve acceleration lock. the goal of. Although this approach can indeed speed up the locking process to a certain extent, it does not essentially solve the problem, that is, the occurrence of cycle slips and the abnormal locking state caused by the initial output frequency being too close to the expected frequency. Moreover, the additional charge pump unit also means larger current, and larger current noise, thereby reducing the phase noise of the system output signal.

FIG. 4 is a schematic diagram of the structure of the fast-locking phase-locked loop circuit for avoiding cycle slips according to the present invention. In addition to the phase frequency detector (PFD), charge pump (CP), loop filter (LPF), voltage controlled oscillator (VCO), and divider, the fast-locking phase-locked loop circuit also adds Intermediate circuit (LOOP_CUT). The frequency discriminator, the charge pump, the intermediate circuit, the loop filter, and the voltage-controlled oscillator are connected in sequence; the output OP of the frequency discriminator is connected to the input IP of the charge pump, and the frequency discriminator The output ON terminal of the phase detector is connected to the input IN terminal of the charge pump; the output terminal of the charge pump is connected to the input IN terminal of the intermediate stage circuit, and the output terminal of the intermediate stage circuit is connected to the input terminal of the loop filter. The output end of the filter is connected to the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to the input end of the frequency divider, and the output end of the frequency divider is connected to the input IN end of the frequency detector , Forming a feedback path.

The intermediate circuit includes: a power supply, a first voltage dividing resistor R1, a second voltage dividing resistor R2, an inverter, a first transmission gate T1, a second transmission gate T2, a counter Counter, and an NMOS switch M1. One end of the second transmission gate T2 is connected to the output end of the charge pump; one port of the intermediate stage circuit is connected to an inverter, and the inverter is connected to an input end of a counter. The output terminal is connected to the gate G terminal of the NMOS switch M1, and the source terminal S of the NMOS switch M1 is grounded; the other port of the intermediate circuit is connected to the other input terminal of the counter; the power supply is connected to the first The voltage dividing resistor R1 is connected, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series, and the second voltage dividing resistor R2 is grounded; the output terminals of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to the One end of the first transmission gate T1 is connected. The other end of the first transmission gate T1, the drain D of the NMOS switch M1, and the other end of the second transmission gate T2 are connected to the input end of the loop filter.

The OPEN_LOOP control signal is input from a port of the intermediate circuit, and the OPEN_LOOP_N signal is obtained after passing through the inverter. The OPEN_LOOP control signal and the OPEN_LOOP_N signal jointly control the opening and closing of the first transmission gate T1, the second transmission gate T2, and the counter. When the control signal OPEN_LOOP is at a high level, the first transmission gate T1 is closed and the second transmission gate T2 is opened. At this time, the feedback path is in a normal locked state, and the charge pump and loop filter pass through the second transmission. The gate T2 is directly connected, and the charge pump charges and discharges the loop filter to change the output voltage signal of the loop filter. The output voltage signal Vc of the loop filter is the control voltage of the voltage controlled oscillator.

When OPEN_LOOP is low, the first transmission gate T1 is opened, and the second transmission gate T2 is closed. At this time, the loop is in an automatic frequency calibration and cycle avoiding state. The power supply transmits the voltage signal VDD to the first voltage divider R1 And the second voltage dividing resistor R2, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 output a voltage signal of VDD/2, and at the same time the output signal PLUSE of the counter Counter is low, that is, the gate of the NMOS switch M1 The G voltage is at a low level and is in the off state. The first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to the loop filter through the first transmission gate T1, so that the first voltage dividing resistor R1 and The second voltage divider resistor R2 can smoothly charge the loop filter through the transmission gate T1, and the loop filter output voltage signal Vc=VDD/2, which is the control voltage of the voltage controlled oscillator.

When the control signal OPEN_LOOP changes from low level to high level, the counter Counter starts to work, and at the same time, the reference clock signal CLK_REF is input to the counter Counter through another port of the intermediate circuit as its clock signal. At this time, when the counter Counter counts, The counter output signal PLUSE is at a high level and the NMOS switch M1 is turned on. At this time, the drain terminal D of the NMOS switch M1 is connected to the loop filter to discharge the loop filter. The input of the loop filter The voltage signal LPF_IN is 0, that is, the control voltage of the voltage controlled oscillator Vc=0.

When the counter Counter finishes counting, its output signal PLUSE becomes low again, and the NMOS switch M1 is turned off. At this time, since OPEN_LOOP is high, the first transmission gate T1 is closed, the second transmission gate T2 is opened, and the charge pump Directly connected to the loop filter through the second transmission gate T2, the charge pump charges and discharges the loop filter to change its output voltage signal, the loop filter output voltage signal Vc, which is the control of the voltage controlled oscillator Voltage, the loop enters a normal locked state at this time.

The operation of the fast lock phase locked loop circuit is specifically as follows: when the locked phase locked loop circuit is activated, the control signal OPEN_LOOP is initially low level, and the loop is in the state of automatic frequency calibration. At this time, the second transmission gate T2 is closed, disconnecting the VCO from the feedback path; and OPEN_LOOP_N is high, the counter is closed, and the output is low, so that the NMOS switch M1 is closed, and the first transmission gate T1 is opened at the same time. The first voltage divider resistor R1 and the second voltage divider resistor R2 provide a voltage signal of VDD/2 (Note: R1=R2), and pass it to the loop filter through the first transmission gate T1, align and charge, and then make it output Voltage signal, that is, the control voltage of the voltage-controlled oscillator Vc=VDD/2. At this time, perform automatic frequency calibration and select the VCO tuning curve so that when Vc=VDD/2, the output frequency of the VCO is closest to the expected frequency of. After the automatic frequency calibration is completed, OPEN_LOOP jumps from low to high, so that the first transmission gate T1 is closed, the second transmission gate T2 is opened, and the feedback path is reconnected; at the same time, the counter starts working, and the reference clock signal CLK_REF It is input to the counter Counter as its clock signal through the other port of the intermediate stage circuit. During this period, the counter Counter outputs a high level, which makes the NMOS switch M1 turn on to discharge the loop filter, and the loop filter input voltage When the signal is 0, the output voltage signal, that is, the control voltage of the voltage-controlled oscillator Vc=0, is controlled so that the output frequency of the VCO is lower than the desired frequency, and therefore the feedback clock frequency is also lower than the reference clock frequency. While the counter is counting, the phase frequency detector continuously receives the reference clock signal and the feedback clock signal. In this way, even if the phase of the reference clock signal lags behind the feedback clock signal at the beginning, it can be adjusted back within this period of time to ensure that there will be no cycle slip when the LOOP CUT releases Vc. After the counter completes counting, the output signal PLUSE becomes low again, and the NMOS switch M1 is turned off. At this time, since OPEN_LOOP is high, the first transmission gate T1 is closed, the second transmission gate T2 is opened, and the charge pump Directly connected to the loop filter through the second transmission gate T2, the charge pump charges and discharges the loop filter to change its output voltage, that is, the magnitude of the control voltage Vc of the voltage-controlled oscillator, and then adjust its output frequency. Really enter the link of normal locking. At the same time, because the output frequency of the VCO is lower than the expected frequency at this time, that is, the feedback clock frequency is lower than the reference clock frequency, so there will be no abnormal lock state caused by the two clock signal frequencies being too close, which greatly extends the lock time .

Figure 5 shows part of the tuning curve of the VCO. It is obvious that as the control voltage Vc increases, the output frequency of the VCO also increases. Generally, in automatic frequency calibration, VDD/2 is often used as the fixed value of Vc. Therefore, the present invention pulls Vc to 0 when the loop is turned on, so as to prevent the initial output frequency of the VCO from being too close to the expected frequency. Causes the occurrence of an abnormal lock state.

Fig. 6 is a signal schematic diagram of the fast-locking phase-locked loop system for avoiding cycle slips according to the present invention. The initial period of time is the loop automatic frequency calibration process, at this time Vc=VDD/2. Then Vc is pulled down to 0, making the feedback clock frequency lower than the reference clock frequency. At this time, if a cycle slip occurs and the phase of the reference clock lags behind the feedback clock, after several reference clock cycles, the phase of the reference clock will exceed the feedback clock again, and then Vc will be released, and the loop will be locked normally. . This avoids the occurrence of cycle slips when the loop actually starts.

Claims

A fast-locking phase-locked loop circuit for avoiding cycle slips, characterized in that: the fast-locking phase-locked loop circuit includes: a frequency discriminator, a charge pump, an intermediate circuit, a loop filter, a voltage controlled oscillator, Frequency divider; the output OP end of the frequency discriminator is connected to the input IP end of the charge pump, the output ON end of the frequency discriminator is connected to the input IN end of the charge pump; the output end of the charge pump is connected The input IN terminal of the intermediate stage circuit, the output terminal of the intermediate stage circuit is connected to the input terminal of the loop filter, the output terminal of the loop filter is connected to the input terminal of the voltage controlled oscillator, and the output terminal of the voltage controlled oscillator Connect the input end of the frequency divider, and the output end of the frequency divider is connected to the input IN end of the frequency discriminator to form a feedback path;

The intermediate stage circuit includes: a power supply, a first voltage dividing resistor R1, a second voltage dividing resistor R2, an inverter, a first transmission gate T1, a second transmission gate T2, a counter, and an NMOS switch M1; One end of the second transmission gate T2 is connected to the output end of the charge pump; one port of the intermediate stage circuit is connected to an inverter, the inverter is connected to an input end of a counter, and the output end of the counter is connected to The gate G of the NMOS switch M1 is connected, and the source S of the NMOS switch M1 is grounded; the other port of the intermediate circuit is connected to the other input of the counter; the power supply is connected to the first voltage divider resistor R1 is connected, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series, and the second voltage dividing resistor R2 is grounded; the output terminals of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to the first transmission One end of the gate T1 is connected; the other end of the first transmission gate T1, the drain D end of the NMOS switch M1, and the other end of the second transmission gate T2 are connected to the input end of the loop filter.
The fast-locking phase-locked loop circuit for avoiding cycle slip according to claim 1, wherein the OPEN_LOOP control signal is input from a port of the intermediate circuit, and the OPEN_LOOP_N signal is obtained after the inverter; the OPEN_LOOP control signal, The OPEN_LOOP_N signal jointly controls the switching of the first transmission gate T1 and the second transmission gate T2, and the counter Counter; when the control signal OPEN_LOOP is high, the first transmission gate T1 is closed and the second transmission gate T2 is opened. When the feedback path is in a normal locked state, the charge pump and the loop filter are directly connected through the second transmission gate T2, and the loop filter outputs the voltage signal Vc, which is the control voltage of the voltage controlled oscillator; and When OPEN_LOOP is at low level, the first transmission gate T1 is opened and the second transmission gate T2 is closed. At this time, the loop is in automatic frequency calibration and cycle slip avoidance state. The power supply transmits the voltage signal VDD to the first voltage divider R1 and the first voltage divider resistor R1. Two voltage dividing resistors R2, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 output a voltage signal of VDD/2, while the output signal PLUSE of the counter is low level, that is, the voltage of the gate G of the NMOS switch M1 Is low and in the off state, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to the loop filter through the first transmission gate T1, and the loop filter outputs a voltage signal Vc =VDD/2, which is the control voltage of the voltage controlled oscillator; when the control signal OPEN_LOOP changes from low to high, the counter starts to work, and at the same time, the reference clock signal CLK_REF is input through another port of the intermediate circuit When the counter is used as its clock signal, when the counter is counting, the output signal PLUSE of the counter is high, and the NMOS switch M1 is turned on. At this time, the drain terminal D of the NMOS switch M1 is connected to the loop filter. The input voltage signal LPF_IN of the loop filter is 0, that is, the control voltage of the voltage-controlled oscillator Vc=0; when the counter finishes counting, its output signal PLUSE becomes low again, and the NMOS switch M1 is turned off. The first transmission gate T1 is closed, the second transmission gate T2 is opened, the charge pump and the loop filter are directly connected through the second transmission gate T2, and the loop filter outputs a voltage signal Vc, which is the control voltage of the voltage controlled oscillator .