JP2022521346A - High speed lock phase lock loop circuit to avoid cycle slip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To disclose a high-speed lock phase lock loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuit. The high speed lock phase lock loop circuit includes a frequency discriminator, a charge pump, an intermediate stage circuit, a loop filter, a voltage controlled oscillator, and a frequency divider. The frequency discriminator, the charge pump, the intermediate stage circuit, the loop filter and the voltage controlled oscillator are connected in this order. The output OUT of the voltage controlled oscillator is connected to the input IN end of the frequency divider, and the output OUT end of the frequency divider is connected to the input IN end of the frequency discriminator to form a feedback path. The present invention loops by adjusting the initial output frequency of the VCO so that the output clock frequency of the VCO and the desired frequency, that is, the reference clock frequency and the feedback clock frequency, are too close at the start of the loop. Avoids a significant increase in lock time when a cycle slip occurs. [Selection diagram] FIG. 4

Description

The present invention belongs to the technical field of integrated circuits, and particularly relates to high speed lock phase lock loop circuits for avoiding cycle slips.

A phase locked loop is a frequency control system and is very widely applied in circuit design such as clock generation, clock coverage, jitter and noise reduction, frequency synthesis and the like. The operation of the PLL is based on the phase difference between the reference clock signal and the feedback of the voltage controlled oscillator (VCO) output clock signal. Cycle slip means that if the feedback clock frequency is lower than the reference clock frequency, charging should be performed, but since the phase of the reference clock is behind the feedback clock, the charge pump discharges the loop filter in reverse. Means that. Or, conversely, if the feedback clock frequency is higher than the reference clock frequency, discharge should be performed, but since the phase of the reference clock is ahead of the feedback clock, the charge pump charges the loop filter in reverse. This phenomenon often occurs when the loop is started or the frequency is hopping.

When the reference clock frequency and the feedback clock frequency are very close, the average outflow or inflow current of the charge pump in each cycle is very small, and the change in the control voltage Vc of the corresponding VCO and the output frequency of the VCO is also very small. This slows the phase change between the reference clock and the feedback clock and significantly increases the loop lock time, which is especially serious in systems with low Kvco and loop bandwidth.

In the conventional design, the loop bandwidth is increased by adding extra current to the charge pump in the lock process in order to increase the lock speed of the loop and avoid a significant increase in loop lock time due to cycle slip. , Reduce the loop lock time and turn off the extra charge pump after the loop lock. This not only reduces the loop bandwidth after loop lock and reduces system output noise, but also speeds up the loop lock process. However, this also increases the power consumption of the system to some extent and increases the complexity of the circuit.

An object of the present invention is to provide a fast lock phase lock loop circuit for cycle slip avoidance without increasing circuit complexity and system power consumption.

The present invention is different from the conventional cycle slip avoidance phase lock loop circuit, in which the initial output frequency of the VCO is desired by adjusting the initial control voltage of the VCO at the start of the loop without adding an extra charge pump. It is varied to have a constant deviation from the frequency and is given a time of 10 to 20 reference clock cycles such that the phase of the reference clock certainly advances or lags behind the feedback clock. This makes it possible to avoid a situation in which the reference clock frequency and the feedback clock frequency are too close to each other and the phase change between the two is too slow in the lock process, resulting in a significant increase in the lock time.

In order to achieve the above object, the present invention is achieved through the following technical means. A high speed lock phase lock loop circuit for avoiding cycle slip is provided, and the high speed lock phase lock loop circuit includes a frequency discriminator, a charge pump, an intermediate stage circuit, a loop filter, a voltage controlled oscillator, and a frequency divider. The output OP end of the frequency discriminator is connected to the input IP end of the charge pump, the output ON end of the frequency discriminator is connected to the input IN end of the charge pump, and the output end of the charge pump is an intermediate stage. It is connected to the input IN end of the circuit, the output end of the intermediate stage circuit is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the voltage controlled oscillator, and the output of the voltage controlled oscillator. The end is connected to the input end of the frequency divider, the output end of the frequency divider is connected to the input IN end of the frequency discriminator, and a feedback path is formed.

Further, in the intermediate stage circuit, a power supply, a first voltage dividing resistor R1, a second voltage dividing resistor R2, an inverter, a first transfer gate T1, a second transfer gate T2, a counter Counter, and an WESTERN switch M1 are included. Is included. One end of the second transfer gate T2 is connected to the output end of the charge pump, one port of the intermediate stage circuit is connected to an inverter, and the inverter is connected to one input end of a counter counter. The output end of the counter Counter is connected to the gate G end of the SYSTEM switch M1, the source S end of the MIMO switch M1 is grounded, and the other port of the intermediate stage circuit is the other input end of the counter Counter. The power supply is connected to the first voltage dividing resistor R1, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series, and the second voltage dividing resistor R2 is connected to the first voltage dividing resistor R1. , The output end of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is connected to one end of the first transfer gate T1. The other end of the first transfer gate T1, the drain D end of the NOTE switch M1, and the other end of the second transfer gate T2 are connected to the input end of the loop filter.

Further, the OPEN_LOOP control signal is input from one port of the intermediate stage circuit, and the OPEN_LOOP_N signal is obtained after passing through the inverter. The OPEN_LOOP control signal and the OPEN_LOOP_N signal jointly control a switch between the first transfer gate T1 and the second transfer gate T2, and a counter Counter. When the control signal OPEN_LOOP is at a high level, the first transfer gate T1 closes and the second transfer gate T2 opens, at which time the feedback path is in a normal locked state and the charge pump and loop filter. Is directly connected via the second transfer gate T2, and the loop filter outputs a voltage signal Vc which is a control voltage of a voltage controlled oscillator. When OPEN_LOOP is low level, the first transfer gate T1 opens and the second transfer gate T2 closes, at which time the loop is in the automatic frequency calibration and cycle slip avoidance state and the power supply is voltage. The signal VDD is transmitted to the first voltage dividing resistor R1 and the second voltage dividing resistor R2, and the first voltage dividing resistor R1 and the second voltage dividing resistor R2 output a voltage signal of VDD / 2. At the same time, the output signal PLUSE of the counter Counter is at low level, that is, the gate G voltage of the nanotube switch M1 is at low level and is in the off state, and the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are in a low level. , Connected to the loop filter via the first transfer gate T1, the loop filter outputs a voltage signal Vc = VDD / 2, which is the control voltage of the voltage control oscillator. When the control signal OPEN_LOOP hops from low level to high level, the counter Counter starts operating, and at the same time, the reference clock signal CLK_REF is input to the counter Counter as its clock signal via the other port of the intermediate stage circuit. , When the counter Counter counts, the output signal PLUSE of the counter Counter is at a high level and the Now an The voltage signal LPF_IN is 0, that is, the control voltage Vc = 0 of the voltage control oscillator. After the counter Counter completes counting, its output signal PLUSE goes low again and the CICS switch M1 turns off, at which time the first transfer gate T1 closes, the second transfer gate T2 opens and the charge pump. And the loop filter are directly connected via the second transfer gate T2, and the loop filter outputs a voltage signal Vc which is a control voltage of a voltage controlled oscillator.

A beneficial effect of the present invention is, according to the fast lock phase lock loop circuit of cycle slip avoidance according to the present invention, an intermediate circuit between the charge pump and the loop filter if the circuit complexity and system power consumption are not increased. Is to add. The intermediate circuit plays two roles, first, in the Automatic Frequency Calibration process, the VCO is cut off from the loop, the Vc is controlled to VDD / 2, and the VCO tuning curve is controlled by the automatic frequency calibration module. Is selected so that it is closest to the desired frequency. Second, after the loop has been pre-initiated, the loop is reconnected and supplied with a low potential Vc of 10-20 reference clock cycles, the corresponding VCO output frequency is lower than the desired frequency. At the same time, since the reference clock frequency> the feedback clock frequency, it is guaranteed that the phase of the reference clock is ahead of the phase of the feedback after some reference clock cycle times have elapsed. This ensures that when the intermediate circuit releases the Vc and the loop actually starts, the frequency of the feedback clock signal is lower than the reference clock signal and its phase is behind the reference clock, and the charge is charged. The pump charges the loop filter to increase the output frequency of the VCO. This prevents a cycle slip phenomenon from occurring at the time of starting the circuit, and a large increase in the loop lock time due to the fact that the reference clock frequency and the feedback clock frequency do not match and the difference is extremely small. By changing the initial frequency of the VCO at the start of the loop, it is guaranteed that the phases of the feedback clock signal CLK_DIV and the reference clock signal CLK_REF are in the correct front-rear relationship, thereby positively avoiding the occurrence of the cycle slip phenomenon. When the output clock frequency and the desired clock frequency are too close to each other at the time of starting the loop, the situation where the loop falls into an abnormal lock state is avoided, and high-speed locking of the phase lock loop is realized.

It is a schematic diagram of the conventional phase lock loop circuit. It is a schematic diagram of the occurrence of a cycle slip phenomenon. It is a schematic diagram of the phase lock loop circuit of the conventional cycle slip avoidance. It is a tuning curve diagram of VCO. It is a schematic diagram of the improved phase lock loop circuit of a cycle slip avoidance of this invention. It is a signal schematic diagram of the improved phase lock loop circuit of a cycle slip avoidance of this invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings in order to further clarify the object and effect of the present invention. It should be understood that what is described here is used only to interpret the invention and is not intended to limit the invention.

FIGS. 1-3 show a conventional lock speed phase lock loop circuit to avoid cycle slip, which adds an extra charge pump unit at lock time to increase the charge pump output current and loop band. By increasing the width, the purpose of speeding up the lock is achieved. This technique can certainly speed up the locking process to some extent, but it does not essentially solve the problem: anomalies due to the occurrence of cycle slip phenomena and the initial output frequency being too close to the desired frequency. It does not solve the lock condition problem. In addition, the extra charge pump unit means greater current, and greater current noise, thereby reducing the phase noise of the system output signal.

FIG. 4 is a schematic configuration diagram of a high-speed lock phase lock loop circuit for avoiding cycle slip according to the present invention. The high-speed lock phase lock loop circuit includes a frequency discriminator (PFD), a charge pump (CP), a loop filter (LPF), a voltage controlled oscillator (VCO), a divider (divider), and an intermediate stage circuit (LOOP_CUT). ) Is added. The frequency discriminator, the charge pump, the intermediate stage circuit, the loop filter and the voltage controlled oscillator are connected in order, the output OP end of the frequency discriminator is connected to the input IP end of the charge pump, and the output of the frequency discriminator is output. The ON end is connected to the input IN end of the charge pump, the output end of the charge pump is connected to the input IN end of the intermediate stage circuit, and the output end of the intermediate stage circuit is connected to the input end of the loop filter. The output end of the loop filter is connected to the input end of the voltage controlled oscillator, the output end of the voltage controlled oscillator is connected to the input end of the frequency divider, and the output end of the frequency divider is the frequency discriminator. It is connected to the input IN end to form a feedback path.

The intermediate stage circuit includes a power supply, a first voltage dividing resistor R1, a second voltage dividing resistor R2, an inverter, a first transfer gate T1, a second transfer gate T2, a counter Counter, and an MIMO switch M1. Will be. One end of the second transfer gate T2 is connected to the output end of the charge pump, one port of the intermediate stage circuit is connected to an inverter, and the inverter is connected to one input end of a counter counter. The output end of the counter Counter is connected to the gate G end of the MIMO switch M1, the source S end of the MIMO switch M1 is grounded, and the other port of the intermediate stage circuit is the other input end of the counter Counter. The power supply is connected to the first voltage dividing resistor R1, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series, and the second voltage dividing resistor R2 is connected to the first voltage dividing resistor R1. , The output ends of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to one end of the first transfer gate T1 and the other end of the first transfer gate T1. The drain D end of the MIMO switch M1 and the other end of the second transfer gate T2 are connected to the input end of the loop filter.

The OPEN_LOOP control signal is input from one port of the intermediate stage circuit, and the OPEN_LOOP_N signal is obtained after passing through the inverter. The OPEN_LOOP control signal and the OPEN_LOOP_N signal jointly control a switch and a counter Counter between the first transfer gate T1 and the second transfer gate T2. When the control signal OPEN_LOOP is at a high level, the first transfer gate T1 closes and the second transfer gate T2 opens, at which time the feedback path is in a normal locked state and the charge pump and loop filter. Is directly connected via the second transfer gate T2, the charge pump charges and discharges the loop filter to change the output voltage signal of the loop filter, and the loop filter is the control voltage of the voltage controlled oscillator. The voltage signal Vc is output.

When OPEN_LOOP is low level, the first transfer gate T1 opens and the second transfer gate T2 closes, at which time the loop is in the automatic frequency calibration and cycle slip avoidance state and the power supply is voltage. The signal VDD is transmitted to the first voltage dividing resistor R1 and the second voltage dividing resistor R2, and the first voltage dividing resistor R1 and the second voltage dividing resistor R2 output a voltage signal of VDD / 2. At the same time, the output signal PLUSE of the counter Counter is at low level, that is, the gate G voltage of the nanotube switch M1 is at low level and is in the off state, and the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are in a low level. , The first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to the loop filter via the first transfer gate T1 so that the loop filter is smoothly charged via the transfer gate T1. The loop filter can output a voltage signal Vc = VDD / 2, which is the control voltage of the voltage control oscillator.

When the control signal OPEN_LOOP hops from low level to high level, the counter Counter starts operating, and at the same time, the reference clock signal CLK_REF is input to the counter Counter as its clock signal via the other port of the intermediate stage circuit. , When the counter Counter counts, the output signal PLUSE of the counter Counter is at a high level and the IGMP switch M1 is turned on. At this time, the drain terminal D of the Now's switch M1 is connected to the loop filter and with respect to the loop filter. The discharge operation is performed, and the input voltage signal LPF_IN of the loop filter is 0, that is, the control voltage Vc = 0 of the voltage control oscillator.

After the counter Counter completes counting, its output signal PLUSE goes low again and the EtOAc switch M1 turns off, at which time the first transfer gate T1 closes and the second because OPEN_LOOP is high level. The transfer gate T2 opens, the charge pump and the loop filter are directly connected via the second transfer gate T2, the charge pump charges and discharges the loop filter to change its output voltage signal, and the loop filter is , The voltage signal Vc, which is the control voltage of the voltage controlled oscillator, is output, and at this time, the loop enters the normal locked state.

The operation of the high-speed lock phase lock loop circuit is specifically as follows. Lock Phase After the lock loop circuit is started, the control signal OPEN_LOOP is initially low level and the loop is in the state of automatic frequency calibration. At this time, the second transfer gate T2 closes, blocking the VCO from the feedback path. OPEN_LOOP_N is high level, the counter Counter is closed, the low level is output, the nanotube switch M1 is closed, and at the same time, the first transfer gate T1 is opened, and the first voltage dividing resistance R1 and the second voltage dividing resistance are closed. R2 provides a voltage signal of VDD / 2 (Note: R1 = R2), which is transmitted to the loop filter via the first transfer gate T1 to charge it, and further, it is a voltage signal of the voltage controlled oscillator. The control voltage Vc = VDD / 2 is output, and at this time, automatic frequency calibration is performed, and when Vc = VDD / 2, the VCO tuning curve is selected so that the VCO output frequency is closest to the desired frequency. .. After the automatic frequency calibration is completed, OPEN_LOOP goes from low level hopping to high level, the first transfer gate T1 closes, the second transfer gate T2 opens, the feedback path communicates again, and the counter Counter operates at the same time. Is started, and the reference clock signal CLK_REF is input to the counter Counter as its clock signal via the other port of the intermediate stage circuit, during which time the counter Counter outputs a high level, the CICS switch M1 is turned on, and the loop is performed. A discharge operation is performed on the filter, the input voltage signal of the loop filter is 0, and the control voltage Vc = 0 of the voltage control oscillator, which is the output voltage signal, is controlled to reduce the output frequency of the VCO from the desired frequency. Also lower, which causes the feedback clock frequency to be lower than the reference clock frequency. During the counting of the counter Counter, the frequency discriminator always receives the reference clock signal and the feedback clock signal. In this way, even if the phase of the reference clock signal is initially delayed from the feedback clock signal, it can be adjusted during this period, and the cycle slip phenomenon does not occur when the LOOP CUT releases Vc. Is guaranteed. After the counter Counter completes the count, the output signal PLUSE goes low again and the EtOAc switch M1 turns off. At this time, since OPEN_LOOP is high level, the first transfer gate T1 is closed and the second transfer is performed. The gate T2 opens, the charge pump and the loop filter are directly connected via the second transfer gate T2, and the charge pump charges and discharges the loop filter, and the control voltage Vc of the voltage controlled oscillator, which is the output voltage thereof, is large. By changing the voltage and further adjusting its output frequency, the loop actually enters the normal lock link. At the same time, at this time, since the output frequency of the VCO is smaller than the desired frequency, that is, the feedback clock frequency is lower than the reference clock frequency, an abnormal lock state occurs due to the two clock signal frequencies being too close to each other, and the lock time occurs. Does not increase significantly.

FIG. 5 is a tuning curve of a part of the VCO, and as is clear, the output frequency of the VCO increases as the control voltage Vc increases. Further, in general, VDD / 2 is often used as a fixed value of Vc at the time of automatic frequency calibration. Therefore, in the present invention, by pulling down Vc to 0 at the time of loop start, the output frequency at the initial VCO and the desired frequency are used. Avoid the occurrence of an abnormal lock state due to being too close to.

FIG. 6 is a schematic signal diagram of a high-speed lock phase lock loop system that avoids cycle slip according to the present invention. The first period is the process of loop automatic frequency calibration, where Vc = VDD / 2. After that, Vc is pulled down to 0, and the feedback clock frequency becomes lower than the reference clock frequency. At this time, when the cycle slip phenomenon occurs and the phase of the reference clock lags behind the feedback clock, after some reference clock cycles have elapsed, the phase of the reference clock exceeds the feedback clock again, and Vc is released. The loop goes through the process of normal locking. This avoids the cycle slip phenomenon when the loop is actually started.

Claims (2)

High speed lock phase lock loop circuit to avoid cycle slip, including frequency discriminator, charge pump, intermediate circuit, loop filter, voltage controlled oscillator, and frequency divider.
The output OP end of the frequency discriminator is connected to the input IP end of the charge pump, the output ON end of the frequency discriminator is connected to the input IN end of the charge pump, and the output end of the charge pump is an intermediate stage. It is connected to the input IN end of the circuit, the output end of the intermediate stage circuit is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the voltage controlled oscillator, and the output of the voltage controlled oscillator. The end is connected to the input end of the frequency divider, the output end of the frequency divider is connected to the input IN end of the frequency discriminator, and a feedback path is formed.
The intermediate stage circuit includes a power supply, a first voltage dividing resistor R1, a second voltage dividing resistor R2, an inverter, a first transfer gate T1, a second transfer gate T2, a counter Counter, and an MIMO switch M1. Re,
One end of the second transfer gate T2 is connected to the output end of the charge pump.
One port of the intermediate stage circuit is connected to an inverter, the inverter is connected to one input end of the counter Counter, and the output end of the counter Counter is connected to the gate G end of the QoS switch M1. The source S end of the MIMO switch M1 is grounded and
The other port of the intermediate stage circuit is connected to the other input end of the counter Counter.
The power supply is connected to the first voltage dividing resistor R1, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series, and the second voltage dividing resistor R2 is grounded.
The output ends of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected to one end of the first transfer gate T1.
Cycle slip avoidance, characterized in that the other end of the first transfer gate T1, the drain D end of the NaCl switch M1 and the other end of the second transfer gate T2 are connected to the input end of the loop filter. Fast lock phase lock loop circuit. The OPEN_LOOP control signal is input from one port of the intermediate stage circuit, and after passing through the inverter, the OPEN_LOOP_N signal is obtained.
The OPEN_LOOP control signal and the OPEN_LOOP_N signal jointly control a switch between the first transfer gate T1 and the second transfer gate T2, and a counter Counter.
When the control signal OPEN_LOOP is at a high level, the first transfer gate T1 closes and the second transfer gate T2 opens, at which time the feedback path is in a normal locked state and the charge pump and loop filter. Is directly connected via the second transfer gate T2, and the loop filter outputs a voltage signal Vc which is a control voltage of a voltage controlled oscillator.
When OPEN_LOOP is low level, the first transfer gate T1 opens and the second transfer gate T2 closes, at which time the loop is in the automatic frequency calibration and cycle slip avoidance state and the power supply is voltage. The signal VDD is transmitted to the first voltage dividing resistor R1 and the second voltage dividing resistor R2, and the first voltage dividing resistor R1 and the second voltage dividing resistor R2 output a voltage signal of VDD / 2. At the same time, the output signal PLUSE of the counter Counter is at low level, that is, the gate G voltage of the nanotube switch M1 is at low level and is in the off state, and the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are in a low level. , Connected to the loop filter via the first transfer gate T1, the loop filter outputs a voltage signal Vc = VDD / 2, which is the control voltage of the voltage control oscillator.
When the control signal OPEN_LOOP hops from low level to high level, the counter Counter starts operating, and at the same time, the reference clock signal CLK_REF is input to the counter Counter as its clock signal via the other port of the intermediate stage circuit. , When the counter Counter counts, the output signal PLUSE of the counter Counter is at a high level and the Now an The voltage signal LPF_IN is 0, that is, the control voltage Vc = 0 of the voltage control oscillator.
After the counter Counter completes counting, its output signal PLUSE goes low again and the CICS switch M1 turns off, at which time the first transfer gate T1 closes, the second transfer gate T2 opens and the charge pump. The cycle according to claim 1, wherein the loop filter is directly connected via a second transfer gate T2, and the loop filter outputs a voltage signal Vc which is a control voltage of a voltage controlled oscillator. High-speed lock phase lock loop circuit to avoid slipping.

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