WO2021036431A1 - 一种数据采集系统及其控制方法、装置、设备和介质 - Google Patents

一种数据采集系统及其控制方法、装置、设备和介质 Download PDF

Info

Publication number
WO2021036431A1
WO2021036431A1 PCT/CN2020/096629 CN2020096629W WO2021036431A1 WO 2021036431 A1 WO2021036431 A1 WO 2021036431A1 CN 2020096629 W CN2020096629 W CN 2020096629W WO 2021036431 A1 WO2021036431 A1 WO 2021036431A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
signal
control
clock
collection
Prior art date
Application number
PCT/CN2020/096629
Other languages
English (en)
French (fr)
Inventor
汤江逊
黄俏
聂玉庆
Original Assignee
珠海格力电器股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 珠海格力电器股份有限公司 filed Critical 珠海格力电器股份有限公司
Priority to US17/624,821 priority Critical patent/US11914418B2/en
Publication of WO2021036431A1 publication Critical patent/WO2021036431A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality

Definitions

  • the present disclosure relates to the field of data collection, and in particular to a data collection system and its control method, device, equipment and medium.
  • the high-speed acquisition system is generally divided into two parts: data acquisition and data processing.
  • data acquisition it will collect data at a high speed and store the collected data in the buffer.
  • processing unit When the processing unit is in an idle state, the data will be collected from the buffer. Extract data and process it.
  • the data collection speed in the high-speed data acquisition system is very fast, and the buffer storage time and storage capacity are limited, when the processing unit is occupied or the processing volume is too large and the processing speed is slow, it may cause storage in the buffer
  • the data is invalid before it reaches the processing unit, resulting in data loss, resulting in incomplete data collection, and during the data collection process, the impact of the environment and temperature of the collection circuit in the collection system may cause the collection of the collected data The period of the signal changes.
  • the embodiments of the present disclosure provide a data collection system to realize the high-speed collection of data while ensuring the integrity of the collected data and the collection of data of the correct period.
  • embodiments of the present disclosure provide a data collection system, including:
  • a signal transmission line includes a plurality of first signal delay units connected in series, and the output end of each first signal delay unit forms a collection point;
  • a plurality of acquisition units, the acquisition unit and the first signal delay unit are in one-to-one correspondence, and between each pair of corresponding acquisition units and the first signal delay unit, the acquisition unit is connected with the acquisition point of the first signal delay unit to Collect the signal at the collection point;
  • the clock unit connected to the acquisition unit.
  • the clock unit includes a first inversion unit and a plurality of second signal delay units connected in series.
  • the second signal delay unit has the same structure as the first signal delay unit, and the clock unit is It is configured to generate a control signal, which is used to control the acquisition time of the acquisition unit;
  • the comparison unit connected to the clock unit is configured to compare the period of the control signal with the period of the standard signal, and generate an adjustment signal according to the comparison result;
  • the adjustment unit connected to the comparison unit is configured to adjust the supply voltage of the signal transmission line and the clock unit according to the adjustment signal, so that the ratio of the period of the control signal to the period of the standard signal meets the set threshold range.
  • the data acquisition system increases the transmission time of the signal to be acquired by transmitting the signal to be acquired to the signal transmission line with multiple signal delay units, and uses the acquisition unit to acquire the signal from the transmission line.
  • the data acquisition system uses the acquisition unit to acquire the signal from the transmission line.
  • the complete signal is collected to ensure that the processing unit There is enough time to process the signals collected by the collection unit.
  • it not only guarantees the integrity of the acquired signal, but also provides a delay with the first signal on the signal transmission line in order to prevent the transmission time of the signal transmission line from being affected by the working environment.
  • the clock unit composed of the second signal delay unit with the same unit structure, compares the control signal generated by the clock unit with the period of the standard clock signal, and determines the delay time offset of the second signal delay unit according to the comparison result According to the deviation of the delay time of the second delay unit, the power supply voltage of the first signal delay unit and the second signal delay unit is compensated so that the first signal delay unit and the second delay unit The delay time of is stable at a fixed value.
  • the number of the first signal delay unit connected in series in the signal transmission line is equal to that of the second signal delay unit connected in series in the clock unit. The number is the same.
  • the number of first signal delay units connected in series in the signal transmission line is the same as the number of second signal delay units connected in series in the clock unit, and the first signal delay unit
  • the structure of the second signal delay unit is the same, so the first signal delay unit constitutes the signal transmission line's transmission time offset, which is the same as the clock offset of the clock unit, so that the first signal is adjusted according to the clock offset.
  • the voltage compensation of the delay unit and the second delay unit ensures that the signal of the correct period is collected.
  • the clock unit further includes a switch unit, the output terminal of any second signal delay unit is connected to the switch unit, and the switch unit is configured to control The second signal delay unit is connected to the input terminal of the first inverting unit.
  • the output terminals of the second signal delay unit are all connected with a switch unit, and the connection between the output terminal of the second signal delay unit and the input terminal of the first inverting unit is controlled by the switch unit, Because the connection between the output terminal of the second signal delay unit and the input terminal of the inverting unit is different, the period of the output control signal is different.
  • the specific state of each switch unit can be set according to the working conditions of the acquisition unit and the processing unit that processes the signal to obtain control signals of different periods to meet the requirements of the acquisition system.
  • the comparison unit includes a first adder, a second adder, and a comparison unit
  • the first adder is configured to receive the clock signal sent by the preset clock device, and accumulate the number of clock signals
  • the second adder is configured to receive control signals and accumulate the number of control signals
  • the comparison unit is respectively connected to the first adder and the second adder, and is configured to compare the accumulated clock signal times of the first adder and the accumulated control signal times of the second adder, and generate an adjustment signal according to the comparison result.
  • the data acquisition system provided by the embodiment of the present disclosure accumulates the period number of the generated control signal and the period number of the clock signal generated by the preset clock device, and determines the period of the control signal according to the comparison result of the accumulated number In the case of deviation, adjust the supply voltage of the first signal delay unit and the second signal delay unit to ensure that the signal transmitted on the signal transmission line has the same transmission time on each first delay unit to ensure the collected signal
  • the cycle is stable and unchanging.
  • the adjustment unit includes a comparator, a sliding varistor, a metal-oxide-semiconductor field effect transistor, and a first resistor,
  • the first input terminal of the comparator is connected with the standard power supply, the second input terminal of the comparator is connected with the second terminal of the sliding rheostat, and the output terminal of the comparator is connected with the gate of the MOS tube;
  • the source of the MOS tube is connected to the power supply, and the drain of the MOS tube is connected to the sliding piece of the sliding resistor;
  • the sliding piece of the sliding rheostat is connected to the output end of the comparison unit, and the second end of the sliding rheostat is connected to the first resistor;
  • the second end of the first resistor is connected to the ground.
  • the input end of the signal transmission line includes a second inverting unit
  • the first inverting unit has the same structure as the second inverting unit.
  • embodiments of the present disclosure provide a method for controlling a data acquisition system, including:
  • an indication signal is sent to the clock unit.
  • the indication signal is configured to control the working state of the switch unit set at the output of the second signal delay unit, so that the clock unit sends a control signal to the acquisition unit, and the control signal is It is configured to control the acquisition unit to acquire the signal at the acquisition point.
  • the control method of the data acquisition system detects in real time the time when the processing device processes the signal sent by the received acquisition unit when the signal is transmitted to the signal transmission line, and sends control signals at different moments to the acquisition unit to control
  • the collection unit collects data at different times to avoid the processing device from receiving multiple identical data, which wastes the resources and time of the device for processing the collected signals.
  • a data collection control device including:
  • a receiving unit configured to receive signals at different moments sent by the collecting unit
  • the calculation unit is configured to calculate the processing time of each signal for each signal received
  • the sending unit is configured to send an indication signal to the clock unit based on the processing time of each signal.
  • the indication signal is used to control the working state of the switch unit set at the output end of the second signal delay unit, so that the clock unit sends control to the acquisition unit Signal, the control signal is used to control the acquisition unit to collect the signal at the acquisition point.
  • the embodiments of the present disclosure provide a control device of a data acquisition system, including: at least one processor, at least one memory, and computer program instructions stored in the memory.
  • the computer program instructions are executed when the processor is executed.
  • the control method of the data acquisition system provided in the second aspect of the embodiments is disclosed.
  • embodiments of the present disclosure provide a computer storage medium on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the method for controlling the data acquisition system provided in the second aspect of the embodiments of the present disclosure is implemented.
  • FIG. 1 is a first structural diagram of a data acquisition system provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram 1 of the circuit structure of a first signal delay unit provided by an embodiment of the disclosure
  • FIG. 3 is a second schematic diagram of the circuit structure of the first signal delay unit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a circuit structure of a first inverting unit provided by an embodiment of the disclosure
  • FIG. 5 is a schematic structural diagram of a switch unit provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of a comparison unit provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic structural diagram of an adjustment unit provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic flowchart of a control method of a data acquisition system provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic structural diagram of a control device of a data acquisition system provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic structural diagram of a control device of a data acquisition system provided by an embodiment of the disclosure.
  • the embodiment of the present disclosure provides a data acquisition system, as shown in FIG. 1, including:
  • the signal transmission line 10 includes a plurality of first signal delay units 11 connected in series, and the output end of each first signal delay unit 11 forms a collection point;
  • the acquisition unit 20 corresponds to the first signal delay unit 11 one-to-one. Between each pair of corresponding acquisition units 20 and the first signal delay unit 11, the acquisition unit 20 and the first signal delay unit 11 are delayed The collection point of the unit 11 is connected to collect the signal at the collection point;
  • the clock unit 30 connected to the acquisition unit.
  • the clock unit includes a first inverting unit 31 and a plurality of second signal delay units 32 connected in series.
  • the structure of the second signal delay unit 32 and the first signal delay unit 11 Similarly, the clock unit is configured to generate a control signal, and the control signal is used to control the acquisition time of the acquisition unit 20;
  • the comparison unit 40 connected to the clock unit 30 is configured to compare the period of the control signal with the period of the standard signal, and generate an adjustment signal according to the comparison result;
  • the adjustment unit 50 connected to the comparison unit 40 is configured to adjust the supply voltage of the signal transmission line 10 and the clock unit 30 according to the adjustment signal so that the ratio of the period of the control signal to the period of the standard signal meets the set threshold range.
  • the setting threshold range can be set according to the collection accuracy requirements of the data collection system and the device specifications of the collection system, which is not limited in the embodiment of the present disclosure.
  • the number of first signal delay units 11 connected in series in the signal transmission line 10 is the same as the number of second signal delay units 32 connected in series in the clock unit 30.
  • the number of the first signal delay unit 11 on the signal transmission line 10 can be determined according to the scene of the data acquisition system, the connected device, the processing speed of the processing device 60, and the delay time of the first signal delay unit 11. Setting, the embodiment of the present disclosure does not limit this.
  • each first signal delay unit 11 is less than or equal to half of the high-level maintenance duration of the signal input to the signal transmission line 10 to ensure that the signal is completely delayed from the first signal. Pass on unit 11.
  • the processing device 60 in FIG. 1 provided by the embodiments of the present disclosure is a processing device that is communicatively connected or electrically connected to the data acquisition system.
  • the data provided in the embodiments of the present disclosure A processing device is provided in the acquisition system and is configured to process the signals collected by the acquisition unit 20.
  • the first signal delay unit 11 provided in the embodiments of the present disclosure, in some embodiments of the present application, is divided into the following three situations according to the delay time and the devices used for delay, which are specifically as follows:
  • the first signal delay unit 11 includes: a first resistor and a first capacitor.
  • the first terminal is connected to the output terminal of the previous delay circuit
  • the second terminal of the first resistor is connected to the first terminal of the first capacitor and the input terminal of the next delay circuit
  • the second terminal of the first capacitor is connected to ground .
  • the specifications of the first resistor and the first capacitor can be selected according to the delay time of the first signal delay unit 11, which is not limited in the embodiment of the present disclosure.
  • the first signal delay unit 11 provided by the embodiment of the present disclosure includes: a first metal-oxide-semiconductor field effect transistor (MOS) transistor 21 and a second MOS transistor 22.
  • MOS metal-oxide-semiconductor field effect transistor
  • the source of the first MOS tube 21 is connected to the power supply, the gate of the first MOS tube 21 is connected to the output terminal of the previous delay circuit, and the drain of the first MOS tube 21 is connected to the source of the second MOS tube 22.
  • the gate of the second MOS tube 22 is connected to the output terminal of the previous delay circuit, the drain of the second MOS tube 22 is connected to the drain of the third MOS tube 23; the gate of the third MOS tube 23 is connected to the upper
  • the output terminal of a delay circuit is connected, the source of the third MOS tube 23 is connected with the drain of the fourth MOS tube 24; the gate of the fourth MOS tube 24 is connected with the output terminal of the previous delay circuit, and the fourth MOS tube is connected to the output terminal of the previous delay circuit.
  • the source of the tube 24 is connected to the ground.
  • the models of the first MOS tube, the second MOS tube, the third MOS tube, and the fourth MOS tube in the first signal delay unit 11 provided by the embodiment of the present disclosure may be based on the first signal delay unit 11
  • the delay time is selected, which is not limited in the embodiment of the present disclosure.
  • the first signal delay unit 11 provided by the embodiment of the present disclosure includes: a first diode 111, a second diode 112 and a second resistor 113.
  • the anode of the first diode 111 is connected to the output terminal of the previous first signal delay unit
  • the cathode of the first diode 111 is connected to the second end of the second resistor 113
  • the second diode 112 The anode of the first signal delay unit is connected to the output end of the previous first signal delay unit
  • the cathode of the second diode 112 is connected to the second end of the second resistor 113
  • the first end of the second resistor 113 is connected to the power supply
  • the second end of the second resistor 113 is connected to the power supply.
  • the second end of the resistor 113 is connected to the input end of the next first signal delay unit.
  • the models of the first diode 111, the second diode 112, and the second resistor 113 in this embodiment can be selected according to the delay time of the first signal delay unit 11.
  • the implementation of the present disclosure The example does not limit this.
  • the three cases of the first signal delay unit 11 provided by some embodiments of the present disclosure are integrated circuits, which are not limited in the embodiments of the present disclosure.
  • the first signal delay unit 11 is another circuit or device that can implement signal delay, and the comparison of the embodiments of the present disclosure is not limited.
  • a second inverting unit is provided at the input end of the signal transmission line.
  • first inversion unit and the second inversion unit are the same.
  • the second inverting unit includes a complementary metal oxide semiconductor CMOS inverter.
  • the input end of the signal transmission line includes two second inverting units.
  • the CMOS inverter integrated circuit is preferably used in the embodiments of the present disclosure to reduce the loss of the data acquisition system.
  • the second inverting unit adopts other devices or circuits that can realize the inverting function, which is not limited in the present disclosure.
  • the acquisition unit 20 includes a type D flip-flop, the input end of the type D flip-flop is connected to the output end of the first signal delay unit 11, and the output end of the type D flip-flop is connected to the processing unit 30 ,
  • the control terminal of the D-type trigger receives the control signal used to control the acquisition time of the acquisition unit 20.
  • the collection time of the collection unit is not the same as the delay time of the signal delay unit to ensure that the complete signal is collected.
  • control terminal of the D-type flip-flop is connected to the clock unit to receive the control signal sent by the clock unit, and collect the signal at the collection point based on the received control signal.
  • the clock unit 30 further includes a switch unit 33, and the output terminal of any second signal delay unit 32 in the clock unit 30 for generating a control signal is connected to the switch unit 33.
  • the switch unit 33 is configured to control the connection between the second signal delay unit 32 and the input terminal of the inverting unit 31.
  • the comparison unit 40 provided in an embodiment of the present disclosure includes:
  • the first adder 41, the second adder 42, and the comparison unit 43 The first adder 41, the second adder 42, and the comparison unit 43.
  • the first adder 41 is configured to receive the clock signal sent by the preset clock device and accumulate the number of clock signals.
  • the second adder 42 is It is configured to receive control signals and accumulate the number of control signals.
  • the comparison unit 43 is connected to the first adder 41 and the second adder 42, and is configured to compare the accumulated clock signal times of the first adder 41 and the first adder 41 Two adder 42 accumulates the number of control signals and generates an adjustment signal based on the comparison result.
  • the clock device is a crystal oscillator.
  • the specific type of crystal oscillator can be selected according to the requirements of the data acquisition system and the accuracy of the crystal oscillator. Not limited.
  • the clock device is provided in the data acquisition system provided in the embodiments of the present disclosure. In other embodiments of the present disclosure, the clock device is in communication with the data acquisition system provided in the embodiments of the present disclosure.
  • the devices in the device are not limited in the embodiments of the present disclosure.
  • the total number of counts of the first adder 41 and the second adder 42 can be set according to actual requirements, for example, according to the collection accuracy required by the data collection system, which is not done in the embodiment of the present disclosure. limited.
  • the adjustment unit 50 provided by the embodiment of the present disclosure includes a comparator 51, a sliding varistor 52, a fifth MOS transistor 53 and a third resistor 54.
  • the first input terminal of the comparator 51 is connected to the standard power supply, the second input terminal of the comparator 51 is connected to the second terminal of the sliding rheostat 52, and the output terminal of the comparator 51 is connected to the gate of the fifth MOS transistor 53.
  • the source of the MOS transistor 53 is connected to the power supply, the drain of the fifth MOS transistor 53 is connected to the sliding piece of the sliding resistor 52, the sliding piece of the sliding varistor 52 is connected to the output terminal of the comparison unit 40, and the second of the sliding varistor 52
  • the terminal is connected to the third resistor 54 and the second terminal of the third resistor 54 is connected to the ground.
  • an embodiment of the present disclosure provides a data collection system, as shown in Fig. 1, and its working principle is as follows:
  • the signal is transmitted from the input terminal 1 of the signal transmission line 10 to an inverting unit (not shown) to obtain a signal with an ideal waveform, and the signal output by the inverting unit is transmitted to a plurality of first signal delay units 11 for delay.
  • the working state of the processing device 60 is detected.
  • the processing device 60 sends an instruction signal for controlling the working state of the switch unit (not shown) to the clock unit 30, To generate a control signal, and send the control signal to the collection unit 20, so that the control collection unit 20 performs signal collection, and transmits the collected signal to the processing device 60 for signal processing.
  • the first adder (not shown) in the comparison unit 40 connected to the clock unit 30 accumulates the number of cycles of the control period, and the second adder (not shown) measures the standard signal The number of cycles is accumulated, and according to the ratio of the accumulated number of the first adder and the second adder with the preset duration, it is determined whether the delay duration of the first signal delay unit 11 and the second delay unit 32 is offset , And adjust the position of the sliding piece of the sliding rheostat (not shown) in the adjustment unit 50 according to the offset, so as to change the position of the second end of the comparator (not shown) connected to the second end of the sliding rheostat, and according to this
  • the comparison result of the point and the standard voltage changes the potential of the sliding rheostat, thereby changing the power supply voltage of each unit in the signal transmission line 10 and the clock unit 30 connected to the sliding rheostat, so that the ratio of the period of the control signal to the period of the standard signal Meet the set threshold range.
  • the embodiment of the present disclosure provides a control method of the data collection system, as shown in FIG. 8. In some embodiments, the following steps are included:
  • Step 801 Receive signals at different moments sent by the collection unit.
  • Step 802 For each received signal, calculate the processing time of each signal.
  • Step 803 Based on the processing time of each signal, send an indication signal to the clock unit.
  • the indication signal is used to control the working state of the switch unit set at the output terminal of the second signal delay unit, so that the clock unit sends a control signal to the acquisition unit to control
  • the signal is used to control the acquisition unit to acquire the signal at the acquisition point.
  • the embodiments of the present disclosure also provide a control device of a data acquisition system.
  • control device of the data acquisition system provided by the embodiment of the present disclosure includes:
  • the receiving unit 901 is configured to receive signals at different moments sent by the collecting unit;
  • the calculation unit 902 is configured to calculate the processing time of each signal for each signal received
  • the sending unit 903 is configured to send an indication signal to the clock unit based on the processing time of each signal.
  • the indication signal is used to control the working state of the switch unit set at the output terminal of the second signal delay unit, so that the clock unit sends to the acquisition unit
  • the control signal is used to control the acquisition unit to acquire the signal at the acquisition point.
  • FIG. 10 shows a schematic diagram of the hardware structure of the control device of the data acquisition system provided by an embodiment of the present disclosure.
  • control device of the data acquisition system includes a processor 1001 and a memory 1002 storing computer program instructions.
  • the above-mentioned processor 1001 includes a central processing unit (CPU), or a specific integrated circuit (Application Specific Integrated Circuit, ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present disclosure. Circuit.
  • CPU central processing unit
  • ASIC Application Specific Integrated Circuit
  • the memory 1002 includes mass storage for data or instructions.
  • the memory 1002 may include a hard disk drive (Hard Disk Drive, HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a Universal Serial Bus (Universal Serial Bus, USB) drive, or two or more Multiple combinations of these.
  • the storage 1002 may include removable or non-removable (or fixed) media.
  • the memory 1002 may be internal or external to the data processing device.
  • the memory 1002 is a non-volatile solid state memory.
  • the memory 1002 includes read-only memory (ROM).
  • the ROM is mask-programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), electrically rewritable ROM (EAROM) or flash memory or both A combination of one or more of these.
  • the processor 1001 reads and executes the computer program instructions stored in the memory 1002 to implement any one of the control methods of the data acquisition system in the foregoing embodiments.
  • control device of the data acquisition system may further include a communication interface 1003 and a bus 1010.
  • the processor 1001, the memory 1002, and the communication interface 1003 are connected through a bus 1010 and complete mutual communication.
  • the communication interface 1003 is mainly used to implement communication between devices, devices, units, and/or devices in the embodiments of the present disclosure.
  • the bus 1010 includes hardware, software, or both, and couples the components of the control device of the data acquisition system to each other.
  • the bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industry standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnect, industry standard architecture (ISA) Bus, Infinite Bandwidth Interconnect, Low Pin Count (LPC) Bus, Memory Bus, Micro Channel Architecture (MCA) Bus, Peripheral Component Interconnect (PCI) Bus, PCI-Express (PCI-X) Bus, Serial Advanced Technology Attachment (SATA) bus, Video Electronics Standards Association Local (VLB) bus or other suitable bus or a combination of two or more of these.
  • the bus 1010 may include one or more buses.
  • control device of the data acquisition system executes the control method of the data acquisition system in the embodiments of the present disclosure based on the state of the processing unit in the data acquisition system, thereby realizing the data acquisition system described in conjunction with FIGS. 8-10 ⁇ Control methods and devices.
  • the embodiment of the present disclosure may provide a computer-readable storage medium for implementation.
  • Computer program instructions are stored on the computer-readable storage medium; when the computer program instructions are executed by the processor, any one of the control methods of the data acquisition system in the foregoing embodiments is implemented.
  • the embodiments of the present disclosure can be provided as a method, a system, or a computer program product. Therefore, the present disclosure may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, optical storage, etc.) containing computer-usable program codes.
  • a computer-usable storage media including but not limited to disk storage, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

Abstract

一种数据采集系统及其控制方法、装置、设备和介质，数据采集系统包括：信号传输线路（10），信号传输线路（10）具有串接的多个第一信号延时单元（11），每一个第一信号延时单元（11）的输出端形成采集点；多个采集单元（20），采集单元（20）与第一信号延时单元（11）的采集点连接以采集采集点处的信号；时钟单元（30），被配置为产生控制信号；比较单元（40），被配置为将控制信号的周期与标准信号的周期进行比较，并根据比较结果，产生调整信号；调整单元（50），被配置为根据调整信号调整信号传输线路（10）与时钟单元（30）的供电电压，以使控制信号的周期与标准信号的周期的比值满足设定阈值范围。

Description

一种数据采集系统及其控制方法、装置、设备和介质
本公开以2019年8月26日递交的、申请号为201910790289.4且名称为“一种数据采集系统及其控制方法、装置、设备和介质”的专利文件为优先权文件，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及数据采集领域，尤其涉及一种数据采集系统及其控制方法、装置、设备和介质。
背景技术
随着数据采集对速度性能的指标要求越来越高，高速数据采集系统在自动化控制、电器测量、航天工程实践中得到十分广泛的应用。
高速采集系统一般分为数据采集和数据处理两部分，在数据采集时，会以很高的速度采集数据，并将采集的数据存储至缓存器中，在处理单元处于空闲状态时，从缓存器中抽取数据并处理。
由于高速数据采集系统中采集数据的速度很快，且缓存器缓的存时间和存储容量均有限，当处理单元被占用或处理量过大导致处理速度较慢时，可能会造成缓冲器中存储的数据在到达处理单元之前便已失效，致使数据丢失，造成采集的数据不完整，且在数据采集过程中，采集系统中采集电路手环境和温度等情况的影响，可能会造成采集数据的采集信号的周期发生变化。
综上，发明人知晓的上述数据采集系统中，在高速采集数据时，发明人意识到可能会出现无法采集到完整的数据和采集到的信号的周期发生变化的情况。
发明内容
本公开实施例提供一种数据采集系统，用以实现在高速采集数据的同时，确保采集数据的完整以及采集到正确周期的数据。
第一方面，本公开实施例提供了一种数据采集系统，包括：
信号传输线路，信号传输线路包括串接的多个第一信号延时单元，每一个第一信号延时单元的输出端形成采集点；
多个采集单元，采集单元与第一信号延时单元一一对应，每一对相互对应的采集单元和第一信号延时单元之间，采集单元与第一信号延时单元的采集点连接以采集采集点处的信号；
与采集单元连接的时钟单元，时钟单元包括串接的一个第一反相单元和多个第二信号延时单元，第二信号延时单元与第一信号延时单元的结构相同，时钟单元被配置为产生控制信号，控制信号用于控制采集单元的采集时间；
与时钟单元连接的比较单元，被配置为将控制信号的周期与标准信号的周期进行比较，并根据比较结果，产生调整信号；
与比较单元连接的调整单元，被配置为根据调整信号调整信号传输线路与时钟单元的供电电压，以使控制信号的周期与标准信号的周期的比值满足设定阈值范围。
本公开实施例提供的数据采集系统，通过将待采集信号传输至具有多个信号延时单元的信号传输线路上传输，使待采集信号的传输时间增长，并利用采集单元从传输线路上采集信号，在采集信号时，在一些实施例中，两次采集时间之间留有一定的时长(保证未采集信号还在信号传输线路上传输)，在一些实施例中，采集到完整的信号，以保证处理单元有足够的时长对采集单元采集的信号进行处理。相比于现有的数据采集系统相比，不但保证了采集信号的完整，且为了防止信号传输线路的传输时长受工作环境的影响发生偏移，提供了与信号传输线路上的第一信号延时单元结构相同的第二信号延时单元构成的时钟单元，并将时钟单元产生的控制信号与标准时钟信号的周期进行比较，并根据比较结果，确定第二信号延时单元的延时时长偏移情况，根据第二延时单 元延时时长的偏移情况，对第一信号延时单元和第二信号延时单元的供电电压进行补偿，以使第一信号延时单元和第二延时单元的延时时长稳定在固定数值。
在一种可能的实施方式中，本公开实施例提供的上述数据采集系统中，信号传输线路中串接的第一信号延时单元的数量与时钟单元中串接的第二信号延时单元的数量相同。
本公开实施例提供的数据采集系统，由于信号传输线路中串接的第一信号延时单元的数量与时钟单元中串接的第二信号延时单元的数量相同，且第一信号延时单元与第二信号延时单元的结构相同，故第一信号延时单元构成信号传输线的传输时长的偏移情况，与时钟单元的时钟偏移情况相同，从而根据时钟偏移情况进行对第一信号延时单元和第二延时单元的电压补偿，从而保证采集到正确周期的信号。
在一种可能的实施方式中，本公开实施例提供的上述数据采集系统中，时钟单元还包括开关单元，任一第二信号延时单元的输出端与开关单元连接，开关单元被配置为控制第二信号延时单元与第一反相单元输入端的连接。
本公开实施例提供的上述数据采集系统，第二信号延时单元的输出端均连接有开关单元，通过开关单元控制第二信号延时单元的输出端与第一反相单元输入端的连接情况，由于第二信号延时单元的输出端与反相单元输入端的连接情况不同，输出的控制信号的周期不同。具体各个开关单元的状态，可以根据采集单元以及对信号进行处理的处理单元的工作情况进行设置，以获取不同周期的控制信号，以满足采集系统的要求。
在一种可能的实施方式中，本公开实施例提供的上述数据采集系统中，比较单元包括第一加法器、第二加法器以及比较单元，
第一加法器被配置为接收预设时钟装置发送的时钟信号，并对时钟信号的个数进行累计；
第二加法器被配置为接收控制信号，并对控制信号的个数进行累计；
比较单元分别与第一加法器和第二加法器连接，被配置为比较第一加法器 的累计的时钟信号次数和第二加法器的累计的控制信号次数，并根据比较结果，产生调整信号。
本公开实施例提供的数据采集系统，将产生的控制信号的周期个数和预设时钟装置产生的时钟信号的周期个数进行累计，并根据累计的个数的比较结果，确定控制信号的周期偏移情况，调整第一信号延时单元和第二信号延时单元的供电电压，保证信号传输线路上传输的信号在每个第一延时单元上传输的时长不变，以保证采集到的信号的周期稳定不变。
在一种可能的实施方式中，本公开实施例提供的上述数据采集系统中，调整单元包括比较器、滑动变阻器、金属-氧化物-半导体场效应晶体MOS管以及第一电阻，
比较器的第一输入端与标准电源连接，比较器的第二输入端与滑动变阻器的第二端连接，比较器的输出端与MOS管的栅极连接；
MOS管的源极与供电电源连接，MOS管的漏极与滑动电阻器的滑片连接；
滑动变阻器的滑片与比较单元的输出端连接，滑动变阻器的第二端与第一电阻连接；
第一电阻的第二端与地连接。
在一种可能的实施方式中，本公开实施例提供的上述数据采集系统中，信号传输线路的输入端包括第二反相单元，
第一反相单元与第二反相单元结构相同。
第二方面，本公开实施例提供了一种数据采集系统的控制方法，包括：
接收采集单元发送的不同时刻的信号；
针对接收到的每一信号，计算每一信号的处理时间；
基于每一信号的处理时间，向时钟单元发送指示信号，指示信号被配置为控制第二信号延时单元输出端设置的开关单元工作状态，以使时钟单元向采集单元发送控制信号，控制信号被配置为控制采集单元采集采集点处的信号。
本公开实施例提供的数据采集系统的控制方法，在信号传输至信号传输线 路上时，实时检测处理装置处理接收的采集单元发送的信号的时间，向采集单元发送不同的时刻的控制信号，以控制采集单元在不同时刻进行数据采集，以避免处理装置接收到多个相同的数据，浪费用于处理采集到的信号的装置的资源和时间。
第三方面，本公开实施例提供了一种数据采集的控制装置，包括：
接收单元，被配置为接收采集单元发送的不同时刻的信号；
计算单元，被配置为针对接收到的每一信号，计算每一信号的处理时间；
发送单元，被配置为基于每一信号的处理时间，向时钟单元发送指示信号，指示信号用于控制第二信号延时单元输出端设置的开关单元工作状态，以使时钟单元向采集单元发送控制信号，控制信号用于控制采集单元采集采集点处的信号。
第四方面，本公开实施例提供了一种数据采集系统的控制设备，包括：至少一个处理器、至少一个存储器以及存储在存储器中的计算机程序指令，当计算机程序指令被处理器执行时实现本公开实施例第二方面提供的数据采集系统的控制方法。
第五方面，本公开实施例提供了一种计算机存储介质，其上存储有计算机程序指令，当计算机程序指令被处理器执行时实现本公开实施例第二方面提供的数据采集系统的控制方法。
附图说明
附图用来提供对本公开的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。在附图中：
图1为本公开实施例提供的一种数据采集系统的结构示意图一；
图2为本公开实施例提供的第一信号延时单元的电路结构示意图一；
图3为本公开实施例提供的第一信号延时单元的电路结构示意图二；
图4为本公开实施例提供的第一反相单元的电路结构示意图；
图5为本公开实施例提供的开关单元的结构示意图；
图6为本公开实施例提供的比较单元的结构示意图；
图7为本公开实施例提供的调整单元的结构示意图；
图8为本公开实施例提供的数据采集系统的控制方法的示意流程图；
图9为本公开实施例提供的数据采集系统的控制装置的结构示意图；
图10为本公开实施例提供的数据采集系统的控制设备的结构示意图。
具体实施方式
以下结合附图对本公开的实施例进行说明，应当理解，此处所描述的实施例仅用于说明和解释本公开，并不用于限定本公开。
下面结合说明说附图，对本公开实施例提供的数据采集系统的具体实施方式进行说明。
本公开实施例提供了一种数据采集系统，如图1所示，包括：
信号传输线路10，信号传输线路包括串接的多个第一信号延时单元11，每一个第一信号延时单元11的输出端形成采集点；
多个采集单元20，采集单元20与第一信号延时单元11一一对应，每一对相互对应的采集单元20和第一信号延时单元11之间，采集单元20与第一信号延时单元11的采集点连接以采集采集点处的信号；
与采集单元连接的时钟单元30，时钟单元包括串接的一个第一反相单元31和多个第二信号延时单元32，第二信号延时单元32与第一信号延时单元11的结构相同，时钟单元被配置为产生控制信号，控制信号用于控制采集单元20的采集时间；
与时钟单元30连接的比较单元40，被配置为将控制信号的周期与标准信号的周期进行比较，并根据比较结果，产生调整信号；
与比较单元40连接的调整单元50，被配置为根据调整信号调整信号传输线路10与时钟单元30的供电电压，以使控制信号的周期与标准信号的周期的 比值满足设定阈值范围。
需要说明的是，设定阈值范围可以根据数据采集系统的采集精度要求以及采集系统的器件规格进行设置，本公开实施例对此不做限定。
在一种可能的实施方式中，信号传输线路10中串接的第一信号延时单元11的数量与时钟单元30中串接的第二信号延时单元32的数量相同。
其中，信号传输线路10上的第一信号延时单元11的数量可以根据数据采集系统所处的场景、连接的装置、处理装置60的处理速度以及第一信号延时单元11的延时时长进行设置，本公开实施例对此不做限定。
需要说明的是，每个第一信号延时单元11的延时时长小于或等于输入至信号传输线路10上的信号的高电平维持时长的一半，才能保证信号完整的从第一信号延时单元11上通过。
其中，在一些实施例中，本公开实施例提供的图1中的处理装置60是与数据采集系统通信连接或者电连接的处理装置，在另一些实施例中，在本公开实施例提供的数据采集系统中设置处理装置，被配置为对采集单元20采集的信号进行处理。
本公开实施例提供的第一信号延时单元11，本申请的一些实施例中，根据延时时长和用于延时的器件的不同，分为以下三种情况，具体如下：
情况一、第一信号延时单元11，包括：第一电阻和第一电容。
第一端与上一个延时电路的输出端连接，第一电阻的第二端与第一电容的第一端以及下一个延时电路的输入端连接，第一电容的第二端与地连接。
需要说明的是，第一电阻和第一电容的规格可以根据第一信号延时单元11的延时时长进行选择，本公开实施例对此不做限定。
情况二、如图2所示，本公开实施例提供的第一信号延时单元11，包括：第一金属-氧化物-半导体场效应晶体(metal oxide semiconductor，MOS)管21、第二MOS管22、第三MOS管23以及第四MOS管24。
具体的，第一MOS管21的源极与供电电源连接，第一MOS管21栅极 与上一个延时电路的输出端连接，第一MOS管21漏极与第二MOS管22的源极连接；第二MOS管22的栅极与上一个延时电路的输出端连接，第二MOS管22的漏极与第三MOS管23的漏极连接；第三MOS管23的栅极与上一个延时电路的输出端连接，第三MOS管23的源极与第四MOS管24的漏极连接；第四MOS管24的栅极与上一个延时电路的输出端连接，第四MOS管24的源极与地连接。
需要说明的是，本公开实施例提供的第一信号延时单元11中的第一MOS管、第二MOS管、第三MOS管以及第四MOS管的型号可以根据第一信号延时单元11的延时时长进行选择，本公开实施例对此不做限定。
情况三、如图3所示，本公开实施例提供的第一信号延时单元11，包括：第一二极管111、第二二极管112以及第二电阻113。
具体的，第一二极管111的阳极与上一个第一信号延时单元的输出端连接，第一二极管111的阴极与第二电阻113的第二端连接，第二二极管112的阳极与上一个第一信号延时单元的输出端连接，第二二极管112的阴极与第二电阻113的第二端连接，第二电阻113的第一端与供电电源连接，第二电阻113的第二端与下一个第一信号延时单元的输入端连接。
需要说明的是，在本实施例中的第一二极管111、第二二极管112以及第二电阻113的型号可以根据第一信号延时单元11的延时时长进行选择，本公开实施例对此不做限定。
需要说明的是，为了减小数据采集系统的体积和功耗，本公开的一些实施例提供的第一信号延时单元11的三种情况为集成电路，本公开实施例对此不做限定。
其中，在本公开其它实施例中，第一信号延时单元11是其它可以实现信号延时的电路或装置，本公开实施例对比不做限定。
在一种可能的实施方式中，为了避免信号在传输到信号传输线路之前受到电磁干扰造成的信号变形，在信号传输线路的输入端设置第二反相单元。
需要说明的是，第一反相单元和第二反相单元的结构相同。
在一种可能的实施方式中，如图4所示，第二反相单元包括互补金属氧化物半导体CMOS反相器。
在一示例中，信号传输线路的输入端包括两个第二反相单元。
其中，在本公开实施例优先采用使用CMOS反相器集成电路，以减小数据采集系统的损耗。
需要说明的是，在本公开其它实施例中第二反相单元采用其它可以实现反相功能的装置或电路，本公开对此不做限定。
在一种可能的实施方式中，采集单元20包括D类触发器，D类触发器的输入端与第一信号延时单元11的输出端连接，D类触发器的输出端与处理单元30连接，D类触发器的控制端接收用于控制采集单元20采集时间的控制信号。
需要说明的是，为了避免出现信号处于第一信号延时单元上，从而造成无法采集的情况，采集单元的采集时长与信号延时单元的延时时长并不相同，以保证采集到完整的信号。
在一示例中，D类触发器的控制端与时钟单元连接，以接收时钟单元发送的控制信号，并基于接收到的控制信号对采集点处的信号进行采集。
在一种可能的实施方式中，如图5所示，时钟单元30还包括开关单元33，用于产生控信号的时钟单元30中任一第二信号延时单元32的输出端连接有开关单元33，开关单元33被配置为控制第二信号延时单元32与反相单元31输入端的连接。
在一种可能的实施方式中，如图6所示，本公开实施例提供的比较单元40，包括：
第一加法器41、第二加法器42以及比较单元43，第一加法器41被配置为接收预设时钟装置发送的时钟信号，并对时钟信号的个数进行累计，第二加法器42被配置为接收控制信号，并对控制信号的个数进行累计，比较单元43 与第一加法器41和第二加法器42连接，被配置为比较第一加法器41的累计的时钟信号次数和第二加法器42的累计的控制信号次数，并根据比较结果，产生调整信号。
需要说明的是，在本公开的一些实施例中，时钟装置是晶体振荡器，具体晶体振荡器的类型可以根据数据采集系统的需求以及晶体振荡器的精准度进行选择，本发明实施例对此不做限定。
在本公开的一些实施例中，时钟装置设置在本公开实施例提供的数据采集系统中，在本公开的另一些实施例中，时钟装置是与本公开实施例提供的数据采集系统通信连接其它装置中的器件，本公开实施例对此不做限定。
需要说明的是，第一加法器41和第二加法器42的计数总个数可以根据实际需求进行设置，例如，依据数据采集系统要求的采集精准度进行设置，本公开实施例对此不做限定。
在一种可能的实施方式中，如图7所示，本公开实施例提供的调整单元50，包括,比较器51、滑动变阻器52、第五MOS管53以及第三电阻54。
比较器51的第一输入端与标准电源连接，比较器51的第二输入端与滑动变阻器52的第二端连接，比较器51的输出端与第五MOS管53的栅极连接，第五MOS管53的源极与供电电源连接，第五MOS管53的漏极与滑动电阻器52的滑片连接，滑动变阻器52的滑片与比较单元40的输出端连接，滑动变阻器52的第二端与第三电阻54连接，第三电阻54的第二端与地连接。
结合图1-图7，本公开实施例提供数据采集系统，如图1所示，其工作原理如下：
信号从信号传输线路10的输入端1进行反相单元(未示出)中，得到理想波形的信号，并将反相单元输出的信号传输至由多个第一信号延时单元11中进行延时传输，在传输过程中，检测处理装置60的工作状态，在确定处理装置60处于空闲状态时，处理装置60向时钟单元30发送用于控制开关单元(未示出)工作状态的指示信号，以产生控制信号，并将控制信号发送给采集 单元20，以使控制采集单元20进行信号采集，并将采集的信号传输至处理装置60中进行信号处理。
在数据采集过程中，与时钟单元30连接的比较单元40中的第一加法器(未示出)对控制周期的周期个数进行累计，通过第二加法器(未示出)对标准信号的周期个数进行累计，并根据预设时长第一加法器和第二加法器的累计个数的比值，确定第一信号延时单元11和第二延时单元32的延时时长是否发生偏移，并根据偏移情况调整调整单元50中滑动变阻器(未示出)的滑片位置，从而改变与滑动变阻器第二端连接的比较器(未示出)的第二端的点位，并根据该点位与标准电压的比较结果，改变滑动变阻器的电位，从而改变与滑动变阻器连接的信号传输线路10与时钟单元30中各个单元的供电电压，以使控制信号的周期与标准信号的周期的比值满足设定阈值范围。
基于图1-图7描述的本公开实施例的数据采集系统，本公开实施例提供了一种数据采集系统的控制方法，如图8所示，在一些实施例中，包括如下步骤：
步骤801、接收采集单元发送的不同时刻的信号。
步骤802、针对接收到的每一信号，计算每一信号的处理时间。
步骤803、基于每一信号的处理时间，向时钟单元发送指示信号，指示信号用于控制第二信号延时单元输出端设置的开关单元工作状态，以使时钟单元向采集单元发送控制信号，控制信号用于控制采集单元采集采集点处的信号。
基于相同的发明构思，本公开实施例还提供一种数据采集系统的控制装置。
如图9所示，本公开实施例提供的数据采集系统的控制装置，包括：
接收单元901，被配置为接收采集单元发送的不同时刻的信号；
计算单元902，被配置为针对接收到的每一信号，计算每一信号的处理时间；
发送单元903，被配置为基于每一信号的处理时间，向时钟单元发送指示信号，指示信号用于控制第二信号延时单元输出端设置的开关单元工作状态，以使时钟单元向采集单元发送控制信号，控制信号用于控制采集单元采集采集 点处的信号。
另外，在一些实施例中，结合图8图9描述的本公开实施例的数据采集系统的控制方法和装置由数据采集系统的控制设备来实现。图10示出了本公开实施例提供的数据采集系统的控制设备的硬件结构示意图。
在另一些实施例中，数据采集系统的控制设备包括处理器1001以及存储有计算机程序指令的存储器1002。
具体地，在一些实施例中，上述处理器1001包括中央处理器(CPU)，或者特定集成电路(Application Specific Integrated Circuit，ASIC)，或者可以被配置成实施本公开实施例的一个或多个集成电路。
一些实施例中，存储器1002包括用于数据或指令的大容量存储器。举例来说而非限制，存储器1002可包括硬盘驱动器(Hard Disk Drive，HDD)、软盘驱动器、闪存、光盘、磁光盘、磁带或通用串行总线(Universal Serial Bus，USB)驱动器或者两个或更多个以上这些的组合。在合适的情况下，存储器1002可包括可移除或不可移除(或固定)的介质。在合适的情况下，存储器1002可在数据处理装置的内部或外部。在特定实施例中，存储器1002是非易失性固态存储器。在特定实施例中，存储器1002包括只读存储器(ROM)。在合适的情况下，该ROM是掩模编程的ROM、可编程ROM(PROM)、可擦除PROM(EPROM)、电可擦除PROM(EEPROM)、电可改写ROM(EAROM)或闪存或者两个或更多个以上这些的组合。
处理器1001通过读取并执行存储器1002中存储的计算机程序指令，以实现上述实施例中的任意一种数据采集系统的控制方法。
在一个示例中，数据采集系统的控制设备还可包括通信接口1003和总线1010。其中，如图10所示，处理器1001、存储器1002、通信接口1003通过总线1010连接并完成相互间的通信。
通信接口1003，主要用于实现本公开实施例中各装置、装置、单元和/或设备之间的通信。
总线1010包括硬件、软件或两者，将数据采集系统的控制设备的部件彼此耦接在一起。举例来说而非限制，总线可包括加速图形端口(AGP)或其他图形总线、增强工业标准架构(EISA)总线、前端总线(FSB)、超传输(HT)互连、工业标准架构(ISA)总线、无限带宽互连、低引脚数(LPC)总线、存储器总线、微信道架构(MCA)总线、外围组件互连(PCI)总线、PCI-Express(PCI-X)总线、串行高级技术附件(SATA)总线、视频电子标准协会局部(VLB)总线或其他合适的总线或者两个或更多个以上这些的组合。在合适的情况下，总线1010可包括一个或多个总线。尽管本公开实施例描述和示出了特定的总线，但本公开考虑任何合适的总线或互连。
在另一些实施例中，数据采集系统的控制设备基于数据采集系统中处理单元的状态，执行本公开实施例中的数据采集系统的控制方法，从而实现结合图8-图10描述的数据采集系统的控制方法和装置。
另外，结合上述实施例中的数据采集系统的控制方法，本公开实施例可提供一种计算机可读存储介质来实现。该计算机可读存储介质上存储有计算机程序指令；该计算机程序指令被处理器执行时实现上述实施例中的任意一种数据采集系统的控制方法。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算 机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种数据采集系统，其特征在于，包括：
    信号传输线路，所述信号传输线路包括串接的多个第一信号延时单元，每一个所述第一信号延时单元的输出端形成采集点；
    多个采集单元，所述采集单元与所述第一信号延时单元一一对应，每一对相互对应的采集单元和第一信号延时单元之间，所述采集单元与所述第一信号延时单元的采集点连接以采集所述采集点处的信号；
    与所述采集单元连接的时钟单元，所述时钟单元包括串接的一个第一反相单元和多个第二信号延时单元，所述第二信号延时单元与所述第一信号延时单元的结构相同，所述时钟单元被配置为产生控制信号，所述控制信号用于控制所述采集单元的采集时间；
    与所述时钟单元连接的比较单元，被配置为将所述控制信号的周期与标准信号的周期进行比较，并根据比较结果，产生调整信号；
    与所述比较单元连接的调整单元，被配置为根据所述调整信号调整所述信号传输线路与所述时钟单元的供电电压，以使所述控制信号的周期与所述标准信号的周期的比值在设定阈值范围。
  2. 根据权利要求1所述的系统，其特征在于，所述信号传输线路中串接的所述第一信号延时单元的数量与所述时钟单元中串接的所述第二信号延时单元的数量相同。
  3. 根据权利要求1所述的系统，其特征在于，所述时钟单元还包括开关单元，任一所述第二信号延时单元的输出端与所述开关单元连接，所述开关单元被配置为控制所述第二信号延时单元与所述第一反相单元输入端的连接。
  4. 根据权利要求1所述的系统，其特征在于，所述比较单元包括第一加法器、第二加法器以及比较单元，
    所述第一加法器被配置为接收预设时钟装置发送的时钟信号，并对所述时钟信号的个数进行累计；
    所述第二加法器被配置为接收所述控制信号，并对所述控制信号的个数进行累计；
    所述比较单元分别与所述第一加法器和所述第二加法器连接，被配置为比较所述第一加法器的累计的所述时钟信号次数和所述第二加法器的累计的所述控制信号次数，并根据比较结果，产生调整信号。
  5. 根据权利要求4所述的系统，其特征在于，所述调整单元包括比较器、滑动变阻器、金属-氧化物-半导体场效应晶体MOS管以及第一电阻，
    所述比较器的第一输入端与标准电源连接，所述比较器的第二输入端与所述滑动变阻器的第二端连接，所述比较器的输出端与所述MOS管的栅极连接；
    所述MOS管的源极与供电电源连接，所述MOS管的漏极与所述滑动电阻器的滑片连接；
    所述滑动变阻器的所述滑片与所述比较单元的输出端连接，所述滑动变阻器的第二端与所述第一电阻连接；
    所述第一电阻的第二端与地连接。
  6. 根据权利要求1所述的系统，其特征在于，所述信号传输线路的输入端包括第二反相单元，
    所述第一反相单元与所述第二反相单元结构相同。
  7. 一种数据采集系统的控制方法，应用于权利要求1-6任一项所述的数据采集系统，其特征在于，包括：
    接收所述采集单元发送的不同时刻的信号；
    针对接收到的每一信号，计算每一信号的处理时间；
    基于所述每一信号的处理时间，向所述时钟单元发送指示信号，所述指示信号用于控制所述第二信号延时单元输出端设置的开关单元工作状态，以使所述时钟单元向所述采集单元发送控制信号，所述控制信号用于控制所述采集单元采集采集点处的信号。
  8. 一种数据采集系统的控制装置，其特征在于，包括：
    接收单元，被配置为接收采集单元发送的不同时刻的信号；
    计算单元，被配置为针对接收到的每一信号，计算每一信号的处理时间；
    发送单元，被配置为基于所述每一信号的处理时间，向时钟单元发送指示信号，所述指示信号被配置为控制第二信号延时单元输出端设置的开关单元工作状态，以使所述时钟单元向所述采集单元发送控制信号，所述控制信号被配置为控制所述采集单元采集采集点处的信号。
  9. 一种数据采集系统的控制设备，其特征在于，包括：至少一个处理器、至少一个存储器以及存储在所述存储器中的计算机程序指令，当所述计算机程序指令被处理器执行时实现如权利要求7所述的数据采集系统的控制方法。
  10. 一种计算机可读存储介质，其上存储有计算机程序指令，其特征在于，当计算机程序指令被处理器执行时实现如权利要求7所述的数据采集系统的控制方法。
PCT/CN2020/096629 2019-08-26 2020-06-17 一种数据采集系统及其控制方法、装置、设备和介质 WO2021036431A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/624,821 US11914418B2 (en) 2019-08-26 2020-06-17 Systems, methods, and apparatuses for performing high-speed data acquisition and maintaining data integrity

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910790289.4 2019-08-26
CN201910790289.4A CN110647067B (zh) 2019-08-26 2019-08-26 一种数据采集系统及其控制方法、装置、设备和介质

Publications (1)

Publication Number Publication Date
WO2021036431A1 true WO2021036431A1 (zh) 2021-03-04

Family

ID=69009814

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/096629 WO2021036431A1 (zh) 2019-08-26 2020-06-17 一种数据采集系统及其控制方法、装置、设备和介质

Country Status (3)

Country Link
US (1) US11914418B2 (zh)
CN (1) CN110647067B (zh)
WO (1) WO2021036431A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110647067B (zh) 2019-08-26 2020-11-03 珠海格力电器股份有限公司 一种数据采集系统及其控制方法、装置、设备和介质
CN112485515B (zh) * 2020-12-11 2022-12-30 广东电网有限责任公司 一种用于电能表费率时段更正方法及系统
CN112601193B (zh) * 2020-12-16 2023-03-10 深圳数联天下智能科技有限公司 一种数据传输方法及其相关装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101587499A (zh) * 2009-06-24 2009-11-25 北京理工大学 基于nand的多通道信号采集系统
CN103136146A (zh) * 2011-12-01 2013-06-05 鸿富锦精密工业（深圳）有限公司 信号采集系统及方法
US20150059432A1 (en) * 2013-08-27 2015-03-05 Crystal Instruments Corporation Cross-path phase calibration for high dynamic range data acquisition
CN107359947A (zh) * 2016-11-07 2017-11-17 天地融科技股份有限公司 电路延时自检测装置和系统
CN109714145A (zh) * 2018-12-29 2019-05-03 杭州迪普科技股份有限公司 一种多通道数据对齐的方法及装置
CN110647067A (zh) * 2019-08-26 2020-01-03 珠海格力电器股份有限公司 一种数据采集系统及其控制方法、装置、设备和介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758644A (ja) * 1993-08-20 1995-03-03 Matsushita Electric Ind Co Ltd 信号圧縮装置
US5719511A (en) * 1996-01-31 1998-02-17 Sigma Designs, Inc. Circuit for generating an output signal synchronized to an input signal
KR100735548B1 (ko) * 2006-01-10 2007-07-04 삼성전자주식회사 지연동기회로 및 방법
CN100465934C (zh) * 2006-05-09 2009-03-04 华为技术有限公司 一种在异步时钟域传输数据的装置及其方法
CN101477581B (zh) * 2008-12-19 2011-05-04 上海理工大学 多智能体区域道路交叉口信号集成控制仿真系统
CN201654786U (zh) * 2009-12-31 2010-11-24 广东正业科技股份有限公司 一种可编程步进延时时基和采样系统
CN107861412A (zh) * 2017-09-27 2018-03-30 全球能源互联网研究院有限公司 信号采集方法、装置及系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101587499A (zh) * 2009-06-24 2009-11-25 北京理工大学 基于nand的多通道信号采集系统
CN103136146A (zh) * 2011-12-01 2013-06-05 鸿富锦精密工业（深圳）有限公司 信号采集系统及方法
US20150059432A1 (en) * 2013-08-27 2015-03-05 Crystal Instruments Corporation Cross-path phase calibration for high dynamic range data acquisition
CN107359947A (zh) * 2016-11-07 2017-11-17 天地融科技股份有限公司 电路延时自检测装置和系统
CN109714145A (zh) * 2018-12-29 2019-05-03 杭州迪普科技股份有限公司 一种多通道数据对齐的方法及装置
CN110647067A (zh) * 2019-08-26 2020-01-03 珠海格力电器股份有限公司 一种数据采集系统及其控制方法、装置、设备和介质

Also Published As

Publication number Publication date
CN110647067B (zh) 2020-11-03
US20220317724A1 (en) 2022-10-06
US11914418B2 (en) 2024-02-27
CN110647067A (zh) 2020-01-03

Similar Documents

Publication Publication Date Title
WO2021036431A1 (zh) 一种数据采集系统及其控制方法、装置、设备和介质
US9673968B2 (en) Multi-wire open-drain link with data symbol transition based clocking
KR20120035755A (ko) 적응형 지연 조절 기능이 구비된 데이터 인터페이스 장치
US20120072759A1 (en) Timing Error Correction System and Method
JP2019161586A (ja) リンギング抑制回路
CN111262559A (zh) 具有校正功能的延迟线电路及其校正方法
CN110266303B (zh) 刷新电路、方法、芯片及数据传输系统
US7369636B2 (en) Asynchronous communication circuit
US20190372749A1 (en) Communication device
CN107197190B (zh) 一种视频时钟的生成方法及装置
CN112433482A (zh) 一种数据采集系统及其控制方法、装置、设备和介质
US7378831B1 (en) System and method for determining a delay time interval of components
JP2018206231A (ja) 電子制御装置
CN105629013B (zh) 一种用于电能计量的定时防潜动装置及其方法
CN104883161A (zh) 混沌脉宽调制和混沌冲激位置调制电路
CN111258243A (zh) 驱动保护电路及操作电路
CN104734675A (zh) 串行信号通信接收端的信号检测电路和方法
CN204597914U (zh) 混沌脉宽调制和混沌冲激位置调制电路
JP6167290B2 (ja) 送信用デバイス、受信用デバイス、伝送装置、送信方法および受信方法
CN110231600B (zh) 一种脉冲整形方法及脉冲整形电路
WO2022264201A1 (ja) 制御・監視信号伝送システム
CN109150354A (zh) 一种时间触发以太网中压缩修正值的计算方法
CN115037285A (zh) 时钟校准装置、设备及方法
US11265043B2 (en) Communication circuit, communication system, and communication method
US20220278819A1 (en) Timing detection and correction method for a slave device in an io-link communication and slave device of an io-link communication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20858654

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20858654

Country of ref document: EP

Kind code of ref document: A1