WO2021035800A1 - 基于同步通道运作架构闪存主控之高效能指令序列控制模块 - Google Patents

基于同步通道运作架构闪存主控之高效能指令序列控制模块 Download PDF

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WO2021035800A1
WO2021035800A1 PCT/CN2019/105067 CN2019105067W WO2021035800A1 WO 2021035800 A1 WO2021035800 A1 WO 2021035800A1 CN 2019105067 W CN2019105067 W CN 2019105067W WO 2021035800 A1 WO2021035800 A1 WO 2021035800A1
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flash memory
controller
sequence
flash
central
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French (fr)
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陈育鸣
李庭育
魏智汎
洪振洲
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江苏华存电子科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present invention relates to the technical field of a high-efficiency instruction sequence controller based on a synchronous channel operation architecture flash memory master control, and specifically relates to a high-efficiency instruction sequence controller based on a synchronous channel operation architecture flash memory master control.
  • the current flash memory master control design requires the processor to do more registers for each flash memory master control module when issuing read or write instructions to multiple flash memory components that perform synchronous channel reads and writes in the super page or super block configuration mode. A similar read and write action is required to complete the operation code control required by the flash memory instruction sequence.
  • This method is not only time-consuming and inefficient, but also consumes a huge amount of processor resources. Especially when frequent operations need to be performed on flash super pages or super blocks, the operating performance cannot be effectively improved. Therefore, an improved technology is urgently needed to solve this problem in the prior art.
  • the purpose of the present invention is to provide a high-performance command sequence controller based on a synchronous channel operation architecture flash memory master to solve the above-mentioned problems in the background art.
  • a high-performance command sequence controller based on a synchronous channel operation architecture flash memory master control, including a master control chip, a central controller, a flash memory storage controller, a flash memory storage component, and a central control Registers, flash super page/block sequence manager, parameter sequence table, the main control chip is provided with a central controller and a number of flash memory storage controllers, the central controller is connected to all flash memory storage controllers, each The flash memory storage controller corresponds to the flash memory storage component, and the central controller is provided with a central control register, a flash super page/block sequence manager, and a parameter sequence table.
  • the flash memory storage controller is provided with an instruction sequence control module, a flash memory sequence controller, and a parameter table, the flash memory sequence controller is respectively connected to the instruction sequence control module and the parameter table, and the flash memory sequence controller is connected to the corresponding The flash memory storage components are connected.
  • the method of use includes the following steps:
  • Step 1 Configure the hub controller of the flash command sequence generator, so that when the host needs to issue arbitrary commands such as read or write to the super block or super page configuration multiple flash memory components, only the processor needs to be mastered from the hub
  • the central controller directly calls any pre-stored flash memory command sequence, transmits or schedules the command to the individual flash memory channel sequence control module, and the individual flash memory storage controller issues the flash memory storage components quickly and without error Arbitrary instruction sequence completes various instruction programs such as reading, writing and erasing;
  • Step 2 After the individual flash memory channel sequence control module receives the same group or different groups of instructions from the central controller or sorts the instructions into a separate instruction queue, it will perform any parameters and physical addresses or characteristics of the flash memory sequence instructions Values and other items, replace the additional configuration parameters of each channel or the remapped physical address and other items;
  • Step 3 If the super page or the super block only needs to write or read part of the page or part of the block, the central controller can also cover the command or the function of individual channels, and then control some but not all channels.
  • the flash memory storage controller grants instructions to enter the queue to achieve the partial write or partial read operation of the super page or super block.
  • Figure 1 is a schematic diagram of the structure of the present invention.
  • Figure 2 is a schematic diagram of the structure of the flash memory storage controller.
  • Fig. 3 is a schematic diagram of the state of the multi-channel flash memory storage controller inside the master chip and the configuration central flash memory command sequence controller.
  • Fig. 4 is a schematic diagram of a situation where the multi-channel flash memory storage controller inside the main control chip is not configured with a central flash memory command sequence controller.
  • the main control chip 1 the central controller 2, the flash memory storage controller 3, the flash memory storage component 4, the central control register 5, the flash super page/block sequence manager 6, the parameter sequence table 7, the instruction sequence control module 8, Flash memory sequence controller 9, parameter table 10.
  • a high-performance command sequence controller based on a synchronous channel operation architecture flash memory master control, including a master chip 1, a central controller 2, a flash memory storage controller 3, and a flash memory storage Component 4, central control register 5, flash super page/block sequence manager 6, parameter sequence table 7, the main control chip 1 is provided with a central controller 2 and a number of flash memory storage controllers 3, the central controller 2 and all The flash memory storage controllers 3 are connected, and each flash memory storage controller 3 corresponds to the flash memory storage component 4.
  • the hub controller 2 is provided with a hub control register 5, a flash memory super page/block sequence manager 6 and a parameter sequence table 7 inside.
  • the flash memory storage controller 3 is provided with an instruction sequence control module 8, a flash memory sequence controller 9 and a parameter table 10.
  • the flash memory sequence controller 9 is respectively connected to the instruction sequence control module 8 and the parameter table 10.
  • the controller 9 is connected to the corresponding flash storage component 4.
  • a high-performance command sequence controller based on a synchronous channel operation architecture flash memory master control includes the following steps:
  • Step 1 Configure the hub controller 2 of the flash memory command sequence generator, so that when the host needs to issue arbitrary instructions such as read or write to the super block or super page configuration multiple flash memory components, only the processor needs to be sent from the hub
  • the central controller 2 directly calls any pre-stored flash memory command sequence, transmits or schedules the command to the individual flash memory channel sequence control module, and the individual flash memory storage controller 3 quickly and accurately checks the flash memory.
  • the storage component 4 issues arbitrary instruction sequences to complete various instruction programs such as reading, writing and erasing;
  • Step 2 After the individual flash memory channel sequence control module receives the same group or different groups of instructions from the central controller 2 or sorts the instructions into a separate instruction queue, it will perform any parameter and physical address of the flash memory sequence instruction. Items such as characteristic value, re-replacement of the additional configuration parameters of each channel or the remapped physical address and other items;
  • Step 3 If the super page or the super block only needs to write or read part of the page or part of the block, the central controller 2 can also mask the command or the function of individual channels, and then perform some but not all channels
  • the flash memory storage controller 3 grants instructions to enter the queue to achieve the partial write or partial read operation of the super page or super block.
  • each channel interface function sequentially issues command sequences, and the flash memory main control module The work efficiency is low.

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Abstract

一种基于同步通道运作架构闪存主控之高效能指令序列控制器，包括主控芯片（1）、中枢控制器（2）、闪存储存控制器（3）、闪存储存组件（4）、中枢控制寄存器（5）、闪存超级页/块序列管理器（6）、参数序列表（7），主控芯片（1）内部设置有中枢控制器（2）和若干个闪存储存控制器（3），中枢控制器（2）与所有的闪存储存控制器（3）相连，每个闪存储存控制器（3）与闪存储存组件（4）相对应，中枢控制器（2）内部设置有中枢控制寄存器（5）、闪存超级页/块序列管理器（6）及参数序列表（7）。该方案各个闪存接口可以同时发出指令序列，有效的提升整体闪存主控模块的工作效能。

Description

基于同步通道运作架构闪存主控之高效能指令序列控制模块 技术领域
本发明涉及基于同步通道运作架构闪存主控之高效能指令序列控制器技术领域，具体为一种基于同步通道运作架构闪存主控之高效能指令序列控制器。
背景技术
现行闪存主控设计在对超级页或超级块配置方式进行同步通道读写的多个闪存组件进行发出读取或写入指令操作时,需要由处理器对各别闪存主控模块之寄存器做多次类似的读写动作以完成闪存指令序列所需之操作代码控制,此方式不但耗时没效率,对于处理器资源之占用也非常巨大。特别是在需要对闪存超级页或超级块做频繁操作时无法有效提升操作性能，因此，亟待一种改进的技术来解决现有技术中所存在的这一问题。
发明内容
本发明的目的在于提供一种基于同步通道运作架构闪存主控之高效能指令序列控制器，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种基于同步通道运作架构闪存主控之高效能指令序列控制器，包括主控芯片、中枢控制器、闪存储存控制器、闪存储存组件、中枢控制寄存器、闪存超级 页/块序列管理器、参数序列表，所述主控芯片内部设置有中枢控制器和若干个闪存储存控制器，所述中枢控制器与所有的闪存储存控制器相连，每个所述闪存储存控制器与闪存储存组件相对应，所述中枢控制器内部设置有中枢控制寄存器、闪存超级页/块序列管理器及参数序列表。
优选的，所述闪存储存控制器内部设置有指令序列控制模块、闪存序列控制器及参数表，所述闪存序列控制器分别与指令序列控制模块及参数表相连，所述闪存序列控制器与对应的闪存储存组件相连。
优选的，其使用方法包括以下步骤：
步骤一：配置闪存指令序列产生器的中枢控制器，使主控端在需要对超级块或超级页配置多个闪存组件发出读取或写入等任意指令时,只需要由处理器从中枢主控制寄存器读写少数信息后,中枢控制器直接调用事先预存的任意一个闪存指令序列,发射或排程指令到个别闪存通道序列控制模块,并由个别闪存储存控制器快速无误的对闪存储存组件发出任意指令序列完成各种读写与抹除等各种指令程序；
步骤二：个别闪存通道序列控制模块在收到中枢控制器下达的同一组或不同组指令或将该指令排序进入各别指令队列之后,会对该闪存序列指令之任意参数与物理位址或特征值等项目,重新置换掉各别通道另外配置的参数或重新映射之物理位址等项目；
步骤三：若超级页或超级块仅需进行部份页或部份块之写入或读出时,中枢控制器也可以遮蔽指令或个别通道职能的方式,进而对部份而非全部通道的闪存储存控制器授予指令进入队列中,以达成该次超级页或超级块的部份写或部份读的操作。
与现有技术相比，本发明的有益效果是：
配置中枢闪存指令序列产生器的主控制器,以同时控制控制多组个别闪存通道的闪存指令队列控制器,使主控端在需要对超级块或超级页配置的多个闪存组件发出读取或写入等任意指令时,只需要由处理器读写少数信息予闪存指令序列产生器之中枢主控制器的寄存器后,藉由直接调用中枢主控制器内已事先预存的任一闪存指令序列,快速无误的发射或排程指令到个别闪存通道序列控制模块,再由个别序列控制模块对各别闪存组件发出任意指令序列,并由各别控制器对各别闪存组件完成各种读写与抹除等指令程序,藉以有效提升整体闪存主控模块的工作效能。
附图说明
图1为本发明的结构示意图。
图2为闪存储存控制器的结构示意图。
图3为主控芯片内部的多通道闪存储存控制器及配置中枢闪存指令序列控制器的状况示意图。
图4为主控芯片内部的多通道闪存储存控制器但未配置中枢闪存指令序列控制器的状况示意图。
图中，主控芯片1、中枢控制器2、闪存储存控制器3、闪存储存组件4、中枢控制寄存器5、闪存超级页/块序列管理器6、参数序列表7、指令序列控制模块8、闪存序列控制器9、参数表10。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明提供一种技术方案：一种基于同步通道运作架构闪存主控之高效能指令序列控制器，包括主控芯片1、中枢控制器2、闪存储存控制器3、闪存储存组件4、中枢控制寄存器5、闪存超级页/块序列管理器6、参数序列表7，主控芯片1内部设置有中枢控制器2和若干个闪存储存控制器3，中枢控制器2与所有的闪存储存控制器3相连，每个闪存储存控制器3与闪存储存组件4相对应，中枢控制器2内部设置有中枢控制寄存器5、闪存超级页/块序列管理器6及参数序列表7。
如图2所示，闪存储存控制器3内部设置有指令序列控制模块 8、闪存序列控制器9及参数表10，闪存序列控制器9分别与指令序列控制模块8及参数表10相连，闪存序列控制器9与对应的闪存储存组件4相连。
如图3所示，一种基于同步通道运作架构闪存主控之高效能指令序列控制器，其使用方法包括以下步骤：
步骤一：配置闪存指令序列产生器的中枢控制器2，使主控端在需要对超级块或超级页配置多个闪存组件发出读取或写入等任意指令时,只需要由处理器从中枢主控制寄存器读写少数信息后,中枢控制器2直接调用事先预存的任意一个闪存指令序列,发射或排程指令到个别闪存通道序列控制模块,并由个别闪存储存控制器3快速无误的对闪存储存组件4发出任意指令序列完成各种读写与抹除等各种指令程序；
步骤二：个别闪存通道序列控制模块在收到中枢控制器2下达的同一组或不同组指令或将该指令排序进入各别指令队列之后,会对该闪存序列指令之任意参数与物理位址或特征值等项目,重新置换掉各别通道另外配置的参数或重新映射之物理位址等项目；
步骤三：若超级页或超级块仅需进行部份页或部份块之写入或读出时,中枢控制器2也可以遮蔽指令或个别通道职能的方式,进而对部份而非全部通道的闪存储存控制器3授予指令进入队列中,以达成该次超级页或超级块的部份写或部份读的操作。
实施例的，如图4所示，如果主控芯片内部的多通道闪存储存控制器但未配置中枢闪存指令序列控制器的情况下，各个通道接口职能依序各自发出指令序列，闪存主控模块的工作效能较低。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (3)

  1. 一种基于同步通道运作架构闪存主控之高效能指令序列控制器，其特征在于：包括主控芯片(1)、中枢控制器(2)、闪存储存控制器(3)、闪存储存组件(4)、中枢控制寄存器(5)、闪存超级页/块序列管理器(6)及参数序列表(7)，所述主控芯片(1)内部设置有中枢控制器(2)和若干个闪存储存控制器(3)，所述中枢控制器(2)与所有的闪存储存控制器(3)相连，每个所述闪存储存控制器(3)与闪存储存组件(4)相对应，所述中枢控制器(2)内部设置有中枢控制寄存器(5)、闪存超级页/块序列管理器(6)及参数序列表(7)。
  2. 根据权利要求1所述的一种基于同步通道运作架构闪存主控之高效能指令序列控制器，其特征在于：所述闪存储存控制器(3)内部设置有指令序列控制模块(8)、闪存序列控制器(9)及参数表(10)，所述闪存序列控制器(9)分别与指令序列控制模块(8)及参数表(10)相连，所述闪存序列控制器(9)与对应的闪存储存组件(4)相连。
  3. 根据权利要求1所述的一种基于同步通道运作架构闪存主控之高效能指令序列控制器，其特征在于：其使用方法包括以下步骤：
    步骤一：配置闪存指令序列产生器的中枢控制器(2)，使主控端在需要对超级块或超级页配置多个闪存组件发出读取或写入等任意指令时,只需要由处理器从中枢主控制寄存器读写少数信息后,中枢控制器(2)直接调用事先预存的任意一个闪存指令序列,发射或排程指令到个别闪存通道序列控制模块,并由个别闪存储存控制器(3) 快速无误的对闪存储存组件(4)发出任意指令序列完成各种读写与抹除等各种指令程序；
    步骤二：个别闪存通道序列控制模块在收到中枢控制器(2)下达的同一组或不同组指令或将该指令排序进入各别指令队列之后,会对该闪存序列指令之任意参数与物理位址或特征值等项目,重新置换掉各别通道另外配置的参数或重新映射之物理位址等项目；
    步骤三：若超级页或超级块仅需进行部份页或部份块之写入或读出时,中枢控制器(2)也可以遮蔽指令或个别通道职能的方式,进而对部份而非全部通道的闪存储存控制器(3)授予指令进入队列中,以达成该次超级页或超级块的部份写或部份读的操作。
PCT/CN2019/105067 2019-08-27 2019-09-10 基于同步通道运作架构闪存主控之高效能指令序列控制模块 WO2021035800A1 (zh)

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