WO2021035419A1 - 显示基板及其制作方法 - Google Patents

显示基板及其制作方法 Download PDF

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Publication number
WO2021035419A1
WO2021035419A1 PCT/CN2019/102312 CN2019102312W WO2021035419A1 WO 2021035419 A1 WO2021035419 A1 WO 2021035419A1 CN 2019102312 W CN2019102312 W CN 2019102312W WO 2021035419 A1 WO2021035419 A1 WO 2021035419A1
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Prior art keywords
light
layer
carrier injection
injection layer
emitting element
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PCT/CN2019/102312
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English (en)
French (fr)
Inventor
杨盛际
王辉
陈小川
黄冠达
王晏酩
卢鹏程
宋亚歌
刘光通
李健通
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/960,046 priority Critical patent/US11539017B2/en
Priority to PCT/CN2019/102312 priority patent/WO2021035419A1/zh
Priority to EP19932229.8A priority patent/EP4020609A4/en
Priority to CN201980001469.8A priority patent/CN112703615B/zh
Publication of WO2021035419A1 publication Critical patent/WO2021035419A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/17—Carrier injection layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/125—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light
    • H10K50/13—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light comprising stacked EL layers within one EL unit
    • H10K50/131—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light comprising stacked EL layers within one EL unit with spacer layers between the electroluminescent layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
    • H10K50/15—Hole transporting layers
    • H10K50/156—Hole transporting layers comprising a multilayered structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
    • H10K50/16—Electron transporting layers
    • H10K50/166—Electron transporting layers comprising a multilayered structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/876—Arrangements for extracting light from the devices comprising a resonant cavity structure, e.g. Bragg reflector pair

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a manufacturing method thereof.
  • Micro OLED (Micro OLED) displays involve the combination of organic light-emitting diode (OLED) technology and CMOS technology, and are related to the cross-integration of the optoelectronics industry and the microelectronics industry, which promotes the development of a new generation of micro display technology and also promotes organic electronics on silicon , And even the research and development of molecular electronics on silicon.
  • OLED organic light-emitting diode
  • Micro OLED (Micro OLED) displays have excellent display characteristics, such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption, and have broad development prospects.
  • Some embodiments of the present disclosure provide a display substrate having a first sub-pixel area and a second sub-pixel area adjacent to each other.
  • the display substrate includes a base substrate, and a first conductive layer sequentially disposed on the base substrate , An organic functional layer and a second conductive layer, the organic functional layer includes a carrier injection layer, the first conductive layer includes mutually insulated A first electrode and a second electrode, the carrier injection layer includes a first carrier injection layer portion and a second carrier injection layer located in the first sub-pixel area and the second sub-pixel area, respectively
  • the second conductive layer includes a third electrode and a fourth electrode connected to each other in the first sub-pixel area and the second sub-pixel area, and the third electrode and the fourth electrode are Integral structure; the first electrode, the first carrier injection layer portion and the third electrode constitute a first light-emitting element, the second electrode, the second carrier injection layer portion and the The fourth electrode constitutes a second light-emitting element, and the display substrate further includes a spacer between the first light
  • the second carrier injection layer is partially disconnected, the carrier injection layer further includes a third carrier injection layer portion, and the third carrier injection layer portion is located between the spacer and the second carrier injection layer.
  • the display substrate further includes a driving circuit, and the driving circuit is connected to the first carrier injection layer.
  • a light-emitting element is electrically connected to the second light-emitting element, and is configured to drive the first light-emitting element and the second light-emitting element;
  • the driving circuit includes a transistor, the transistor includes a semiconductor layer, and the semiconductor layer is located Inside the base substrate.
  • the carrier injection layer is an electron injection layer or a hole injection layer.
  • the spacer has a concave portion on a side surface adjacent to the first carrier injection layer portion and the second carrier injection layer portion.
  • the width of the spacer in the direction away from the base substrate, the width of the spacer first becomes smaller and then becomes larger.
  • the cross section of the spacer in a direction perpendicular to the base substrate is an inverted trapezoid.
  • the carrier injection layer further includes a third carrier injection layer portion, and the carrier injection layer portion is located between the spacer and the second conductive layer and is respectively connected to the The first carrier injection layer portion and the second carrier injection layer portion are spaced apart.
  • the ratio of the thickness of the second conductive layer to the thickness of the spacer ranges from 0.5-2.
  • the spacer includes an anti-reflective coating
  • the anti-reflective coating includes an anti-reflective organic material
  • the material of the spacer is a negative photoresist material or an inorganic insulating material.
  • the carrier injection layer further includes a third carrier injection layer portion, the third carrier injection layer portion is located between the spacer and the second conductive layer, and respectively It is spaced apart from the first carrier injection layer portion and the second carrier injection layer portion.
  • the organic functional layer further includes a charge generation layer
  • the charge generation layer includes a first charge generation layer portion and a second charge that are respectively located in the first sub-pixel region and the second sub-pixel region.
  • a layer portion is generated, and the spacer further separates the first charge generation layer portion and the second charge generation layer portion.
  • the first light-emitting element and the second light-emitting element are respectively configured to emit white light.
  • the organic functional layer includes a plurality of light-emitting layers stacked in a direction perpendicular to the base substrate.
  • At least two of the plurality of light-emitting layers are connected in series with each other, and the charge generation layer is located between two adjacent light-emitting layers of the at least two light-emitting layers.
  • the plurality of light-emitting layers includes a red-green light-emitting layer and a blue light layer, the red-green light-emitting layer and the blue light layer are connected in series with each other, and the connection layer is located between the red-green light-emitting layer and the blue light layer. between.
  • the red and green light emitting layers include a red light layer and a green light layer that are arranged adjacently, and the red light layer is closer to the first conductive layer.
  • the display substrate further includes a third light-emitting element located in a third sub-pixel area, and the first light-emitting element, the second light-emitting element, and the third light-emitting element constitute a pixel unit.
  • the display substrate further includes a color filter layer, and the color filter layer is located on a side of the first light-emitting element and the second light-emitting element away from the base substrate.
  • Some embodiments of the present disclosure further provide a manufacturing method of a display substrate, the display substrate having a first sub-pixel area and a second sub-pixel area adjacent to each other, and the manufacturing method includes: providing a base substrate; forming a driving circuit; A first conductive layer, an organic functional layer, and a second conductive layer are sequentially formed on the base substrate.
  • the first conductive layer includes a first conductive layer located in the first sub-pixel region and the second sub-pixel region, respectively.
  • An electrode and a second electrode the organic functional layer includes a carrier injection layer, and the carrier injection layer includes first carrier injection located in the first sub-pixel region and the second sub-pixel region, respectively Layer portion and a second carrier injection layer portion, the second conductive layer includes a third electrode and a fourth electrode respectively located in the first sub-pixel area and the second sub-pixel area, the first electrode ,
  • the first carrier injection layer portion and the third electrode constitute a first light-emitting element, and the second electrode, the second carrier injection layer portion, and the fourth electrode constitute a second light-emitting element ,
  • a spacer is formed between the first light-emitting element and the second light-emitting element, and the driving circuit is electrically connected to the first light-emitting element and the second light-emitting element, and is configured to drive the first light-emitting element.
  • the light-emitting element and the second light-emitting element, the drive circuit includes a transistor, the transistor includes a semiconductor layer, the semiconductor layer is located inside the base substrate, and the spacer inserts the first carrier injection layer Part and the second carrier injection layer are partly disconnected.
  • the spacer is formed with a recessed portion on a side surface adjacent to the first carrier injection layer portion and the second carrier injection layer portion.
  • forming a spacer between the first sub-pixel area and the second sub-pixel area includes: forming an anti-reflective material layer, and forming a photoresist layer on the anti-reflective material layer, The photoresist layer is exposed, the exposed photoresist layer is developed with a developer to obtain a photoresist pattern, and the anti-reflective material layer is etched using the developer through the photoresist pattern, The spacer is formed.
  • the anti-reflective material layer is formed on the first electrode and the second electrode.
  • the first conductive layer is formed on the photoresist pattern, and a lift-off process is performed on the photoresist pattern to form the first electrode and the second electrode.
  • the organic functional layer is formed on the spacer, and the carrier injection layer is disconnected at the spacer, thereby forming the first carrier injection layer portion and the second carrier injection layer. Two carriers are injected into the layer part.
  • FIG. 1A is a schematic diagram of leakage of an OLED display light-emitting device
  • FIG. 1B is one of the spectrograms of an OLED display light-emitting device
  • Fig. 1C is the second spectrogram of an OLED display light-emitting device
  • FIG. 2A is one of the schematic plan views of the display substrate provided by some embodiments of the present disclosure.
  • 2B is one of the cross-sectional views of the display substrate provided by some embodiments of the present disclosure.
  • 2C is the second cross-sectional view of the display substrate provided by some embodiments of the present disclosure.
  • 3A is a schematic diagram of a cross-sectional shape of a spacer provided by some embodiments of the present disclosure.
  • 3B is a partial enlarged view of a display substrate provided by some embodiments of the present disclosure.
  • 3C is an SEM image of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of the structure of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 5 is a second plan view of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 6 is the third cross-sectional view of the display substrate provided by some embodiments of the present disclosure.
  • FIG. 7A is a schematic diagram of a driving circuit principle of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 7B is a circuit diagram of a specific implementation example of a voltage control circuit and a driving circuit of a display substrate provided by some embodiments of the present disclosure
  • FIGS. 8A-8F are step diagrams of a manufacturing method of a display substrate provided by some embodiments of the present disclosure.
  • FIGS 9A-9E are step diagrams of manufacturing methods of display substrates provided by other embodiments of the present disclosure.
  • FIG. 10 is a spectrum diagram of a display substrate provided by some embodiments of the disclosure.
  • Micro OLED (Micro OLED) displays usually have a size of less than 100 microns, such as a size of less than 50 microns, etc. It involves the combination of organic light emitting diode (OLED) technology and CMOS technology, and the OLED array is prepared on a silicon-based substrate including CMOS circuits. .
  • OLED organic light emitting diode
  • OLED devices are formed by using a fine metal mask (Fine Metal Mask, FMM) to evaporate different organic functional layers (such as electron/hole injection layers).
  • FMM Fine Metal Mask
  • FFM is used to pattern the organic functional layers.
  • Corresponding patterns are formed in different pixel areas.
  • FMM has limited accuracy and cannot achieve high image resolution (that is, pixels per inch, PPI for short), which limits the resolution of OLED devices. Therefore, a white light OLED combined with a color film layer can be used to achieve full-color display.
  • the organic functional layer is usually formed as a continuous structure covering multiple sub-pixel regions, which is prone to leakage in the lateral direction, causing cross-color between sub-pixels, and reducing the color gamut of the display device.
  • the carrier injection layer e.g., electron injection layer (EIL), hole injection layer (HIL)), light-emitting layer, carrier injection layer (CGL) and other organic functional sublayers in OLED devices usually include metal elements.
  • EIL electron injection layer
  • HIL hole injection layer
  • CGL carrier injection layer
  • metal elements metal ions or heavily doped materials containing metal elements will generate mobile charges under the action of voltage, which will cause leakage between sub-pixels in the lateral direction, thereby causing cross-color problems.
  • FIG. 1A shows a schematic diagram of cross-color occurrence of an OLED display device
  • FIG. 1B is a spectrum diagram of the OLED display device.
  • the OLED display device adopts a white light OLED combined with a color film layer to realize a full-color display.
  • FIGS. 1A and 1B when the sub-pixels in the red light region (R) are lighted up, due to the leakage of current in the carrier injection layer (CGL) 1, the adjacent green light region ( G) emit light, thereby reducing the light emission purity of a single sub-pixel (for example, including red, green and blue sub-pixels), resulting in a reduction in the color gamut of the entire OLED display device.
  • CGL carrier injection layer
  • Figure 1C shows another example of the spectrogram of an OLED display device.
  • the figure shows the spectra of the three sub-pixels of red (R), green (G), and blue (B) simultaneously lit and the three sub-pixels respectively. Light up the spectrum.
  • R red
  • G green
  • B blue
  • Light up the spectrum As shown in the figure, when the three sub-pixels are lit separately, light of different colors escapes from the adjacent sub-pixels, which causes the color gamut of the entire OLED display device to decrease.
  • the OLED display device color gamut index (NTSC) is only 30%.
  • the embodiments of the present disclosure provide a display substrate.
  • the carrier injection layer is naturally disconnected at the spacers during deposition, that is, the carriers in adjacent sub-pixel regions are naturally disconnected.
  • the carrier injection layer is separated by the spacer, thereby effectively avoiding cross-color between sub-pixels caused by the lateral leakage of the carrier injection layer, increasing the color gamut of the display substrate and improving the display quality.
  • FIG. 2A is a schematic plan view of a display substrate provided by an embodiment of the disclosure.
  • the display substrate 20 includes a plurality of gate lines 11 and a plurality of data lines 12, and the plurality of gate lines 11 and the plurality of data lines 12 cross each other to define a plurality of sub-pixel regions 100 distributed in an array in the display region 110.
  • Each sub-pixel area 100 is provided with one sub-pixel, and each sub-pixel includes a light-emitting element and a driving circuit for driving the light-emitting element.
  • the driving circuit is, for example, a conventional pixel circuit.
  • the driving circuit includes a conventional 2T1C (ie, two transistors and a capacitor) pixel circuit, 4T2C, 5T1C, 7T1C and other nTmC (n, m are positive integers) pixel circuits, and in different embodiments, the driving circuit also It may further include a compensation circuit, the compensation circuit including an internal compensation circuit or an external compensation circuit, and the compensation circuit may include a transistor, a capacitor, and the like.
  • the driving circuit may further include a reset circuit, a light-emitting control circuit, a detection circuit, etc., as required.
  • the display substrate may further include a data driving circuit 6 and a gate driving circuit 7 located in the non-display area 120 outside the display area 110.
  • the data driving circuit and the gate driving circuit are connected to each other through the data line 12 and the gate line 11, respectively.
  • the driving circuit of the light-emitting element is connected to provide an electric signal.
  • the data driving circuit is used to provide data signals
  • the gate driving circuit is used to provide scanning signals, and can be further used to provide various control signals, power signals, and the like.
  • the display substrate adopts a silicon substrate as the base substrate 101, and the driving circuit (pixel circuit) 206, the gate driving circuit 6 and the data driving circuit 7 may all be integrated on the silicon substrate.
  • the gate drive circuit 6 and the data drive circuit 7 can also be formed in a region corresponding to the display area of the display substrate, and not necessarily located in a non- Display area.
  • Fig. 2B shows an example of a cross-sectional view of the display substrate shown in Fig. 2A along the A-A' direction. For clarity, only the adjacent first and second sub-pixel regions are shown in the figure, and for each sub-pixel region, only the light-emitting element and the driving circuit 206 directly connected to the light-emitting element are shown.
  • Transistor the transistor may be a driving transistor, which is configured to control the magnitude of current for driving the light-emitting element to emit light.
  • the transistor may also be a light-emission control transistor, which is used to control whether a current for driving the light-emitting element to emit light flows. The embodiment of the present disclosure does not limit this. As shown in FIG.
  • the display substrate 20 includes a base substrate 101, a first conductive layer 301, an organic functional layer 302, and a second conductive layer 303 disposed on the base substrate 101.
  • the organic functional layer 302 includes carriers. Injection layer 321.
  • the first conductive layer 301 includes a first electrode 211 and a second electrode 221 insulated from each other in the first sub-pixel area and the second sub-pixel area, respectively, and the first electrode 211 and the second electrode 221 are disconnected from each other.
  • the second conductive layer 303 includes a third electrode 212 and a fourth electrode 222 connected to each other in the first sub-pixel area and the second sub-pixel area, respectively.
  • the third electrode 212 and the fourth electrode 222 are an integral structure, that is, the third electrode 212 and the fourth electrode 222 are continuous and smooth structures formed by the same conductive material layer, and there is no difference between different regions in the second conductive layer. interface.
  • the display substrate provided by the embodiment of the present disclosure may be formed on a silicon substrate, and the driving circuit 206 may be integrated on the silicon substrate to form the driving substrate 102.
  • the first light-emitting element 201 and the second light-emitting element 202 are formed on a driving substrate 102 including a silicon substrate 101.
  • the driving substrate includes a driving circuit 206 formed on the silicon substrate 101.
  • the silicon substrate is, for example, monocrystalline silicon or high-density silicon. Purity silicon.
  • the driving circuit 206 is formed on the silicon substrate 101 by a semiconductor process, for example, the active layer (ie, semiconductor layer) of the transistor, the first electrode and the second electrode are formed in the silicon substrate 101 by a doping process, and formed by a silicon oxidation process.
  • the insulating layer 104, and a plurality of conductive layers 105, 106, etc., are formed by a sputtering process.
  • the semiconductor layer of the transistor (the active layer 122 in FIG. 2B) is located inside the base substrate 101 or is a part of the base substrate 101.
  • the driving circuit 206 includes a complementary metal oxide semiconductor circuit (CMOS circuit).
  • CMOS circuit complementary metal oxide semiconductor circuit
  • FIG. 2C shows a specific example in which PMOS transistors and NMOS transistors are formed in a silicon substrate. As shown in FIG. 2C, the NMOS and PMOS are integrated in a P-type silicon substrate, the active layer of the NMOS is a part of the P-type substrate, and the active layer of the PMOS is made by performing N-type doping in the P-type substrate. Miscellaneous.
  • the gate driving circuit 6 and the data driving circuit 7 may also be integrated in the silicon substrate 101 through the semiconductor process described above.
  • the gate driving circuit and the data driving circuit can adopt conventional circuit structures in the field, which are not limited in the embodiments of the present disclosure.
  • the first electrode 211 of the first light-emitting element 201 is formed on the surface of the driving substrate 102, and passes through the contact hole 103 filled with a conductive material (for example, tungsten) and the plurality of conductive layers and the first transistor
  • the first pole 123 of 203 is electrically connected.
  • FIG. 2B exemplarily shows an insulating layer 104 and two conductive layers 105 and 106, however, the number of layers of the insulating layer 104 and the conductive layer is not limited in the embodiment of the present disclosure.
  • the topmost conductive layer 106 in the driving substrate 102 is reflective, for example, a laminated structure of titanium/titanium nitride/aluminum.
  • the conductive layer 106 includes a plurality of sub-layers arranged at intervals, which are respectively arranged in a one-to-one correspondence with the plurality of electrodes included in the first conductive layer 301.
  • the conductive layer 106 can be set as a reflective layer for reflecting the light emitted by the light-emitting element and improving the light extraction efficiency.
  • the orthographic projection of each electrode in the first conductive layer 301 on the base substrate 101 falls within the orthographic projection of the portion of the conductive layer 106 corresponding to the electrode on the base substrate 101.
  • the first conductive layer 301 may use a transparent conductive oxide material with a high work function, such as ITO, IZO, IGZO, AZO, etc.
  • silicon-based technology can achieve higher accuracy (for example, PPI can reach 6,500 or even more than 10,000).
  • the distance d between the first electrode 211 of the first light-emitting element 201 and the first electrode 221 of the second light-emitting element 202 (that is, the width of the spacer 202) d is less than 1 micrometer.
  • the organic functional layer 302 includes a first organic functional layer and a second organic functional layer located in a first sub-pixel area and a second sub-pixel area, respectively.
  • the first electrode 211, the first organic functional layer and the third electrode 212 constitute a first light-emitting element 201
  • the second electrode 221, the second organic functional layer and the fourth electrode 222 constitute a second light-emitting element 202.
  • the first light-emitting element 201/the second light-emitting element 202 may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), etc.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the embodiment of the present disclosure does not limit the type of the light-emitting element.
  • the light-emitting layer of the OLED can be a small molecular organic material or a high molecular organic material.
  • the first light-emitting element 201 and the second light-emitting element 202 have a top emission structure
  • the first electrode 211 and the second electrode 221 have reflectivity.
  • the first electrodes 211 and 221 include materials with high work function and high reflectivity to serve as anodes, such as a stacked structure of Ti/Al/Ti/Mo, in which metallic titanium can be used as a buffer layer to improve the adhesion between layers , Al as a highly reflective material and Mo as a high work function material directly contacting the organic functional layer can improve the carrier injection capability.
  • the second conductive layer 303 serves as a cathode.
  • the second conductive layer 302 may be a transparent conductive material or a laminated structure of a transparent conductive material and a metal material.
  • the second conductive layer 302 can be a transparent metal oxide conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc., and can also be carbon nanotubes, graphene, Transparent nano conductive materials such as nano silver wires.
  • the organic functional layer 302 includes a layer structure stacked on each other in a direction perpendicular to the substrate 101, including at least one carrier injection layer (and at least one light-emitting layer.
  • the carrier injection layer may be an electron injection layer (EIL) or Hole injection layer (HIL).
  • EIL electron injection layer
  • HIL Hole injection layer
  • the electron injection layer is located on the side of the light-emitting layer close to the cathode, which is used to reduce the barrier to inject electrons from the cathode, so that electrons can be effectively injected from the cathode into the light-emitting layer.
  • the hole injection layer is located in the light-emitting layer.
  • the side of the layer close to the anode is used to reduce the barrier of hole injection from the anode, so that holes can be effectively injected from the anode into the light-emitting layer. Therefore, when choosing the material of the electron/hole injection layer, the material needs to be considered Energy level and electrode material matching.
  • the material of the electron injection layer can be LiQ (lithium quinolate), AlQ3 (aluminum quinolate), etc.
  • the material of the hole injection layer can be CuPc (polyester carbonate). ), TiOPc, m-MTDATA, 2-TNATA, etc.
  • the organic functional layer 302 may further include an electron/hole transport layer, an electron/hole blocking layer, a charge generation layer, etc., as required.
  • the carrier injection layer 321 includes a first carrier injection layer portion 213 and a second carrier injection layer portion 223 respectively located in the first sub-pixel area and the second sub-pixel area.
  • the display substrate 20 further includes a spacer 220 located between the first light-emitting element 201 and the second light-emitting element 202, and the spacer 220 cuts off the first carrier injection layer portion 213 and the second carrier injection layer portion 223. open. For example, as shown in FIG.
  • the spacer 220 is located between the first electrode 211 and the second electrode 221 and extends in a direction perpendicular to the base substrate 101 to inject the first carrier into the layer portion 213 and the second electrode 221.
  • the two carrier injection layer portion 223 is disconnected, that is, the first carrier injection layer portion 213 and the second carrier injection layer portion 223 are spaced apart from each other, and the two are not connected or contacted.
  • the carrier injection layer 302 further includes a third carrier injection layer portion 233.
  • the third carrier injection layer portion 233 is located between the spacer 220 and the second conductive layer 303, and is connected to the second conductive layer 303, respectively.
  • One carrier injection layer portion 213 and the second carrier injection layer portion 223 are disconnected.
  • the spacer 220 has a concave portion on the side adjacent to the first carrier injection layer portion 213 and the second carrier injection layer portion 223 (from the end of the spacer away from the base substrate). Look).
  • the concave portion is directly connected to the top surface (the surface away from the base substrate) of the spacer 220.
  • the side surface of the spacer 220 may include a smooth concave curved surface, may also include an uneven concave surface, and may also include a combination of a plurality of concave surfaces.
  • the disclosed embodiment does not limit the specific form of the concave portion.
  • FIG. 3A shows a schematic diagram of several cross-sectional shapes of the spacers.
  • the spacers are all placed upright, that is, the base substrate is located under each spacer in the figure.
  • the width of the spacer 220 first becomes smaller and then becomes larger.
  • the farther away from the base substrate 101 the larger the cross-sectional area of the spacer 220 parallel to the base substrate 101; for example, the cross section of the spacer in the direction perpendicular to the base substrate 101 is an inverted trapezoid.
  • the spacer 220 has a rectangular cross section in a direction perpendicular to the base substrate 101.
  • the step coverage of the organic materials is poor, and it is difficult to adhere to the concave portion (such as the surface marked by the dashed line in FIG. 3A) or the vertical surface, so the carrier
  • the injection layer 321 is disconnected at the corresponding spacer 220, that is, between adjacent sub-pixels, thereby avoiding leakage between sub-pixels with different carrier injection layers, and also avoiding cross-color caused by the leakage. And the color gamut is reduced.
  • the spacer 220 includes an anti-reflection coating (ARC), and the anti-reflection coating includes an anti-reflection organic material.
  • ARC anti-reflection coating
  • the anti-reflection coating can be used as a bottom anti-reflection coating (BARC) in photolithography, which can effectively suppress the standing wave effect in the photoresist layer caused by the light reflected by the substrate, and improve the photolithography.
  • BARC bottom anti-reflection coating
  • the anti-reflective coating is an organic material that is easily soluble in the developer of the photoresist used with it, such as an organic polymer or copolymer.
  • the material of the anti-reflective coating includes monomer units having olefin, alkyne, or aromatic groups.
  • the material of the anti-reflective coating includes ester, acrylate, or isocyanate monomers.
  • the material of the anti-reflective coating includes acrylic polymer or copolymer or styrene polymer or copolymer. According to the material of the anti-reflective coating, and after the photoresist is determined, the developer is selected accordingly.
  • the material of the spacer 220 is a negative photoresist material or an inorganic insulating material, such as silicon nitride or oxide.
  • the carrier injection layer can be disconnected between adjacent sub-pixel regions, thereby effectively avoiding lateral leakage of the carrier injection layer
  • the resulting cross-color between sub-pixels increases the color gamut of the display substrate and improves the display quality.
  • 3B illustrates a partial enlarged schematic diagram of the display substrate at the spacer 220.
  • the ratio of the thickness h1 of the second conductive layer 303 to the thickness h2 of the spacer The range is 0.5-2.
  • the thickness of the spacer 220 is in the range of 100-250 nanometers, and the average width is in the range of 0.5-1.2 micrometers.
  • the thickness of the second conductive layer 303 is in the range of 100-300 nanometers.
  • the second conductive layer serves as a cathode, and the material is a laminated structure of a metal and a transparent metal oxide conductive material.
  • the second conductive layer 303 has a Mg/Ag/IZO laminated structure, the Mg/Ag material is closer to the organic functional layer 302, and the thickness is more than ten nanometers. This is because the work function of metal is lower than that of metal oxide conductive materials, and direct contact with the organic functional layer can improve the carrier (electron) injection capability.
  • FIG. 3C shows a scanning electron microscope (SEM) image of a partial cross-section of the display substrate.
  • the spacer 220 has a rectangular cross-section in a direction perpendicular to the base substrate 101.
  • the layer structure shown in black indicated by the reference number 4 in the figure is an auxiliary layer formed above and next to the charge generation layer to assist judgment, and this auxiliary layer does not exist in actual devices. It can be seen from FIG. 3A that, at the corresponding spacer 220, the portion of the organic functional layer including the carrier injection layer 321 under the auxiliary layer 4 is substantially completely disconnected.
  • the thickness H1 of the organic functional layer near the spacer 220 is small, which is precisely because the organic material is difficult to adhere to the sidewall of the spacer 220 with a larger slope.
  • the organic functional layer 302 gradually becomes thinner in thickness in the directions D1, D2 directed to the spacer 220 at the center of the sub-pixel area.
  • the thickness of the second conductive layer 303 near the spacer 220 is small. This is precisely because the thermal evaporation energy in the evaporation process is small, and the deposited material is difficult to be deposited on a steep slope. It is caused by the adhesion of the sidewall of the spacer 220. For example, the thickness of the second conductive layer 303 in the directions D1 and D2 directed to the spacer 220 at the center of the sub-pixel area gradually becomes thinner.
  • the third electrode 212 and the fourth electrode 222 are an integral structure, and the second conductive layer 302 is a continuous and smooth structure without an interface in between.
  • the thickness of the second conductive layer 303 may be greater than 100 nanometers.
  • the first light-emitting element 201 and the second light-emitting element 202 are respectively configured to emit white light.
  • the embodiment of the present disclosure also does not limit the structure and light-emitting mechanism of the organic functional layer 302.
  • the organic functional layer 302 includes multiple light-emitting layers that are perpendicular to the base substrate. Stack in the direction of 101.
  • the organic functional layer 302 includes two light emitting layers (yellow blue) or three light emitting layers (red, green and blue) stacked on each other.
  • At least two of the plurality of light-emitting layers are connected in series with each other through a charge generation layer (CGL) to form a tandem structure (tandem structure), and the charge generation layer includes an N-type charge generation layer and a P-type charge generation layer for balancing the load.
  • CGL charge generation layer
  • tandem structure tandem structure
  • the charge generation layer includes an N-type charge generation layer and a P-type charge generation layer for balancing the load.
  • the N-type charge generation layer may be doped with alkali metals such as lithium (Li), sodium (Na), potassium (K) or cesium (Cs) or such as magnesium (Mg), strontium (Sr), barium (Ba) Or radium (Ra) alkaline earth metal (but not limited to any one of them) organic layer; the P-type charge generation layer can be formed by doping an organic matrix material with hole transport ability with a dopant. The obtained organic layer is formed.
  • the tandem structure helps to improve the luminous efficiency and luminous brightness of the device.
  • the light-emitting energy levels corresponding to adjacent light-emitting layers are relatively close, so that materials such as light-emitting layer materials, electron transport materials, hole transport materials, and electrode materials of the light-emitting element can be selected in a large range, and the implementation difficulty is relatively low.
  • FIG. 4 shows a schematic diagram of a display substrate provided by other embodiments of the present disclosure.
  • the display substrate 20 further includes a third light-emitting element 207.
  • the first light-emitting element 201, the second light-emitting element 202, and the third light-emitting element 207 are respectively located in different sub-pixels, thereby forming one
  • the pixel unit PX, combined with the color film layer 210, can emit full-color light.
  • the light-emitting element shown in FIG. 4 further includes a charge generation layer (CGL), and the light-emitting element has a tandem structure.
  • the organic functional layer 302 includes a red light layer, a green light layer, and a blue light layer.
  • the red light layer and the green light layer are adjacent to each other to form a red and green light emitting layer and a blue light layer.
  • the layers are connected in series, and the charge generation layer is located between the red and green light-emitting layers and the blue light layer.
  • the organic functional layer 302 shown in FIG. 4 includes a plurality of carrier injection layers (HIL1, HIL2, EIL), for example, at least one carrier injection layer is disconnected by the spacer 220.
  • the organic functional layer 302 is completely separated by the spacer 220, that is, all the carrier injection layers are separated by the spacer 220; in this case, the charge generation layer is also separated by the spacer 220, That is, the first charge generation layer portion of the charge generation layer in the first sub-pixel area and the second charge generation layer portion in the second sub-pixel area are disconnected from each other.
  • the organic functional layer 302 further includes an electron transport layer (ETL1) and a hole transport layer (HTL2) located on both sides of the charge generation layer, and the N-type charge generation layer in the charge generation layer is closer to the electron transport layer. , The P-type charge generation layer in the charge generation layer is closer to the hole transport layer.
  • ETL1 electron transport layer
  • HTL2 hole transport layer
  • one of the first conductive layer and the second conductive layer is reflective, and the other is semi-transparent or translucent.
  • the light-emitting element has a top-emission structure.
  • the first conductive layer has reflectivity
  • the second conductive layer has translucency or translucency.
  • the red light layer and the green light layer are located on the side of the carrier injection layer close to the first conductive layer
  • the blue layer is located on the side of the carrier injection layer away from the first conductive layer.
  • each light-emitting layer can satisfy the above-mentioned relationship, and the light-emitting purity and brightness can be improved.
  • the red light layer, the green light layer, and the blue light layer are sequentially stacked on the first conductive layer 301, and the red light layer is closer to the first conductive layer. Since the long-wave luminescent material easily absorbs the short-wave, this arrangement prevents the emitted light from being absorbed by other luminous layers, thereby improving the light-emitting efficiency.
  • the first conductive layer 301 is formed as the anode of the light-emitting element
  • the second conductive layer 303 is formed as the cathode of the light-emitting element.
  • the first conductive layer 301 is made of a high work function material, such as high reflectivity, such as a stacked structure of Ti/Al/Ti/Mo, wherein metal titanium can be used as a buffer layer to improve the adhesion between layers, Al as a highly reflective material, and Mo as a high work function material directly contacting the organic functional layer can improve the carrier injection capability.
  • the material of the second conductive layer 303 is a conductive material with low work function and high transmittance.
  • the second conductive layer 303 may be a transparent metal oxide conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), and indium oxide.
  • IZO indium zinc oxide
  • ITO indium tin oxide
  • IGZO gallium zinc
  • the thickness of the second conductive layer 303 may be greater than 100 nanometers. In the case of the transparent conductive layer of the second conductive layer 303, since the transparent conductive layer means that the light transmittance is very high, the thickness has little effect on the light transmittance of the transparent conductive layer.
  • the red light layer, the green light layer and the blue light layer are respectively CBP obtained by doping red, green, and blue phosphorescent materials into the host material: (ppy)2Ir(acac), CBP: FIrpic and CBP: Btp2Ir (acac).
  • FIG. 2B shows the first transistor 203 and the second transistor 204 electrically connected to the first light-emitting element 201 and the second light-emitting element 202, respectively.
  • the embodiment of the present disclosure does not limit the specific types of the first transistor 203 and the second transistor 204.
  • the first transistor 203 is exemplified below, and this description is also applicable to the second transistor 204, so it will not be repeated.
  • the first transistor 203 includes a gate 121, a gate insulating layer 125, an active layer 122, a first electrode 123, and a second electrode 124.
  • the embodiment of the present disclosure does not limit the type, material, and structure of the first transistor 203.
  • the active layer of the first transistor 203 may be microcrystalline silicon, amorphous silicon, Inorganic semiconductor materials such as polysilicon (low-temperature polysilicon or high-temperature polysilicon), oxide semiconductors (such as IGZO), or organic materials, such as PBTTT, PDBT-co-TT, PDQT, PDVT-10, and dinaphtho-parallel two Organic semiconductor materials such as thiophene (DNTT) or pentacene.
  • the first transistor 203 may be N-type or P-type.
  • the first electrode 123 of the first transistor 203 is electrically connected to the first electrode 211 of the first light-emitting element 201.
  • the transistors used in the embodiments of the present disclosure can all be thin film transistors, field effect transistors or other switching devices with the same characteristics.
  • Some embodiments of the present disclosure use field effect transistors (such as MOS field-effect transistors) formed in a silicon substrate. Effect transistor) as an example.
  • the silicon substrate is doped (p-type doping or n-type doping) to form the active layer of the transistor, that is, the active layer of the transistor is located in the silicon substrate, or The active layer of the transistor is a part of the silicon substrate.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole can be directly described as the first pole and the other pole is the second pole.
  • FIG. 5 shows a schematic plan view of a display substrate 20 provided by other embodiments of the present disclosure. As shown in the figure, a spacer 220 is provided between each adjacent (including the row direction and column direction of the pixel array) two sub-pixel regions 100 (light emitting elements).
  • Fig. 6 shows another example of a cross-sectional view of Fig. 2A along the A-A' direction.
  • the display substrate 20 further includes a bonding pad 230 located in the non-display area 120.
  • the bonding electrode 230 is usually used for bonding with external components after the display area device is completed. ) To provide signals for the display substrate, such as power supply voltage signals.
  • the bonding electrode 230 can be arranged in the same layer as the conductive structure in the display area 110 to save process.
  • the bonding electrode 230 can be arranged in the same layer as the conductive layer of the top layer (farthest from the base substrate 101) below the light-emitting element in the display area 110 to facilitate the subsequent bonding process.
  • the bonding The electrode 230 is arranged in the same layer as the source and drain electrode layers of the transistors in the display area 110.
  • the "same layer arrangement" in the embodiments of the present disclosure means that multiple structures are formed from the same material film through the same or different patterning processes, and thus have the same material.
  • the display substrate further includes an encapsulation layer 208, a color film layer 210, a cover plate 209, etc. on the side of the first light-emitting element 201 and the second light-emitting element 202 away from the base substrate 101.
  • the encapsulation layer 208 is configured to seal the light-emitting element to prevent external moisture and oxygen from penetrating into the light-emitting element and the pixel circuit and causing damage to the device.
  • the encapsulation layer 208 includes an organic thin film or a structure in which an organic thin film and an inorganic thin film are alternately stacked.
  • a water absorption layer may be further provided between the encapsulation layer 208 and the light-emitting element, configured to absorb residual water vapor or sol in the preliminary manufacturing process of the light-emitting element.
  • the cover plate 209 is, for example, a glass cover plate.
  • the cover plate 209 and the encapsulation layer 208 may be an integral structure.
  • the display substrate 20 is an organic light emitting diode (OLED) display substrate or a micro OLED (Micro OLED) display substrate.
  • OLED organic light emitting diode
  • Micro OLED Micro OLED
  • FIG. 7A is a schematic diagram of a driving circuit principle of a display substrate provided by some embodiments of the present disclosure.
  • the display substrate includes a plurality of light-emitting elements L (such as the above-mentioned first light-emitting element 201 and second light-emitting element 202) located in the display area 110 (area AA) and a driving circuit 206 coupled to each light-emitting element L in a one-to-one correspondence,
  • the driving circuit 206 includes a driving transistor configured to control the magnitude of current for driving the light-emitting element to emit light.
  • the display substrate may also include a plurality of voltage control circuits 30 located in the non-display area 120.
  • At least two drive circuits 206 in a row share one voltage control circuit 30, and the first pole of the drive transistor in the row drive circuit 206 is coupled to the common voltage control circuit 30, and the second pole of each drive transistor is connected to the corresponding light emitting circuit.
  • the element L is coupled.
  • the voltage control circuit 30 is configured to output the initialization signal Vinit to the first pole of the driving transistor in response to the reset control signal RE, and control the corresponding light emitting element L to reset; and in response to the light emission control signal EM, output the first power signal VDD To the first pole of the driving transistor to drive the light-emitting element L to emit light.
  • the voltage control circuit 30 outputs the initialization signal Vinit to the first pole of the driving transistor under the control of the reset control signal RE to control the reset of the corresponding light-emitting element, thereby avoiding the voltage pair applied to the light-emitting element when the previous frame emits light. The effect of the next frame of light, thereby improving the afterimage phenomenon.
  • the display substrate may further include a plurality of pixel units PX located in the display area 110, each pixel unit PX, for example, a plurality of sub-pixels; each sub-pixel includes a light-emitting element L and a driving circuit 206, respectively.
  • the pixel unit PX may include three sub-pixels of different colors. These 3 sub-pixels can emit white light separately, and can emit full-color light in combination with the color film layer.
  • the driving circuits 206 in at least two adjacent sub-pixels in the same row may share one voltage control circuit 30.
  • all the driving circuits 206 in the same row may share one voltage control circuit 30.
  • the driving circuits 206 in two, three or more adjacent sub-pixels in the same row may share one voltage control circuit 30, which is not limited here. In this way, the area occupied by the driving circuit 206 in the display area 110 can be reduced by sharing the voltage control circuit 30.
  • FIG. 7B is a circuit diagram of a specific implementation example of a voltage control circuit and driving of a display substrate provided by some embodiments of the present disclosure.
  • the driving transistor M0 in the driving circuit 206 is directly connected to the light-emitting element L, and may be, for example, the first transistor 203 or the second transistor 204 described above.
  • the anode of the light emitting element L is electrically connected to the driving transistor M0, and the cathode of the light emitting element L is electrically connected to the second power supply terminal VSS.
  • the voltage of the second power terminal VSS is generally a negative voltage or the ground voltage VGND (generally 0V), and the voltage of the initialization signal Vinit can also be set to the ground voltage VGND, which is not limited here.
  • the light-emitting element L can be configured as a Micro-OLED or a Mini-OLED, which is further conducive to the realization of a high PPI organic light-emitting display panel.
  • the voltage control circuit 30 may include a first switching transistor M1 and a second switching transistor M2.
  • the gate of the first switch transistor M1 is used to receive the reset control signal RE
  • the first pole of the first switch transistor M1 is used to receive the initialization signal Vinit
  • the second pole of the first switch transistor M1 corresponds to the first pole of the corresponding driving transistor M0. ⁇ S coupling.
  • the gate of the second switch transistor M2 is used to receive the light emission control signal EM
  • the first pole of the second switch transistor M2 is used to receive the first power signal VDD
  • the second pole of the second switch transistor M2 is connected to the corresponding drive transistor M0.
  • the first pole S is coupled.
  • a transistor may be connected in series between the first switching transistor M1 and the driving transistor M0.
  • the types of the first switching transistor M1 and the second switching transistor M2 may be different.
  • the first switch transistor M1 is an N-type transistor
  • the second switch transistor M2 is a P-type transistor
  • the first switch transistor M1 is a P-type transistor
  • the second switch transistor M2 is an N-type transistor.
  • the type of the first switching transistor M1 and the second switching transistor M2 can also be the same.
  • the types of the first switching transistor M1 and the second switching transistor M2 need to be designed according to the actual application environment, which is not limited here.
  • the driving circuit 206 may further include a third switching transistor M3 and a storage capacitor Cst.
  • the gate of the third switch transistor M3 is used to receive the first gate scan signal S1
  • the first pole of the third switch transistor M3 is used to receive the data signal DA
  • the second pole of the third switch transistor M3 is connected to the driving transistor M0.
  • the gate G is coupled.
  • the first terminal of the storage capacitor Cst is coupled to the gate G of the driving transistor M0, and the second terminal of the storage capacitor Cst is coupled to the ground terminal GND.
  • the driving circuit 206 may further include a fourth switch transistor M4.
  • the gate of the fourth switch transistor M4 is used to receive the second gate scanning signal S2, the first pole of the fourth switch transistor M4 is used to receive the data signal DA, and the second pole of the fourth switch transistor M4 is connected to the driving transistor M0.
  • the gate G is coupled.
  • the type of the fourth switching transistor M4 and the third switching transistor M3 are different.
  • the third switch transistor M3 is an N-type transistor
  • the fourth switch transistor M4 is a P-type transistor
  • the fourth switch transistor M4 is an N-type transistor.
  • the data signal DA when the voltage of the data signal DA is a voltage corresponding to a high gray scale, the data signal DA is transmitted to the gate G of the driving transistor M0 by, for example, the P-type fourth switch transistor M4 is turned on, which can avoid data
  • the voltage of the signal DA is affected by, for example, the threshold voltage of the N-type third switching transistor M3.
  • the N-type third switch transistor M3 When the voltage of the data signal DA is a voltage corresponding to a low gray scale, for example, the N-type third switch transistor M3 is turned on to transmit the data signal DA to the gate G of the driving transistor M0, which can prevent the voltage of the data signal DA from being affected.
  • the influence of the threshold voltage of the P-type fourth switching transistor M4. This can increase the voltage range input to the gate G of the driving transistor M0.
  • an embodiment of the present disclosure also provides an electronic device, including the above-mentioned display substrate 20.
  • the electronic device is a product or component with any display function, such as a digital photo frame, a smart bracelet, a smart watch, a mobile phone, a tablet computer, a display, a notebook computer, a navigator, and the like.
  • the embodiments of the present disclosure also provide a method for manufacturing the above-mentioned display substrate.
  • the manufacturing method at least includes: providing a base substrate; sequentially forming a first conductive layer, an organic functional layer, and a second conductive layer on the base substrate.
  • the layer includes a first electrode and a second electrode respectively located in the first sub-pixel area and the second sub-pixel area
  • the organic functional layer includes a carrier injection layer
  • the carrier injection layer includes a carrier injection layer located in the first sub-pixel area.
  • the pixel area and the first carrier injection layer portion and the second carrier injection layer portion of the second sub-pixel area, the second conductive layer includes the first sub-pixel area and the second sub-pixel area respectively.
  • the third electrode and the fourth electrode, the first electrode, the first carrier injection layer portion and the third electrode constitute a first light-emitting element
  • the second electrode, the second carrier injection layer portion and the second electrode The four electrodes constitute the second light-emitting element to form a driving circuit
  • the driving circuit is electrically connected to the first light-emitting element and the second light-emitting element, and is configured to drive the first light-emitting element and the second light-emitting element.
  • a spacer is formed between the light-emitting element and the second light-emitting element
  • the driving circuit includes a transistor
  • the transistor includes a semiconductor layer
  • the semiconductor layer is located inside the base substrate
  • the spacer is part of the first carrier injection layer and
  • the second carrier injection layer is partially spaced apart
  • the carrier injection layer further includes a third carrier injection layer portion
  • the third carrier injection layer portion is located between the spacer and the second conductive layer , And are spaced apart from the first carrier injection layer portion and the second carrier injection layer portion.
  • a silicon substrate may be used as the substrate, and the driving circuit 206 may be formed on the silicon substrate 101 by using a CMOS integrated circuit process.
  • CMOS integrated circuit process For details, reference may be made to the description of FIG. 2B, which will not be repeated here.
  • the following will mainly describe the manufacturing methods of the first light-emitting element and the second light-emitting element, and the base substrate and the driving circuit are collectively referred to as the driving substrate, and the driving substrate is electrically connected to the first light-emitting element and the second light-emitting element. And it is configured to drive the first light-emitting element and the second light-emitting element to emit light.
  • FIGS. 8A-8F show step diagrams of a manufacturing method of a display substrate provided by some embodiments of the present disclosure.
  • an anti-reflective material layer 112 and a photoresist layer 113 are sequentially formed on the driving substrate 102.
  • the anti-reflective material layer 112 is formed under the photoresist layer 13, and is used as a bottom anti-reflection coating (BARC) in photolithography, which can effectively inhibit the reflection of light from the substrate.
  • BARC bottom anti-reflection coating
  • the standing wave effect caused in the adhesive layer 13 improves the line width uniformity of the photolithography and the etching accuracy of the photoresist.
  • the material of the anti-reflective material layer 112 is an organic material that is easily soluble in the developer used for the photoresist layer 13, such as an organic polymer or copolymer.
  • the anti-reflective material layer 112 includes monomer units having olefin, alkyne, or aromatic groups.
  • the anti-reflective material layer 112 includes ester, acrylate, or isocyanate monomers.
  • the anti-reflective material layer 112 includes acrylic polymer or copolymer or styrene polymer or copolymer.
  • the exposed photoresist layer 113 is developed with a developer to obtain a photoresist pattern 113a, and the anti-reflective material layer 112 is corroded by the developer to form a spacer 220 as shown in the figure.
  • the width of the spacer 220 in the direction away from the driving substrate 102 is not uniform, but first becomes smaller and then becomes larger. This is because, on the one hand, the developer etched the reflective material layer 112 is isotropic wet etching, which is prone to lateral undercutting. Therefore, the bottom is up, and the width in the lateral direction tends to decrease; on the other hand, The top end of the spacer 220 close to the photoresist pattern 113a is protected by the upper photoresist pattern 113a and has approximately the same cross-sectional area as the photoresist pattern 113a, thus forming a concave side surface as shown in FIG. 8B Spacer.
  • a first conductive layer 111 is formed on the photoresist pattern 113a, and then the photoresist pattern 113a is stripped to form a first conductive pattern layer as shown in FIG. 8D, that is, a first light emitting layer is formed.
  • the anti-reflective material layer 112 is multiplexed as the spacer 220. Therefore, no additional process and cost are required to form the spacer 220.
  • the thickness of the first conductive layer 111 is smaller than the thickness of the anti-reflective material layer 112.
  • the first conductive layer 111 includes a material with a high work function and a high reflectivity to serve as an anode, such as a metal or a metal alloy.
  • FIG. 8E shows an exemplary enlarged schematic view of the first electrode 211 of the first light-emitting element.
  • the first electrode 211 includes Ti/Al/Ti/Mo (A/B/C/D ) Laminated structure, in which metallic titanium (layers A and C) can be used as a buffer layer to improve the adhesion between layers, aluminum (layer B) as a highly reflective material, and molybdenum (layer D) as a high work function material directly interacts with organic
  • the functional layer contact can improve the carrier injection capability.
  • aluminum is completely wrapped by the upper titanium and molybdenum layers. Since aluminum has a low work function, while molybdenum and titanium have relatively high work functions, molybdenum and titanium are wrapped around aluminum to prevent aluminum from being exposed. Direct contact with the organic functional layer on the first conductive layer 111 affects the carrier injection capability.
  • the laminated structure can be formed by an electron beam evaporation process, for example.
  • the target material is placed eccentrically with respect to the substrate, so that the evaporated titanium material can reach the concave side of the spacer 200 to form a completely filled titanium layer and enhance the adhesion of the substrate surface
  • the aluminum layer place the target centered relative to the substrate.
  • the spacer 220 formed earlier has a wider top end, so the aluminum cannot completely cover the titanium underneath (as shown in Figure 8E, the range marked by the dashed line );
  • the target material is placed eccentrically relative to the substrate, respectively, to form a completely filled titanium layer and a molybdenum layer, and the aluminum layer is completely wrapped. It can be seen that this process utilizes the recessed side surface of the spacer 220 to form a highly efficient electrode material.
  • an organic functional material layer 114 is formed on the first conductive layer 111.
  • the organic functional material layer 114 can be formed on the entire surface by, for example, an Open Mask combined with an evaporation process.
  • it can include at least one light-emitting layer, At least a carrier injection layer, an electron/hole transport layer, an electron/hole blocking layer, a charge generation layer, etc., are not repeated here. Since the step coverage of organic materials is poor, it is difficult to adhere to the concave surface of the spacer.
  • the carrier injection layer is located at the spacer 220, thereby forming the first carrier injection layer portion 213 and the second carrier injection layer part 213 and the second carrier injection layer spaced apart from each other.
  • the carrier injection layer part 223 and the third carrier injection layer part 233 are examples of the carrier injection layer 233.
  • the patterning process (such as the yellow light process) for forming the spacer 220 will not adversely affect the performance of the organic functional material layer.
  • a second conductive layer 303 is formed on the organic functional material layer 114 to form the second electrode 212 of the first light-emitting element 201 and the second electrode 222 of the second light-emitting element 202 to form the first light-emitting element 201 and the second light-emitting element 202.
  • the material of the second conductive layer 303 can be, for example, a transparent metal oxide conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc., or carbon nanotubes, graphite Transparent nano conductive materials such as olefin and nano silver wire.
  • FIGS. 9A-9E show step diagrams of manufacturing methods of pixel structures provided by other embodiments of the present disclosure.
  • the main difference between this embodiment and the above-mentioned embodiment lies in the way in which the spacer is formed.
  • a first conductive layer is formed on the driving substrate 102, and a patterning process is performed on the first conductive layer to form the first electrode 211 of the first light-emitting element 201 and the first electrode 211 of the second light-emitting element 202 arranged at intervals. Electrode 221.
  • a spacer 220 is formed at the interval between the first electrode 211 of the first light-emitting element 201 and the first electrode 221 of the second light-emitting element 202.
  • the spacer 220 is additionally formed, so the selection of materials and processes is more flexible.
  • an anti-reflective material layer 112 and a photoresist layer 113 are sequentially formed on the first conductive layer. After exposing and developing the photoresist 113, a spacer 220 as shown in FIG. 9C is obtained.
  • the material and formation process of the anti-reflective material layer refer to the above-mentioned embodiment, and will not be repeated here.
  • a negative photoresist material may be used to form the spacer 220.
  • the cross section of the spacer 220 is an inverted trapezoid. This is because during the exposure process, the closer the negative photoresist is to the substrate 20, the lower the sensitivity, so that the spacer 200 with a small bottom area and a large top area can be obtained after development.
  • the spacer 220 may be formed by using an inorganic insulating material in combination with a dry etching process.
  • the material of the spacer 220 is silicon nitride, oxide or oxynitride.
  • the cross section of the spacer 220 is rectangular. This is because the dry etching process has good anisotropy, and there is almost no lateral undercutting during the etching process, so a pattern with a cross-section close to a rectangle can be obtained.
  • an organic functional material layer is sequentially formed on the spacer, for example, an entire surface of the organic functional material layer is formed by using an Open Mask combined with an evaporation process. Since the step coverage of the organic material is poor and it is difficult to adhere to the concave surface of the spacer, the organic functional material layer is broken at the corresponding spacer 220 to form the organic functional layer of each light-emitting element.
  • the patterning process (such as the yellow light process) for forming the spacer 220 will not adversely affect the performance of the organic functional material layer.
  • FIG. 10 shows a spectrum diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • the figure respectively shows the spectrum diagram of the three sub-pixels of red (R), green (G), and blue (B) lit at the same time and the three sub-pixels. Spectral graphs lit separately.
  • the display device formed by the display substrate The color gamut can reach more than 80%.

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Abstract

一种显示基板及其制作方法，该显示基板具有相邻的第一子像素区和第二子像素区，该显示基板包括衬底基板、依次设置于该衬底基板上的第一导电层、有机功能层和第二导电层，该有机功能层包括载流子注入层，该载流子注入层包括分别位于该第一子像素区和该第二子像素区的第一载流子注入层部分和第二载流子注入层部分，该显示基板还包括位于第一子像素区和第二子像素区的间隔体，该间隔体将该第一载流子注入层部分和该第二载流子注入层部分断开，该载流子注入层还包括第三载流子注入层部分，该第三载流子注入层部分位于该间隔体和该第二导电层之间，且分别与该第一载流子注入层部分和该第二载流子注入层部分断开。该显示基板可以有效防止子像素间的漏电和串色。

Description

显示基板及其制作方法 技术领域
本公开实施例涉及一种显示基板及其制作方法。
背景技术
微型OLED(Micro OLED)显示器涉及有机发光二极管(OLED)技术和CMOS技术的结合，与光电子产业和微电子产业的交叉集成相关，促进了新一代微型显示技术的发展，也推进了硅上有机电子、甚至是硅上分子电子的研究和发展。
微型OLED(Micro OLED)显示器具有优秀的显示特性，例如分辨率高、亮度高、色彩丰富、驱动电压低、响应速度快、功耗低等，具有广阔的发展前景。
发明内容
本公开一些实施例提供一种显示基板，具有相邻的第一子像素区和第二子像素区，所述显示基板包括衬底基板、依次设置于所述衬底基板上的第一导电层、有机功能层和第二导电层，所述有机功能层包括载流子注入层，所述第一导电层包括分别位于所述第一子像素区和所述第二子像素区的彼此绝缘的第一电极和第二电极，所述载流子注入层包括分别位于所述第一子像素区和所述第二子像素区的第一载流子注入层部分和第二载流子注入层部分，所述第二导电层包括分别位于所述第一子像素区和所述第二子像素区的彼此连接的第三电极和第四电极，所述第三电极和所述第四电极为一体的结构；所述第一电极、所述第一载流子注入层部分和所述第三电极构成第一发光元件，所述第二电极、所述第二载流子注入层部分和所述第四电极构成第二发光元件，所述显示基板还包括位于第一发光元件和所述第二发光元件之间的间隔体，所述间隔体将所述第一载流子注入层部分和所述第二载流子注入层部分断开，所述载流子注入层还包括第三载流子注入层部分，所述第三载流子注入层部分位于所述间隔体和所述第二导电层之间，且分别与所述第一载流子 注入层部分和所述第二载流子注入层部分断开；所述显示基板还包括驱动电路，所述驱动电路与所述第一发光元件和所述第二发光元件电连接，且配置为驱动所述第一发光元件和所述第二发光元件；所述驱动电路包括晶体管，所述晶体管包括半导体层，所述半导体层位于所述衬底基板内部。
在一些示例中，所述载流子注入层为电子注入层或空穴注入层。
在一些示例中，所述间隔体在与所述第一载流子注入层部分和所述第二载流子注入层部分相邻的侧面具有凹入部分。
在一些示例中，在远离所述衬底基板的方向上，所述间隔体的宽度先变小后变大。
在一些示例中，所述间隔体在垂直于所述衬底基板的方向上的截面为倒梯形。
在一些示例中，所述载流子注入层还包括第三载流子注入层部分，所述载流子注入层部分位于所述间隔体和所述第二导电层之间，且分别与所述第一载流子注入层部分和所述第二载流子注入层部分间隔。
在一些示例中，在垂直于所述衬底基板的方向上，所述第二导电层的厚度与所述间隔体的厚度的比值范围为0.5-2。
在一些示例中，所述间隔体包括抗反射涂层，所述抗反射涂层包括抗反射有机材料。
在一些示例中，所述间隔体的材料为负性光刻胶材料或无机绝缘材料。
在一些示例中，所述载流子注入层还包括第三载流子注入层部分，所述第三载流子注入层部分位于所述间隔体和所述第二导电层之间，且分别与所述第一载流子注入层部分和所述第二载流子注入层部分间隔。
在一些示例中，所述有机功能层还包括电荷生成层，所述电荷生成层包括分别位于所述第一子像素区和所述第二子像素区的第一电荷生成层部分和第二电荷生成层部分，所述间隔体还将所述第一电荷生成层部分和所述第二电荷生成层部分间隔。
在一些示例中，所述第一发光元件和所述第二发光元件分别配置为发白光。
在一些示例中，所述有机功能层包括多个发光层，所述多个发光层在垂直于所述衬底基板的方向上堆叠。
在一些示例中，所述多个发光层中的至少两个彼此串联，所述电荷生成层位于所述至少两个发光层中相邻两个发光层之间。
在一些示例中，所述多个发光层包括红绿发光层和蓝光层，所述红绿发光层与所述蓝光层彼此串联，所述连接层位于所述红绿发光层和所述蓝光层之间。
在一些示例中，所述红绿发光层包括相邻设置的红光层和绿光层，所述红光层更靠近所述第一导电层。
在一些示例中，所述显示基板还包括位于第三子像素区的第三发光元件，所述第一发光元件、所述第二发光元件和所述第三发光元件构成一个像素单元。
在一些示例中，所述显示基板还包括彩膜层，所述彩膜层位于所述第一发光元件和所述第二发光元件远离所述衬底基板的一侧。
本公开一些实施例还提供一种显示基板的制作方法，所述显示基板具有相邻的第一子像素区和第二子像素区，所述制作方法包括：提供衬底基板；形成驱动电路；在所述衬底基板上依次形成第一导电层、有机功能层和第二导电层，所述第一导电层包括分别位于所述第一子像素区和所述第二子像素区的第一电极和第二电极，所述有机功能层包括载流子注入层，所述载流子注入层包括分别位于所述第一子像素区和所述第二子像素区的第一载流子注入层部分和第二载流子注入层部分，所述第二导电层包括分别位于所述第一子像素区和所述第二子像素区的第三电极和第四电极，所述第一电极、所述第一载流子注入层部分和所述第三电极构成第一发光元件，所述第二电极、所述第二载流子注入层部分和所述第四电极构成第二发光元件，在所述第一发光元件和所述第二发光元件之间形成间隔体，所述驱动电路与所述第一发光元件和所述第二发光元件电连接，且配置为驱动所述第一发光元件和所述第二发光元件，所述驱动电路包括晶体管，所述晶体管包括半导体层，所述半导体层位于所述衬底基板内部，所述间隔体将所述第一载流子注入层部分和所述第二载流子注入层部分断开。
在一些示例中，所述间隔体在与所述第一载流子注入层部分和所述第二载流子注入层部分相邻的侧面形成有凹入部分。
在一些示例中，在所述第一子像素区和所述第二子像素区之间形成间隔体包括：形成抗反射材料层，并在所述抗反射材料层上形成光刻胶层，对所述光刻胶层进行曝光，将曝光后的光刻胶层使用显影液显影以得到光刻胶图案，且通过所述光刻胶图案使用所述显影液刻蚀所述抗反射材料层，形成所述间隔体。
在一些示例中，所述抗反射材料层形成于所述第一电极和所述第二电极上。
在一些示例中，所述第一导电层形成于所述光刻胶图案上，对所述光刻胶图案进行剥离工艺形成所述第一电极和所述第二电极。
在一些示例中，所述有机功能层形成于所述间隔体上，所述载流子注入层在所述间隔体处断开，从而形成所述第一载流子注入层部分和所述第二载流子注入层部分。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1A为一种OLED显示发光器件的漏电示意图；
图1B为一种OLED显示发光器件的光谱图之一；
图1C为一种OLED显示发光器件的光谱图之二；
图2A为本公开一些实施例提供的显示基板的平面示意图之一；
图2B为本公开一些实施例提供的显示基板的剖视图之一；
图2C为本公开一些实施例提供的显示基板的剖视图之二；
图3A为本公开一些实施例提供的间隔体的截面形状示意图；
图3B为本公开一些实施例提供的显示基板的局部放大图；
图3C为本公开一些实施例提供的显示基板的SEM图；
图4为本公开一些实施例提供的显示基板的结构示意图；
图5为本公开一些实施例提供的显示基板的平面示意图之二；
图6为本公开一些实施例提供的显示基板的剖视图之三；
图7A为本公开一些实施例提供的一种显示基板的驱动电路原理示意图；
图7B为本公开一些实施例提供的一种显示基板的电压控制电路和驱动电路的具体实现示例的电路图；
图8A-8F为本公开一些实施例提供的显示基板的制作方法的步骤图；
图9A-9E为本公开另一些实施例提供的显示基板的制作方法的步骤图；以及
图10为本公开一些实施例提供的显示基板的光谱图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
微型OLED(Micro OLED)显示器通常具有小于100微米的尺寸，例如小于50微米的尺寸等，涉及有机发光二极管(OLED)技术和CMOS 技术的结合，将OLED阵列制备在包括CMOS电路的硅基基板上。
通常情况下，OLED器件通过采用精细金属掩模(Fine Metal Mask，FMM)蒸镀不同的有机功能层(如电子/空穴注入层)的方式形成，例如，采用FFM对有机功能层进行构图从而在不同像素区形成对应的图案。然而，FMM精度有限，无法实现高图像分辨率(即每英寸所拥有的像素，Pixels Per Inch，简称PPI)，这对OLED器件的分辨率造成了限制。因此，可以采用白光OLED结合彩膜层的方式实现全彩显示。然而，在这种工艺中，通常有机功能层形成为覆盖多个子像素区的连续结构，容易在横向上发生漏电，造成子像素间的串色，并降低了显示器件的色域。例如，OLED器件中的载流子注入层(如电子注入层(EIL)、空穴注入层(HIL))、发光层、载流子注入层(CGL)等有机功能子层通常包括金属元素，例如包括金属离子或为含金属元素的重掺杂材料，在电压作用下会产生移动的电荷，从而引起横向上的子像素之间的漏电，进而造成串色问题。
图1A示出了一种OLED显示器件发生串色的示意图，图1B为该OLED显示器件的光谱图。该OLED显示器件采用白光OLED结合彩膜层实现全彩显示。如图1A和1B所示，当点亮红光区(R)的子像素时，由于载流子注入层(CGL)1中发生漏电，导致相邻的例如处于非发光状态的绿光区(G)发光，从而使得单个子像素(例如包括红绿蓝子像素)的发光纯度降低，导致整个OLED显示器件的色域降低。
图1C示出了一种OLED显示器件的光谱图的另一个示例，图中分别示出了红(R)绿(G)蓝(B)三种子像素同时点亮的光谱图以及三种子像素分别点亮的光谱图。如图所示，当三种子像素分别点亮时，都有不同颜色的光从相邻的子像素逸出，这导致整个OLED显示器件色域降低。根据计算，该OLED显示器件色域指标(NTSC)仅为30％。
本公开实施例提供一种显示基板，通过在相邻子像素区之间设置间隔体，使得载流子注入层在沉积时在间隔体处自然断开，也即相邻子像素区中的载流子注入层被该间隔体间隔，从而有效避免载流子注入层的横向漏电导致的子像素间串色，提高了该显示基板的色域，改善了显示质量。
图2A为本公开实施例提供的一种显示基板的平面示意图。如图所示，该显示基板20包括多条栅线11和多条数据线12，多条栅线11和多条数据线12彼此交叉在显示区110中定义出阵列分布的多个子像素区100，每个子像素区100设置一个子像素，每个子像素包括发光元件和驱动该发光元件的驱动电路。该驱动电路例如为常规的像素电路。例如，该驱动电路包括常规的2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数)像素电路，并且不同的实施例中，该驱动电路还可以进一步包括补偿电路，该补偿电路包括内部补偿电路或外部补偿电路，补偿电路可以包括晶体管、电容等。例如，根据需要，该驱动电路还可以进一步包括复位电路、发光控制电路、检测电路等。例如，该显示基板还可以包括位于显示区110外的非显示区120中的数据驱动电路6和栅极驱动电路7，该数据驱动电路和栅极驱动电路分别通过数据线12和栅线11与发光元件的驱动电路连接以提供电信号。该数据驱动电路用于提供数据信号，该栅极驱动电路用于提供扫描信号，还可以进一步用于提供各种控制信号、电源信号等。
在另一些示例中，例如，该显示基板采用硅基板作为衬底基板101，该驱动电路(像素电路)206、该栅极驱动电路6和数据驱动电路7都可以集成于该硅基板上。在此情形下，由于硅基电路可以实现较高的精度，该栅极驱动电路6和数据驱动电路7例如也可以形成于对应于该显示基板的显示区的区域中，而并不一定位于非显示区。
图2B示出了图2A所示显示基板沿A-A’方向的剖视图的一个示例。为了清楚起见，图中仅示出了相邻的第一子像素区和第二子像素区，并且对于每个子像素区，仅示出了发光元件以及驱动电路206中与该发光元件直接连接的晶体管。例如，该晶体管可以是驱动晶体管，配置为控制驱动发光元件发光的电流的大小。例如，该晶体管也可以为发光控制晶体管，用于控制驱动发光元件发光的电流是否流过。本公开的实施例对此不作限制。如图2B所示，该显示基板20包括衬底基板101、设置于衬底基板101上的第一导电层301、有机功能层302和第二导电层303，该有机功能层302包括载流子注入层321。第一导电层301包括分别位于第一子像素区和第二子像素区的彼此绝缘的第一电极211和 第二电极221，该第一电极211和第二电极221彼此断开。该第二导电层303包括分别位于第一子像素区和第二子像素区的彼此连接的第三电极212和第四电极222。第三电极212和第四电极222为一体的结构，也即第三电极212和第四电极222由同一导电材料层形成的连续光滑的结构，该第二导电层中不同的区域之间不存在界面。
如图2B所示，本公开实施例提供的显示基板可以与形成于硅基板上，驱动电路206可以集成于硅基板上形成驱动基板102。该第一发光元件201和第二发光元件202形成于包括硅基板101的驱动基板102上，该驱动基板包括形成于该硅基板101上的驱动电路206，该硅基板例如为单晶硅或者高纯度硅。驱动电路206通过半导体工艺形成于硅基板101上，例如，通过掺杂工艺在硅基板101中形成晶体管的有源层(即半导体层)、第一极和第二极，并通过硅氧化工艺形成绝缘层104、以及通过溅射工艺形成多个导电层105、106等。晶体管的半导体层(如图2B中的有源层122)位于衬底基板101的内部，或者为衬底基板101的一部分。
例如，该驱动电路206包括互补型金属氧化物半导体电路(CMOS电路)。图2C示出了硅基板中形成PMOS晶体管和NMOS晶体管的具体示例。如图2C所示，该NMOS和PMOS集成于P型硅基板中，该NMOS的有源层为该P型基板的一部分，该PMOS的有源层为通过在该P型基板中进行N型掺杂得到。
例如，上述栅极驱动电路6和数据驱动电路7也可以通过上述半导体工艺集成在硅基板101中。该栅极驱动电路和数据驱动电路可以采用本领域内的常规电路结构，本公开的实施例对此不作限制。
如图2B所示，第一发光元件201的第一电极211形成于该驱动基板102的表面，并通过填充有导电材料(例如为钨)的接触孔103以及该多个导电层与第一晶体管203的第一极123实现电连接。图2B中示例性地示出了一层绝缘层104和两层导电层105、106，然而本公开实施例对于绝缘层104和导电层的层数不作限制。
例如，如图2B所示，驱动基板102中的最顶层导电层106具有反射性，例如为钛/氮化钛/铝的层叠结构。例如，该导电层106包括间隔 设置的多个子层，分别与第一导电层301所包括的多个电极一一对应设置。在顶发射结构中，该导电层106可以设置为反射层，用于反射发光元件发出的光线，提高出光效率。例如，第一导电层301中的每个电极在衬底基板101上的正投影落入该电极对应的导电层106的部分在该衬底基板101上的正投影内。在这种情形，第一导电层301可以采用具有高功函数的透明导电氧化物材料，例如ITO、IZO、IGZO、AZO等。
有赖于成熟的CMOS集成电路技术，硅基工艺可以实现较高的精度(例如PPI可以达到6500甚至一万以上)。例如，第一发光元件201的第一电极211和第二发光元件202的第一电极221之间的间距(也即该间隔体202的宽度)d小于1微米。
该有机功能层302包括分别位于第一子像素区和第二子像素区的第一有机功能层和第二有机功能层。该第一电极211、第一有机功能层和第三电极212构成第一发光元件201，该第二电极221、第二有机功能层和第四电极222构成第二发光元件202。
例如，该第一发光元件201/第二发光元件202可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等，本公开实施例对于发光元件的类型不作限定。例如，OLED的发光层可以为小分子有机材料或高分子有机材料。
例如，第一发光元件201和第二发光元件202为顶发射结构，第一电极211和第二电极221具有反射性。例如，第一电极211和221包括高功函数和高反射性的材料以充当阳极，例如为Ti/Al/Ti/Mo的叠层结构，其中金属钛可以作为缓冲层提高层间的粘合性，Al作为高反射材料，Mo作为高功函数材料直接与有机功能层接触可以提高载流子的注入能力。相应地第二导电层303充当阴极，例如，该第二导电层302可以是透明导电材料或者透明导电材料与金属材料的叠层结构。例如该第二导电层302可以是透明金属氧化物导电材料，如氧化铟锌(IZO)、氧化铟锡(ITO)、氧化铟镓锌(IGZO)等，还可以是碳纳米管、石墨烯、纳米银线等透明纳米导电材料。
该有机功能层302包括在垂直于衬底101方向上彼此堆叠的层结构，包括至少一个载流子注入层(和至少一个发光层。该载流子注入层 可以是电子注入层(EIL)或空穴注入层(HIL)。电子注入层位于发光层靠近阴极的一侧，用于降低从阴极注入电子的势垒，使电子能从阴极有效地注入到发光层中。空穴注入层位于发光层靠近阳极的一侧，用于降低从阳极注入空穴的势垒，使空穴能从阳极有效地注入到发光层中。因此，在选择电子/空穴注入层材料的时候，需要考虑材料能级和电极材料的匹配。例如，电子注入层材料可以是LiQ(8-羟基喹啉锂)、AlQ3(8-羟基喹啉铝)等；空穴注入层的材料可以是CuPc(聚酯碳酸)，TiOPc、m-MTDATA、2-TNATA等。
例如，该有机功能层302根据需要还可以包括、电子/空穴传输层、电子/空穴阻挡层、电荷生成层等。
图2B中仅示意性地示出了该有机功能层302中的发光层靠近第一导电层301的载流子注入层321，而对于其它功能层并没有详细标注。该载流子注入层321包括分别位于第一子像素区和第二子像素区的第一载流子注入层部分213和第二载流子注入层部分223。该显示基板20还包括位于第一发光元件201和第二发光元件202之间的间隔体220，该间隔体220将第一载流子注入层部分213和第二载流子注入层部分223断开。例如，如图2B所示，该间隔体220位于第一电极211和第二电极221之间，并在垂直于衬底基板101的方向上延伸，将第一载流子注入层部分213和第二载流子注入层部分223断开，也即第一载流子注入层部分213和第二载流子注入层部分223彼此间隔，二者不连接、不接触。
如图2B所示，载流子注入层302还包括第三载流子注入层部分233，第三载流子注入层部分233位于间隔体220和第二导电层303之间，且分别与第一载流子注入层部分213和第二载流子注入层部分223断开。
如图2B所示，该间隔体220在与第一载流子注入层部分213和第二载流子注入层部分223相邻的侧面具有凹入部分(从该间隔体远离衬底基板的一端看)。例如，该凹入部分与该间隔体220的顶面(远离衬底基板的表面)直接连接。该间隔体220的侧面可以包括平滑的内凹曲面，也可以包括不平滑的凹入面，还可以包括多个凹入面的组合。本公 开实施例对凹入部分的具体形式不作限定。
图3A示出了该间隔体的几种剖面形状示意图，该间隔体均为正立放置，也即在图中衬底基板位于每个间隔体的下方。例如，在一些示例中，在远离衬底基板101的方向上，间隔体220的宽度先变小后变大。
在另一些示例中，距离衬底基板101越远，间隔体220平行于衬底基板101的横截面积越大；例如，间隔体在垂直于衬底基板101的方向上的截面为倒梯形。
在又一些示例中，该间隔体220在垂直于衬底基板101方向的截面为矩形。
在有机材料的沉积过程中，由于热蒸发能量较小，有机材料的台阶覆盖性较差，难以在该凹入部分(例如图3A中虚线标注的表面)或垂直面上附着，因此载流子注入层321在对应间隔体220处，也即相邻的子像素之间发生断开，从而避免了载流子注入层不同的子像素之间发生漏电，也避免了由于该漏电引起的串色及色域降低等问题。
例如，在至少一个实施例中，该间隔体220包括抗反射涂层(antireflection coating，ARC)，该抗反射涂层包括抗反射有机材料。例如，该抗反射涂层可以在光刻中作为底部抗反射涂层(bottom antireflection coating,BARC)，能够有效抑制由衬底反射光线而在光刻胶层中引起的驻波效应，提高光刻的线宽均一性以及光刻胶的刻蚀精准度。
例如，该抗反射涂层为易溶于与之配合使用的光刻胶的显影液的有机材料，例如为有机聚合物或共聚物。例如，该抗反射涂层的材料包括具有烯烃、炔烃或芳族基团的单体单元。例如，该抗反射涂层的材料包括酯、丙烯酸酯、或异氰酸酯单体。例如，该抗反射涂层的材料包括丙烯酸酯聚合物或共聚物或者苯乙烯聚合物或共聚物。根据抗反射涂层的材料，并且在确定了光刻胶之后，相应地选择显影液。
例如，该间隔体220的材料为负性光刻胶材料或无机绝缘材料，例如为硅的氮化物或氧化物。
通过在第一发光元件201和第二发光元件202之间设置该间隔体220，可以地将载流子注入层在相邻子像素区之间断开，从而有效避免 载流子注入层的横向漏电导致的子像素间串色，提高了该显示基板的色域，改善了显示质量。
图3B示意出了该显示基板在间隔体220处的部分放大示意图，如图所示，在垂直于衬底基板101的方向上，第二导电层303的厚度h1与间隔体的厚度h2的比值范围为0.5-2。例如，间隔体220的厚度范围为100-250纳米，平均宽度范围为0.5-1.2微米。例如，第二导电层303的厚度范围为100-300纳米。例如，第二导电层作为阴极，材料为金属与透明金属氧化物导电材料的层叠机构。例如，第二导电层303为Mg/Ag/IZO层叠结构，Mg/Ag材料更靠近有机功能层302，且厚度为十几纳米。这是因为金属的功函数较金属氧化物导电材料的功函数更低，直接与有机功能层接触可以提高载流子(电子)的注入能力。
图3C示出了该显示基板部分剖面扫描电镜(SEM)图。如图3C所示，该间隔体220在垂直于衬底基板101方向的截面为矩形。图中标号4所指示的显示为黑色的层结构是在电荷生成层上方并紧邻电荷生成层形成的用于辅助判断的辅助层，该辅助层在实际器件中是并不存在的。从图3A可以看出，在对应间隔体220处，位于该辅助层4下方的包括该载流子注入层321的有机功能层部分基本上全部断开。
例如，如图3C所示，有机功能层在靠近间隔体220处的厚度H1较小，这正是由于有机材料难以在坡度较大的间隔体220的侧壁附着所导致的。例如，有机功能层302在子像素区的中心处指向间隔体220的方向D1、D2上厚度逐渐变薄。
例如，如图3C所示，类似地，第二导电层303在靠近间隔体220处的厚度较小，这正是由于蒸镀工艺中热蒸发能量较小，沉积的材料难以在坡度较大的间隔体220的侧壁附着所导致的。例如，第二导电层303在子像素区的中心处指向间隔体220的方向D1、D2上厚度逐渐变薄。
如图3C所示，第三电极212和第四电极222为一体的结构，该第二导电层302为连续光滑的结构，中间不存在界面。
例如，为了防止第二导电层303发生断裂，该第二导电层303的厚度可以大于100纳米。
例如，该第一发光元件201和第二发光元件202分别配置为发白光。本公开实施例对于该有机功能层302的结构和发光机制也不作限制。
例如，为了提高发光效率以及发光器件的色域，也可以采用多层彼此堆叠的发光层发白光，也即该有机功能层302包括多个发光层，该多个发光层在垂直于衬底基板101的方向上堆叠。例如，该有机功能层302包括彼此堆叠的两个发光层(黄蓝)或三个发光层(红绿蓝)。
例如，该多个发光层中的至少两个彼此通过电荷生成层(CGL)串联形成串联结构(tandem结构)，该电荷生成层包括N型电荷生成层以及P型电荷生成层，用于平衡载流子的输送。该N型电荷产生层可以由掺杂有诸如锂(Li)、钠(Na)、钾(K)或铯(Cs)的碱金属或诸如镁(Mg)、锶(Sr)、钡(Ba)或镭(Ra)的碱土金属(但不限于它们中的任何一种)的有机层形成；该P型电荷产生层可以由通过将具有空穴传输能力的有机基质材料与掺杂剂掺杂而获得的有机层形成。串联结构有助于提高器件的发光效率和发光亮度。
例如，相邻的发光层对应的发光能级相对接近，这样对于发光元件的发光层材料、电子传输材料、空穴传输材料及电极材料等材料的选择范围较大，实现难度较低。
图4示出了本公开另一些实施例提供的一种显示基板的示意图。如图4所示，该显示基板20还包括第三发光元件207，例如，该第一发光元件201、第二发光元件202和第三发光元件207分别位于不同的子像素中，由此构成一个像素单元PX，该像素单元PX结合彩膜层210可以发出全彩光。
图4所示的发光元件还包括电荷生成层(CGL)，该发光元件为串联结构(tandem structure)。如图4所示，该有机功能层302包括红光层、绿光层和蓝光层，其中红光层和绿光层彼此相邻构成红绿发光层和蓝光层，该红绿发光层和蓝光层彼此串联，电荷生成层位于红绿发光层和蓝光层之间。
例如，图4所示的有机功能层302包括多个载流子注入层(HIL1、HIL2、EIL)，例如，至少一个载流子注入层被间隔体220断开。在另一些示例中，有机功能层302被间隔体220全部隔断，也即所有的载流 子注入层都被间隔体220断开；在此情形，该电荷生成层也被间隔体220断开，也即该电荷生成层位于第一子像素区的第一电荷生成层部分和位于第二子像素区的第二电荷生成层部分彼此断开。
例如，该有机功能层302还包括分别位于该电荷生成层两侧的电子传输层(ETL1)和空穴传输层(HTL2)，该电荷生成层中的N型电荷生成层更靠近该电子传输层，该电荷生成层中的P型电荷生成层更靠近该空穴传输层。
例如，该第一导电层和第二导电层其中之一具有反射性，另一个具有半透性或者透光性。例如，在第一发光元件201中，第一电极211和第三电极212构成微腔，可以使得各发光层到反射层的距离与该发光层所发出光的波长满足2Δ＝mλ(m＝1，2，3，……)，其中Δ为光程，光程等于介质折射率乘以光在介质中传播的距离乘以介质的折射率，从而使得该发射光和反射光在该微腔中发生共振，从而提高发光的纯度，进一步提高显示基板的色域和发光亮度。
例如，该发光元件为顶发射结构，在这种情形，该第一导电层具有反射性，该第二导电层具有半透性或者透光性。例如，红光层和绿光层位于该载流子注入层靠近第一导电层的一侧，蓝光层位于该载流子注入层远离该第一导电层的一侧。
通过这种设置，可以使得各发光层满足上述关系，提高发光纯度和亮度。另一方面，该红光层、绿光层和蓝光层依次层叠设置于该第一导电层301上，该红光层更靠近该第一导电层。由于长波发光材料容易吸收短波，这种设置避免发出的光线被其它发光层吸收，从而提高出光效率。
例如，该第一导电层301形成为发光元件的阳极，第二导电层303形成为发光元件的阴极。例如，该第一导电层301为高功函数材料，例如还具有高反射性，例如为Ti/Al/Ti/Mo的叠层结构，其中金属钛可以作为缓冲层提高层间的粘合性，Al作为高反射材料，Mo作为高功函数材料直接与有机功能层接触可以提高载流子的注入能力。例如，该第二导电层303的材料为具有低功函数及高透射率的导电材料，例如可以是透明金属氧化物导电材料，如氧化铟锌(IZO)、氧化铟锡(ITO)、 氧化铟镓锌(IGZO)等，还可以是碳纳米管、石墨烯、纳米银线等透明纳米导电材料。例如，为了防止第二导电层303由于间隔体220的设置而发生断裂，第二导电层303的厚度可以大于100纳米。在第二导电层303位透明导电层的情形下，由于透明导电层意味着透光率非常高，因此该厚度对透明导电层的透光率的影响不大。
例如，该红光层、绿光层和蓝光层分别为将红光、绿光、蓝光磷光材料掺杂到主体材料中得到的CBP：(ppy)2Ir(acac)、CBP：FIrpic和CBP：Btp2Ir(acac)。
继续参照图2B，图2B分别示出了与该第一发光元件201和第二发光元件202电连接的第一晶体管203和第二晶体管204。本公开的实施例对第一晶体管203和第二晶体管204的具体类型不作限制。以下对第一晶体管203进行示例性说明，该说明也适用于第二晶体管204，因而不再赘述。
例如，第一晶体管203包括栅极121、栅极绝缘层125、有源层122、第一极123和第二极124。本公开的实施例对于第一晶体管203的类型、材料、结构不作限制，例如其可以为顶栅型、底栅型等，第一晶体管203的有源层可以为微晶硅、非晶硅、多晶硅(低温多晶硅或高温多晶硅)、氧化物半导体(例如IGZO)等无机半导体材料，或者还可以为有机材料，例如为PBTTT、PDBT-co-TT、PDQT、PDVT-10、二萘并-并二噻吩(DNTT)或并五苯等有机半导体材料。例如，第一晶体管203可以为N型或P型。
例如，第一晶体管203的第一极123与第一发光元件201的第一电极211电连接。
需要说明的是，本公开实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的一些实施例以形成在硅基板中的场效应晶体管(如MOS场效应晶体管)为例进行说明，在该示例中，对硅基板进行掺杂(p型掺杂或n型掺杂)形成晶体管的有源层，也即晶体管的有源层位于硅基板内，或者晶体管的有源层为硅基板的一部分。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施 例中，为了区分晶体管除栅极之外的两极，例如，可直接描述了其中一极为第一极，另一极为第二极。
图5示出了本公开又一些实施例提供的显示基板20的平面示意图。如图所示，在每相邻(包括该像素阵列的行方向和列方向)两个子像素区100(发光元件)之间均设置有间隔体220。
图6示出了图2A沿A-A’方向的剖视图的另一个示例。如图所示，显示基板20还包括位于非显示区120中的绑定电极(Bonding Pad)230，该绑定电极230通常用于在显示区器件制作完成后，与外部元件进行绑定(Bonding)以为显示基板提供信号，例如电源电压信号等。该绑定电极230可以和显示区110中的导电结构同层设置以节省工艺。例如，绑定电极230可以与显示区110中发光元件以下的最顶层(最远离衬底基板101)的导电层同层设置以方便后续的绑定工艺，例如，如图6所示，绑定电极230与显示区110中的晶体管的源漏电极层同层设置。
需要说明的是，本公开实施例中的“同层设置”是指多个结构由同一材料膜经相同或不同的构图工艺形成，因而具有相同的材料。
例如，该显示基板还包括位于第一发光元件201和第二发光元件202远离衬底基板101一侧的封装层208、彩膜层210以及盖板209等。例如，该封装层208配置为对发光元件进行密封以防止外界的湿气和氧向该发光元件及像素电路的渗透而造成对器件的损坏。例如，封装层208包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层208与发光元件之间还可以设置吸水层，配置为吸收发光元件在前期制作工艺中残余的水汽或者溶胶。盖板209例如为玻璃盖板。例如，盖板209和封装层208可以为一体的结构。
例如，该显示基板20为有机发光二极管(OLED)显示基板或微型OLED(Micro OLED)显示基板。
图7A为本公开一些实施例提供的一种显示基板的驱动电路原理示意图。该显示基板包括位于显示区域110(AA区)中的多个发光元件L(例如上述第一发光元件201和第二发光元件202)以及与各发光元件L一一对应耦接的驱动电路206，驱动电路206包括驱动晶体管，该驱动晶体管配置为控制驱动发光元件发光的电流的大小。该显示基板还 可以包括位于非显示区120中的多个电压控制电路30。例如，一行中至少两个驱动电路206共用一个电压控制电路30，且一行驱动电路206中驱动晶体管的第一极与共用的电压控制电路30耦接，各驱动晶体管的第二极与对应的发光元件L耦接。电压控制电路30被配置为响应于复位控制信号RE，将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光元件L复位；以及响应于发光控制信号EM，将第一电源信号VDD输出至驱动晶体管的第一极，以驱动发光元件L发光。通过共用电压控制电路20，可以简化显示区域130中各驱动电路的结构，降低显示区域130中驱动电路的占用面积，从而可以使显示区域130设置更多的驱动电路和发光元件，实现高PPI的有机发光显示面板。并且，电压控制电路30在复位控制信号RE的控制下将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光元件复位，从而可以避免上一帧发光时加载于发光元件上的电压对下一帧发光的影响，进而改善残影现象。
例如，该显示基板还可以包括位于显示区域110的多个像素单元PX，每个像素单元PX例如多个子像素；各子像素分别包括一个发光元件L与一个驱动电路206。进一步地，像素单元PX可以包括3个不同颜色的子像素。这3个子像素可以分别发出白光，并结合彩膜层可以发出全彩光。
例如，可以使同一行中相邻的至少两个子像素中的驱动电路206共用一个电压控制电路30。例如，在一些示例中，如图8A所示，可以使同一行中的所有驱动电路206共用一个电压控制电路30。或者，在其他示例中，也可以使同一行中相邻的两个、三个或更多子像素中的驱动电路206共用一个电压控制电路30，在此不作限定。这样，通过共用电压控制电路30可以降低显示区域110中驱动电路206的占用面积。
图7B为本公开一些实施例提供的一种显示基板的电压控制电路和驱动的具体实现示例的电路图。例如，驱动电路206中的驱动晶体管M0直接与发光元件L连接，例如可以为上述第一晶体管203或第二晶体管204。发光元件L的正极与驱动晶体管M0电连接，发光元件L的负极与第二电源端VSS电连接。第二电源端VSS的电压一般为负电压 或接地电压VGND(一般为0V)，初始化信号Vinit的电压也可以设置为接地电压VGND，在此不作限定。例如，可以将发光元件L设置为Micro-OLED或Mini-OLED，这样进一步有利于实现高PPI的有机发光显示面板。
例如，以一行中包括的两个驱动电路206为例，电压控制电路30可以包括第一开关晶体管M1和第二开关晶体管M2。第一开关晶体管M1的栅极用于接收复位控制信号RE，第一开关晶体管M1的第一极用于接收初始化信号Vinit，第一开关晶体管M1的第二极与对应的驱动晶体管M0的第一极S耦接。第二开关晶体管M2的栅极用于接收发光控制信号EM，第二开关晶体管M2的第一极用于接收第一电源信号VDD，第二开关晶体管M2的第二极与对应的驱动晶体管M0的第一极S耦接。例如，在另一些实施例中，为了降低走线的负载，提高像素驱动的均一性，还可以在第一开关晶体管M1和驱动晶体管M0之间串联一个晶体管。
例如，可以使第一开关晶体管M1与第二开关晶体管M2的类型不同。例如，第一开关晶体管M1为N型晶体管，第二开关晶体管M2为P型晶体管。或者，第一开关晶体管M1为P型晶体管，第二开关晶体管M2为N型晶体管。当然，也可以使第一开关晶体管M1与第二开关晶体管M2的类型相同。在实际应用中，需要根据实际应用环境来设计第一开关晶体管M1与第二开关晶体管M2的类型，在此不作限定。
例如，驱动电路206还可以包括第三开关晶体管M3和存储电容Cst。例如，第三开关晶体管M3的栅极用于接收第一栅极扫描信号S1，第三开关晶体管M3的第一极用于接收数据信号DA，第三开关晶体管M3的第二极与驱动晶体管M0的栅极G耦接。存储电容Cst的第一端与驱动晶体管M0的栅极G耦接，存储电容Cst的第二端与接地端GND耦接。
例如，驱动电路206还可以包括第四开关晶体管M4。例如，第四开关晶体管M4的栅极用于接收第二栅极扫描信号S2，第四开关晶体管M4的第一极用于接收数据信号DA，第四开关晶体管M4的第二极与驱动晶体管M0的栅极G耦接。并且，第四开关晶体管M4与第三开 关晶体管M3的类型不同。例如，第三开关晶体管M3为N型晶体管，第四开关晶体管M4为P型晶体管；或者，第三开关晶体管M3为P型晶体管，第四开关晶体管M4为N型晶体管。
需要说明的是，在数据信号DA的电压为高灰阶对应的电压时，通过例如P型的第四开关晶体管M4导通以将数据信号DA传输给驱动晶体管M0的栅极G，可以避免数据信号DA的电压受例如N型的第三开关晶体管M3的阈值电压的影响。在数据信号DA的电压为低灰阶对应的电压时，通过例如N型的第三开关晶体管M3导通以将数据信号DA传输给驱动晶体管M0的栅极G，可以避免数据信号DA的电压受例如P型的第四开关晶体管M4的阈值电压的影响。这样可以提高输入到驱动晶体管M0的栅极G上的电压范围。
本公开实施例还提供一种电子装置，包括上述显示基板20。例如，该电子装置为数码相框、智能手环、智能手表、手机、平板电脑、显示器、笔记本电脑、导航仪等具有任何显示功能的产品或者部件。
本公开实施例还提供上述显示基板的制作方法，该制作方法至少包括：提供衬底基板；在该衬底基板上依次形成第一导电层、有机功能层和第二导电层，该第一导电层包括分别位于该第一子像素区和该第二子像素区的第一电极和第二电极，该有机功能层包括载流子注入层，该载流子注入层包括分别位于该第一子像素区和该第二子像素区的第一载流子注入层部分和第二载流子注入层部分，该第二导电层包括分别位于该第一子像素区和该第二子像素区的第三电极和第四电极，该第一电极、该第一载流子注入层部分和该第三电极构成第一发光元件，该第二电极、该第二载流子注入层部分和该第四电极构成第二发光元件，形成驱动电路，该驱动电路与该第一发光元件和该第二发光元件电连接，且配置为驱动该第一发光元件和该第二发光元件，在该第一发光元件和该第二发光元件之间形成间隔体，该驱动电路包括晶体管，该晶体管包括半导体层，该半导体层位于该衬底基板内部，该间隔体将该第一载流子注入层部分和该第二载流子注入层部分间隔开，该载流子注入层还包括第三载流子注入层部分，该第三载流子注入层部分位于该间隔体和该第二导电层之间，且分别与该第一载流子注入层部分和该第二载流子注入 层部分间隔。
例如，参考图2B，可以采用硅衬底基板作为该衬底基板，并采用CMOS集成电路工艺在硅基板101上形成驱动电路206，具体可以参考图2B的描述，此处不再赘述。这些工艺例如可以由晶圆厂代工完成，之后再由后端的面板厂在基板102上完成发光元件的制作工艺以及后续的封装工艺等。
为了方便说明，以下将主要说明第一发光元件和第二发光元件的制作方法，并将衬底基板及驱动电路统称作驱动基板，该驱动基板与第一发光元件和第二发光元件电连接，并配置为驱动第一发光元件和第二发光元件发光。
图8A-8F示出了本公开一些实施例提供的显示基板的制作方法的步骤图。
如图8A所示，在驱动基板102上依次形成抗反射材料层112和光刻胶层113。在该实施例中，抗反射材料层112形成在光刻胶层13下方，在光刻中作为底部抗反射涂层(bottom antireflection coating,BARC)，可以有效抑制由衬底反射光线而在光刻胶层13中引起的驻波效应，提高光刻的线宽均一性以及光刻胶的刻蚀精准度。
例如，该抗反射材料层112的材料为易溶于用于光刻胶层13的显影液的有机材料，例如为有机聚合物或共聚物。例如，该抗反射材料层112包括具有烯烃、炔烃或芳族基团的单体单元。例如，该抗反射材料层112包括酯、丙烯酸酯、或异氰酸酯单体。例如，该抗反射材料层112包括丙烯酸酯聚合物或共聚物或者苯乙烯聚合物或共聚物。
如图8B所示，将曝光后的光刻胶层113使用显影液显影以得到光刻胶图案113a，同时该抗反射材料层112被显影液腐蚀，形成如图所示的间隔体220。
如图8B所示，该间隔体220在远离驱动基板102的方向上的宽度不均一，而是先变小后变大。这是由于一方面，显影液刻蚀反射材料层112为各向同性的湿法刻蚀，容易发生横向钻蚀，因此底端至上，横向上的宽度会有减小的趋势；而另一方面，间隔体220靠近光刻胶图案113a的顶端被上方的光刻胶图案113a保护而具有与该光刻胶图案113a 近似相同的横截面积，因此形成如图8B所示的具有凹入侧面的间隔体。
如图8C-8D所示，在光刻胶图案113a上形成第一导电层111，然后对剥离光刻胶图案113a，形成如图8D所示的第一导电图案层，也即形成第一发光元件的第一电极211和第二发光元件的第二电极221。在该实施例中，抗反射材料层112复用作了间隔体220。因此形成该间隔体220并不需要额外的工艺和成本。
该第一导电层111的厚度小于抗反射材料层112的厚度。例如，第一导电层111包括高功函数和高反射性的材料以充当阳极，例如包括金属或金属合金。包括图8E示出了第一发光元件的第一电极211示例性的放大示意图，如图所示，该第一电极211包括依次层叠的Ti/Al/Ti/Mo(A/B/C/D)的叠层结构，其中金属钛(层A和C)可以作为缓冲层提高层间的粘合性，铝(层B)作为高反射材料，钼(层D)作为高功函数材料直接与有机功能层接触可以提高载流子的注入能力。在该叠层结构中，铝被上方的钛和钼层完全包裹，由于铝的功函数较低，而钼和钛的功函数相对较高，因此将钼和钛包裹住铝以避免铝暴露在外与第一导电层111上的有机功能层直接接触影响载流子的注入能力。
该层叠结构例如可以通过电子束蒸发工艺形成。例如，在形成底层钛(层A)时，将靶材相对于基板偏心放置，从而蒸发出的钛材料可以到达间隔体200的凹入侧面，形成完全填充的钛层，增强基板表面的粘合力；在形成铝层时，将靶材相对于基板正心放置，在先形成的间隔体220由于具有较宽的顶端，因而铝不能完全覆盖底下的钛(如图8E所示虚线标注的范围)；而在后续形成钛层和钼层时，又分别将靶材相对于基板偏心放置，从而分别形成完全填充的钛层和钼层，将铝层完全包裹。由此可知，该工艺利用了间隔体220的凹入侧面，形成了高效率的电极材料。
如图8F所示，在第一导电层111上形成有机功能材料层114，该有机功能材料层114例如可以采用Open Mask结合蒸镀工艺整面形成，例如根据需要可以包括至少一层发光层、至少层载流子注入层、电子/空穴传输层、电子/空穴阻挡层、电荷生成层等，此处不再赘述。由于有机材料的台阶覆盖性较差，难以附着在该间隔体的凹入面，该载流子 注入层在间隔体220处，从而形成彼此间隔的第一载流子注入层部分213、第二载流子注入层部分223和第三载流子注入层部分233。
在该工艺中，无需对有机功能材料层进行额外的构图工艺，因此显示器件的分辨率不会受到掩膜板的精度的限制；另一方面，由于间隔体220形成在有机功能材料层之前，因此形成该间隔体220的构图工艺(如黄光工艺)不会对有机功能材料层的性能造成不利的影响。
然后在该有机功能材料层114上形成第二导电层303以形成第一发光元件201的第二电极212和第二发光元件202的第二电极222以形成第一发光元件201和第二发光元件202。该第二导电层303的材料例如可以是透明金属氧化物导电材料，如氧化铟锌(IZO)、氧化铟锡(ITO)、氧化铟镓锌(IGZO)等，还可以是碳纳米管、石墨烯、纳米银线等透明纳米导电材料。
图9A-9E示出了本公开另一些实施例提供的像素结构的制作方法的步骤图。该实施例与上述实施例的不同之处主要在于该间隔体的形成方式不同。
如图9A所示，在驱动基板102上形成第一导电层，并且对该第一导电层进行构图工艺形成间隔设置的第一发光元件201的第一电极211和第二发光元件202的第一电极221。
该第一导电层的材料和构图工艺可以参考上述实施例，此处不再赘述。
然后在第一发光元件201的第一电极211和第二发光元件202的第一电极221的间隔处形成间隔体220。在该实施例中，该间隔体220额外形成，因此材料和工艺的选择较为灵活。
例如，如图9B所示，在该第一导电层上依次形成抗反射材料层112和光刻胶层113。对光刻胶113进行曝光、显影后得到如图9C所示的间隔体220。该抗反射材料层的材料和形成工艺参考上述实施例，此处不再赘述。
在另一些实施例中，可以采用负性光刻胶材料形成该间隔体220。如图9D所示，该间隔体220的截面为倒梯形。这是由于在曝光过程中，负性光刻胶越靠近基板20感光度越低，因而显影后即可获得底面积小、 顶面积大的间隔体200。
在又一些实施例中，可以采用无机绝缘材料结合干刻工艺形成该间隔体220。例如该间隔体220的材料为硅的氮化物、氧化物或者氮氧化物。如图9E所示，该间隔体220的截面为矩形。这是由于干刻工艺具有良好的各向异性，在刻蚀过程中几乎不发生横向钻蚀，因而可以得到截面接近矩形的图案。
然后在该间隔体上依次形成有机功能材料层，例如采用Open Mask结合蒸镀工艺形成整面的有机功能材料层。由于有机材料的台阶覆盖性较差，难以附着在该间隔体的凹入面，因此该有机功能材料层在对应间隔体220处断开，形成各发光元件的有机功能层。
接着在该有机功能材料层上形成第二导电层等，此处不再赘述。
在该制作方法中，无需对有机功能材料层进行额外的构图工艺，因此显示器件的分辨率不会受到掩膜板的精度的限制；另一方面，由于间隔体220形成在有机功能材料层之前，因此形成该间隔体220的构图工艺(如黄光工艺)不会对有机功能材料层的性能造成不利的影响。
图10示出了本公开至少一个实施例提供的显示基板的光谱图，图中分别示出了红(R)绿(G)蓝(B)三种子像素同时点亮的光谱图以及三种子像素分别点亮的光谱图。
对照图1C，如图10所示，当三种子像素分别点亮时，其它颜色的光得到了很好的抑制，三种子像素的色坐标得到了大幅度提升，由该显示基板形成的显示器件的色域可以达到80％以上。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (24)

  1. 一种显示基板，具有相邻的第一子像素区和第二子像素区，其中，所述显示基板包括衬底基板、依次设置于所述衬底基板上的第一导电层、有机功能层和第二导电层，所述有机功能层包括载流子注入层，
    所述第一导电层包括分别位于所述第一子像素区和所述第二子像素区的彼此绝缘的第一电极和第二电极，所述载流子注入层包括分别位于所述第一子像素区和所述第二子像素区的第一载流子注入层部分和第二载流子注入层部分，所述第二导电层包括分别位于所述第一子像素区和所述第二子像素区的彼此连接的第三电极和第四电极，所述第三电极和所述第四电极为一体的结构；
    所述第一电极、所述第一载流子注入层部分和所述第三电极构成第一发光元件，所述第二电极、所述第二载流子注入层部分和所述第四电极构成第二发光元件，
    所述显示基板还包括位于第一发光元件和所述第二发光元件之间的间隔体，所述间隔体将所述第一载流子注入层部分和所述第二载流子注入层部分断开，
    所述载流子注入层还包括第三载流子注入层部分，所述第三载流子注入层部分位于所述间隔体和所述第二导电层之间，且分别与所述第一载流子注入层部分和所述第二载流子注入层部分断开；
    所述显示基板还包括驱动电路，所述驱动电路与所述第一发光元件和所述第二发光元件电连接，且配置为驱动所述第一发光元件和所述第二发光元件；所述驱动电路包括晶体管，所述晶体管包括半导体层，所述半导体层位于所述衬底基板内部。
  2. 如权利要求1所述的显示基板，其中，所述载流子注入层为电子注入层或空穴注入层。
  3. 如权利要求1或2所述的显示基板，其中，所述间隔体在与所述第一载流子注入层部分和所述第二载流子注入层部分相邻的侧面具有凹入部分。
  4. 如权利要求1-3任一所述的显示基板，其中，在远离所述衬底基板的方向上，所述间隔体的宽度先变小后变大。
  5. 如权利要求1-3任一所述的显示基板，其中，所述间隔体在垂 直于所述衬底基板的方向上的截面为倒梯形。
  6. 如权利要求1-5任一所述的显示基板，其中，所述载流子注入层还包括第三载流子注入层部分，
    所述载流子注入层部分位于所述间隔体和所述第二导电层之间，且分别与所述第一载流子注入层部分和所述第二载流子注入层部分间隔。
  7. 如权利要求1-6任一所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第二导电层的厚度与所述间隔体的厚度的比值范围为0.5-2。
  8. 如权利要求1-7任一所述的显示基板，其中，所述间隔体包括抗反射涂层，所述抗反射涂层包括抗反射有机材料。
  9. 如权利要求1-8任一所述的显示基板，其中，所述间隔体的材料为负性光刻胶材料或无机绝缘材料。
  10. 如权利要求1-9任一所述的显示基板，其中，所述载流子注入层还包括第三载流子注入层部分，所述第三载流子注入层部分位于所述间隔体和所述第二导电层之间，且分别与所述第一载流子注入层部分和所述第二载流子注入层部分间隔。
  11. 如权利要求1-10任一所述的显示基板，其中，所述有机功能层还包括电荷生成层，所述电荷生成层包括分别位于所述第一子像素区和所述第二子像素区的第一电荷生成层部分和第二电荷生成层部分，
    所述间隔体还将所述第一电荷生成层部分和所述第二电荷生成层部分间隔。
  12. 如权利要求1-11任一所述的显示基板，其中，所述第一发光元件和所述第二发光元件分别配置为发白光。
  13. 如权利要求1-12任一所述的显示基板，其中，所述有机功能层包括多个发光层，所述多个发光层在垂直于所述衬底基板的方向上堆叠。
  14. 如权利要求13所述的显示基板，其中，所述多个发光层中的至少两个彼此串联，所述电荷生成层位于所述至少两个发光层中相邻两个发光层之间。
  15. 如权利要求14所述的显示基板，其中，所述多个发光层包括红绿发光层和蓝光层，所述红绿发光层与所述蓝光层彼此串联，所述连接层位于所述红绿发光层和所述蓝光层之间。
  16. 如权利要求15所述的显示基板，其中，所述红绿发光层包括相邻设置的红光层和绿光层，所述红光层更靠近所述第一导电层。
  17. 如权利要求1-16任一所述的显示基板，还包括位于第三子像素区的第三发光元件，其中，所述第一发光元件、所述第二发光元件和所述第三发光元件构成一个像素单元。
  18. 如权利要求1-17任一所述的显示基板，还包括彩膜层，其中，所述彩膜层位于所述第一发光元件和所述第二发光元件远离所述衬底基板的一侧。
  19. 一种显示基板的制作方法，所述显示基板具有相邻的第一子像素区和第二子像素区，所述制作方法包括：
    提供衬底基板；
    形成驱动电路；
    在所述衬底基板上依次形成第一导电层、有机功能层和第二导电层，其中，所述第一导电层包括分别位于所述第一子像素区和所述第二子像素区的第一电极和第二电极，所述有机功能层包括载流子注入层，所述载流子注入层包括分别位于所述第一子像素区和所述第二子像素区的第一载流子注入层部分和第二载流子注入层部分，所述第二导电层包括分别位于所述第一子像素区和所述第二子像素区的第三电极和第四电极，所述第一电极、所述第一载流子注入层部分和所述第三电极构成第一发光元件，所述第二电极、所述第二载流子注入层部分和所述第四电极构成第二发光元件，在所述第一发光元件和所述第二发光元件之间形成间隔体，
    其中，所述驱动电路与所述第一发光元件和所述第二发光元件电连接，且配置为驱动所述第一发光元件和所述第二发光元件，
    所述驱动电路包括晶体管，所述晶体管包括半导体层，所述半导体层位于所述衬底基板内部，
    所述间隔体将所述第一载流子注入层部分和所述第二载流子注入层部分断开。
  20. 如权利要求19所述的制作方法，其中，所述间隔体在与所述第一载流子注入层部分和所述第二载流子注入层部分相邻的侧面形成有凹入部分。
  21. 如权利要求19或20所述的制作方法，其中，在所述第一子像 素区和所述第二子像素区之间形成间隔体包括：
    形成抗反射材料层，并在所述抗反射材料层上形成光刻胶层，
    对所述光刻胶层进行曝光，
    将曝光后的光刻胶层使用显影液显影以得到光刻胶图案，且通过所述光刻胶图案使用所述显影液刻蚀所述抗反射材料层，形成所述间隔体。
  22. 如权利要求21所述的制作方法，其中，所述抗反射材料层形成于所述第一电极和所述第二电极上。
  23. 如权利要求21所述的制作方法，其中，所述第一导电层形成于所述光刻胶图案上，对所述光刻胶图案进行剥离工艺形成所述第一电极和所述第二电极。
  24. 如权利要求21-23任一所述的制作方法，其中，
    所述有机功能层形成于所述间隔体上，
    所述载流子注入层在所述间隔体处断开，从而形成所述第一载流子注入层部分和所述第二载流子注入层部分。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114628449A (zh) * 2021-11-30 2022-06-14 京东方科技集团股份有限公司 显示基板及其制作方法、以及显示装置
CN115516641A (zh) * 2021-11-30 2022-12-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11967274B2 (en) * 2020-10-30 2024-04-23 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, display panel, and display device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130087770A1 (en) * 2011-10-06 2013-04-11 Samsung Mobile Display Co., Ltd. Organic Light Emitting Display Device
CN104617226A (zh) * 2015-02-28 2015-05-13 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置及显示补偿方法
CN106158914A (zh) * 2016-07-29 2016-11-23 京东方科技集团股份有限公司 Oled阵列基板及其制作方法、oled显示面板
CN107425131A (zh) * 2017-09-13 2017-12-01 京东方科技集团股份有限公司 一种woled器件及其制作方法
CN107689385A (zh) * 2017-03-20 2018-02-13 广东聚华印刷显示技术有限公司 顶发射型电致发光显示器件及其制作方法
CN107978618A (zh) * 2016-10-24 2018-05-01 上海和辉光电有限公司 一种显示面板、显示装置及显示面板制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012186158A (ja) * 2011-02-14 2012-09-27 Semiconductor Energy Lab Co Ltd 照明装置及び発光装置の作製方法及び製造装置
JP6076683B2 (ja) * 2012-10-17 2017-02-08 株式会社半導体エネルギー研究所 発光装置
CN104882468B (zh) * 2015-06-09 2017-12-15 京东方科技集团股份有限公司 有机电致发光显示基板及其制作方法、显示装置
CN107369702B (zh) 2017-08-16 2020-03-17 武汉华星光电半导体显示技术有限公司 一种oled显示面板及其制作方法
JP6789196B2 (ja) * 2017-09-08 2020-11-25 株式会社Ｊｏｌｅｄ 有機ｅｌ表示パネル及び有機ｅｌ表示パネルの製造方法
FR3079909B1 (fr) 2018-04-05 2022-10-14 Microoled Dispositif electroluminescent a resolution et fiabilite ameliorees

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130087770A1 (en) * 2011-10-06 2013-04-11 Samsung Mobile Display Co., Ltd. Organic Light Emitting Display Device
CN104617226A (zh) * 2015-02-28 2015-05-13 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置及显示补偿方法
CN106158914A (zh) * 2016-07-29 2016-11-23 京东方科技集团股份有限公司 Oled阵列基板及其制作方法、oled显示面板
CN107978618A (zh) * 2016-10-24 2018-05-01 上海和辉光电有限公司 一种显示面板、显示装置及显示面板制作方法
CN107689385A (zh) * 2017-03-20 2018-02-13 广东聚华印刷显示技术有限公司 顶发射型电致发光显示器件及其制作方法
CN107425131A (zh) * 2017-09-13 2017-12-01 京东方科技集团股份有限公司 一种woled器件及其制作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4020609A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114628449A (zh) * 2021-11-30 2022-06-14 京东方科技集团股份有限公司 显示基板及其制作方法、以及显示装置
CN115516641A (zh) * 2021-11-30 2022-12-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN114628449B (zh) * 2021-11-30 2023-08-29 京东方科技集团股份有限公司 显示基板及其制作方法、以及显示装置
CN115516641B (zh) * 2021-11-30 2024-04-05 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

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