WO2021033269A1 - Semiconductor package - Google Patents

Semiconductor package Download PDF

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Publication number
WO2021033269A1
WO2021033269A1 PCT/JP2019/032474 JP2019032474W WO2021033269A1 WO 2021033269 A1 WO2021033269 A1 WO 2021033269A1 JP 2019032474 W JP2019032474 W JP 2019032474W WO 2021033269 A1 WO2021033269 A1 WO 2021033269A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
sealing metal
semiconductor substrate
wiring
width
Prior art date
Application number
PCT/JP2019/032474
Other languages
French (fr)
Japanese (ja)
Inventor
倫宏 前川
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US17/600,786 priority Critical patent/US20220181220A1/en
Priority to JP2021541388A priority patent/JP7176641B2/en
Priority to EP19942492.0A priority patent/EP4020541A4/en
Priority to CN201980099340.5A priority patent/CN114270497A/en
Priority to PCT/JP2019/032474 priority patent/WO2021033269A1/en
Publication of WO2021033269A1 publication Critical patent/WO2021033269A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/16315—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/164—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Definitions

  • the present invention relates to a semiconductor package.
  • a semiconductor package has been proposed in which a lid is bonded to a semiconductor substrate via a sealing metal layer and a device formed on the semiconductor substrate is vacuum-sealed (see, for example, Patent Document 1).
  • the material of the semiconductor substrate is Si or the like, and there is a difference in physical property values such as the coefficient of linear expansion or Young's modulus from the material of the encapsulating metal layer. Therefore, there is a problem that stress is generated, the semiconductor substrate is broken, and the heat cycle resistance is lowered.
  • the present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor package capable of improving the heat cycle withstand capability.
  • the semiconductor package according to the present invention includes a semiconductor substrate, a device formed on the main surface of the semiconductor substrate, a passivation film covering the main surface, and metallizing formed on the passivation film so as to surround the device.
  • a soft dummy wiring is formed at least between the outer portion of the corner portion of the sealing metal layer and the semiconductor substrate. Since the stress transfer from the sealing metal layer to the semiconductor substrate can be suppressed by this dummy wiring, it is possible to prevent the semiconductor substrate from breaking and improve the heat cycle resistance.
  • FIG. 8 is an enlarged cross-sectional view of the outer peripheral portion of the sealing metal layer crossed by the wiring of FIG. It is a figure which shows the strip-shaped model used for the stress simulation.
  • FIG. 8 is a cross-sectional view taken along the line VII-VIII of FIG.
  • FIG. 1 is a plan view showing a semiconductor package according to the first embodiment.
  • FIG. 2 is a cross-sectional view taken along the line I-II of FIG.
  • FIG. 3 is a cross-sectional view taken along the line III-IV of FIG.
  • the device 2, the wiring 3, and the pad 4 are formed on the main surface of the semiconductor substrate 1 made of Si.
  • the device 2 includes, for example, a sensor such as an image sensor, a circuit, and the like.
  • the pad 4 is connected to the device 2 via the wiring 3.
  • a passivation film 5 such as SiN is formed on the semiconductor substrate 1 so as to cover the device 2, the wiring 3, and the pad 4.
  • the passivation film 5 on the device 2 may be partially or wholly processed.
  • the device 2 includes an image sensor, it may be made into an inner lens by performing partial processing, or it may be made into a thin film to increase the transmittance.
  • the metallized pattern 6 is formed on the passivation film 5 so as to surround the device 2 in a plan view.
  • the sealing metal layer 7 is formed on the metallized pattern 6.
  • a metallize pattern 9 is formed on the lower surface of the lid 8 at a position corresponding to the metallize pattern 6 on the semiconductor substrate 1 side.
  • the metallized pattern 9 of the lid 8 is joined to the metallized pattern 6 on the semiconductor substrate 1 side via the sealing metal layer 7, and the device 2 is vacuum-sealed.
  • the metallizing pattern 7 of the sealing metal layer 7 and the metallizing pattern 9 of the lid 8 are superposed on the metallizing pattern 6 and placed in a vacuum heating device to create a vacuum state, and the sealing metal layer 7 is heated and melted for joining.
  • the hollow portion surrounded by the semiconductor substrate 1, the lid 8, and the sealing metal layer 7 is kept in a vacuum state.
  • the width of the sealing metal layer 7 is narrowed, the gap generated in the sealing metal layer 7 and the influence of stress generated by the difference between the internal pressure and the external pressure cannot be withstood, and the possibility of vacuum breakage increases. Therefore, it is necessary to secure a certain width or more of the width of the sealing metal layer 7.
  • the pad 4 is formed on the outside of the hollow portion and is electrically connected to a wiring board or the like (not shown).
  • a gas adsorbent (getter) or the like may be provided in the hollow portion in order to maintain the internal vacuum.
  • an antireflection film may be provided on the lid 8 in order to improve the transmittance of infrared rays. Further, the effect of deterioration of the degree of vacuum due to gas release from the surface of the semiconductor substrate 1 may be reduced by etching the lid 8 to secure a large vacuum holding volume. Further, when the device 2 includes an image sensor, the lid 8 is provided with an uneven structure having a wavelength equal to or lower than the detection wavelength, so that the refractive indexes of the atmosphere, the lid 8 and the vacuum portion are apparently modulated stepwise, and as a result, the transmittance is increased. Can be improved.
  • Metallized patterns 6 and 9 are laminates in which, for example, Ti, Cu, Ni, Au, and Pd are deposited in an arbitrary order, and are formed by a sputtering method or a plating method. The material or forming method is not limited to this and can be appropriately selected.
  • the sealing metal layer 7 is made of, for example, a solder such as SnAgCu or AuSn. The material of the sealing metal layer 7 is not limited to this, and a material suitable for joining with the metallized patterns 6 and 9 can be appropriately selected.
  • the metallized patterns 6 and 9 and the encapsulating metal layer 7 have a square frame shape in a plan view seen from a direction perpendicular to the main surface of the semiconductor substrate 1. Therefore, the sealing metal layer 7 has four corners 10 in a plan view.
  • a dummy wiring 11 that is not electrically connected to the device 2 is formed between the outer portion of the corner portion 10 of the sealing metal layer 7 and the semiconductor substrate 1.
  • the wiring 3 and the dummy wiring 11 are made of, for example, AlSi, AlSiCu, or the like, and have a lower elastic modulus than the metallized patterns 6 and 9, that is, are soft.
  • the soft dummy wiring 11 is formed at least between the outer portion of the corner portion 10 of the sealing metal layer 7 and the semiconductor substrate 1.
  • the stress transmission from the sealing metal layer 7 to the semiconductor substrate 1 can be suppressed by the dummy wiring 11, it is possible to prevent the semiconductor substrate 1 from breaking and improve the heat cycle resistance.
  • a soft metal such as Al
  • the difference in stress between the metallized patterns 6 and 9 is large, there is a high possibility that another mode defect such as delamination or breakage will occur, which is not realistic.
  • the wiring 3 is connected to the pad 4 and the device 2 by bypassing the corner portion 10 of the sealing metal layer 7.
  • the wiring 3 is connected to the pad 4 and the device 2 by bypassing the corner portion 10 of the sealing metal layer 7.
  • the material of the lid 8 is Si, which is the same as that of the semiconductor substrate 1, there is no difference in physical property values such as the coefficient of linear expansion between the lid 8 and the semiconductor substrate 1, so that the physical property values with the sealing metal layer 7 are simply obtained. Only the stress due to the difference between the two needs to be considered.
  • the material of the lid 8 is not limited to Si, and may be glass, Ge, or the like. When the material of the semiconductor substrate 1 and the material of the lid 8 are different in this way, the stress increases due to the difference in the physical property values of the two, so that the suppression of stress transmission by the dummy wiring 11 is particularly effective.
  • FIG. 4 is a cross-sectional view showing the semiconductor package according to the second embodiment.
  • the dummy wiring 11 is formed on the semiconductor substrate 1 in the same layer as the wiring 3, and both have the same thickness and material.
  • the thickness of the passivation film 5 is generally set to 0.5 ⁇ m to several ⁇ m, it is very thin as compared with the thickness of the sealing metal layer 7. Therefore, the stress transmission suppressing effect of the first embodiment can be obtained even with the configuration of the present embodiment. Other configurations and effects are the same as in the first embodiment.
  • FIG. 5 is a plan view showing the semiconductor package according to the third embodiment.
  • FIG. 6 is a cross-sectional view taken along the line V-VI of FIG.
  • the stress increases not only in the outer portion of the corner portion 10 of the sealing metal layer 7 but also in the inner portion. Therefore, in the present embodiment, the dummy wiring 11 is also formed between the inner portion of the corner portion 10 of the sealing metal layer 7 and the semiconductor substrate 1. Since the stress transmission from the sealing metal layer 7 to the semiconductor substrate 1 can be further suppressed by the dummy wiring 11, the heat cycle resistance can be further improved.
  • Other configurations and effects are the same as in the first embodiment.
  • FIG. 7 is a cross-sectional view showing the semiconductor package according to the fourth embodiment.
  • the dummy wiring 11 is also formed between the outer portion of the corner portion 10 of the sealing metal layer 7 and the lid 8. Since the stress transmission from the sealing metal layer 7 to the lid 8 can be suppressed by the dummy wiring 11, the stress resistance of the lid 8 is strengthened, and the reliability of the degree of vacuum can be ensured. Other configurations and effects are the same as in the first embodiment.
  • a dummy wiring 11 may be formed between the inner portion of the corner portion 10 of the sealing metal layer 7 and the lid 8.
  • FIG. 8 is a plan view showing the semiconductor package according to the fifth embodiment. Similar to the first embodiment, the dummy wiring 11 is formed between the sealing metal layer 7 and the semiconductor substrate 1. However, in the present embodiment, the dummy wiring 11 is provided not only along the corner portion 10 of the sealing metal layer 7 but also along the outer peripheral portion and the inner peripheral portion. There is a place where the dummy wiring 11 is not provided on one side of the sealing metal layer 7 having a square frame shape in a plan view. At this point, the wiring 3 crosses the sealing metal layer 7 to connect the device 2 in the package and the external pad 4.
  • FIG. 9 is an enlarged cross-sectional view of the outer peripheral portion of the sealing metal layer crossed by the wiring of FIG.
  • a region 12 in the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7 in which neither the wiring 3 nor the dummy wiring 11 exists.
  • stress is generated due to the difference in physical property values between the semiconductor substrate 1 and the sealing metal layer 7.
  • a stress relaxation region 13 in which the stress is relaxed.
  • the stress P generated in the sealing metal layer 7 is the vector sum of the stress Ph applied in the thickness direction and the stress Pw applied in the width direction of the sealing metal layer 7. It becomes. Assuming that the width of the region 12 in which neither the wiring 3 nor the dummy wiring 11 exists is W and the thickness of the sealing metal layer 7 is H, the stress Ph is proportional to H 3 ⁇ W and the stress Pw is proportional to W 3 ⁇ H. Therefore, the stress can be reduced by reducing the width W of the region 12.
  • the semiconductor substrate 1 is a Si wafer having a plane orientation (100), (110) or (111).
  • the semiconductor substrate 1 has a crystal structure having cleavage planes in the vertical direction and the 45 ° direction with respect to the main plane. Therefore, the semiconductor substrate 1 is liable to break in the vertical direction and the 45 ° direction. Therefore, the fracture can be reduced by shifting the stress vector from the 45 ° direction.
  • the stress in the vertical direction causes surface peeling, but since the peeling resistance of the substrate is generally higher than the breaking resistance, the stress in the vertical direction does not matter much.
  • FIG. 10 is a diagram showing a strip-shaped model used for stress simulation.
  • the left figure shows the case where there is no wiring 3 which is a stress relaxation layer, and the right figure shows the case where there is wiring 3.
  • the width of the region is 150 ⁇ m
  • the thickness of the sealing metal layer 7 is 90 ⁇ m
  • the thickness of the wiring 3 is 0.8 ⁇ m. Since the wiring 3 is deformed following the stress of the sealing metal layer 7 and the amount of strain in the sealing metal layer 7 is relaxed, the stress in the lateral direction is reduced.
  • CASE 1 indicates a case where there is no wiring 3.
  • CASE 2 indicates a case where the wiring 3 is provided in all the width directions.
  • CASE 3 indicates a case where the wiring 3 is in the range of 20 ⁇ m in the width of 150 ⁇ m.
  • the stress Ph1 in the thickness direction is 360 Mpa
  • the stress Pw1 in the width direction is about 1050 Mpa. Since the thickness of the wiring 3 is very small compared to the width, the stress Ph2 in the thickness direction is about 360 MPa even in the CASE 2 in which the wiring 3 exists, which is almost the same as the CASE 1. On the other hand, the stress Pw2 in the width direction is greatly reduced to 185 MPa. Therefore, in order to prevent the semiconductor substrate 1 from breaking, it is not necessary to consider the stress relaxation region 13 in which the wiring 3 or the dummy wiring 11 exists, and the W / H ratio of the region 12 in which the wiring 3 and the dummy wiring 11 do not exist is controlled. do it.
  • FIG. 11 is a diagram showing the relationship between the W / H ratio and the stress vector angle.
  • FIG. 12 is an enlarged view of a part of FIG.
  • the stress vector angle indicates the angle of the stress vector with respect to the main surface of the semiconductor substrate 1. It can be seen that the stress vector angle can be set to 70 ° or more when W / H ⁇ 0.6. That is, the stress vector can be shifted from the 45 ° direction where it is easy to break.
  • an example in which Si wafers having plane orientations (100), (110), or (111) are used is used, but the plane orientations are different, that is, the cleavage plane is 45 °, such as a SiC wafer or a GaN wafer. You may use a substrate that is not.
  • the same effect can be obtained by shifting the stress vector angle from the cleavage plane angle. Even when these substrates are used, the peeling resistance of the substrate is higher than the breaking resistance as described above, so that the stress in the vertical direction does not matter much. Therefore, it is preferable to keep the vector angle at 70 ° or more in order to improve the crack resistance.
  • FIG. 13 is a diagram showing the relationship between the W / H ratio and the stress ratio.
  • FIG. 14 is an enlarged view of a part of FIG.
  • the stress ratio is the magnitude of stress standardized based on the case where the W / H ratio is 1. It can be seen that the stress can be reduced to near the lower limit by setting W / H ⁇ 0.6.
  • the width W of the region 12 in which the wiring 3 and the dummy wiring 11 do not exist in the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7 is set to the thickness H of the sealing metal layer 7. It shall be 0.6 times or less (W / H ⁇ 0.6). Thereby, the breakage of the semiconductor substrate 1 can be reduced.
  • the dummy wiring 11 may be provided so as to satisfy the above relational expression only at the point where the stress is particularly concentrated.
  • the thickness H of the sealing metal layer 7 is set to about 40 to 100 ⁇ m. It is very difficult to deposit the sealing metal layer 7 having a thickness larger than this by a method such as vapor deposition, sputtering, or dispensing, and the cost increases. Therefore, it is necessary to set the width W of the region 12 to 25 to 60 ⁇ m.
  • FIG. 15 is a plan view showing the semiconductor package according to the sixth embodiment.
  • Wiring 3 extends along the outer circumference or the inner circumference of the sealing metal layer 7 at the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7. Therefore, when the width is measured along the outer circumference or the inner circumference of the sealing metal layer 7, the width of the wiring 3 in the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7 is the central portion of the sealing metal layer 7. It is wider than the width of the wiring 3.
  • the width of the wiring 3 is generally 100 ⁇ m or less.
  • FIG. 16 is a plan view showing the semiconductor package according to the seventh embodiment.
  • FIG. 17 is an enlarged perspective view of the region A of FIG.
  • the width of the region 12 in which the plurality of wirings 3 do not exist is the first width W1 along the outer circumference or the inner circumference of the sealing metal layer 7, and the second width in the direction perpendicular to the outer circumference or the inner circumference of the sealing metal layer 7. Width W2 and. Both the first width W1 and the second width W2 are 0.6 times or less the thickness H of the sealing metal layer 7 (W1, W2 ⁇ 0.6 ⁇ H). As a result, the stress can be relaxed as compared with the case where only the first width W1 is 0.6 times or less the thickness H of the sealing metal layer 7.
  • FIG. 18 is a plan view showing the semiconductor package according to the eighth embodiment.
  • the wiring 3 and the dummy wiring 11 are arranged in parallel with each other along the outer circumference of the sealing metal layer 7 at the outer peripheral portion of the sealing metal layer 7.
  • FIG. 19 is a cross-sectional view taken along the line VII-VIII of FIG. The arrows in the figure indicate the tensile stress vector.
  • the stress vector is dispersed and the stress is relaxed by the stepped structure of the wiring 3 and the dummy wiring 11 arranged in parallel. Therefore, it is possible to prevent the semiconductor substrate 1 from breaking and improve the heat cycle resistance. Further, since the wettability of the sealing metal layer 7 at the time of thermal melting can be improved, the occurrence of leakage between the hollow portion and the outside can be suppressed. Further, it is possible to prevent the sealing metal layer 7 from protruding during thermal melting.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A device (2) is formed on the main surface of a semiconductor substrate (1). A passivation film (5) covers the main surface. A metallized pattern (6) is formed on the passivation film (5) so as to surround the device (2). A sealing metal layer (7) having corners (10) in a plan view is formed on the metallized pattern (6). A lid (8) is joined to the metallized pattern (6) with the sealing metal layer (7) therebetween so as to vacuum-seal the device (2). Dummy wiring (11) more flexible than the metallized pattern (6) and not electrically connected to the device (2) is formed at least between the semiconductor substrate (1) and the outer parts of the corners of the sealing metal layer (7).

Description

半導体パッケージSemiconductor package
　本発明は、半導体パッケージに関する。 The present invention relates to a semiconductor package.
　半導体基板に封止金属層を介してリッドを接合して半導体基板に形成されたデバイスを真空封止した半導体パッケージが提案されている（例えば、特許文献１参照）。 A semiconductor package has been proposed in which a lid is bonded to a semiconductor substrate via a sealing metal layer and a device formed on the semiconductor substrate is vacuum-sealed (see, for example, Patent Document 1).
日本特開２０１０－２６１８０６号公報Japanese Patent Application Laid-Open No. 2010-261806
　半導体基板の材料はＳｉなどであり、封止金属層の材料とは線膨張係数又はヤング率等の物性値の違いがある。このため、応力が発生し、半導体基板が破断してヒートサイクル耐量が低下するという問題があった。 The material of the semiconductor substrate is Si or the like, and there is a difference in physical property values such as the coefficient of linear expansion or Young's modulus from the material of the encapsulating metal layer. Therefore, there is a problem that stress is generated, the semiconductor substrate is broken, and the heat cycle resistance is lowered.
　本発明は、上述のような課題を解決するためになされたもので、その目的はヒートサイクル耐量を向上することができる半導体パッケージを得るものである。 The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor package capable of improving the heat cycle withstand capability.
　本発明に係る半導体パッケージは、半導体基板と、前記半導体基板の主面に形成されたデバイスと、前記主面を覆うパッシベーション膜と、前記デバイスを囲むように前記パッシベーション膜の上に形成されたメタライズパターンと、前記メタライズパターンの上に形成され、平面視で角部を有する封止金属層と、前記封止金属層を介して前記メタライズパターンに接合され、前記デバイスを真空封止するリッドと、少なくとも前記封止金属層の前記角部の外側部分と前記半導体基板との間に形成され、前記メタライズパターンよりも柔らかく、前記デバイスに電気的に接続されていないダミー配線とを備えることを特徴とする。 The semiconductor package according to the present invention includes a semiconductor substrate, a device formed on the main surface of the semiconductor substrate, a passivation film covering the main surface, and metallizing formed on the passivation film so as to surround the device. A pattern, a sealing metal layer formed on the metallized pattern and having corners in a plan view, a lid bonded to the metallized pattern via the sealing metal layer, and vacuum-sealing the device. It is characterized by including at least a dummy wiring formed between the outer portion of the corner portion of the sealing metal layer and the semiconductor substrate, which is softer than the metallized pattern and is not electrically connected to the device. To do.
　本発明では、柔らかいダミー配線を少なくとも封止金属層の角部の外側部分と半導体基板との間に形成する。このダミー配線により封止金属層から半導体基板への応力伝達を抑制できるため、半導体基板の破断を防いでヒートサイクル耐量を向上することができる。 In the present invention, a soft dummy wiring is formed at least between the outer portion of the corner portion of the sealing metal layer and the semiconductor substrate. Since the stress transfer from the sealing metal layer to the semiconductor substrate can be suppressed by this dummy wiring, it is possible to prevent the semiconductor substrate from breaking and improve the heat cycle resistance.
実施の形態１に係る半導体パッケージを示す平面図である。It is a top view which shows the semiconductor package which concerns on Embodiment 1. FIG. 図１のＩ－ＩＩに沿った断面図である。It is sectional drawing which follows I-II of FIG. 図１のＩＩＩ－ＩＶに沿った断面図である。It is sectional drawing which follows III-IV of FIG. 実施の形態２に係る半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package which concerns on Embodiment 2. 実施の形態３に係る半導体パッケージを示す平面図である。It is a top view which shows the semiconductor package which concerns on Embodiment 3. 図５のＶ－ＶＩに沿った断面図である。FIG. 5 is a cross-sectional view taken along the line V-VI of FIG. 実施の形態４に係る半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package which concerns on Embodiment 4. 実施の形態５に係る半導体パッケージを示す平面図である。It is a top view which shows the semiconductor package which concerns on Embodiment 5. 図８の配線が横切る封止金属層の外周部を拡大した断面図である。FIG. 8 is an enlarged cross-sectional view of the outer peripheral portion of the sealing metal layer crossed by the wiring of FIG. 応力のシミュレーションに用いた短冊状モデルを示す図である。It is a figure which shows the strip-shaped model used for the stress simulation. Ｗ／Ｈ比と応力ベクトル角の関係を示す図である。It is a figure which shows the relationship between a W / H ratio and a stress vector angle. 図１１の一部を拡大した図である。It is an enlarged view of a part of FIG. Ｗ／Ｈ比と応力比の関係を示す図である。It is a figure which shows the relationship between the W / H ratio and the stress ratio. 図１３の一部を拡大した図である。It is an enlarged view of a part of FIG. 実施の形態６に係る半導体パッケージを示す平面図である。It is a top view which shows the semiconductor package which concerns on Embodiment 6. 実施の形態７に係る半導体パッケージを示す平面図である。It is a top view which shows the semiconductor package which concerns on Embodiment 7. 図１６の領域Ａを拡大した斜視図である。It is an enlarged perspective view of the area A of FIG. 実施の形態８に係る半導体パッケージを示す平面図である。It is a top view which shows the semiconductor package which concerns on Embodiment 8. 図１８のＶＩＩ－ＶＩＩＩに沿った断面図である。FIG. 8 is a cross-sectional view taken along the line VII-VIII of FIG.
　実施の形態に係る半導体パッケージについて図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。 The semiconductor package according to the embodiment will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.
実施の形態１．
　図１は、実施の形態１に係る半導体パッケージを示す平面図である。図２は図１のＩ－ＩＩに沿った断面図である。図３は図１のＩＩＩ－ＩＶに沿った断面図である。例えばＳｉからなる半導体基板１の主面にデバイス２と配線３とパッド４が形成されている。デバイス２は例えば撮像素子等のセンサ、回路等を含む。パッド４は配線３を介してデバイス２に接続されている。デバイス２、配線３、パッド４を覆うように半導体基板１の上にＳｉＮ等のパッシベーション膜５が形成されている。パッド４の上においてパッシベーション膜５に開口が形成されパッド４の上面中央部が露出している。デバイス２上のパッシベーション膜５に部分的又は全体的な加工を行ってもよい。例えば、デバイス２が撮像素子を含む場合、部分的な加工を行うことでインナーレンズ化してもよいし、透過率を高めるための薄膜化を行ってもよい。 Embodiment 1.
FIG. 1 is a plan view showing a semiconductor package according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line I-II of FIG. FIG. 3 is a cross-sectional view taken along the line III-IV of FIG. For example, the device 2, the wiring 3, and the pad 4 are formed on the main surface of the semiconductor substrate 1 made of Si. The device 2 includes, for example, a sensor such as an image sensor, a circuit, and the like. The pad 4 is connected to the device 2 via the wiring 3. A passivation film 5 such as SiN is formed on the semiconductor substrate 1 so as to cover the device 2, the wiring 3, and the pad 4. An opening is formed in the passivation film 5 on the pad 4, and the central portion of the upper surface of the pad 4 is exposed. The passivation film 5 on the device 2 may be partially or wholly processed. For example, when the device 2 includes an image sensor, it may be made into an inner lens by performing partial processing, or it may be made into a thin film to increase the transmittance.
　メタライズパターン６が平面視でデバイス２を囲むようにパッシベーション膜５の上に形成されている。封止金属層７がメタライズパターン６の上に形成されている。リッド８の下面において半導体基板１側のメタライズパターン６に対応する位置にメタライズパターン９が形成されている。リッド８のメタライズパターン９が封止金属層７を介して半導体基板１側のメタライズパターン６に接合され、デバイス２を真空封止する。例えば、メタライズパターン６の上に封止金属層７とリッド８のメタライズパターン９を重ねて真空加熱装置に入れて真空状態にし、封止金属層７を加熱溶融して接合を行う。 The metallized pattern 6 is formed on the passivation film 5 so as to surround the device 2 in a plan view. The sealing metal layer 7 is formed on the metallized pattern 6. A metallize pattern 9 is formed on the lower surface of the lid 8 at a position corresponding to the metallize pattern 6 on the semiconductor substrate 1 side. The metallized pattern 9 of the lid 8 is joined to the metallized pattern 6 on the semiconductor substrate 1 side via the sealing metal layer 7, and the device 2 is vacuum-sealed. For example, the metallizing pattern 7 of the sealing metal layer 7 and the metallizing pattern 9 of the lid 8 are superposed on the metallizing pattern 6 and placed in a vacuum heating device to create a vacuum state, and the sealing metal layer 7 is heated and melted for joining.
　半導体基板１とリッド８と封止金属層７で囲まれた中空部が真空状態に保たれている。ただし、封止金属層７の横幅を狭くすると、封止金属層７に発生する隙間、内圧と外圧の差により発生する応力の影響に耐えられず真空破れが発生する可能性が高くなる。従って、封止金属層７の横幅を一定以上は確保する必要がある。パッド４は中空部の外側に形成され、配線基板等（図示せず）と電気的に接続される。なお、内部の真空を維持するために中空部にガス吸着剤（ゲッター）等を設けてもよい。また、赤外線の透過率を向上させるためにリッド８に反射防止膜（ＡＲ）を設けてもよい。また、リッド８にエッチング処理を行って真空保持体積を大きく確保することで、半導体基板１表面からのガス放出による真空度悪化の影響を低減してもよい。また、デバイス２が撮像素子を含む場合、リッド８に検知波長以下の凹凸構造を設けることで、大気とリッド８と真空部の屈折率を見かけ上段階的に変調させ、結果的に透過率を向上させることができる。 The hollow portion surrounded by the semiconductor substrate 1, the lid 8, and the sealing metal layer 7 is kept in a vacuum state. However, if the width of the sealing metal layer 7 is narrowed, the gap generated in the sealing metal layer 7 and the influence of stress generated by the difference between the internal pressure and the external pressure cannot be withstood, and the possibility of vacuum breakage increases. Therefore, it is necessary to secure a certain width or more of the width of the sealing metal layer 7. The pad 4 is formed on the outside of the hollow portion and is electrically connected to a wiring board or the like (not shown). A gas adsorbent (getter) or the like may be provided in the hollow portion in order to maintain the internal vacuum. Further, an antireflection film (AR) may be provided on the lid 8 in order to improve the transmittance of infrared rays. Further, the effect of deterioration of the degree of vacuum due to gas release from the surface of the semiconductor substrate 1 may be reduced by etching the lid 8 to secure a large vacuum holding volume. Further, when the device 2 includes an image sensor, the lid 8 is provided with an uneven structure having a wavelength equal to or lower than the detection wavelength, so that the refractive indexes of the atmosphere, the lid 8 and the vacuum portion are apparently modulated stepwise, and as a result, the transmittance is increased. Can be improved.
　メタライズパターン６，９は例えばＴｉ、Ｃｕ、Ｎｉ、Ａｕ、Ｐｄが任意の順に堆積された積層体であり、スパッタ法又はめっき法により形成される。材料又は形成方法はこれに限らず適宜選択可能である。封止金属層７は例えばＳｎＡｇＣｕ又はＡｕＳｎ等のはんだからなる。封止金属層７の材料はこれに限らず、メタライズパターン６，９との接合に適した材料を適宜選定できる。 Metallized patterns 6 and 9 are laminates in which, for example, Ti, Cu, Ni, Au, and Pd are deposited in an arbitrary order, and are formed by a sputtering method or a plating method. The material or forming method is not limited to this and can be appropriately selected. The sealing metal layer 7 is made of, for example, a solder such as SnAgCu or AuSn. The material of the sealing metal layer 7 is not limited to this, and a material suitable for joining with the metallized patterns 6 and 9 can be appropriately selected.
　メタライズパターン６，９及び封止金属層７は、半導体基板１の主面に対して垂直方向から見た平面視で四角の枠状になっている。従って、封止金属層７は平面視で４つの角部１０を有する。デバイス２に電気的に接続されていないダミー配線１１が封止金属層７の角部１０の外側部分と半導体基板１との間に形成されている。配線３及びダミー配線１１は例えばＡｌＳｉ、ＡｌＳｉＣｕ等からなり、メタライズパターン６，９よりも弾性率が低い、つまり柔らかい。 The metallized patterns 6 and 9 and the encapsulating metal layer 7 have a square frame shape in a plan view seen from a direction perpendicular to the main surface of the semiconductor substrate 1. Therefore, the sealing metal layer 7 has four corners 10 in a plan view. A dummy wiring 11 that is not electrically connected to the device 2 is formed between the outer portion of the corner portion 10 of the sealing metal layer 7 and the semiconductor substrate 1. The wiring 3 and the dummy wiring 11 are made of, for example, AlSi, AlSiCu, or the like, and have a lower elastic modulus than the metallized patterns 6 and 9, that is, are soft.
　半導体基板１の材料と封止金属層７の材料との線膨張係数又はヤング率等の物性値の違いにより応力が発生する。この応力は特に封止金属層７の角部１０の外側部分に集中する。封止金属層７の形状を完全な円形にしない限りは、この応力の集中を無くすことはできない。例えば封止金属層７の四角枠形状の角を落とすか又はRを付けたとしても応力の集中を完全に無くすことはできない。そこで、本実施の形態では、柔らかいダミー配線１１を少なくとも封止金属層７の角部１０の外側部分と半導体基板１との間に形成する。このダミー配線１１により封止金属層７から半導体基板１への応力伝達を抑制できるため、半導体基板１の破断を防いでヒートサイクル耐量を向上することができる。ここで、メタライズパターン６，９としてＡｌ等の柔らかい金属を厚く堆積することで応力伝達を抑制することは原理的に可能ではある。しかし、その場合メタライズパターン６，９の層間応力差が大きく発生することで、層間剥離又は層間破断等の別モード不良が発生する可能性が高く、現実的ではない。 Stress is generated due to the difference in physical property values such as the coefficient of linear expansion or Young's modulus between the material of the semiconductor substrate 1 and the material of the sealing metal layer 7. This stress is particularly concentrated on the outer portion of the corner portion 10 of the sealing metal layer 7. This stress concentration cannot be eliminated unless the shape of the sealing metal layer 7 is completely circular. For example, even if the corners of the square frame shape of the sealing metal layer 7 are dropped or R is added, the stress concentration cannot be completely eliminated. Therefore, in the present embodiment, the soft dummy wiring 11 is formed at least between the outer portion of the corner portion 10 of the sealing metal layer 7 and the semiconductor substrate 1. Since the stress transmission from the sealing metal layer 7 to the semiconductor substrate 1 can be suppressed by the dummy wiring 11, it is possible to prevent the semiconductor substrate 1 from breaking and improve the heat cycle resistance. Here, in principle, it is possible to suppress stress transmission by thickly depositing a soft metal such as Al as the metallize patterns 6 and 9. However, in that case, since the difference in stress between the metallized patterns 6 and 9 is large, there is a high possibility that another mode defect such as delamination or breakage will occur, which is not realistic.
　また、配線３は封止金属層７の角部１０を迂回してパッド４とデバイス２に接続されている。このように応力が集中する封止金属層７の角部１０を避けるように配線３を配置することにより、配線３の断線による不具合を防ぐことができる。 Further, the wiring 3 is connected to the pad 4 and the device 2 by bypassing the corner portion 10 of the sealing metal layer 7. By arranging the wiring 3 so as to avoid the corners 10 of the sealing metal layer 7 where stress is concentrated in this way, it is possible to prevent problems due to disconnection of the wiring 3.
　また、リッド８の材料が半導体基板１と同じＳｉの場合は、リッド８と半導体基板１との間に線膨張係数等の物性値の差は無いため、単に封止金属層７との物性値の差による応力のみを考慮すればよい。ただし、リッド８の材料はＳｉに限らず、ガラス、Ｇｅ等でもよい。このように半導体基板１の材料とリッド８の材料が異なる場合には両者の物性値の差により応力が増加するため、ダミー配線１１による応力伝達の抑制が特に有効となる。 Further, when the material of the lid 8 is Si, which is the same as that of the semiconductor substrate 1, there is no difference in physical property values such as the coefficient of linear expansion between the lid 8 and the semiconductor substrate 1, so that the physical property values with the sealing metal layer 7 are simply obtained. Only the stress due to the difference between the two needs to be considered. However, the material of the lid 8 is not limited to Si, and may be glass, Ge, or the like. When the material of the semiconductor substrate 1 and the material of the lid 8 are different in this way, the stress increases due to the difference in the physical property values of the two, so that the suppression of stress transmission by the dummy wiring 11 is particularly effective.
実施の形態２．
　図４は、実施の形態２に係る半導体パッケージを示す断面図である。本実施の形態では、ダミー配線１１は半導体基板１の上において配線３と同層で形成され、両者は厚みと材料が同じである。この場合にはダミー配線１１と配線３を同時に形成できるため、ダミー配線１１の形成のために製造工程を追加する必要が無い。また、パッシベーション膜５の厚みは一般的に０．５μｍ～数μｍで設定されるため、封止金属層７の厚みと比べて非常に薄い。従って、本実施の形態の構成でも実施の形態１の応力伝達抑制効果を得ることができる。その他の構成及び効果は実施の形態１と同様である。 Embodiment 2.
FIG. 4 is a cross-sectional view showing the semiconductor package according to the second embodiment. In the present embodiment, the dummy wiring 11 is formed on the semiconductor substrate 1 in the same layer as the wiring 3, and both have the same thickness and material. In this case, since the dummy wiring 11 and the wiring 3 can be formed at the same time, it is not necessary to add a manufacturing process for forming the dummy wiring 11. Further, since the thickness of the passivation film 5 is generally set to 0.5 μm to several μm, it is very thin as compared with the thickness of the sealing metal layer 7. Therefore, the stress transmission suppressing effect of the first embodiment can be obtained even with the configuration of the present embodiment. Other configurations and effects are the same as in the first embodiment.
実施の形態３．
　図５は、実施の形態３に係る半導体パッケージを示す平面図である。図６は図５のＶ－ＶＩに沿った断面図である。応力は封止金属層７の角部１０の外側部分だけではなく、内側部分でも大きくなる。そこで、本実施の形態では、封止金属層７の角部１０の内側部分と半導体基板１との間にもダミー配線１１を形成する。このダミー配線１１により封止金属層７から半導体基板１への応力伝達を更に抑制できるため、ヒートサイクル耐量を更に向上することができる。その他の構成及び効果は実施の形態１と同様である。 Embodiment 3.
FIG. 5 is a plan view showing the semiconductor package according to the third embodiment. FIG. 6 is a cross-sectional view taken along the line V-VI of FIG. The stress increases not only in the outer portion of the corner portion 10 of the sealing metal layer 7 but also in the inner portion. Therefore, in the present embodiment, the dummy wiring 11 is also formed between the inner portion of the corner portion 10 of the sealing metal layer 7 and the semiconductor substrate 1. Since the stress transmission from the sealing metal layer 7 to the semiconductor substrate 1 can be further suppressed by the dummy wiring 11, the heat cycle resistance can be further improved. Other configurations and effects are the same as in the first embodiment.
実施の形態４．
　図７は、実施の形態４に係る半導体パッケージを示す断面図である。応力によりリッド８が破断するとパッケージ内の真空度が劣化する。そこで、本実施の形態では、封止金属層７の角部１０の外側部分とリッド８との間にもダミー配線１１を形成する。このダミー配線１１により封止金属層７からリッド８への応力伝達を抑制できるため、リッド８の応力耐性が強化され、真空度の信頼性を確保することができる。その他の構成及び効果は実施の形態１と同様である。なお、封止金属層７の角部１０の内側部分とリッド８との間にダミー配線１１を形成してもよい。 Embodiment 4.
FIG. 7 is a cross-sectional view showing the semiconductor package according to the fourth embodiment. When the lid 8 breaks due to stress, the degree of vacuum inside the package deteriorates. Therefore, in the present embodiment, the dummy wiring 11 is also formed between the outer portion of the corner portion 10 of the sealing metal layer 7 and the lid 8. Since the stress transmission from the sealing metal layer 7 to the lid 8 can be suppressed by the dummy wiring 11, the stress resistance of the lid 8 is strengthened, and the reliability of the degree of vacuum can be ensured. Other configurations and effects are the same as in the first embodiment. A dummy wiring 11 may be formed between the inner portion of the corner portion 10 of the sealing metal layer 7 and the lid 8.
実施の形態５．
　図８は、実施の形態５に係る半導体パッケージを示す平面図である。実施の形態１等と同様にダミー配線１１が封止金属層７と半導体基板１の間に形成されている。ただし、本実施の形態では、ダミー配線１１は封止金属層７の角部１０だけでなく、外周部及び内周部に沿って設けられている。平面視で四角い枠状の封止金属層７の一辺にダミー配線１１が設けられていない箇所がある。この箇所において、配線３が封止金属層７を横切ってパッケージ内のデバイス２と外部のパッド４を接続している。 Embodiment 5.
FIG. 8 is a plan view showing the semiconductor package according to the fifth embodiment. Similar to the first embodiment, the dummy wiring 11 is formed between the sealing metal layer 7 and the semiconductor substrate 1. However, in the present embodiment, the dummy wiring 11 is provided not only along the corner portion 10 of the sealing metal layer 7 but also along the outer peripheral portion and the inner peripheral portion. There is a place where the dummy wiring 11 is not provided on one side of the sealing metal layer 7 having a square frame shape in a plan view. At this point, the wiring 3 crosses the sealing metal layer 7 to connect the device 2 in the package and the external pad 4.
　図９は、図８の配線が横切る封止金属層の外周部を拡大した断面図である。封止金属層７の外周部及び内周部において配線３もダミー配線１１も存在しない領域１２がある。この領域１２において、半導体基板１と封止金属層７の物性値の違いによる応力が発生する。一方、配線３又はダミー配線１１の上方は、応力が緩和される応力緩和領域１３となる。 FIG. 9 is an enlarged cross-sectional view of the outer peripheral portion of the sealing metal layer crossed by the wiring of FIG. There is a region 12 in the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7 in which neither the wiring 3 nor the dummy wiring 11 exists. In this region 12, stress is generated due to the difference in physical property values between the semiconductor substrate 1 and the sealing metal layer 7. On the other hand, above the wiring 3 or the dummy wiring 11, there is a stress relaxation region 13 in which the stress is relaxed.
　封止金属層７を一つの部材としてマクロ的にとらえた場合、封止金属層７に発生する応力Ｐは封止金属層７の厚み方向にかかる応力Ｐｈと幅方向にかかる応力Ｐｗのベクトル和となる。配線３もダミー配線１１も存在しない領域１２の幅をＷ、封止金属層７の厚みをＨとすると、応力ＰｈはＨ３×Ｗに比例し、応力ＰｗはＷ３×Ｈに比例する。従って、領域１２の幅Ｗを低減することで応力を低減することができる。 When the sealing metal layer 7 is macroscopically regarded as one member, the stress P generated in the sealing metal layer 7 is the vector sum of the stress Ph applied in the thickness direction and the stress Pw applied in the width direction of the sealing metal layer 7. It becomes. Assuming that the width of the region 12 in which neither the wiring 3 nor the dummy wiring 11 exists is W and the thickness of the sealing metal layer 7 is H, the stress Ph is proportional to H 3 × W and the stress Pw is proportional to W 3 × H. Therefore, the stress can be reduced by reducing the width W of the region 12.
　また、半導体基板１は面方位（１００）、（１１０）又は（１１１）のＳｉウエハである。この場合、半導体基板１は、主面に対して垂直方向と４５°方向に劈開面がある結晶構造を有する。このため、半導体基板１は垂直方向と４５°方向に破断しやすい。従って、応力ベクトルを４５°方向からずらせば破断を低減することができる。なお、垂直方向の応力は面剥離を発生させるが、一般的に基板の剥離耐量は破断耐量よりも高いため、垂直方向の応力はあまり問題とならない。 Further, the semiconductor substrate 1 is a Si wafer having a plane orientation (100), (110) or (111). In this case, the semiconductor substrate 1 has a crystal structure having cleavage planes in the vertical direction and the 45 ° direction with respect to the main plane. Therefore, the semiconductor substrate 1 is liable to break in the vertical direction and the 45 ° direction. Therefore, the fracture can be reduced by shifting the stress vector from the 45 ° direction. The stress in the vertical direction causes surface peeling, but since the peeling resistance of the substrate is generally higher than the breaking resistance, the stress in the vertical direction does not matter much.
　ここで、応力緩和領域１３の効果を定量的に示す。図１０は、応力のシミュレーションに用いた短冊状モデルを示す図である。左図は応力緩和層である配線３が無い場合を示し、右図は配線３が有る場合を示す。領域の幅は１５０μｍ、封止金属層７の厚みは９０μｍ、配線３の厚みは０．８μｍである。配線３が封止金属層７の応力に追従して変形して封止金属層７内の歪量が緩和されるため、横方向の応力が低減される。 Here, the effect of the stress relaxation region 13 is quantitatively shown. FIG. 10 is a diagram showing a strip-shaped model used for stress simulation. The left figure shows the case where there is no wiring 3 which is a stress relaxation layer, and the right figure shows the case where there is wiring 3. The width of the region is 150 μm, the thickness of the sealing metal layer 7 is 90 μm, and the thickness of the wiring 3 is 0.8 μm. Since the wiring 3 is deformed following the stress of the sealing metal layer 7 and the amount of strain in the sealing metal layer 7 is relaxed, the stress in the lateral direction is reduced.
　以下の表にシミュレーション結果を示す。ＣＡＳＥ１は配線３が無い場合を示す。ＣＡＳＥ２は幅方向全てに配線３が有る場合を示す。ＣＡＳＥ３は幅１５０μｍ中の２０μｍの範囲に配線３が有る場合を示す。
Figure JPOXMLDOC01-appb-I000001
The simulation results are shown in the table below. CASE 1 indicates a case where there is no wiring 3. CASE 2 indicates a case where the wiring 3 is provided in all the width directions. CASE 3 indicates a case where the wiring 3 is in the range of 20 μm in the width of 150 μm.
Figure JPOXMLDOC01-appb-I000001
　配線３が存在するＣＡＳＥ２では、配線３が存在しないＣＡＳＥ１に比べて配線３の上下で応力が緩和されていることが分かる。ＣＡＳＥ３では配線３の上下の応力差が大きいため、歪による断線の可能性がある。 It can be seen that in CASE 2 in which the wiring 3 is present, the stress is relaxed above and below the wiring 3 as compared with CASE 1 in which the wiring 3 is not present. In CASE3, since the stress difference between the upper and lower parts of the wiring 3 is large, there is a possibility of disconnection due to distortion.
　配線３が存在しないＣＡＳＥ１では厚み方向の応力Ｐｈ１は３６０Ｍｐａ、幅方向の応力Ｐｗ１は１０５０Ｍｐａ程度となる。配線３の厚みは幅に比べて非常に小さいため、配線３が存在するＣＡＳＥ２でも厚み方向の応力Ｐｈ２は３６０Ｍｐａ程度であり、ＣＡＳＥ１とほぼ変わらない。一方、幅方向の応力Ｐｗ２は１８５ＭＰａと大きく低減される。従って、半導体基板１の破断を防ぐ上で、配線３又はダミー配線１１が存在する応力緩和領域１３は考慮する必要がなく、配線３及びダミー配線１１が存在しない領域１２のＷ／Ｈ比を制御すればよい。 In CASE 1 in which the wiring 3 does not exist, the stress Ph1 in the thickness direction is 360 Mpa, and the stress Pw1 in the width direction is about 1050 Mpa. Since the thickness of the wiring 3 is very small compared to the width, the stress Ph2 in the thickness direction is about 360 MPa even in the CASE 2 in which the wiring 3 exists, which is almost the same as the CASE 1. On the other hand, the stress Pw2 in the width direction is greatly reduced to 185 MPa. Therefore, in order to prevent the semiconductor substrate 1 from breaking, it is not necessary to consider the stress relaxation region 13 in which the wiring 3 or the dummy wiring 11 exists, and the W / H ratio of the region 12 in which the wiring 3 and the dummy wiring 11 do not exist is controlled. do it.
　図１１は、Ｗ／Ｈ比と応力ベクトル角の関係を示す図である。図１２は図１１の一部を拡大した図である。応力ベクトル角は、半導体基板１の主面に対する応力ベクトルの角度を示す。Ｗ／Ｈ≦０．６で応力ベクトル角を７０°以上に設定できることが分かる。即ち、応力ベクトルを破断しやすい４５°方向からずらすことができる。なお、本実施の形態では面方位（１００）、（１１０）又は（１１１）のＳｉウエハを使用する例を用いたが、ＳｉＣウエハ又はＧａＮウエハ等、面方位が異なる、つまり劈開面が４５°ではない基板を用いてもよい。この場合でも、劈開面角度から応力ベクトル角をずらすことで、同様の効果を得ることができる。これらの基板を用いる場合でも上述の通り基板の剥離耐量は破断耐量よりも高いため、垂直方向の応力はあまり問題とならない。従って、クラック耐量を向上させるために、ベクトル角を７０°以上に保つことが好ましい。 FIG. 11 is a diagram showing the relationship between the W / H ratio and the stress vector angle. FIG. 12 is an enlarged view of a part of FIG. The stress vector angle indicates the angle of the stress vector with respect to the main surface of the semiconductor substrate 1. It can be seen that the stress vector angle can be set to 70 ° or more when W / H ≦ 0.6. That is, the stress vector can be shifted from the 45 ° direction where it is easy to break. In this embodiment, an example in which Si wafers having plane orientations (100), (110), or (111) are used is used, but the plane orientations are different, that is, the cleavage plane is 45 °, such as a SiC wafer or a GaN wafer. You may use a substrate that is not. Even in this case, the same effect can be obtained by shifting the stress vector angle from the cleavage plane angle. Even when these substrates are used, the peeling resistance of the substrate is higher than the breaking resistance as described above, so that the stress in the vertical direction does not matter much. Therefore, it is preferable to keep the vector angle at 70 ° or more in order to improve the crack resistance.
　図１３は、Ｗ／Ｈ比と応力比の関係を示す図である。図１４は図１３の一部を拡大した図である。応力比は、Ｗ／Ｈ比が１の場合を基準にして規格化した応力の大きさである。Ｗ／Ｈ≦０．６とすることで、応力を下限値近くまで低減できることが分かる。 FIG. 13 is a diagram showing the relationship between the W / H ratio and the stress ratio. FIG. 14 is an enlarged view of a part of FIG. The stress ratio is the magnitude of stress standardized based on the case where the W / H ratio is 1. It can be seen that the stress can be reduced to near the lower limit by setting W / H ≦ 0.6.
　上記の結果に基づいて、本実施の形態では、封止金属層７の外周部及び内周部において配線３及びダミー配線１１が存在しない領域１２の幅Ｗを封止金属層７の厚みＨの０．６倍以下とする（Ｗ／Ｈ≦０．６）。これにより、半導体基板１の破断を低減することができる。複数の領域１２が存在する場合、その全てがＷ／Ｈ≦０．６を満たすことが最も好ましい。ただし、特に応力が集中する点に対してのみ上記関係式を満たすようにダミー配線１１を設けてもよい。 Based on the above results, in the present embodiment, the width W of the region 12 in which the wiring 3 and the dummy wiring 11 do not exist in the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7 is set to the thickness H of the sealing metal layer 7. It shall be 0.6 times or less (W / H ≦ 0.6). Thereby, the breakage of the semiconductor substrate 1 can be reduced. When a plurality of regions 12 are present, it is most preferable that all of them satisfy W / H ≦ 0.6. However, the dummy wiring 11 may be provided so as to satisfy the above relational expression only at the point where the stress is particularly concentrated.
　実際には封止金属層７の厚みＨは４０～１００μｍ程度に設定されている。これ以上の厚みの封止金属層７を蒸着、スパッタ又はディスペンス等の方法で堆積させることは非常に困難であり、コストが大きくなる。従って、領域１２の幅Ｗを２５～６０μｍに設定する必要がある。 Actually, the thickness H of the sealing metal layer 7 is set to about 40 to 100 μm. It is very difficult to deposit the sealing metal layer 7 having a thickness larger than this by a method such as vapor deposition, sputtering, or dispensing, and the cost increases. Therefore, it is necessary to set the width W of the region 12 to 25 to 60 μm.
実施の形態６．
　図１５は、実施の形態６に係る半導体パッケージを示す平面図である。封止金属層７の外周部及び内周部において配線３が封止金属層７の外周又は内周に沿って延びている。このため、封止金属層７の外周又は内周に沿って幅を測定した場合に、封止金属層７の外周部及び内周部における配線３の幅は封止金属層７の中央部における配線３の幅よりも広くなる。 Embodiment 6.
FIG. 15 is a plan view showing the semiconductor package according to the sixth embodiment. Wiring 3 extends along the outer circumference or the inner circumference of the sealing metal layer 7 at the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7. Therefore, when the width is measured along the outer circumference or the inner circumference of the sealing metal layer 7, the width of the wiring 3 in the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7 is the central portion of the sealing metal layer 7. It is wider than the width of the wiring 3.
　このように応力が集中する封止金属層７の外周部及び内周部における配線３の幅を広くすることで、封止金属層７を横切る配線３の断線を防ぐことができる。ただし、配線３を太く配置しすぎた場合、半導体基板１又はパッシベーション膜５との応力差により、スライド破壊という配線信頼性を損なう不具合が生じることが一般的に知られている。このため、配線３の幅は１００μｍ以下とすることが一般的である。本実施の形態にかかる対策を行うことで、封止金属層７の中央部における配線３の幅を狭くすることができる。これにより、配線３とパッシベーション膜５の応力関係により発生するスライド破壊を抑制することができる。 By widening the width of the wiring 3 at the outer peripheral portion and the inner peripheral portion of the sealing metal layer 7 in which stress is concentrated in this way, it is possible to prevent the wiring 3 from being broken across the sealing metal layer 7. However, it is generally known that when the wiring 3 is arranged too thick, a problem of slide failure, which impairs the wiring reliability, occurs due to the stress difference between the semiconductor substrate 1 and the passivation film 5. Therefore, the width of the wiring 3 is generally 100 μm or less. By taking the measures according to the present embodiment, the width of the wiring 3 in the central portion of the sealing metal layer 7 can be narrowed. As a result, slide fracture caused by the stress relationship between the wiring 3 and the passivation film 5 can be suppressed.
実施の形態７．
　図１６は、実施の形態７に係る半導体パッケージを示す平面図である。図１７は図１６の領域Ａを拡大した斜視図である。複数の配線３が存在しない領域１２の幅は、封止金属層７の外周又は内周に沿った第１の幅Ｗ１と、封止金属層７の外周又は内周とは垂直方向の第２の幅Ｗ２とを有する。第１の幅Ｗ１と第２の幅Ｗ２の両方が封止金属層７の厚みＨの０．６倍以下である（Ｗ１，Ｗ２≦０．６×Ｈ）。これにより、第１の幅Ｗ１だけが封止金属層７の厚みＨの０．６倍以下である場合よりも応力を緩和することができる。 Embodiment 7.
FIG. 16 is a plan view showing the semiconductor package according to the seventh embodiment. FIG. 17 is an enlarged perspective view of the region A of FIG. The width of the region 12 in which the plurality of wirings 3 do not exist is the first width W1 along the outer circumference or the inner circumference of the sealing metal layer 7, and the second width in the direction perpendicular to the outer circumference or the inner circumference of the sealing metal layer 7. Width W2 and. Both the first width W1 and the second width W2 are 0.6 times or less the thickness H of the sealing metal layer 7 (W1, W2 ≦ 0.6 × H). As a result, the stress can be relaxed as compared with the case where only the first width W1 is 0.6 times or less the thickness H of the sealing metal layer 7.
実施の形態８．
　図１８は、実施の形態８に係る半導体パッケージを示す平面図である。配線３とダミー配線１１が封止金属層７の外周部において封止金属層７の外周に沿って互いに平行に並んでいる。図１９は図１８のＶＩＩ－ＶＩＩＩに沿った断面図である。図中の矢印は引っ張り応力ベクトルを示す。平行に並んだ配線３とダミー配線１１の段差構造により応力ベクトルが分散し応力が緩和される。このため、半導体基板１の破断を防いでヒートサイクル耐量を向上することができる。また、封止金属層７の熱融解時の濡れ性を向上することができるため、中空部と外部との間のリーク発生を抑制することができる。また、封止金属層７が熱融解時にはみだすのを防ぐことができる。 Embodiment 8.
FIG. 18 is a plan view showing the semiconductor package according to the eighth embodiment. The wiring 3 and the dummy wiring 11 are arranged in parallel with each other along the outer circumference of the sealing metal layer 7 at the outer peripheral portion of the sealing metal layer 7. FIG. 19 is a cross-sectional view taken along the line VII-VIII of FIG. The arrows in the figure indicate the tensile stress vector. The stress vector is dispersed and the stress is relaxed by the stepped structure of the wiring 3 and the dummy wiring 11 arranged in parallel. Therefore, it is possible to prevent the semiconductor substrate 1 from breaking and improve the heat cycle resistance. Further, since the wettability of the sealing metal layer 7 at the time of thermal melting can be improved, the occurrence of leakage between the hollow portion and the outside can be suppressed. Further, it is possible to prevent the sealing metal layer 7 from protruding during thermal melting.
　また、配線３とダミー配線１１の幅を１００μｍ以下にすることで、配線３又はダミー配線１１とパッシベーション膜５の応力関係により発生するスライド破壊を抑制することができる。その他の構成及び効果は実施の形態５と同様である。 Further, by setting the width of the wiring 3 and the dummy wiring 11 to 100 μm or less, it is possible to suppress the slide fracture caused by the stress relationship between the wiring 3 or the dummy wiring 11 and the passivation film 5. Other configurations and effects are the same as in the fifth embodiment.
１　半導体基板、２　デバイス、３　配線、５　パッシベーション膜、６　メタライズパターン、７　封止金属層、８　リッド、１０　角部、１１　ダミー配線、１２　領域 1 semiconductor substrate, 2 devices, 3 wiring, 5 passivation film, 6 metallized pattern, 7 encapsulating metal layer, 8 lid, 10 corners, 11 dummy wiring, 12 areas

Claims (12)

  1. 　半導体基板と、
    　前記半導体基板の主面に形成されたデバイスと、
    　前記主面を覆うパッシベーション膜と、
    　前記デバイスを囲むように前記パッシベーション膜の上に形成されたメタライズパターンと、
    　前記メタライズパターンの上に形成され、平面視で角部を有する封止金属層と、
    　前記封止金属層を介して前記メタライズパターンに接合され、前記デバイスを真空封止するリッドと、
    　少なくとも前記封止金属層の前記角部の外側部分と前記半導体基板との間に形成され、前記メタライズパターンよりも柔らかく、前記デバイスに電気的に接続されていないダミー配線とを備えることを特徴とする半導体パッケージ。     With a semiconductor substrate
    A device formed on the main surface of the semiconductor substrate and
    A passivation film covering the main surface and
    A metallized pattern formed on the passivation film so as to surround the device,
    A sealing metal layer formed on the metallized pattern and having corners in a plan view,
    A lid that is joined to the metallized pattern via the sealing metal layer and vacuum seals the device.
    It is characterized by including at least a dummy wiring formed between the outer portion of the corner portion of the sealing metal layer and the semiconductor substrate, which is softer than the metallized pattern and is not electrically connected to the device. Semiconductor package.
  2. 　前記半導体基板の前記主面に形成され、前記デバイスに電気的に接続された配線を更に備え、
    　前記配線は前記封止金属層の前記角部を避けるように配置されていることを特徴とする請求項１に記載の半導体パッケージ。     Further comprising wiring formed on the main surface of the semiconductor substrate and electrically connected to the device.
    The semiconductor package according to claim 1, wherein the wiring is arranged so as to avoid the corner portion of the sealing metal layer.
  3. 　前記半導体基板の材料と前記リッドの材料は異なることを特徴とする請求項１又は２に記載の半導体パッケージ。 The semiconductor package according to claim 1 or 2, wherein the material of the semiconductor substrate and the material of the lid are different.
  4. 　前記ダミー配線は前記配線と同層で形成されていることを特徴とする請求項２に記載の半導体パッケージ。 The semiconductor package according to claim 2, wherein the dummy wiring is formed in the same layer as the wiring.
  5. 　前記ダミー配線は、前記封止金属層の前記角部の内側部分と前記半導体基板との間に形成されていることを特徴とする請求項１～４の何れか１項に記載の半導体パッケージ。 The semiconductor package according to any one of claims 1 to 4, wherein the dummy wiring is formed between the inner portion of the corner portion of the sealing metal layer and the semiconductor substrate.
  6. 　前記ダミー配線は、前記封止金属層の前記角部の前記外側部分と前記リッドとの間に形成されていることを特徴とする請求項１～５の何れか１項に記載の半導体パッケージ。 The semiconductor package according to any one of claims 1 to 5, wherein the dummy wiring is formed between the outer portion of the corner portion of the sealing metal layer and the lid.
  7. 　半導体基板と、
    　前記半導体基板の主面に形成されたデバイスと、
    　前記半導体基板の前記主面に形成された複数の配線と、
    　前記主面及び前記複数の配線を覆うパッシベーション膜と、
    　前記デバイスを囲むように前記パッシベーション膜の上に形成されたメタライズパターンと、
    　前記メタライズパターンの上に配置された封止金属層と、
    　前記封止金属層を介して前記メタライズパターンに接合され、前記デバイスを真空封止するリッドとを備え、
    　前記複数の配線は前記メタライズパターンよりも柔らかく、
    　前記封止金属層の外周部及び内周部において前記複数の配線が存在しない領域の幅は前記封止金属層の厚みの０．６倍以下であることを特徴とする半導体パッケージ。     With a semiconductor substrate
    A device formed on the main surface of the semiconductor substrate and
    A plurality of wirings formed on the main surface of the semiconductor substrate, and
    A passivation film covering the main surface and the plurality of wirings,
    A metallized pattern formed on the passivation film so as to surround the device,
    An encapsulating metal layer arranged on the metallized pattern and
    A lid that is joined to the metallized pattern via the sealing metal layer and vacuum seals the device.
    The plurality of wires are softer than the metallized pattern,
    A semiconductor package characterized in that the width of a region in which the plurality of wirings do not exist on the outer peripheral portion and the inner peripheral portion of the sealing metal layer is 0.6 times or less the thickness of the sealing metal layer.
  8. 　前記半導体基板は、前記主面に対して４５°方向に劈開面がある結晶構造を有することを特徴とする請求項７に記載の半導体パッケージ。 The semiconductor package according to claim 7, wherein the semiconductor substrate has a crystal structure having a cleavage plane in a direction of 45 ° with respect to the main surface.
  9. 　前記封止金属層の前記外周部及び前記内周部における前記配線の幅は前記封止金属層の中央部における前記配線の幅よりも広いことを特徴とする請求項７又は８に記載の半導体パッケージ。 The semiconductor according to claim 7 or 8, wherein the width of the wiring in the outer peripheral portion and the inner peripheral portion of the sealing metal layer is wider than the width of the wiring in the central portion of the sealing metal layer. package.
  10. 　前記領域の幅は、前記封止金属層の外周又は内周に沿った第１の幅と、前記封止金属層の前記外周又は前記内周とは垂直方向の第２の幅とを有し、
    　前記第１の幅と前記第２の幅の両方が前記封止金属層の厚みの０．６倍以下であることを特徴とする請求項７～９の何れか１項に記載の半導体パッケージ。     The width of the region has a first width along the outer circumference or the inner circumference of the sealing metal layer and a second width in a direction perpendicular to the outer circumference or the inner circumference of the sealing metal layer. ,
    The semiconductor package according to any one of claims 7 to 9, wherein both the first width and the second width are 0.6 times or less the thickness of the sealing metal layer.
  11. 　半導体基板と、
    　前記半導体基板の主面に形成されたデバイスと、
    　前記半導体基板の前記主面に形成された複数の配線と、
    　前記主面及び前記複数の配線を覆うパッシベーション膜と、
    　前記デバイスを囲むように前記パッシベーション膜の上に形成されたメタライズパターンと、
    　前記メタライズパターンの上に配置された封止金属層と、
    　前記封止金属層を介して前記メタライズパターンに接合され、前記デバイスを真空封止するリッドとを備え、
    　前記複数の配線が前記封止金属層の外周部において互いに離間しつつ前記封止金属層の外周に沿って互いに平行に並んでいることを特徴とする半導体パッケージ。     With a semiconductor substrate
    A device formed on the main surface of the semiconductor substrate and
    A plurality of wirings formed on the main surface of the semiconductor substrate, and
    A passivation film covering the main surface and the plurality of wirings,
    A metallized pattern formed on the passivation film so as to surround the device,
    An encapsulating metal layer arranged on the metallized pattern and
    A lid that is joined to the metallized pattern via the sealing metal layer and vacuum seals the device.
    A semiconductor package characterized in that the plurality of wirings are arranged in parallel with each other along the outer periphery of the sealing metal layer while being separated from each other at the outer peripheral portion of the sealing metal layer.
  12. 　前記複数の配線の各々の幅は１００μｍ以下であることを特徴とする請求項１１に記載の半導体パッケージ。 The semiconductor package according to claim 11, wherein each of the plurality of wirings has a width of 100 μm or less.
PCT/JP2019/032474 2019-08-20 2019-08-20 Semiconductor package WO2021033269A1 (en)

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WO2008153082A1 (en) * 2007-06-12 2008-12-18 Sumitomo Bakelite Company Limited Resin composition, embedding material, insulating layer, and semiconductor device
JP2010080591A (en) * 2008-08-28 2010-04-08 Oki Semiconductor Co Ltd Camera module and method of manufacturing the same

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US20040080917A1 (en) * 2002-10-23 2004-04-29 Steddom Clark Morrison Integrated microwave package and the process for making the same
CA2946526C (en) * 2014-08-11 2021-03-23 Raytheon Company Hermetically sealed package having stress reducing layer

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Publication number Priority date Publication date Assignee Title
WO2008153082A1 (en) * 2007-06-12 2008-12-18 Sumitomo Bakelite Company Limited Resin composition, embedding material, insulating layer, and semiconductor device
JP2010080591A (en) * 2008-08-28 2010-04-08 Oki Semiconductor Co Ltd Camera module and method of manufacturing the same

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