JP2019091932A - Hermetically sealed package having stress reducing layer - Google Patents

Abstract

To provide a sealed package having a device disposed on a wafer structure and a lid structure bonded to the device wafer.SOLUTION: A device wafer includes: a substrate; a metal ring disposed on a surface portion of the substrate around the device; and a bonding material disposed on the metal ring. A first layer of the metal ring includes a stress relief buffer layer having a ductility higher than that of the surface portion of the substrate and a width greater than that of the bonding material. The metal ring extends laterally beyond at least one of inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than that of the surface portion of the substrate and less than that of the bonding material.SELECTED DRAWING: Figure 5

Description

  The present disclosure relates generally to electronic packages. And, more particularly, to microelectromechanical system (MEMS) packages.

  As is known in the prior art, electro-mechanical systems (MEMS) are integrated microdevices or systems that combine electronic and mechanical components. MEMS devices can be manufactured, for example, using standard integrated circuit batch processing techniques. Typical applications of MEMS devices include detecting, controlling and driving on a micro scale. Such MEMS devices may function individually or in an array to produce an effect at macro scale.

  In the prior art, and as is known, many MEMS devices require a hermetically sealed environment to achieve the highest performance. This may be a vacuum environment, a controlled pressure environment, or a controlled gas environment. The package environment also provides protection and an optimal operating environment for MEMS devices. Specific examples of these MEMSs include infrared MEMSs such as bolometers, sometimes referred to as microbolometers, predetermined inertia MEMSs such as gyros and accelerometers, and opto-mechanical devices such as moving mirror arrays . In the past, MEMS devices have been separately packaged in vacuum compatible packages after MEMS device wafer fabrication and dicing. Often, however, the cost of packaging a MEMS device in a conventional metal or ceramic package can be on the order of about 10 to 100 times the device manufacturing cost. This is especially true if a vacuum is required in the package.

  Over the years, various types of infrared detectors have been developed. Many include substrates having a focal plane array thereon. The focal plane array includes a plurality of detector elements (detection devices), each corresponding to each pixel. The substrate comprises an integrated circuit electrically connected to the detector element. It is commonly known as a readout integrated circuit (ROIC), which integrates the signals from each detector element and mutiplexes the signals from the chip using appropriate adjustments and processing. Used for

  As with certain micro-electro-mechanical (MEMS) devices, bolometers may need to be sealed in a vacuum or other controlled environment for best performance. Typical requirements for the packaging of bolometer arrays are reliable hermetic seals capable of maintaining high vacuum for extended periods, integration of IR window material with good infrared transmission And high yield / low cost packaging. Both the reliability and the cost of the MEMS device depend on the chosen encapsulation (packaging). For MEMS based bolometers, packaging may be done at chip level or wafer level. The common method of packaging in this instance is to manufacture a protective, IR-transparent cap wafer or window cap wafer (Window Cap Wafer, WCW) and active IR detector bolometer area Prior to dicing, bond to the containing semiconductor substrate or the exposed surface of the device wafer. Cap wafers, sometimes also referred to as window or lid structures, are formed therein with a cavity. When the cap wafer is flipped and bonded to the device wafer, the cavities provide sufficient clearance to accommodate and protect the MEMS devices therein. U.S. Pat. No. 5,701,008, entitled "Integrated infrared and gas molecule grating in a vacuum package", inventor Ray et al., Issued Dec. 23, 1997. U.S. Pat. As described therein, and with reference to FIGS. 1 and 2, the package assembly is shown, preferably having a readout integrated circuit (ROIC) substrate 2 of semiconductor material, preferably silicon. doing. An infrared (IR) detector array 14 is disposed on the substrate 2 and includes a plurality of individual detector elements 6, also referred to as pixels. Although FIG. 2 shows only a 5 × 6 rectangular array of detector pixels 6 in the detector area 10, a typical IR integrated circuit will typically be up to hundreds or thousands × hundreds or thousands of pixels 6 It will be appreciated that the planar IR detector array of In most commercial applications, IR detectors are mostly uncooled and by detecting the increase in temperature resulting from the heat applied to the detector by IR radiation, IR Detect the intensity of the radiation. A typical layer of uncooled IR detectors is a vanadium oxide (VOx) microbolometer (MB), where a plurality of individual detectors are mostly on an ROIC substrate, by conventional semiconductor manufacturing processes In the form of an array. The MB array detects IR radiation by detecting IR generated heat, and is also called focal plane array (FPA) or sensor chip assembly (SCA). The substrate 2 is an integrated circuit used to process the signal generated by the bolometer. In this case, the bolometer is a microbridge resistance whose resistance changes as the temperature changes. Incoming radiation causes a change in the temperature of the microbridge. Although other semiconductor materials such as silicon (Si) may be used, VOx is commonly available and cost effective used in most commercial IR detection applications .

  As described in US Pat. No. 5,701,008 referred to above, the vacuum sealing assembly includes a sealing seal 8 surrounding the IR detector array to seal the detector array from the atmosphere. The seal 8 may be, for example, indium, gold-tin or other solder, and the height of the seal is precisely controlled when the seal is placed on the substrate 2 or preferably the wafer 10 Be done. The seal 8 supports a second substrate, a cap wafer, here an IR transparent window, here for example silicon. With wafer level packaging, the window wafer 10 is such that it has a coefficient of thermal expansion consistent with the FPA wafer, which is also silicon. The wafer 10 is a getter material (gettering material) formed on a defined area of the surface of the wafer 10 having a defined surface area, as described in US Pat. No. 5,701,008 referred to above. Not shown).

  Also in the prior art, as is also known, wafer level packaging (WLP) has been developed to handle the high cost of packaging MEMS by removing the conventional package. One such WLP package is described in US Pat. No. 6,521,477, entitled "Vacuum package fabrication of integrated circuit components", inventor Gooch et al., Issued February 18, 2003. In one WLP process, two wafers can be bonded together using a bonding material to yield a bonded wafer. For example, one of the wafers is a semiconductor (eg, silicon) device and has a detector device in the detector area of the wafer. The detector area is located in the central interior area of the device wafer along with the readout integrated circuit (ROIC) bonded to the other wafer. The lid wafer is placed on the detector area of the device wafer using sheet metal rings of solder. After shaping the device in a semiconductor wafer, the wafer includes a thin overglass layer, such as silicon nitride or silicon oxynitride (SiON). In order to form the bottom layer of titanium, seal ring metal is formed using conventional photolithographic processing to act as a substrate adhesive layer to the ROIC overglass. Next, an intermediate layer of Nickel, which acts as a diffusion barrier, is followed by a layer of gold to suppress oxidation formation and to strengthen the solder joints. Thereafter, it is referred to as "seal ring". A similar set of layers is formed on the lid wafer to provide a mating surface for the solder seal between the device and the lid wafer. After formation of the seal ring, solder is applied to, for example, 80% gold and 20% tin, either or both of the device and the lid wafer.

  While the WLP technology described provides an effective package, the inventor has found that the edge of the seal ring is a device or ROCI due to the difference in thermal expansion between gold tin 7 solder and the semiconductor device wafer. It was confirmed that the stress was increased in the high stress area as shown in FIG. 3 which is in contact with the wafer. These stresses can result in overglass and unwanted crack growth in the device or underlying structure of the ROIC wafer, as shown in FIG. These cracks can break the interconnect traces in the interlayer dielectric layer (ILD) and the ROIC ILD leading to failure.

  More specifically, the inventor has confirmed in the prior art that the seal ring metal stack (about 0.5 μm thick) and the solder (up to 11 μm thick) have coincident edges. When the solder cools below its melting temperature, about 280 degrees centigrade, the solder shrinks faster than the lower seal ring and the ROIC (the coefficient of thermal expansion (CTE) of the solder is about 16 ppm and the CTE of silicon is about 3 ppm ). And the solder is very hard (gold-tin solder has a large Young's modulus) and so it can not deform to relieve stress. Shrinkage of the solder layer tends to pull the edge of the solder joint, which is the cause of the stress point r, and results in cracks at the edge of the joint. Simply increasing the thickness of the titanium (Ti) portion at the bottom of the seal ring has little effect on stress. This is because the stress still remains with the solder tension of the seal ring, resulting in a stress point. Localized on the ROIC surface by terminating the solder shorts of the edge of the metal adhering to the ROIC surface and providing an intervening layer, eg a titanium stress relaxation buffer layer The sharp edges that transfer stress to the end regions end on the ROIC surface and are covered with a more ductile material. The inventor has further found that in one embodiment, the stress relaxation buffer layer may be thickened, or in another embodiment, the titanium bonding material adhesion layer may be thickened, if the coincident edges are removed. It has been confirmed that thickening the lower titanium layer by any of the above further reduces the stress. However, it is only if the matched edge is removed first.

  In accordance with the present disclosure, a structure is provided. The structure is a substrate; a metal ring disposed on the surface portion of the substrate around the surface portion of the substrate; a bonding material disposed on the metal ring, having inner and outer edges Including bonding materials; And here, the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.

  In one embodiment, the first layer of metal ring includes a stress relaxation buffer layer disposed on a surface portion of the substrate, the first layer being higher than the ductility of the surface portion at a predetermined temperature It has ductility and is wider than the width of the bonding material. The stress relief buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material.

  In one embodiment, the stress relaxation buffer layer has a coefficient of thermal expansion greater than the coefficient of thermal expansion of the surface portion of the substrate and less than the coefficient of thermal expansion of the bonding material.

  In one embodiment, the outer region of the top surface of the metal ring comprises a material that inhibits adhesion of the bonding material to the top surface. And here, the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.

  In one embodiment, the structure includes a bonding material masking layer on top of the metal ring. The bonding material passes through the window in the masking layer exposing a portion of the top surface of the metal layer, and where the portion of the bonding material is windowed onto the exposed portion of the top surface of the metal layer Have passed.

  In one embodiment, portions of the metal ring extend laterally beyond at least one of the inner and outer edges of the bonding material.

  In one embodiment, the structure comprises a lid. And, here, the bonding material bonds the substrate to the lid.

  The stress relief buffer layer effectively adheres to the substrate and is wetted by the bonding material. Furthermore, the stress relaxation buffer layer has a CTE that is preferably intermediate between the coefficient of thermal expansion (CTE) of the surface portion of the substrate joined to the stress relaxation buffer layer and the CTE of the solder or bonding material, and Instead of cracking as in the case of brittle materials such as SiON and Silicon, it has the properties of a ductile material that locally generate areas of high stress. An exemplary stress relieving buffer layer material is titanium.

  With such a configuration, the stress generated between the substrate, eg, the semiconductor wafer, and the adhesive layer causes the edge of the bonding material to contact the stress relaxation buffer layer from the point where the edge of the bonding material contacts the semiconductor wafer Shifted to the point, and thus shifted away from the semiconductor wafer and any associated overglass or brittle material. Thus, the stress relief buffer layer acts as a stress reducing layer, shifting the high stress area from the brittle overglass to the more ductile lower layer.

  More specifically, when using solder with high thermal contraction rate to bond and seal two wafers to form a package, the solder cools from its melting temperature As it shrinks, it causes high levels of stress in the lower semiconductor wafer at the edge of the solder joint. The use of stress relaxation buffer layer 1 isolates the high stress area at the edge of the solder joint from the underlying brittle semiconductor wafer. By interposing a stress relaxation buffer layer which has a higher level of ductility than that of the semiconductor wafer and a thermal contraction rate which is lower than the solder layer and still higher than that of the lower wafer. Thus, the present disclosure allows the integration of high CTE solder or other bonding materials with brittle overglass on semiconductor structures. Furthermore, the process can be used for device wafers, lids, or both.

  It is to be understood that the term ring shape ("ring-shaped") refers to and includes shapes that surround a space. The shape may be circular, rectangular, square, oval, or have an irregular shape, such as a serpentine or serpentine shape.

  The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims.

FIG. 1 is a simplified cross-sectional perspective view of a vacuum package for an IR detector array according to the prior art. FIG. 2 is a simplified top view of an IR detector array used in the assembly of FIG. 1 in accordance with the prior art. FIG. 3 is a cross-sectional view of the IR detector array of FIG. 2, the cross section being along line 3--3 in FIG. 2 according to the prior art. FIG. 4 is a plan view of a cross section of a sealed package in accordance with the present disclosure, the cross section being along line 4-4 in FIG. 5 is a side view of the cross section of the package of FIG. 4, the cross section being along line 5-5 in FIG. 4. FIG. 5A is an enlarged portion according to the side view of the cross section of FIG. 5 and the enlarged portion is where it is surrounded by arrows 5A-5A in FIG. FIG. 6 is a side view of a cross section of a sealed package in accordance with another embodiment of the present disclosure. FIG. 6A is an enlarged portion according to the side view of the cross section of FIG. 6, the enlarged portion being where it is surrounded by arrows 6A-6A in FIG.

  Like reference symbols in the various drawings indicate like elements.

  With reference now to FIGS. 4 and 5, a hermetically sealed package 100 for the sealing device 102 is shown. The package 100 comprises, in its central area, a substrate 104 having a device 102; a device 102; a cap wafer 108 (FIG. 5); and a pair of metal rings, here for example multilayer metal rings, 107 DW metal rings , 107 CW; The metal ring 107DW is disposed on the surface of the substrate 104 around the surface area 106 of the substrate 104, and the other metal ring 107CW is on the surface of the cap wafer 108 around the central area 106. Is located in It should be appreciated that in some applications, the metal ring 107CW may not be required. The metal ring 107DW is a ring-shaped stress relieving buffer layer 109DW (more specifically, as shown more clearly in FIG. 5A) disposed on and in direct contact with the surface of the substrate 104. Seal ring structure 110DW (FIG. 5) on the top surface of the ring-shaped stress relaxation buffer layer 109DW; and on the overglass layer 116 of the substrate 104 and in direct contact); Including. A metal ring 107CW is a ring-shaped stress relief buffer layer 109CW on the surface of the cap wafer 108 around the central region 106; and a seal ring structure 110CW on the top surface of the ring-shaped stress relief buffer layer 109CW) ;including. A bonding material 118 is placed between the two seal ring structures 110DW, 110CW, as shown in FIG. Thus, as described in more detail below, the ring-shaped stress relief buffer layer 109CW is the underlying material of the ring seal structure 110CW, and the ring-shaped stress relief buffer layer 109DW is a ring seal. It is the lower material of the structure 110DW. The stress relief buffer layers 109CW and 109DW respectively serve as a stress relief buffer layer of a ring-shaped bonding material for the cap wafer 108 and the device wafer (or substrate 104).

  More specifically, the substrate 104 is a semiconductor device wafer 112, here, for example, silicon, which provides a read only integrated circuit ROIC; a device wafer 112 having metal interconnect electrically conductive traces for the ROIC component. Over the top surface, an interlayer dielectric layer (ILD) 114; and, as shown, an overglass layer 116 disposed over the layer 114. As shown, the device 102 is here, for example, an array of infrared (IR) detectors, where, for example, a bolometer is located in the central region 106 above the overglass 116. The cap wafer 108 is any infrared transparent material and, as shown, has a cavity disposed above the device 102 and may include a getter material, not shown.

  The ring-shaped stress relief buffer layers 109DW, CW respectively are high ductile materials, here for example titanium, for reasons to be described. The ring-shaped stress relief buffer layer 109DW is disposed on the overglass layer 116 as described above. Each of the two seal ring structures 110DW and 110CW, respectively, is a lower, lower, substrate adhesion layer 122, placed over the stress relief buffer layer 109 over the overglass 116 and cap wafer 108, respectively. For example, titanium; as shown, a diffusion barrier layer 124, here, for example, nickel (Ni) or platinum (Pt), disposed over the substrate adhesion layer 122, with the bonding material 118 being a substrate adhesion. To prevent diffusion into (or interact with) layer 122; and, as shown, an oxidation block / junction material adhesion layer 126, disposed here over diffusion barrier layer 124, For example, gold (Au) prevents oxidation formation and promotes solder wetting. Intended for; including.

  It is noted that each one of the ring-shaped pairs of stress relief buffer layers 109CW, 109DW is wider than the seal ring structures 110CW, 110DW, respectively, and the bonding material 118. In this embodiment, the inner and outer edges 109a, 109b, respectively, of the ring-shaped stress relief buffer layers 109CW, 109DW extend beyond at least one of the inner and outer, here the seal ring structures 110CW, 110DW. Step 224 is formed on either side of the seal ring structure 110 CW, 110 DW, both over the inner and outer edges 110 b by a length L, respectively. The stress relief buffer layer 109DW and the seal ring structure 110DW are more clearly shown in FIG. 5A.

  More specifically, in this embodiment, the overglass 116 is here, for example, 2000 Angstrom thick silicon oxynitride (SiON), and each of the ring-shaped stress relief buffer layers 109DW, CW is used. Is, for example, a layer of titanium having a thickness greater than 500 angstroms, and here is, for example, 2500 angstroms thick. Here, for example, each one of the ring-shaped stress relief buffer layers 109DW, CW is formed using a photolithographic lift-off process. In view of the formation of the stress relieving layer 109DW and recognizing that the stress relieving layer 109CW is formed in a similar manner, the ring-shaped stress relieving buffer layer 109DW is here, for example, of the overglass layer 116. It is formed by first forming a layer of photoresist, not shown. A ring-shaped stress relief buffer layer 109DW remains in the area of the photoresist layer inside and outside the area of the device, and thereby leaving a ring-shaped area on the wafer surface, there being a ring-shaped stress there. A relaxed buffer layer 109DW is formed and exposed. Next, the entire surface of the wafer is coated with titanium using either evaporation or physical vapor deposition (PVD) processes. Note that a portion of the titanium will be deposited on the patterned photoresist, and another portion will be deposited on the exposed ring shaped portion of the wafer. Thereafter, the photoresist is lifted off of the wafer, thereby removing the portion of titanium above the photoresist and leaving a ring-shaped stress relief buffer layer 109DW on the wafer. The materials can also be manufactured using mechanical masks without the need for photolithography processes. Next, another lift-off process is used to form the seal ring structure 110DW. Here it is, for example, titanium having a thickness of 2000 angstroms deposited using either a vapor deposition or physical vapor deposition (PVD) process. Nickel having a thickness of 2500 angstroms deposited using either a vapor deposition or physical vapor deposition (PVD) process, and deposited using either a vapor deposition or physical vapor deposition (PVD) process Gold, having a thickness of 2500 angstroms, follows. The width of the ring-shaped stress relaxation buffer layer 109DW is here in the range of 300 micrometers, the width of the ring-shaped seal ring structure 110DW is here here, for example, the width of the ring-shaped stress relaxation buffer layer 109DW It is noted that the inner and outer edges 109a, 109b of the narrow (200 micrometre) and ring-shaped stress relief buffer layer 109DW are set back, respectively. Here, for example, the inner and outer edges 110a, 110b, respectively, of the seal ring structure 110DW are each set back by a length L, and here, for example, the inner and outer edges 110a of the ring-shaped stress relief buffer layer 109DW , 110b, respectively, 50 micrometers. As shown in FIG. 5A, this is to form step 224. Here, for example, a step 224 50 micrometers wide is formed. As a result, the sharp edge of the bonding material 118, for example solder (here, for example, gold / tin (here, for example, 80% gold, 20% tin)) is setback from the edge of the ring-shaped stress relaxation buffer layer 109DW. And lifted onto the surface of the substrate 104 and cap wafer 108, respectively. As a result, the high stress points described in FIG. 3 are shifted (lifted away from the overlayer 116). The stress relaxation buffer layer 109DW is then effectively inserted into the high stress point path, thereby reducing the stress in the brittle SiON overglass layer 116. The stress relaxation buffer layer 109DW is higher than the ductility of the SiON overglass layer 166 at a given temperature, such as room temperature (20-23 degrees Celsius) or the temperature of the package 100 when the lid 108 is bonded to the substrate 118. The ductility and coefficient of thermal expansion (CTE) of the stress relaxation buffer layer 109DW, which is inserted between the solder 118 and the substrate 118, is the CTE value of the solder and the overglass layer. Note that it is a value between the CTE value of 116. The higher ductility of the stress relaxation buffer layer 109DW compared to the SiON overglass layer 116 can further reduce the stress in the brittle SiON overglass layer 116 for small levels of local deformation. .

  As a result, the high stress point SP is shifted out of the brittle SiON layer 116 (where it was placed in FIG. 3) and into the more ductile stress relaxation buffer layer 109DW. The stress points associated with the sharp edges of the stress relaxation buffer layer 109DW are of increased stress relaxation buffer layer 109DW by virtue of the stress relaxation buffer layer 109DW having a CTE closer to the coefficient of thermal expansion of the lower substrate 104. Combined with the relative thinness (here, for example 2500 angstroms), it is reduced to an insignificant point. In addition, small steps 224 (FIG. 5) dislike some solder because the surface is finished with titanium oxide after being exposed to air, and thus, solder to resist the spread of the molten solder 118 from the joint Work as a dam (solder dam). That is, the surfaces of 109CW and 109DW are titanium that is rapidly oxidized to titanium oxide, and titanium oxide is a material that suppresses adhesion by the bonding material 118.

  The thermal expansion coefficient (CTE) of AuSn (gold tin) solder is 16 ppm / K, CTE of Ti (titanium) 8.5 8.5 ppm / degree Fahrenheit (degree Kelvin), CTE of silicon (silicon) 2.6 2.6 ppm / fahrenheit Note that the degree, and the CTE of SiON (silicon oxynitride) 華 2 ppm / Fahrenheit. The ring-shaped stress relaxation buffer layer 109DW includes the CTE of the surface portion of the substrate joined to the ring-shaped stress relaxation buffer layer 109DW (that is, the over glass layer 116 (2 ppm / Fahrenheit)) and the seal ring structure. It is noted that it has a coefficient of thermal expansion (CTE) (approximately 8.5 ppm / Fahrenheit) (generally in between) with the CTE (16 ppm / K) of the bonding material 118 above 110 DW.

  Thus, it is noted that the CTE difference between gold-tin solder 118 and silicon is very large (6 times). These are the two main materials that are causing stress problems. When the solder cools from the molten state of the solder, it wants to shrink more than six times that of the deposited silicon. The stress relaxation buffer layer 109DW preferably has an intermediate thermal expansion coefficient (CTE) between the CTE of the overglass layer 116 and the CTE of the solder or bonding material 118, and in the case of brittle materials such as silicon oxynitride and silicon It should be noted that instead of cracking like, the ductile stress relief buffer layer 109DW can locally create areas of high stress. The stress relaxation buffer layer 109CW has a ductility higher than that of the silicon cap wafer 108, and the coefficient of thermal expansion (CTE) of the stress relaxation buffer layer 109CW is inserted between the solder 118 and the silicon cap wafer 108. Also, keep in mind that

  Referring now to FIG. 6, a sealed package 100 'is shown in accordance with another embodiment of the present disclosure. Here, the seal ring structure 110DW ′ comprises a titanium substrate adhesion / diffusion barrier layer 122 ′ (FIG. 6A), and in practice, the layer 122 ′ comprises the diffusion barrier layer 122 and the stress relieving layer 109DW. It has become. Thus, the substrate adhesion / diffusion barrier layer 122 'is actually titanium thickened to a layer approximately 4000 angstroms thick and serves the dual purpose of the substrate adhesion layer 122 and the stress relief layer 109DW. The solder marks 150, here for example titanium or titanium nitride, have windows formed therein using a photolithographic etching process or lift-off lithography to expose the lower part of the bonding material adhesion layer 126. There is. It is noted that if titanium is used for the solder mask 150, the titanium is quickly oxidized to titanium oxide and that titanium oxide suppresses adhesion of the bonding material 118. Similarly, titanium nitride suppresses the adhesion of the bonding material 118.

  Bonding material 118, here, for example, solder, is deposited into the window over the exposed portion of bonding material adhesion layer 126. It is noted that the sealing material 116 is narrower than the metal ring 107DW '. The metal ring now includes a seal ring structure 110DW 'and a solder mark 150, which causes the edge of the bonding material 118 to set back from the edge of the metal ring 107DW' as shown. It is also noted that this setback forms solder dams equivalent to step 224 described above in connection with FIGS. 5 and 5A. It should be understood that a similar structure is used for the metal ring on cap wafer 108 in this example.

  A structure according to the present disclosure is disposed on a metal ring having a substrate; a metal ring disposed on a surface portion of the substrate around a surface portion of the substrate; an inner and an outer edge It should be properly understood from this that the bonding material comprises: and the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. One or more of the following features may include separate or combined with other features. Here, the first layer of metal ring includes a stress relaxation buffer layer disposed on the surface portion of the substrate, and the first layer has higher ductility than the surface portion at a predetermined temperature And the stress relief buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. Here, the stress relaxation buffer layer has a thermal expansion coefficient which is larger than the thermal expansion coefficient of the surface portion of the substrate and smaller than the thermal expansion coefficient of the bonding material. Here, the region of the upper surface of the metal ring comprises a material that inhibits the adhesion of the bonding material to the upper surface, and a portion of the metal ring is transverse to at least one of the inner and outer edges of the bonding material It is spreading in the direction. The structure includes a bonding material masking layer over the top surface of the metal ring, the bonding material passing through a window in the masking layer exposing a portion of the top surface of the metal layer, and A portion of the bonding material passes through the window over the exposed portion of the top surface of the metal layer. Here, a portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The structure includes a lid and a device disposed on the substrate, wherein the bonding material bonds the substrate to the lid. Here, the stress relaxation buffer layer has a thermal expansion coefficient which is larger than the thermal expansion coefficient of the surface portion of the substrate and smaller than the thermal expansion coefficient of the bonding material. The structure includes a bonding material masking layer on the top surface. A bonding material masking layer is included on the top surface of the metal ring, the bonding material passing through the window in the masking layer exposing a portion of the top surface of the metal layer, and where the portion of the bonding material Pass through the window over the exposed portion of the top surface of the metal layer. Here, the stress relaxation buffer layer is disposed on and in direct contact with the surface portion of the substrate. Here, the first layer of metal ring includes a stress relaxation buffer layer disposed on the surface portion of the substrate. Here, the first layer of the metal ring is titanium. Here, the first layer of the metal ring is copper or aluminum. Here, the upper side surface of the substrate is silicon oxynitride. Here, the substrate contains silicon. Here, the first layer of metal ring is titanium having a thickness greater than 500 angstroms.

  Structures in accordance with the present disclosure should also be properly understood to include the following. The structure includes a substrate; a stress relief buffer layer; and a seal ring disposed on the stress relief buffer layer and around a surface portion of the substrate. Here, the stress relaxation buffer layer has ductility higher than that of the surface portion of the substrate at a predetermined temperature. A bonding material is disposed on the seal ring, the bonding material having an inner and an outer edge. And here, the stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. Additionally, the ring-shaped stress relief layer may have a CTE between the coefficient of thermal expansion (CTE) of the surface portion of the substrate and the CTE of the bonding material on the seal ring.

  Structures in accordance with the present disclosure should also be properly understood to include the following. The present structure comprises: a substrate; a device disposed on the substrate; a seal ring disposed on the substrate around the device; a joining material disposed on the seal ring; a joining material and the substrate A layer disposed between and laterally extending beyond at least one of the inner and outer edges of the bonding material; the lid; Jointing. Furthermore, the layer has a CTE between the coefficient of thermal expansion (CTE) of the surface portion of the substrate and the CTE of the bonding material on the seal ring.

  Packages in accordance with the present disclosure should also be properly understood to include the following. The package comprises: a substrate; a device disposed on the surface of the package; a metal ring disposed on the surface portion of the substrate around the device; a lid; a bonding material disposed on opposite ends of the metal ring Including. Here, the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material, and the bonding material bonds the lid to the substrate. One or more of the following features may be included independently or in combination with other features. The feature is that the first layer of the metal ring includes a stress relaxation buffer layer disposed on the surface portion of the substrate, the first layer having a ductility higher than that of the surface portion at a predetermined temperature And the stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. Here, the stress relaxation buffer layer has a thermal expansion coefficient which is larger than the thermal expansion coefficient of the surface portion of the substrate and smaller than the thermal expansion coefficient of the bonding material. Here, the region of the upper surface of the metal ring comprises a material which inhibits the adhesion of the bonding material to the upper surface, and a portion of the metal ring extends laterally across at least one of the inner and outer edges of the bonding material It is spreading. The package includes a bonding material masking layer on the top surface of the metal ring, the bonding material passing through the window in the masking layer exposing a portion of the top surface of the metal layer, and the portion of bonding material is Passing the window over the exposed portion of the top surface of the metal layer.

  A number of embodiments of the present disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. For example, sealed packages can be used for a wide variety of devices. Infrared MEMS such as, but not limited to, bolometers, sometimes referred to as microbolometers, and certain inertia MEMSs such as gyros and accelerometers, junction-only devices for packages, non-evacuated applications ( Such as DLP) or wafer bonded MEMS in a vacuum package. Additionally, other materials may be used for the stress relief buffer layers 109DW and / or 109CW. For example, copper or aluminum. Additionally, other materials may be used for the substrate adhesive layer 122. For example, such as TiN. In this case, both Ti and Ni act as diffusion barriers for different stages of the manufacturing process. Additionally, other materials may be used for the bonding material. For example, it is such as CuSn. Furthermore, still other overglass materials may be used. For example, such as SiN. Accordingly, other embodiments are within the scope of the following claims.

Claims (22)

A sealed package structure,
A substrate having a surface comprising silicon,
A device disposed on the surface of the substrate;
A metal seal ring disposed on the surface of the substrate with respect to the device, the metal seal ring being
An oxide block / junction material adhesion layer disposed on top of the metal seal ring;
A diffusion barrier layer disposed below the oxide block / junction material adhesion layer;
With metal seal rings, including
A bonding material disposed on the metal seal ring;
A metal stress relief buffer layer disposed between the metal seal ring and the surface of the substrate, the bonding material having a yield strength as large as the yield strength of the metal stress relief buffer layer Having a metal stress relaxation buffer layer,
Lid structure,
Including
The bonding material and the metal seal ring cause the surface of the substrate to crack without the metal stress relaxation buffer layer,
The metal stress relief buffer layer has an inner and outer edge of the metal seal ring by a length sufficient to prevent cracking of the substrate in bonding the metal seal ring to the lid structure using the bonding material Extending laterally beyond at least one of the at least one to form the sealed package,
Structure. The metal stress relaxation buffer layer has a yield strength less than that of the bonding material,
The metal stress relief buffer layer breaks down with a force applied to the metal stress relief buffer layer prior to a force that causes the substrate to crack in forming the sealed package.
The structure according to claim 1. The metal stress relaxation buffer layer has a thermal expansion coefficient greater than the thermal expansion coefficient of the surface of the substrate and smaller than the thermal expansion coefficient of the bonding material.
The structure according to claim 1. The metal seal ring includes a substrate adhesion layer disposed between the metal stress relief buffer layer and the diffusion barrier layer.
The structure according to claim 1. The metal stress relief buffer layer is disposed in direct contact on the surface of the substrate
The structure according to claim 1. The substrate comprises silicon nitride,
The structure according to claim 1. The substrate is silicon oxynitride,
The structure according to claim 1. The metal stress relaxation buffer layer is titanium having a thickness greater than 500 angstroms.
The structure according to claim 1. The metal stress relief buffer layer extends laterally beyond at least one of the inner and outer edges of the metal seal ring by a length greater than 200 micrometers.
The structure according to claim 1. The metal stress relief buffer layer extends laterally beyond at least one of the inner and outer edges of the metal seal ring by a length greater than the height of the bonding material.
The structure according to claim 1. The height of the bonding material is about 11 micrometers,
A structure according to claim 10. The metal seal ring has a thickness on the order of 0.5 micrometers, and
The thickness of the metal stress relaxation buffer layer is from 500 angstroms to 2500 angstroms.
A structure according to claim 10. The metal seal ring includes a substrate adhesive layer and is completely spaced from the surface of the substrate by the metal stress relief buffer layer.
The structure according to claim 1. The bonding material has a eutectic temperature above 250 degrees Celsius,
The structure according to claim 1. A sealed package,
A substrate having a surface comprising silicon,
A device disposed on the surface of the substrate;
A metal seal ring disposed on the surface of the substrate with respect to the device, the metal seal ring being
An oxide block / junction material adhesion layer disposed on top of the metal seal ring;
A diffusion barrier layer disposed below the oxide block / junction material adhesion layer;
With metal seal rings, including
A bonding material disposed on the oxide block / bonding material adhesion layer of the metal seal ring;
A metal stress relief buffer layer disposed between the metal seal ring and the surface of the substrate, the bonding material having a yield strength as large as the yield strength of the metal stress relief buffer layer Having a metal stress relaxation buffer layer,
Lid structure,
Including
The bonding material and the metal seal ring cause the surface of the substrate to crack without the metal stress relaxation buffer layer,
The metal stress relieving buffer layer extends laterally beyond the bonding material by a length sufficient to prevent cracking of the substrate in bonding the metal seal ring to the lid structure using the bonding material. Form a spread and sealed package,
Sealed package. The metal stress relaxation buffer layer has a yield strength smaller than that of the bonding material.
The structure according to claim 1. The metal stress relaxation buffer layer has a yield strength smaller than that of the bonding material.
A sealed package according to claim 15. A sealed package,
A substrate having a surface comprising silicon,
A device disposed on the surface of the substrate;
A metal seal ring disposed on the surface of the substrate with respect to the device, the metal seal ring being
An oxide block / junction material adhesion layer disposed on top of the metal seal ring;
A diffusion barrier layer disposed below the oxide block / junction material adhesion layer;
A substrate adhesion layer disposed below the diffusion barrier layer;
With metal seal rings, including
A bonding material disposed on the oxide block / bonding material adhesion layer of the metal seal ring;
A metal stress relief buffer layer disposed between the substrate adhesive layer of the metal seal ring and the surface of the substrate;
Lid structure,
Including
The metal stress relief buffer layer extends laterally beyond at least one of the inner and outer edges of the metal seal ring.
Sealed package. The bonding material has a tensile strength as large as that of the metal stress relaxation buffer layer,
The sealed package of claim 18. The magnitude of the tensile strength of the bonding material is about 10 ² megapascals (MPa),
20. The sealed package of claim 19. The magnitude of the tensile strength of the bonding material is about 10 ² megapascals (MPa),
A sealed package according to claim 15. The magnitude of the tensile strength of the bonding material is about 10 ² megapascals (MPa),
The sealed package of claim 18.

Images