WO2021027121A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2021027121A1
WO2021027121A1 PCT/CN2019/116715 CN2019116715W WO2021027121A1 WO 2021027121 A1 WO2021027121 A1 WO 2021027121A1 CN 2019116715 W CN2019116715 W CN 2019116715W WO 2021027121 A1 WO2021027121 A1 WO 2021027121A1
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WIPO (PCT)
Prior art keywords
layer
metal wiring
barrier layer
display panel
substrate
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PCT/CN2019/116715
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English (en)
French (fr)
Inventor
何昆鹏
唐甲
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/626,345 priority Critical patent/US20210359064A1/en
Publication of WO2021027121A1 publication Critical patent/WO2021027121A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/341—Short-circuit prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the invention relates to the field of display technology, in particular to a display panel and a preparation method thereof.
  • OLED Organic Light-Emitting Diode
  • a planarization layer is usually made after the TFT (Thin Film Transistor) device is prepared.
  • the material of the planarization layer is generally an organic photosensitive photoresist, but TFT devices will use
  • metal with higher reflectivity will be exposed on the side of the metal traces, and the exposed metal will reflect the ultraviolet light irradiated by the exposure machine.
  • the reflected light will make the planarization layer absorb a certain amount of light energy and affect the planarization
  • the local film thickness of the layer causes burr-like protrusions on the surface of the negative flattening film or surface pits on the positive flattening layer. Severe bumps or pits will affect the performance of the OLED device or even cause the short circuit of the OLED device .
  • the metal film layer deposited on the substrate 10' is wet-etched to form a metal trace 20'.
  • the exposed metal reflects the light from the exposure machine above the TFT device, and the planarization layer 30' receives the reflected light energy, resulting in the formation of burr-like protrusions on the surface of part of the negative planarization layer 30'.
  • the anode 40', the pixel definition layer 50', the luminescent material layer 60', and the cathode 70' are sequentially prepared on the upper surface.
  • an uneven anode 40 is formed on the surface of the planarization layer 30' ', the surface of the anode 40' forms protrusions, which greatly increases the risk of short circuit between the cathode 70' and the anode 40'.
  • the present invention provides a display panel and a preparation method thereof to solve the problem of the existing display panel. Since a large number of metal traces are used in TFT devices, the sides of the metal traces generally have burr-like protrusions that reflect the exposure machine UV light, the planarization layer will absorb the light energy of the reflected light to a certain extent, affect the local film thickness on the surface of the planarization layer, and cause burr-like protrusions on the surface of the negative planarization layer or the positive planarization layer Surface pits, which in turn lead to short circuits of OLED devices, further affect display technical issues.
  • the present invention provides a display panel, including a substrate, a metal wiring layer provided on the substrate, an OLED light emitting layer, a barrier layer, and a planarization layer provided on the metal wiring layer; the metal The wiring layer includes a plurality of metal wirings; the barrier layer is arranged between the metal wiring layer and the OLED light-emitting layer; the planarization layer is arranged between the barrier layer and the OLED light-emitting layer Wherein, the barrier layer covers the metal wiring layer, and the material of the barrier layer is a photoresist material that absorbs ultraviolet light.
  • the barrier layer is a patterned grid structure, and the grid lines of the barrier layer cover the metal wiring in the metal wiring layer.
  • the barrier layer is a full-surface film structure.
  • a passivation layer is provided on a surface of the metal wiring layer facing away from the substrate.
  • the present invention provides another display panel, which includes a substrate, a metal wiring layer provided on the substrate, an OLED light emitting layer provided on the metal wiring layer, and a barrier layer; the metal wiring layer It includes a plurality of metal traces; the barrier layer is disposed between the metal trace layer and the OLED light-emitting layer; wherein, the barrier layer covers the metal trace layer.
  • the display panel further includes a planarization layer disposed between the barrier layer and the OLED light-emitting layer.
  • the barrier layer is a patterned grid structure, and the grid lines of the barrier layer cover the metal wiring in the metal wiring layer.
  • the barrier layer is a full-surface film structure.
  • the material of the barrier layer is a photoresist material that absorbs ultraviolet light.
  • a passivation layer is provided on a surface of the metal wiring layer facing away from the substrate.
  • the present invention also provides a method for manufacturing a display panel, including the following steps:
  • the barrier layer is a patterned grid structure, and the grid lines of the barrier layer cover the metal wiring in the metal wiring layer.
  • the S30 before the S30, it further includes: preparing a planarization layer on the barrier layer.
  • the material of the barrier layer is a photoresist material that absorbs ultraviolet light.
  • the barrier layer is a full-surface film structure.
  • the method before the S20, the method further includes: preparing a passivation layer on the metal wiring layer.
  • the beneficial effects of the present invention are: by providing a barrier layer capable of absorbing ultraviolet light on the metal traces, it can prevent the ultraviolet light of the exposure machine from irradiating the lower metal traces, thereby avoiding the bottom layer during the subsequent production of the planarization layer
  • the light reflected on the flattening layer causes the flattening layer to receive abnormal light energy locally and produces bumps or pits, thereby improving the flatness of the pixel definition area, and greatly reducing the unevenness of the film in the pixel. Risk of short circuit or abnormal performance of OLED devices.
  • FIG. 1 is a schematic diagram of the structure of a display panel in the prior art
  • FIG. 2 is a schematic diagram of the structure of the display panel according to the first embodiment of the present invention.
  • FIG. 3 is a flow chart of the steps of the manufacturing method of the display panel of the present invention.
  • 4 to 7 are schematic structural diagrams of the manufacturing process of the display panel of the first embodiment.
  • the present invention is aimed at the existing display panel. Since a large amount of metal is used in the TFT device, the side of the metal trace will have burr-like protrusions, which will reflect the ultraviolet light of the exposure machine, and the planarization layer is an organic photosensitive photoresist. It will absorb the light energy of the reflected light, affect the thickness of part of the planarization layer, and cause burr-like protrusions or pits on the surface of the planarization layer, which may affect the performance of the OLED device, and even cause the short circuit of the OLED device.
  • This embodiment can solve the technical problem that affects the display.
  • this embodiment provides a display panel, which includes a substrate 10, a metal wiring layer 20, a barrier layer 40, an OLED light-emitting layer 60, and a planarization layer 50.
  • the metal wiring layer 20 is disposed on the substrate
  • the OLED light-emitting layer 60 is disposed on the metal wiring layer 20
  • the barrier layer 40 is disposed on the metal wiring layer 20 and the substrate. Between the OLED light-emitting layers.
  • the metal wiring layer 20 includes a plurality of metal wirings 21, and the barrier layer 40 covers all the metal wirings 21 in the metal wiring layer 20.
  • the metal trace 21 As the patterned metal trace 21 is prepared by wet etching, the metal trace 21 will be exposed on the side surface of the metal film with higher reflectivity, forming burr-like protrusions, which will reflect the exposure machine above
  • the barrier layer 40 is arranged above the metal wiring layer 20 to absorb the ultraviolet light that is irradiated, so as to prevent the ultraviolet light from irradiating the metal wiring 21 in the lower layer, thereby avoiding the preparation of the During the planarization layer 50, when the ultraviolet light reflected from the bottom layer irradiates the planarization layer 50, it affects the local film thickness of the planarization layer 50, thereby providing a substrate with better flatness for preparing the OLED device .
  • the metal wiring 21 may be one or more of metal lines such as a source, a drain, a gate, a data line, and a scan line, and a plurality of the metal wiring 21 may be arranged in layers according to specific requirements.
  • the metal wiring layer 20 has a multilayer structure, and the barrier layer 40 is arranged in the multilayer structure far away from the substrate 10 Above the metal wiring layer 20 to ensure that the barrier layer 40 can cover all the metal wiring 21.
  • the material of the barrier layer 40 is a photoresist material that has strong absorption of ultraviolet light, and can also be other photoresist materials that have a low reflectivity and a dark color that blocks ultraviolet light from reaching the underlying metal.
  • the planarization layer 50 is disposed between the barrier layer 40 and the OLED light-emitting layer 60, and the planarization layer 50 provides a flat substrate for the OLED light-emitting layer 60.
  • the barrier layer 40 may be a full-surface film structure, covering the entire surface of the metal wiring layer 20.
  • the barrier layer 40 may be a patterned grid structure, but it should be ensured that the grid lines of the barrier layer 40 cover all the metal traces in the metal trace layer 20 twenty one.
  • the barrier layer 40 is a full-surface design and the upper surface has a good planarization effect, there is no need to provide the planarization layer 50.
  • the barrier layer 40 can be directly used as a flat substrate for the OLED device The surface preparation; if the barrier layer 40 is a grid-like structure design, the planarization layer 50 needs to be provided to provide a flat substrate for preparing OLED devices.
  • a passivation layer 30 is provided on a surface of the metal wiring layer 20 facing away from the substrate, and the passivation layer 30 is used to protect the metal wiring in the metal wiring layer 20.
  • the OLED light-emitting layer 60 includes an anode 61, an organic light-emitting material layer 62, and a cathode 63 which are sequentially disposed on the planarization layer 50.
  • the display panel 100 further includes a pixel definition layer 70 disposed on the planarization layer 50, and the pixel definition layer 70 is used to define a pixel area, so that the organic light emitting material layer 62 is vapor-deposited on the pixel area Inside.
  • the present embodiment provides a method for manufacturing the above-mentioned display panel 100, including:
  • a substrate 10 is provided, and a metal wiring layer 20 is provided on the substrate 10;
  • the substrate 10 may be a glass substrate, or a flexible substrate such as polyimide
  • the metal wiring layer 20 includes a plurality of metal wirings 21, such as metal wirings such as source and drain, data lines, etc. .
  • the method further includes preparing a passivation layer 30 on the metal wiring 21, and the material of the passivation layer 30 is silicon oxide, but is not limited to silicon oxide;
  • a photoresist material capable of absorbing ultraviolet light is deposited on the entire surface of the passivation layer 30 and covers the metal wiring layer 20 to form the barrier layer 40;
  • the barrier layer 40 can also be patterned to form a grid structure, and the grid lines of the barrier layer 40 cover the metal traces in the metal trace layer 20. It is ensured that the barrier layer 40 can block the ultraviolet light entering the lower metal layer.
  • the S30 further includes preparing a planarization layer 50 on the barrier layer 40 to provide a flat substrate for the subsequent preparation of the OLED light-emitting layer 60;
  • the bottom layer will not reflect the ultraviolet light of the exposure machine, and it will not cause the planarization layer 50 to receive abnormal light energy and produce burrs and convexities. Raises or pits, thereby improving the flatness of the pixel area, thereby greatly reducing the risk of short circuits or abnormal performance caused by the unevenness of the film in the pixel area;
  • an anode 61 is first prepared on the planarization layer 50, and the anode 61 is indium tin oxide or a laminated structure of indium tin oxide and other metals, but Not limited to these two structures, since the flatness of the planarization layer 50 is good, the formed film of the anode 61 has good flatness;
  • a pixel definition layer 70 is prepared on the planarization layer 50.
  • the pixel definition layer 70 defines a pixel area.
  • the pixel definition layer 70 can be a positive photosensitive photoresist or a negative photosensitive photoresist, but not Limited to this;
  • an organic light-emitting material layer 62 is prepared on the anode 61, and the organic light-emitting material layer 62 is formed in the pixel area;
  • a cathode 63 is formed on the organic light-emitting material layer 62, and the cathode 63 is a metal or alloy such as aluminum, silver, and magnesium.
  • Beneficial effects By providing a barrier layer that can absorb ultraviolet light on the metal traces, it can prevent the UV light of the exposure machine from irradiating the lower metal traces, thereby preventing the light from the bottom layer from being reflected to the lower metal traces when the planarization layer is subsequently produced.
  • the flattening layer On the flattening layer, the flattening layer will receive abnormal light energy locally and produce bumps or pits, thereby improving the flatness of the pixel definition area, and greatly reducing the unevenness of the film in the pixel, which causes short circuit or short circuit of the OLED device. Risk of abnormal performance.

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

一种显示面板，包括衬底、金属走线层、OLED发光层、以及阻挡层，阻挡层设置于金属走线层和OLED发光层之间，阻挡层覆盖所述金属走线层。通过在金属走线上设置能够吸收紫外光的阻挡层，可阻止曝光机的紫外光线照射到下层金属走线上，避免底层光线反射到平坦化层上，能够降低像素内的膜层不平坦度导致OLED器件短路或性能异常的风险。

Description

显示面板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及其制备方法。
 背景技术
随着OLED(Organic Light-Emitting Diode，有机发光二极管）技术的发展，制备OLED器件的方式分为蒸镀和打印两种，在阴极和阳极之间的OLED器件的厚度较小，通常厚度在100~500纳米，因此制备OLED器件的基底的平坦性尤为重要，像素定义区内过大或过陡的段差均会导致OLED器件的短路或性能异常。
为了填平像素定义内的段差，通常会在TFT(Thin Film Transistor，薄膜晶体管)器件制备完成后制作一层平坦化层，平坦化层的材料一般为有机光敏性光阻，但是TFT器件会使用到大量金属走线，金属走线的侧面会有反射率较高的金属露出，露出的金属会反射曝光机照射的紫外光线，反射的光线会使平坦化层吸收一定的光能量，影响平坦化层的局部膜层厚度，造成负型平坦化膜层表面的毛刺状突起或正型平坦化层的表面凹坑，严重程度的凸起或凹坑会影响OLED器件的性能甚至导致OLED器件的短路。
如图1所示，在衬底10’上沉积的金属膜层经过湿法刻蚀后形成金属走线20’，金属走线20’的侧面21’存在毛刺，会露出反射率较高的金属，露出的金属反射TFT器件上方的曝光机射进的光线，平坦化层30’接收反射的光能量，造成负型平坦化层30’的部分膜层表面形成毛刺状突起，在平坦化层30’上依次制备阳极40’、像素定义层50’、发光材料层60’、阴极70’，由于平坦化层30’的表面形成凸起，造成在平坦化层30’表面形成不平坦的阳极40’，阳极40’的表面形成凸起，导致阴极70’和阳极40’短路的风险大大增加。
 技术问题
本发明提供一种显示面板及其制备方法，以解决现有的显示面板，由于TFT器件中会使用到大量金属走线，而金属走线的侧面一般会有毛刺状凸起，会反射曝光机的紫外光线，平坦化层在一定程度上会吸收反射的光线的光能量，影响平坦化层表面的局部膜层厚度，造成负型平坦化膜层表面的毛刺状突起或正型平坦化层的表面凹坑，进而导致OLED器件的短路，进而影响显示的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种显示面板，包括衬底、设置于所述衬底上的金属走线层、设置于所述金属走线层上的OLED发光层、阻挡层、以及平坦化层；所述金属走线层包括多条金属走线；所述阻挡层设置于所述金属走线层和所述OLED发光层之间；所述平坦化层设置于所述阻挡层和所述OLED发光层之间；其中，所述阻挡层覆盖所述金属走线层，所述阻挡层的材料为吸收紫外光的光阻材料。
在本发明的一种实施例中，所述阻挡层为图案化的网格状结构，所述阻挡层的网格线覆盖所述金属走线层中的金属走线。
在本发明的一种实施例中，所述阻挡层为整面式的膜层结构。
在本发明的一种实施例中，所述金属走线层背离所述衬底的一侧表面设置有钝化层。
本发明提供另外一种显示面板，包括衬底、设置于所述衬底上的金属走线层、设置于所述金属走线层上的OLED发光层、以及阻挡层；所述金属走线层包括多条金属走线；所述阻挡层，设置于所述金属走线层和所述OLED发光层之间；其中，所述阻挡层覆盖所述金属走线层。
在本发明的一种实施例中，所述显示面板还包括设置于所述阻挡层和所述OLED发光层之间的平坦化层。
在本发明的一种实施例中，所述阻挡层为图案化的网格状结构，所述阻挡层的网格线覆盖所述金属走线层中的金属走线。
在本发明的一种实施例中，所述阻挡层为整面式的膜层结构。
在本发明的一种实施例中，所述阻挡层的材料为吸收紫外光的光阻材料。
在本发明的一种实施例中，所述金属走线层背离所述衬底的一侧表面设置有钝化层。
本发明还提供一种显示面板的制备方法，包括以下步骤：
S10，提供一衬底，所述衬底上设置有金属走线层；
S20，在所述金属走线层上制备阻挡层，其中，所述阻挡层覆盖所述金属走线层；
S30，在所述阻挡层上制备OLED发光层。
在本发明的一种实施例中，在所述S20中，所述阻挡层为图案化的网格状结构，所述阻挡层的网格线覆盖所述金属走线层中的金属走线。
在本发明的一种实施例中，在所述S30之前还包括：在所述阻挡层上制备平坦化层。
在本发明的一种实施例中，所述阻挡层的材料为吸收紫外光的光阻材料。
在本发明的一种实施例中，所述阻挡层为整面式的膜层结构。
在本发明的一种实施例中，在所述S20之前还包括：在所述金属走线层上制备钝化层。
 有益效果
本发明的有益效果为：通过在金属走线上设置一层能够吸收紫外光的阻挡层，能够阻止曝光机的紫外光线照射到下层金属走线上，进而在后续制作平坦化层时，避免底层的光线反射到平坦化层上，引起平坦化层局部接收光能异常而产生凸起或凹坑，进而提升像素定义区的平坦度，在很大程度上降低像素内的膜层不平坦度导致OLED器件短路或性能异常的风险。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的显示面板的结构示意图；
图2为本发明实施例一的显示面板的结构示意图；
图3为本发明的显示面板的制备方法的步骤流程图；
图4~图7为实施例一的显示面板的制备过程的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的显示面板，由于TFT器件中会使用到大量金属，而金属走线的侧面会有毛刺状凸起，会反射曝光机的紫外光线，平坦化层为有机光敏性光阻，会吸收反射的光线的光能量，影响平坦化层的部分膜层厚度，造成平坦化膜层表面的毛刺状凸起或凹坑，进而可能影响OLED器件的性能，甚至导致OLED器件的短路，从而影响显示的技术问题，本实施例能够解决该缺陷。
如图2所示，本实施例提供一种显示面板，包括衬底10、金属走线层20、阻挡层40、OLED发光层60、平坦化层50。
其中，所述金属走线层20设置于所述衬底上，所述OLED发光层60设置于所述金属走线层20上，所述阻挡层40设置于所述金属走线层20与所述OLED发光层之间。
所述金属走线层20包括多条金属走线21，所述阻挡层40覆盖所述金属走线层20中的全部金属走线21。
由于采用湿法刻蚀来制备图案化的所述金属走线21，导致所述金属走线21的侧面会露出反射率较高的金属膜层，形成毛刺状凸起，会反射上方的曝光机照射进的紫外光线，所述阻挡层40设置于所述金属走线层20的上方，可吸收这些紫外光线，避免这些紫外光线照射进下层所述金属走线21上，进而避免在制备所述平坦化层50时，底层反射回来的紫外光线照射到所述平坦化层50时，影响所述平坦化层50的局部膜层厚度，进而为制备所述OLED器件提供一个平坦度较好的基底。
所述金属走线21可为源极、漏极、栅极、数据线、以及扫描线等金属线中的一种或多种，多条所述金属走线21可根据具体需求分层设置。当多条所述金属走线21分层设置时，对应地，所述金属走线层20为多层结构，所述阻挡层40设置于所述多层结构中的远离所述衬底10的金属走线层20的上方，以保证所述阻挡层40能够覆盖所有的金属走线21。
所述阻挡层40的材料为对紫外光有强吸收的光阻材料，也可为低反射率的深色阻挡紫外光线照射到下层金属的其他光阻材料。
所述平坦化层50设置于所述阻挡层40和所述OLED发光层60之间，所述平坦化层50为所述OLED发光层60提供一平坦的基底。
在本实施例中，所述阻挡层40可为整面式的膜层结构，整面覆盖于所述金属走线层20上。
在其他实施例中，所述阻挡层40可为图案化的网格状结构，但需保证的是，所述阻挡层40的网格线覆盖所述金属走线层20中的全部金属走线21。
若所述阻挡层40为整面式设计且上表面平坦化效果较好，则不需要再设置所述平坦化层50，所述阻挡层40可直接作为一平坦的基底供所述OLED器件在其表面制备；若所述阻挡层40为网格状结构设计，则需要设置所述平坦化层50，为制备OLED器件提供一平坦的基底。
所述金属走线层20背离所述衬底的一侧表面设置有钝化层30，所述钝化层30用以保护所述金属走线层20中的金属走线。
所述OLED发光层60包括依次设置于所述平坦化层50上的阳极61、有机发光材料层62、以及阴极63。
所述显示面板100还包括设置于所述平坦化层50上的像素定义层70，所述像素定义层70用以限定出像素区，使得所述有机发光材料层62蒸镀于所述像素区内。
如图3所示，本实施例提供上述显示面板100的制备方法，包括：
如图4所示，S10，提供一衬底10，所述衬底10上设置有金属走线层20；
具体地，所述衬底10可为玻璃基板，也可为聚酰亚胺等柔性基板，所述金属走线层20包括多条金属走线21，例如源漏极、数据线等金属走线。
S20，在所述金属走线层20上制备阻挡层40，其中，所述阻挡层40覆盖所述金属走线层20；
在所述S20之前，还包括在所述金属走线21上制备钝化层30，所述钝化层30的材料为氧化硅，但不限于氧化硅；
在所述S20中，在所述钝化层30上整面沉积能够吸收紫外光的光阻材料，且覆盖所述金属走线层20，以用于形成所述阻挡层40；
在其他实施例中，还可对所述阻挡层40进行图案化设计，使其形成网格状结构，所述阻挡层40的网格线覆盖所述金属走线层20中的金属走线，保证所述阻挡层40能够遮挡进入下层金属层的紫外光线。
S30，在所述阻挡层40上制备OLED发光层60；
如图5所示，在所述S30之前，还包括在所述阻挡层40上制备平坦化层50，为后续制备所述OLED发光层60提供一平坦基底；
由于设置了一层所述阻挡层40，在制备所述平坦化层50时，底层不会有曝光机的紫外光反射回来，不会引起所述平坦化层50接收光能异常而产生毛刺凸起或凹坑，从而提升像素区的平坦度，进而大大降低由于像素区内膜层的不平坦导致的短路或性能异常的风险；
如图6和图7所示，在所述S30中，先在所述平坦化层50上制备阳极61，所述阳极61为氧化铟锡，或氧化铟锡与其他金属的叠层结构，但不限于这两种结构，由于所述平坦化层50的平坦性较好，因此形成的所述阳极61的膜层的平坦性较好；
再在所述平坦化层50上制备像素定义层70，所述像素定义层70限定出像素区，所述像素定义层70可为正性光敏性光阻或负性光敏性光阻，但不限于此；
之后在所述阳极61上制备有机发光材料层62，所述有机发光材料层62形成于所述像素区内；
最后在所述有机发光材料层62上形成阴极63，所述阴极63为铝、银、镁等金属或合金。
有益效果：通过在金属走线上设置一层能够吸收紫外光的阻挡层，能够阻止曝光机的紫外光线照射到下层金属走线上，进而在后续制作平坦化层时，避免底层的光线反射到平坦化层上，引起平坦化层局部接收光能异常而产生凸起或凹坑，进而提升像素定义区的平坦度，在很大程度上降低像素内的膜层不平坦度导致OLED器件短路或性能异常的风险。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种显示面板，其包括：
    衬底；
    金属走线层，设置于所述衬底上，所述金属走线层包括多条金属走线；
    OLED发光层，设置于所述金属走线层上；
    阻挡层，设置于所述金属走线层和所述OLED发光层之间；以及
    平坦化层，设置于所述阻挡层和所述OLED发光层之间；其中，
    所述阻挡层覆盖所述金属走线层，所述阻挡层的材料为吸收紫外光的光阻材料。
  2. 根据权利要求1所述的显示面板，其中，所述阻挡层为图案化的网格状结构，所述阻挡层的网格线覆盖所述金属走线层中的金属走线。
  3. 根据权利要求1所述的显示面板，其中，所述阻挡层为整面式的膜层结构。
  4. 根据权利要求1所述的显示面板，其中，所述金属走线层背离所述衬底的一侧表面设置有钝化层。
  5. 一种显示面板，其包括：
    衬底；
    金属走线层，设置于所述衬底上，所述金属走线层包括多条金属走线；
    OLED发光层，设置于所述金属走线层上；以及
    阻挡层，设置于所述金属走线层和所述OLED发光层之间；其中，
    所述阻挡层覆盖所述金属走线层。
  6. 根据权利要求5所述的显示面板，其中，所述显示面板还包括设置于所述阻挡层和所述OLED发光层之间的平坦化层。
  7. 根据权利要求6所述的显示面板，其中，所述阻挡层为图案化的网格状结构，所述阻挡层的网格线覆盖所述金属走线层中的金属走线。
  8. 根据权利要求5所述的显示面板，其中，所述阻挡层为整面式的膜层结构。
  9. 根据权利要求5所述的显示面板，其中，所述阻挡层的材料为吸收紫外光的光阻材料。
  10. 根据权利要求1所述的显示面板，其中，所述金属走线层背离所述衬底的一侧表面设置有钝化层。
  11. 一种显示面板的制备方法，其包括以下步骤：
    S10，提供一衬底，所述衬底上设置有金属走线层；
    S20，在所述金属走线层上制备阻挡层，其中，所述阻挡层覆盖所述金属走线层；
    S30，在所述阻挡层上制备OLED发光层。
  12. 根据权利要求11所述的制备方法，其中，在所述S20中，所述阻挡层为图案化的网格状结构，所述阻挡层的网格线覆盖所述金属走线层中的金属走线。
  13. 根据权利要求12所述的制备方法，其中，在所述S30之前还包括：在所述阻挡层上制备平坦化层。
  14. 根据权利要求11所述的制备方法，其中，所述阻挡层的材料为吸收紫外光的光阻材料。
  15. 根据权利要求11所述的制备方法，其中，所述阻挡层为整面式的膜层结构。
  16. 根据权利要求11所述的制备方法，其中，在所述S20之前还包括：在所述金属走线层上制备钝化层。
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