WO2021027092A1 - 薄膜晶体管及其制造方法 - Google Patents

薄膜晶体管及其制造方法 Download PDF

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WO2021027092A1
WO2021027092A1 PCT/CN2019/115430 CN2019115430W WO2021027092A1 WO 2021027092 A1 WO2021027092 A1 WO 2021027092A1 CN 2019115430 W CN2019115430 W CN 2019115430W WO 2021027092 A1 WO2021027092 A1 WO 2021027092A1
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active layer
layer
thin film
film transistor
source electrode
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French (fr)
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刘方梅
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to a metal oxide semiconductor device and a manufacturing method thereof, in particular to a back-channel etching type metal oxide thin film transistor and a manufacturing method thereof.
  • BCE Back channel etched metal oxide thin film transistors
  • the existing thin film transistor manufacturing method uses argon (Ar) plasma to bombard the IGZO target during IGZO coating, and controls the oxygen vacancy in IGZO through oxygen. (oxygen vacancy) concentration, and then the drain/source is made of metal material on IGZO.
  • Ar argon
  • the present invention provides a thin film transistor and a manufacturing method thereof to solve the problem that the thin film transistor in the prior art is prone to produce short channel effect.
  • one aspect of the present invention provides a thin film transistor, including: a substrate; a gate electrode disposed on the substrate; an insulating layer covering the gate electrode; a first active layer disposed On the insulating layer and above the gate, the material of the first active layer is a metal oxide filled with oxygen vacancies; a second active layer is arranged on the first active layer Above, the material of the second active layer is a metal oxide filled with oxygen vacancies with nitrogen; a source electrode is arranged on the second active layer; a drain electrode is arranged on the second active layer Above, the drain and the source are respectively located above the two opposite sides of the gate, each of the source and the drain has a metal nitride layer, and the metal nitride layer resists Connected to the second active layer; and a protective layer, covering the first active layer, the second active layer, the source electrode and the drain electrode.
  • each of the source electrode and the drain electrode has a metal portion, and the metal portion is away from the second active layer.
  • a thickness range of the first active layer has a first upper limit and a first lower limit
  • a thickness range of the second active layer has a second An upper limit value and a second lower limit value, the second upper limit value being equal to the first lower limit value
  • a thin film transistor which includes: a substrate; a gate electrode disposed on the substrate; an insulating layer covering the gate electrode; and a first active layer, Is arranged on the insulating layer and above the gate; a second active layer is arranged on the first active layer, and the material of the second active layer is a metal filled with oxygen vacancies with nitrogen Oxide; a source electrode disposed on the second active layer; a drain electrode disposed on the second active layer, the drain electrode and the source electrode are located opposite to the gate electrode Above the two sides; and a protective layer covering the first active layer, the second active layer, the source electrode and the drain electrode.
  • the material of the first active layer is a metal oxide filled with oxygen vacancies with oxygen.
  • each of the source electrode and the drain electrode has a metal nitride layer, and the metal nitride layer abuts against the second active layer.
  • each of the source electrode and the drain electrode has a metal portion, and the metal portion is away from the second active layer.
  • a thickness range of the first active layer has a first upper limit and a first lower limit
  • a thickness range of the second active layer has a second An upper limit value and a second lower limit value, the second upper limit value being equal to the first lower limit value
  • Another aspect of the present invention provides a method of manufacturing a thin film transistor, including: preparing a substrate; manufacturing a gate on the substrate; depositing an insulating layer, the insulating layer covering the gate; A metal oxide is deposited on the layer as a first active layer; a metal oxide is deposited on the first active layer as a second active layer, and argon is introduced during the deposition of the second active layer And nitrogen; fabricating a source and a drain on the second active layer; and depositing a protective layer that covers the first active layer, the second active layer, and the The source and the drain.
  • argon and oxygen are introduced during the deposition of the first active layer.
  • each of the source electrode and the drain electrode has a metal nitride layer, and the metal nitride layer abuts against the second active layer.
  • each of the source electrode and the drain electrode has a metal portion, and the metal portion is away from the second active layer.
  • a thickness range of the first active layer has a first upper limit and a first lower limit
  • a thickness range of the second active layer has a second An upper limit value and a second lower limit value, the second upper limit value being equal to the first lower limit value
  • the thin film transistor of the present invention and the manufacturing method thereof adopt a double-layer structure active layer, and argon and nitrogen are introduced during the deposition of the second active layer.
  • Nitrogen can stay in the second active layer more than oxygen to fill the oxygen vacancies, so that the effective channel length of the present invention is longer, which can be used to suppress the short channel effect and effectively improve the ease of use of single-layer structure thin film transistors. A situation where a short channel effect occurs.
  • FIG. 1 is a schematic diagram of a thin film transistor according to an embodiment of the invention.
  • FIG. 2 is a schematic diagram of another thin film transistor for comparison with the above-mentioned embodiment of the present invention.
  • the method of manufacturing a thin film transistor according to an embodiment of the present invention can be used to manufacture a back channel etch (BCE) type metal oxide thin film transistor.
  • the metal oxide may be indium gallium zinc oxide (IGZO), but not Within this limit, the metal oxide can also be selected from among zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), indium gallium oxide (IGO), indium zinc oxide (IZO), tin zinc oxide (ZTO) and indium zinc tin oxide (IZTO) or other materials.
  • IGZO is mainly used as an example for description. The following examples illustrate the implementation details of the above thin film transistor, but it is not limited thereto.
  • the thin film transistor of an embodiment of the present invention may include a substrate 1, a gate electrode 2, an insulating layer 3, a first active layer 4a, and a second active layer.
  • the gate electrode 2 may be disposed on the substrate 1; the insulating layer 3 may cover the gate electrode 2; the first active layer 4a may be disposed on the insulating layer 3 and located on the gate electrode 2 above; the second active layer 4b can be disposed on the first active layer 4a, the material of the second active layer 4b is a metal oxide filled with oxygen vacancy by nitrogen (N)
  • the source 5a can be provided on the second active layer 4b; the drain 5b can be provided on the second active layer 4b, the drain 5b and the source 5a are respectively Located above the two opposite sides of the gate electrode 2; the protective layer 6 can cover the first active layer 4a, the second active layer 4b, the source electrode 5a and the drain electrode 5b, In order to protect the first active layer 4a, the second active layer 4b, the source electrode 5a, and the drain electrode 5b from the external environment, specifically, the protection layer 6 may also cover the The insulating layer 3, for example, the protective layer 6 is deposited on the insulating layer 3.
  • the material of the substrate 1 may be glass or a flexible substrate material, etc.
  • the material of the gate electrode 2 may be a metal material, such as molybdenum titanium alloy and copper (Mo-Ti/Cu ) Mixture or molybdenum and copper (Mo/Cu) mixture, etc.
  • the material of the insulating layer 3 can be silicon oxide (SiOx) or silicon nitride (SiNx), where x is a reasonable amount.
  • the material of the first active layer 4a may be a metal oxide filled with oxygen vacancies with oxygen (O), for example: IGZO with oxygen ions filled with oxygen vacancies, etc.; the second active layer
  • the material of 4b can be a metal oxide with nitrogen (N) filling the oxygen vacancy, for example: IGZO with nitrogen ions filling the oxygen vacancy. Therefore, the electronegativity of nitrogen is weaker than that of oxygen, and nitrogen ions can be effectively used to fill the oxygen vacancies of the metal oxide, reduce the conductive area, and increase the length of the effective channel.
  • a thickness range of the first active layer 4a has a first upper limit (such as 400 ⁇ ) and a first lower limit (such as 200 ⁇ ), and the second active layer 4a
  • a thickness range of 4b has a second upper limit (for example, 200 ⁇ ) and a second lower limit (for example, 50 ⁇ ), and the second upper limit is equal to the first lower limit.
  • each of the source electrode 5a and the drain electrode 5b may be selected from materials such as copper (Cu), aluminum (Al), nickel (Ni), magnesium (Mg), chromium (Cr ), titanium (Ti), molybdenum (Mo), tungsten (W) or alloys thereof, each of the source electrode 5a and the drain electrode 5b has a metal nitride layer 51, such as titanium nitride (TiN ), the metal nitride layer 51 abuts against the second active layer 4b, the source electrode 5a and the drain electrode 5b may also have a metal part 52, such as molybdenum titanium alloy and copper (Mo- Ti/Cu) mixture, the metal part 52 is far away from the second active layer 4b, which can prevent undercuts.
  • a metal nitride layer 51 such as titanium nitride (TiN )
  • the metal nitride layer 51 abuts against the second active layer 4b
  • the thin film transistor of the above embodiment of the present invention adopts a double-layer structure active layer (such as IGZO), and the conductive area at the surface of the source electrode, the drain electrode and the second active layer only forms a relatively thin layer.
  • active layer such as IGZO
  • metal nitride With metal nitride, the conductive region becomes shorter, so that the effective channel length of a channel region between the two conductive regions becomes longer.
  • the manufacturing method of the thin film transistor of the above embodiment of the present invention may include the following steps: preparing a substrate 1; manufacturing a gate electrode 2 on the substrate 1; depositing an insulating layer (GI) 3.
  • the insulating layer 3 covers the gate electrode 2; the metal oxide is deposited on the insulating layer 3 as a first active layer 4a; the metal oxide is deposited on the first active layer 4a as a second Active layer 4b, argon and nitrogen are introduced during the deposition of the second active layer 4b; a source electrode 5a and a drain electrode 5b are fabricated on the second active layer 4b; and a protective layer is deposited (PV) 6, the protective layer 6 can cover the first active layer 4a, the second active layer 4b, the source electrode 5a, and the drain electrode 5b. Specifically, the protective layer 6 can also cover the insulating layer 3.
  • the substrate 1 is prepared, for example, the substrate 1 (such as a glass substrate) that can be used for manufacturing thin film transistors is cleaned and pre-baked to facilitate subsequent steps.
  • the substrate 1 such as a glass substrate
  • the gate electrode 2 is fabricated on the substrate 1.
  • the gate electrode 2 can be deposited on the substrate 1 by physical vapor deposition (PVD), and the material of the gate electrode 2 can be molybdenum titanium Alloy and copper (Mo-Ti/Cu), the thickness of the gate 2 can be between 3300 and 8000 ⁇ (angstrom, angstroms), and can be defined by patterning techniques (such as yellow light and etching techniques) Graphics.
  • the insulating layer 3 for example: deposit a layer of silicon oxide (SiOx) film on the gate 2 using plasma enhanced chemical vapor deposition (PECVD) as the insulating layer 3, but not
  • PECVD plasma enhanced chemical vapor deposition
  • SiNx silicon nitride
  • a metal oxide is deposited on the insulating layer 3 as the first active layer 4a, for example, a layer of IGZO is deposited on the insulating layer 3 by using PVD as the first active layer 4a.
  • a mixed gas of argon and oxygen (Ar/O2) is introduced, and the mixing ratio can be adjusted according to actual applications.
  • the deposition thickness of the first active layer 4a can be between 200 and 400 ⁇ .
  • a metal oxide is deposited on the first active layer 4a as the second active layer 4b.
  • another IGZO layer can be deposited by PECVD as the second active layer 4b.
  • the deposition process is The mixed gas of argon and nitrogen (Ar/N2) is introduced into the gas, the mixing ratio can be adjusted according to the actual application, the deposition thickness of the second active layer 4b can be between 50 to 200 ⁇ , and can be used such as Yellow light and etching technology define a pattern.
  • the source electrode 5a and the drain electrode 5b are fabricated on the second active layer 4b, for example: the source electrode 5a and the drain electrode 5b are deposited on the second active layer 4b by PVD, and the The material of the source electrode 5a and the drain electrode 5b can be, for example, Mo-Ti/Cu, etc.
  • the thickness of the source electrode 5a and the drain electrode 5b can be between 3300 to 8000 ⁇ , and can be defined by techniques such as yellow light and etching Create a graphic.
  • the protective layer 6 is deposited.
  • PECVD can be used to deposit at least one SiOx or SiNx or SiOx/SiNx film as the protective layer 6, and the thickness of the protective layer 6 can be between 1000 and 5000 ⁇ .
  • the active layer (such as IGZO) of the above-mentioned embodiment of the present invention adopts a double-layer structure, and the carrier gas of the first active layer 4a is argon and oxygen (Ar /O2) mixing; when the second active layer 4b is deposited and coated, the carrier gas is mixed with argon and nitrogen (Ar/N2), because nitrogen can fill the oxygen vacancy like oxygen, but the electronegativity of nitrogen is weaker than oxygen, Nitrogen is used instead of oxygen, so that the number of ions that chemically react with the metal elements of the source 5a and the drain 5b is small. For example, a small amount of nitrogen ions reacts with the titanium in the source electrode 5a and the drain electrode 5b, and the reaction of titanium with a large amount of oxygen ions is not as strong.
  • the source electrode 5a and the drain electrode 5b of the above-mentioned embodiment of the present invention only obtain a small amount of nitrogen around the plurality of conductive regions 41 of the second active layer 4b to form a relatively relatively small layer.
  • Thin metal nitrides (such as TiN) will have more nitrogen staying in the second active layer 4b to fill the oxygen vacancies, and the conductive regions 41 will become shorter, so that there is a gap between the conductive regions 41
  • the effective channel length L1 of the channel region 42 becomes longer.
  • another type of thin film transistor using a single-layer structure active layer includes, for example, a substrate 91, a gate electrode 92, an insulating layer 93, an active layer 94, a source electrode 95a, and a The drain 95b and a protection layer 96.
  • the source 95a/drain 95b is in contact with IGZO
  • the titanium monoxide (TiO) layer 951 and a metal portion 952 due to the more oxygen vacancies in the active layer 94, make the conductivity of the two conductive regions 941 around the titanium oxide layer 951 become higher, resulting in The length L2 of the effective channel of a channel region 942 between the two conductive regions 941 becomes shorter, so that a thin film transistor with a smaller channel design value is likely to produce a short channel effect.
  • the thin film transistor and the manufacturing method of the present invention adopt a double-layer structure active layer, and argon gas is introduced during the deposition of the second active layer.
  • nitrogen nitrogen can stay in the second active layer more than oxygen to fill the oxygen vacancies, making the effective channel length of the present invention longer (L1 in Figure 1 is greater than L2 in Figure 2), which can be used to suppress short Channel effect, effectively improving the short-channel effect of thin film transistors with single-layer structure.

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Abstract

一种薄膜晶体管及其制造方法，所述薄膜晶体管包括一基板（1）；一闸极（2），设置于所述基板（1）上；一绝缘层（3），覆盖所述闸极（2）；一第一有源层（4a），设置在所述绝缘层（3）上且位于所述闸极（2）上方；一第二有源层（4b），设置在所述第一有源层（4a）上，所述第二有源层（4b）的材料为由氮填补氧空缺的金属氧化物；一源极（5a），设置在所述第二有源层（4b）上；一漏极（5b），设置在所述第二有源层（4b）上，所述漏极（5b）与所述源极（5a）分别位于所述闸极（2）的相对二侧上方；及一保护层（6），包覆所述第一有源层（4a）、所述第二有源层（4b）、所述源极（5a）及所述漏极（5b）。

Description

薄膜晶体管及其制造方法 技术领域
本发明是有关于一种金属氧化物半导体元件及其制造方法，特别是有关于一种背沟道蚀刻型金属氧化物的薄膜晶体管及其制造方法。
 背景技术
背沟道蚀刻型(BCE)金属氧化物的薄膜晶体管(TFT)具有工艺简单、寄生电容小及开口率高等优点。随着显示器导入GOA技术，对TFT器件电学性能的均匀性和稳定性的要求日益迫切。
以利用所述金属氧化物(如IGZO)作为有源层为例，现有薄膜晶体管制造方法在IGZO镀膜时会通过氩(Ar)电浆轰击IGZO靶材，并通过氧气控制IGZO中的氧空缺(oxygen vacancy)浓度，后续再于IGZO上以金属材料制造漏极/源极。
以钼钛合金与铜(Mo-Ti/Cu)制作所述源极/漏极为例，因为IGZO中的氧与所述源极/漏极的钛会互相结合，在所述源极/漏极与IGZO的接触面形成一层氧化钛(TiO)，导致IGZO中的氧空缺变多，由于产生一个氧空缺会释放两个自由电子，使得氧化钛周围区域的有源层(即IGZO)的导电性变高，造成实际沟道长度变短，使得沟道设计值较小的薄膜晶体管容易产生短沟道效应(DIBL)。
因此，现有技术存在缺陷，亟需改进。
 技术问题
本发明提供一种薄膜晶体管及其制造方法，以解决现有技术所存在的薄膜晶体管易产生短沟道效应的问题。
 技术解决方案
为了解决上述问题，本发明的一方面提供一种薄膜晶体管，包括：一基板；一闸极，设置于所述基板上；一绝缘层，覆盖所述闸极；一第一有源层，设置在所述绝缘层上且位于所述闸极上方，所述第一有源层的材料为由氧填补氧空缺的金属氧化物；一第二有源层，设置在所述第一有源层上，所述第二有源层的材料为由氮填补氧空缺的金属氧化物；一源极，设置在所述第二有源层上；一漏极，设置在所述第二有源层上，所述漏极与所述源极分别位于所述闸极的相对二侧上方，所述源极及所述漏极中的每个具有一金属氮化物层，所述金属氮化物层抵接所述第二有源层；及一保护层，包覆所述第一有源层、所述第二有源层、所述源极及所述漏极。
在本发明的一实施例中，所述源极及所述漏极中的每个具有一金属部，所述金属部远离所述第二有源层。
在本发明的一实施例中，所述第一有源层的一厚度范围具有一第一上限值及一第一下限值，所述第二有源层的一厚度范围具有一第二上限值及一第二下限值，所述第二上限值等于所述第一下限值。
为了解决上述问题，本发明的另一方面提供一种薄膜晶体管，包括：一基板；一闸极，设置于所述基板上；一绝缘层，覆盖所述闸极；一第一有源层，设置在所述绝缘层上且位于所述闸极上方；一第二有源层，设置在所述第一有源层上，所述第二有源层的材料为由氮填补氧空缺的金属氧化物；一源极，设置在所述第二有源层上；一漏极，设置在所述第二有源层上，所述漏极与所述源极分别位于所述闸极的相对二侧上方；及一保护层，包覆所述第一有源层、所述第二有源层、所述源极及所述漏极。
在本发明的一实施例中，所述第一有源层的材料为由氧填补氧空缺的金属氧化物。
在本发明的一实施例中，所述源极及所述漏极中的每个具有一金属氮化物层，所述金属氮化物层抵接所述第二有源层。
在本发明的一实施例中，所述源极及所述漏极中的每个具有一金属部，所述金属部远离所述第二有源层。
在本发明的一实施例中，所述第一有源层的一厚度范围具有一第一上限值及一第一下限值，所述第二有源层的一厚度范围具有一第二上限值及一第二下限值，所述第二上限值等于所述第一下限值。
本发明的另一方面提供一种薄膜晶体管的制造方法，包括：准备一基板；在所述基板上制造一闸极；沉积一绝缘层，所述绝缘层覆盖所述闸极；在所述绝缘层上沉积金属氧化物作为一第一有源层；在所述第一有源层上沉积金属氧化物作为一第二有源层，沉积所述第二有源层的过程中通入氩气及氮气；在所述第二有源层上制造一源极及一漏极；及沉积一保护层，所述保护层包覆所述第一有源层、所述第二有源层、所述源极及所述漏极。
在本发明的一实施例中，沉积所述第一有源层的过程中通入氩气及氧气。
在本发明的一实施例中，所述源极及所述漏极中的每个具有一金属氮化物层，所述金属氮化物层抵接所述第二有源层。
在本发明的一实施例中，所述源极及所述漏极中的每个具有一金属部，所述金属部远离所述第二有源层。
在本发明的一实施例中，所述第一有源层的一厚度范围具有一第一上限值及一第一下限值，所述第二有源层的一厚度范围具有一第二上限值及一第二下限值，所述第二上限值等于所述第一下限值。
 有益效果
与其他技术(如采用单层结构有源层)相较，本发明的薄膜晶体管及其制造方法采用双层结构有源层，沉积所述第二有源层的过程中通入氩气及氮气，氮比氧更能停留在所述第二有源层中填补氧空缺，使得本发明的有效沟道的长度较长，可用于抑制短沟道效应，有效改善采用单层结构的薄膜晶体管容易产生短沟道效应的情况。
 附图说明
图1是本发明一实施例的薄膜晶体管的示意图。
图2是与本发明上述实施例作为对比的另一种薄膜晶体管的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
本发明一实施例的薄膜晶体管的制造方法可用于制造一种背沟道蚀刻(BCE)型金属氧化物的薄膜晶体管，例如：所述金属氧化物可以为氧化铟镓锌(IGZO)，但不以此为限，所述金属氧化物还可以选自诸如氧化锌(ZnO)、氧化铟(InO)、氧化镓(GaO)、氧化铟镓(IGO)、氧化铟锌(IZO)、氧化锡锌(ZTO)及氧化铟锌锡(IZTO)或其他材料，在本实施例中主要以IGZO为例进行说明，以下举例说明上述薄膜晶体管的实施细节，但不以此为限。
请参照图1所示，如图1所示，本发明一实施例的薄膜晶体管可包括一基板1、一闸极2、一绝缘层3、一第一有源层4a、一第二有源层4b、一源极5a、一漏极5b及一保护层6。所述闸极2可设置于所述基板1上；所述绝缘层3可覆盖所述闸极2；所述第一有源层4a可设置在所述绝缘层3上且位于所述闸极2上方；所述第二有源层4b可设置在所述第一有源层4a上，所述第二有源层4b的材料为由氮(N)填补氧空缺(oxygen vacancy)的金属氧化物；所述源极5a可设置在所述第二有源层4b上；所述漏极5b可设置在所述第二有源层4b上，所述漏极5b与所述源极5a分别位于所述闸极2的相对二侧上方；所述保护层6可包覆所述第一有源层4a、所述第二有源层4b、所述源极5a及所述漏极5b，以保护所述第一有源层4a、所述第二有源层4b、所述源极5a及所述漏极5b不受外界环境影响，具体地，所述保护层6还可覆盖所述绝缘层3，例如：在所述绝缘层3上沉积所述保护层6。
举例来说，如图1所示，所述基板1的材料可为玻璃或柔性基板材料等；所述闸极2的材料可为金属材料，例如：钼钛合金与铜(Mo-Ti/Cu)混合物或钼与铜(Mo/Cu)混合物等；所述绝缘层3的材料可为氧化硅(SiOx)或氮化硅(SiNx)，其中x为可合理存在的数量。
如图1所示，所述第一有源层4a的材料可为由氧(O)填补氧空缺的金属氧化物，例如：由氧离子填补氧空缺的IGZO等；所述第二有源层4b的材料可为由氮(N)填补氧空缺的金属氧化物，例如：由氮离子填补氧空缺的IGZO等。从而，可以利用氮的电负性比氧弱的特性，有效地利用氮离子填补金属氧化物的氧空缺，缩小导电区域，以增加有效沟道的长度。
在此实施例中，所述第一有源层4a的一厚度范围具有一第一上限值(如400 Å)及一第一下限值(如200 Å)，所述第二有源层4b的一厚度范围具有一第二上限值(如200 Å)及一第二下限值(如50 Å)，所述第二上限值等于所述第一下限值。
如图1所示，所述源极5a及所述漏极5b中的每个的材料可选自诸如铜(Cu)、铝(Al)、镍(Ni)、镁(Mg)、铬(Cr)、钛(Ti)、钼(Mo)、钨(W)或其合金，所述源极5a及所述漏极5b中的每个具有一金属氮化物层51，例如：氮化钛(TiN)等，所述金属氮化物层51抵接所述第二有源层4b，所述源极5a与所述漏极5b还可具有一金属部52，例如：钼钛合金与铜(Mo-Ti/Cu)的混合物，所述金属部52远离所述第二有源层4b，可防止出现底切(undercut)。
从而，本发明上述实施例薄膜晶体管采用双层结构有源层(如IGZO)，所述源极、漏极与所述第二有源层表面处的导电区域只会形成一层相对较薄的金属氮化物，所述导电区域变短，使得所述二导电区域之间的一沟道区域的有效沟道的长度变长。以下举例说明上述薄膜晶体管的制造方法，但不以此为限。
请再参照图1所示，本发明上述实施例的薄膜晶体管的制造方法可包括下列步骤：准备一基板1；在所述基板1上制造一闸极2；沉积一绝缘层(GI)3，所述绝缘层3覆盖所述闸极2；在所述绝缘层3上沉积金属氧化物作为一第一有源层4a；在所述第一有源层4a上沉积金属氧化物作为一第二有源层4b，沉积所述第二有源层4b的过程中通入氩气及氮气；在所述第二有源层4b上制造一源极5a及一漏极5b；及沉积一保护层(PV)6，所述保护层6可包覆所述第一有源层4a、所述第二有源层4b、所述源极5a及所述漏极5b，具体地，所述保护层6还可覆盖所述绝缘层3。
举例来说，如图1所示，首先，准备所述基板1，例如：将可用于制造薄膜晶体管的基板1(如玻璃基板)进行清洗和预烘烤，以利进行后续步骤。
接着，在所述基板1上制造所述闸极2，例如：可利用物理气相沉积法(PVD)在所述基板1上沉积所述栅极2，所述闸极2的材料可为钼钛合金与铜(Mo-Ti/Cu),所述闸极2的厚度可介于3300至8000 Å (angstrom，埃)之间，并可用图案化技术(诸如黄光及蚀刻技术等)定义出一图形。
接着，沉积所述绝缘层3，例如：在所述栅极2上利用等离子体增强化学气相沉积法(PECVD)沉积一层氧化硅(SiOx)薄膜作为所述绝缘层3，但不以此为限，也可改为沉积一层氮化硅(SiNx)薄膜作为所述绝缘层3，所述绝缘层3的厚度可介于1000至5000 Å之间。
接着，在所述绝缘层3上沉积金属氧化物作为所述第一有源层4a，例如：在所述绝缘层3上利用PVD沉积一层IGZO作为所述第一有源层4a层,其沉积过程中通入氩气与氧气(Ar/O2)的混合气体，其混合比例可依实际应用进行调整，所述第一有源层4a层的沉积厚度可介于200至400 Å之间。
接着，在所述第一有源层4a上沉积金属氧化物作为所述第二有源层4b，例如：可利用PECVD沉积另一层IGZO层作为所述第二有源层4b,其沉积过程中通入氩气与氮气(Ar/N2)的混合气体，其混合比例可依实际应用进行调整，所述第二有源层4b的沉积厚度可介于50至200 Å之间，并可用诸如黄光及蚀刻技术定义出一图形。
接着，在所述第二有源层4b上制造所述源极5a及漏极5b，例如：在所述第二有源层4b上利用PVD沉积所述源极5a及漏极5b，沉积所述源极5a及漏极5b的材料可例如为Mo-Ti/Cu等，所述源极5a及漏极5b的厚度可介于3300至8000 Å之间，并可用诸如黄光及蚀刻技术定义出一图形。
接着，沉积所述保护层6，例如：可利用PECVD沉积至少一层SiOx或SiNx或SiOx/SiNx薄膜作为所述保护层6，所述保护层6的厚度可介于1000至5000 Å之间。
应被注意的是，如图1所示，本发明上述实施例的有源层(如IGZO)采用双层结构，所述第一有源层4a沉积镀膜时载气采用氩气与氧气(Ar/O2)混合；所述第二有源层4b沉积镀膜时载气用氩气与氮气(Ar/N2)混合，由于氮跟氧一样可填补氧空缺，但氮的电负性比氧弱，采用氮气取代氧气，使得与所述源极5a及漏极5b的金属元素起化学反应的离子数量较少。例如：少量的氮离子与所述源极5a、漏极5b中的钛反应，不会像钛与大量的氧离子反应那么强烈。
从而，如图1所示，本发明上述实施例的所述源极5a、漏极5b在所述第二有源层4b的多个导电区域41周围只会取得少量的氮形成一层相对较薄的金属氮化物(如TiN)，将有更多的氮停留在所述第二有源层4b中填补氧空缺，所述导电区域41变短，使得在所述导电区域41之间的一沟道区域42的有效沟道的长度L1变长。
对比地，如图2所示，采用单层结构有源层的另一种薄膜晶体管例如包括一基板91、一闸极92、一绝缘层93、一有源层94、一源极95a、一漏极95b及一保护层96。因为有源层(如IGZO)94中的氧与所述源极95a/漏极95b(如Mo-Ti/Cu)的钛容易互相结合，在所述源极95a/漏极95b形成与IGZO接触的一氧化钛(TiO)层951及一金属部952，由于所述有源层94中的氧空缺较多，使得所述氧化钛层951周围的二导电区域941的导电性变高，造成所述二导电区域941之间的一沟道区域942的有效沟道的长度L2变短，使得沟道设计值较小的薄膜晶体管容易产生短沟道效应。
从而，与其他技术(如采用单层结构有源层)相较，本发明的薄膜晶体管及其制造方法采用双层结构有源层，沉积所述第二有源层的过程中通入氩气及氮气，氮比氧更能停留在所述第二有源层中填补氧空缺，使得本发明的有效沟道的长度比较长(如图1的L1大于图2的L2)，可用于抑制短沟道效应，有效改善采用单层结构的薄膜晶体管容易产生短沟道效应的情况。
综上所述，虽然本申请已经以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种薄膜晶体管，其包括：
    一基板；
    一闸极，设置于所述基板上；
    一绝缘层，覆盖所述闸极；
    一第一有源层，设置在所述绝缘层上且位于所述闸极上方，所述第一有源层的材料为由氧填补氧空缺的金属氧化物；
    一第二有源层，设置在所述第一有源层上，所述第二有源层的材料为由氮填补氧空缺的金属氧化物；
    一源极，设置在所述第二有源层上；
    一漏极，设置在所述第二有源层上，所述漏极与所述源极分别位于所述闸极的相对二侧上方，所述源极及所述漏极中的每个具有一金属氮化物层，所述金属氮化物层抵接所述第二有源层；及
    一保护层，包覆所述第一有源层、所述第二有源层、所述源极及所述漏极。
  2. 如权利要求1所述的薄膜晶体管，其中所述源极及所述漏极中的每个具有一金属部，所述金属部远离所述第二有源层。
  3. 如权利要求1所述的薄膜晶体管，其中所述第一有源层的一厚度范围具有一第一上限值及一第一下限值，所述第二有源层的一厚度范围具有一第二上限值及一第二下限值，所述第二上限值等于所述第一下限值。
  4. 一种薄膜晶体管，其包括：
    一基板；
    一闸极，设置于所述基板上；
    一绝缘层，覆盖所述闸极；
    一第一有源层，设置在所述绝缘层上且位于所述闸极上方；
    一第二有源层，设置在所述第一有源层上，所述第二有源层的材料为由氮填补氧空缺的金属氧化物；
    一源极，设置在所述第二有源层上；
    一漏极，设置在所述第二有源层上，所述漏极与所述源极分别位于所述闸极的相对二侧上方；及
    一保护层，包覆所述第一有源层、所述第二有源层、所述源极及所述漏极。
  5. 如权利要求4所述的薄膜晶体管，其中所述第一有源层的材料为由氧填补氧空缺的金属氧化物。
  6. 如权利要求4所述的薄膜晶体管，其中所述源极及所述漏极中的每个具有一金属氮化物层，所述金属氮化物层抵接所述第二有源层。
  7. 如权利要求6所述的薄膜晶体管，其中所述源极及所述漏极中的每个具有一金属部，所述金属部远离所述第二有源层。
  8. 如权利要求4所述的薄膜晶体管，其中所述第一有源层的一厚度范围具有一第一上限值及一第一下限值，所述第二有源层的一厚度范围具有一第二上限值及一第二下限值，所述第二上限值等于所述第一下限值。
  9. 一种薄膜晶体管的制造方法，其包括：
    准备一基板；
    在所述基板上制造一闸极；
    沉积一绝缘层，所述绝缘层覆盖所述闸极；
    在所述绝缘层上沉积金属氧化物作为一第一有源层；
    在所述第一有源层上沉积金属氧化物作为一第二有源层，沉积所述第二有源层的过程中通入氩气及氮气；
    在所述第二有源层上制造一源极及一漏极；及
    沉积一保护层，所述保护层包覆所述第一有源层、所述第二有源层、所述源极及所述漏极。
  10. 如权利要求9所述的薄膜晶体管的制造方法，其中沉积所述第一有源层的过程中通入氩气及氧气。
  11. 如权利要求9所述的薄膜晶体管的制造方法，其中所述源极及所述漏极中的每个具有一金属氮化物层，所述金属氮化物层抵接所述第二有源层。
  12. 如权利要求11所述的薄膜晶体管的制造方法，其中所述源极及所述漏极中的每个具有一金属部，所述金属部远离所述第二有源层。
  13. 如权利要求9所述的薄膜晶体管的制造方法，其中所述第一有源层的一厚度范围具有一第一上限值及一第一下限值，所述第二有源层的一厚度范围具有一第二上限值及一第二下限值，所述第二上限值等于所述第一下限值。
PCT/CN2019/115430 2019-08-09 2019-11-04 薄膜晶体管及其制造方法 Ceased WO2021027092A1 (zh)

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