WO2021022476A1

WO2021022476A1 - Waveguide structure, integrated optical chip, and method for realizing electrical isolation

Info

Publication number: WO2021022476A1
Application number: PCT/CN2019/099441
Authority: WO
Inventors: 邵海峰; 陈宏民
Original assignee: 华为技术有限公司
Priority date: 2019-08-06
Filing date: 2019-08-06
Publication date: 2021-02-11
Also published as: CN114128061A

Abstract

A waveguide structure, an integrated optical chip, and a method for realizing electrical isolation, wherein same are used to solve the problems of electrical crosstalk generated in an integrated optical chip and an increase in the power consumption of the integrated optical chip due to the different working voltages of different active optical devices. The waveguide structure comprises a substrate, a first doped layer, a second doped layer and a first waveguide core layer stacked in sequence from bottom to top, wherein the first waveguide core layer covers a partial region of the upper surface of the second doped layer; the second doped layer comprises an upper barrier layer and a sacrificial layer; the sacrificial layer is located between the upper barrier layer and the first waveguide core layer, and is used for supporting the upper barrier layer; the second doped layer is internally provided with at least one cavity, and the cavity penetrates through the second doped layer along the direction of extension of the cavity; the first waveguide core layer is located right above the cavity, and the direction of extension of the cavity is perpendicular to the direction of extension of the first waveguide core layer; and the doping type of the first doped layer and that of the second doped layer are opposite.

Description

Waveguide structure, integrated optical chip and method for realizing electrical isolation

Technical field

This application relates to the field of semiconductor technology, in particular to a waveguide structure, an integrated optical chip, and a method for achieving electrical isolation.

Background technique

With the rapid development of Internet technology, the amount of information has exploded, and optical communication technology is widely used in network data transmission to meet the requirements of network transmission performance.

As the core device of the optical module, the integrated optical chip plays an important role in optical communication. The integrated optical chip uses a semi-insulating substrate to integrate active optical devices such as lasers, modulators, semiconductor optical amplifiers (SOA), and detectors, and these active devices are connected by optical waveguides. These active optical devices usually share the same conductive layer (such as N-type doped layer or P-type doped layer), and active optical devices need to apply corresponding work on the shared conductive layer in the area where the active optical device is located. Voltage can achieve its own functions (such as modulation, amplification, detection, etc.). For active optical devices with different functions, different working voltages are usually applied, so that a voltage difference is formed between different regions of the shared conductive layer. There is current flowing between different areas of the shared conductive layer, which may increase the power consumption of the integrated optical chip, affect the normal operation of the integrated optical chip, and may also cause electrical crosstalk between two active optical devices with different working voltages .

For example, in current coherent optical communication, the laser, semiconductor optical amplifier, modulator in the integrated optical chip, and the optical waveguide connecting these active optical devices share the N-type doped layer. Among them, the modulator needs to be loaded with a forward voltage, such as +10V, on the N-type doped layer where the modulator is working, while the laser and optical amplifier need to be loaded with 0V voltage on the N-type doped layer when working, resulting in the modulator and the laser , There is a 10V voltage difference in the N-type doped layer between the amplifiers, which generates a lot of heat and power consumption.

Summary of the invention

This application provides a waveguide structure, an integrated optical chip, and a method for achieving electrical isolation, so as to solve the problem of electrical crosstalk in the integrated optical chip due to the different working voltages of different active optical devices in the integrated optical chip, and increase the power of the integrated optical chip. The problem of consumption.

In the first aspect, this application provides a waveguide structure, which is applied to an integrated optical chip. The waveguide structure includes a substrate, a first doped layer, a second doped layer, and a first waveguide core layer stacked in sequence from bottom to top, and the first waveguide core layer covers a part of the upper surface of the second doped layer . Wherein, the second doped layer includes an upper barrier layer and a sacrificial layer, and the sacrificial layer is located between the upper barrier layer and the first waveguide core layer for supporting the upper barrier layer. There is at least one cavity in the second doped layer, the cavity penetrates the second doped layer along the extension direction of the cavity, the first waveguide core layer is located directly above the cavity, and the extension direction of the cavity is the same as that of the first waveguide. The extending directions of the core layers are perpendicular to each other. The first doped layer can be an N-type doped layer or a P-type doped layer. When the first doped layer is an N-type doped layer, the second doped layer is a P-type doped layer. When the layer is a P-type doped layer, the second doped layer is an N-type doped layer, that is, the first doped layer and the second doped layer have opposite doping types.

Through the above solution, since the second doped layer of the waveguide structure has at least one cavity, and the thickness of the upper barrier layer directly above the cavity can be controlled to a smaller value according to actual requirements, the cavity can be increased. The impedance of the upper barrier layer directly above reduces the current transmitted by the upper barrier layer directly above the cavity in the direction extending along the waveguide core layer. In addition, the doping types of the first doped layer and the second doped layer are opposite, so that the waveguide structure is formed on opposite sides of the cavity and shares the substrate, the first doped layer and the second doped layer of the waveguide structure. A PNP structure or an NPN structure is formed between the active optical devices of the layer, and the PNP structure or the NPN structure is reversely cut off when the active optical device is working, further suppressing the transmission of the second doped layer in the direction extending along the waveguide core layer的current. Therefore, the waveguide structure provided by the embodiments of the present application can effectively suppress the current transmitted by the second doped layer in the direction along the waveguide core layer, and thus can realize the active structure formed on opposite sides of the cavity of the waveguide structure in the integrated optical chip. Electrical isolation between optical devices.

In a possible implementation manner, the projection of the first waveguide core layer on the plane of the bottom wall of the cavity is located in the bottom wall of the cavity, wherein the bottom wall of the cavity is a partial area of the upper surface of the first doped layer . In other words, the cavity is enclosed by the upper barrier layer, the sacrificial layer and the first doped layer.

In a possible embodiment, in order to further increase the electrical isolation effect of the waveguide structure, target ions are implanted in the upper barrier layer directly above the cavity, and the target ions are used to increase the upper barrier layer directly above the cavity的impedance. Wherein, the target ions may be ions such as helium ions that can increase the resistance of the blocking layer on the portion directly above the cavity.

Since the thickness of the upper barrier layer in the waveguide structure can be controlled according to actual needs, usually the thickness of the upper barrier layer is small, so the energy required for ion implantation is lower, which can solve the electrical isolation effect caused by the limitation of ion implantation energy on ion implantation depth The problem of poorness enables the target ions to be implanted as far as possible into the entire thickness range of the upper barrier layer directly above the cavity, thereby making the impedance of the upper barrier layer directly above the cavity larger, which can effectively isolate the electrical isolation .

In a possible embodiment, the thickness of the upper barrier layer directly above the cavity is less than or equal to a set value, and the set value is the maximum depth at which target ions can be implanted into the upper barrier layer directly above the cavity, to The target ions can be implanted into the entire thickness range of the upper barrier layer directly above the cavity.

In a possible embodiment, the waveguide structure further includes a third doped layer, the third doped layer is located above the first waveguide core layer, wherein the second doped layer is an N-type doped layer, and the third doped layer It is a P-type doped layer; or, the second doped layer is a P-type doped layer, and the third doped layer is an N-type doped layer. Further, the material of the third doped layer may be indium phosphide InP.

In a possible embodiment, the first doped layer includes a buffer layer and a lower barrier layer, the buffer layer is located between the lower barrier layer and the substrate; the bottom wall of the cavity is a partial area of the upper surface of the lower barrier layer.

In a second aspect, the present application also provides an integrated optical chip. The integrated optical chip includes the waveguide structure, the first active component, and the second active component described in any one of the possible implementations of the first aspect. The upper surface of the upper barrier layer is provided with a first active component and a second active component isolated from each other. The first active component and the second active component are respectively located on opposite sides of the cavity. Just below is a part of the sacrificial layer, directly below the second active component is another part of the sacrificial layer, the sacrificial layer directly below the first active component and the sacrificial layer directly below the second active component are separated by the cavity Come.

Wherein, the first active component includes a second waveguide core layer and a fourth doped layer stacked sequentially from bottom to top. The second active component includes a third waveguide core layer and a fifth doped layer stacked sequentially from bottom to top. , The second waveguide core layer and the third waveguide core layer are respectively connected with the first waveguide core layer. The second doped layer is an N-type doped layer, the fourth doped layer and the fifth doped layer are both P-type doped layers; alternatively, the second doped layer is a P-type doped layer, and the fourth doped layer And the fifth doped layer is an N-type doped layer.

In a possible embodiment, the first active component and the part of the waveguide structure directly below the first active component (including the second doped layer directly below the first active component, the first doped layer and the substrate ) To form the first active optical device, the second active component and the part of the waveguide structure directly below the second active component (including the second doped layer directly below the second active component, the first doped layer and The substrate) forms the second active optical device, that is, the first active optical device and the second active optical device share the substrate, the first doped layer and the second doped layer.

In a possible implementation, when the integrated optical chip is working, the voltage of the first active device is different from the voltage of the second active device. In particular, the voltage on the second doped layer in the first active device is different from the voltage on the second doped layer. The voltage on the second doped layer in the second active device is different.

In a possible implementation, the first active optical device may be a modulator, and the second active optical device may be a laser, an optical amplifier, or an optical detector.

In a possible implementation manner, in order to achieve electrical isolation of the first active optical device and the second active optical device in directions other than the extending direction of the first waveguide core layer, there are first The groove and the second groove, the first groove and the second groove all penetrate the second doped layer. Wherein, the first active optical device, the second active optical device and the isolation device are all located between the first groove and the second groove, and the isolation device includes a first waveguide core layer, a second doped layer, and a first doped The part of the impurity layer directly below the second doped layer and the part of the substrate directly below the second doped layer.

In the third aspect, this application also provides a method of electrical isolation, which is used to achieve electrical isolation between active optical devices in an integrated optical chip. The method includes: sequentially growing a first doped layer, a second doped layer, and a first waveguide core layer on a substrate, the first waveguide core layer covers a part of the upper surface of the second doped layer, and the second doping The layer includes an upper barrier layer and a sacrificial layer, the sacrificial layer is located between the first doped layer and the upper barrier layer; the first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer, or , The first doped layer is a P-type doped layer, the second doped layer is an N-type doped layer; the first waveguide core layer is etched to form a waveguide trench, the depth of the waveguide trench is greater than The thickness of the first waveguide core layer; the second doped layer exposed in the waveguide trench is etched to form at least one cavity in the second doped layer, and the remaining sacrificial layer after etching is used to support the upper barrier layer The cavity penetrates the second doped layer along the extending direction of the cavity, the first waveguide core layer is located directly above the cavity, and the extending direction of the cavity and the extending direction of the first waveguide core layer are perpendicular to each other.

In a possible implementation, the second doped layer exposed in the waveguide trench is etched to form at least one cavity in the second doped layer, which specifically includes the following steps: the upper barrier exposed in the waveguide trench The layer is etched to form at least one etch window; wherein the depth of the etch window is greater than the thickness of the upper barrier layer; an etchant is added to the at least one etch window to etch the sacrificial layer to form at least one cavity.

In a possible implementation, the second doped layer exposed in the waveguide trench is etched, and after at least one cavity is formed in the second doped layer, the method further includes: blocking the part directly above the cavity The target ions are implanted into the layer; wherein the target ions are used to increase the impedance of the barrier layer on the part directly above the cavity.

It is understandable that any of the integrated optical chips provided above includes the waveguide structure described in the first aspect, and any one of the foregoing methods for achieving electrical isolation can prepare the waveguide structure described in the first aspect. The beneficial effects that can be achieved can refer to the beneficial effects in the corresponding waveguide structure provided in the first aspect, which will not be repeated here.

Description of the drawings

1A is one of the three-dimensional schematic diagrams of a waveguide structure provided by an embodiment of the application;

FIG. 1B is one of the schematic cross-sectional views of a waveguide structure in the BB' direction according to an embodiment of the application;

FIG. 1C is one of the schematic cross-sectional views in the AA' direction of a waveguide structure according to an embodiment of the application;

FIG. 1D is the second cross-sectional schematic diagram of a waveguide structure in the AA' direction according to an embodiment of the application;

2 is a schematic diagram of the relationship between a waveguide structure and an active optical device according to an embodiment of the application;

3A is the second schematic diagram of a three-dimensional structure of a waveguide structure provided by an embodiment of this application;

3B is a schematic cross-sectional view of a waveguide structure in the CC' direction according to an embodiment of the application;

3C is the second schematic cross-sectional view of a waveguide structure in the BB' direction according to an embodiment of the application;

4A is the third schematic diagram of a three-dimensional structure of a waveguide structure provided by an embodiment of this application;

4B is the second schematic cross-sectional view of a waveguide structure in the AA' direction according to an embodiment of the application;

4C is the third schematic cross-sectional view of a waveguide structure in the BB' direction according to an embodiment of the application;

5A is a fourth schematic diagram of a three-dimensional structure of a waveguide structure provided by an embodiment of this application;

5B is the third schematic cross-sectional view of a waveguide structure in the AA' direction according to an embodiment of the application;

FIG. 5C is the fourth cross-sectional schematic diagram of a waveguide structure in the BB' direction according to an embodiment of the application;

6 is a fifth schematic diagram of a three-dimensional structure of a waveguide structure provided by an embodiment of this application;

FIG. 7A is one of the top schematic diagrams of an integrated optical chip provided by an embodiment of the application;

FIG. 7B is one of the schematic cross-sectional views in the AA' direction of an integrated optical chip according to an embodiment of the application;

FIG. 8 is a schematic structural diagram of a modulator provided by an embodiment of the application;

9A is the second schematic top view of an integrated optical chip provided by an embodiment of the application;

FIG. 9B is one of the schematic cross-sectional views of an integrated optical chip in the BB' direction according to an embodiment of the application;

10A is the third schematic top view of an integrated optical chip provided by an embodiment of this application;

10B is a fourth schematic top view of an integrated optical chip provided by an embodiment of this application;

10C is a fifth schematic top view of an integrated optical chip provided by an embodiment of the application;

FIG. 11 is a schematic flowchart of an electrical isolation method provided by an embodiment of the application;

FIG. 12 is a schematic diagram of the relationship between an ion implantation angle and the upper barrier layer provided by an embodiment of the application.

detailed description

Active optical devices such as lasers, modulators, SOA, and detectors integrated in integrated optical chips usually share the same conductive layer (such as N-type doped layer or P-type doped layer), while active optical devices need to share conductive layers. Only when the corresponding working voltage is applied to the area where the active optical device on the layer is located can its own functions (such as modulation, amplification, detection, etc.) be realized. For active optical devices with different functions, it is usually necessary to apply different working voltages to form a voltage difference between different regions of the shared conductive layer (because different regions of the shared conductive layer are respectively provided with active optical devices with different working voltages), This leads to an increase in the power consumption of the integrated optical chip, which affects the normal operation of the integrated optical chip. In addition, electrical crosstalk may also occur between two active optical devices with different operating voltages.

In the prior art, helium ion implantation is usually used to form electrical isolation between different regions of the conductive layer of the integrated optical chip. It should be known that the conductive layer of the integrated optical chip is shared by multiple active optical devices, and the multiple active optical devices are located in different regions of the conductive layer. However, the conductive layer shared by the active optical devices in the integrated optical chip is usually thicker, because when the conductive layer shared by the active optical devices in the integrated optical chip is thick, it has many benefits to the integrated optical chip, such as beneficial to the active optical chip. The loading of the bias voltage (or working voltage) on the device can reduce the resistance of the shared conductive layer in the active optical device and can increase the bandwidth of the modulator. However, due to the limited energy of ion implantation during helium ion implantation, the corresponding implantation depth is limited. For example, the implantation depth corresponding to the energy of 400keV is about 1.6um. Correspondingly, the greater the implantation depth, the higher the energy required, and the higher the cost of ion implantation. Therefore, only using the helium ion implantation method, the electrical isolation effect between the regions where different active optical devices are located in the conductive layer shared by the active optical devices in the integrated optical chip is poor.

In addition, the active optical devices in the integrated optical chip are connected by optical waveguides (or waveguide core layers), that is, the active optical devices in the integrated optical chip are optically connected through the waveguide core layer on the shared conductive layer, which also increases The difficulty of electrical isolation in the direction in which the waveguide core layer extends (the direction of optical signal propagation) between the regions where different active optical devices are located in the conductive layer shared by the active optical devices.

In order to solve the above-mentioned problems, the present application provides a waveguide structure for achieving electrical isolation between active optical devices in an integrated optical chip.

It should be noted that the multiple involved in this application refers to two or more. In addition, it should be understood that in the description of this application, words such as "first" or "second" are only used to distinguish the description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

1A is a three-dimensional schematic diagram of a waveguide structure 100 provided by this application. The waveguide structure 100 is applied to an integrated optical chip to realize the propagation direction of the optical signal of the active optical device in the integrated optical chip (that is, the optical waveguide in the integrated chip). Extension direction) electrical isolation. Referring to FIG. 1A, the waveguide structure 100 includes a substrate 110, a first doped layer 120, a second doped layer 130, and a first waveguide core layer 140 that are sequentially stacked from bottom to top. The first waveguide core layer 140 covers a partial area of the upper surface of the second doped layer 130.

It should be noted that in this application, the so-called upper surface of any layer (for example, the first doped layer 120) refers to the surface of the layer (for example, the first doped layer 120) facing upward, and any layer (for example, The lower surface of the first doped layer 120) refers to the surface of the layer (for example, the first doped layer 120) facing downward. It should be understood that the upper and lower surfaces of any layer are opposite. It should be understood that in this application, upper and lower are a pair of relative concepts, and the upper and lower refer to the current placement orientation of the drawings of this application. For example, as shown in FIG. 1A, the first doped layer 120 is located above the substrate 110 and below the second doped layer 130, and the first waveguide core layer 140 is located above the second doped layer 130.

The second doped layer 130 includes an upper barrier layer 131 and a sacrificial layer 132. The sacrificial layer 132 is located between the upper barrier layer 131 and the first waveguide core layer 140 and is used to support the upper barrier layer 131. There is at least one cavity 133 in the second doped layer 130. A cross-sectional view of the waveguide structure 100 in the BB' direction (the extending direction of the cavity 133) is shown in FIG. 1B. It can be seen from FIG. 1B that the cavity 133 runs along the cavity. The extending direction of the cavity 133 penetrates the second doped layer 130, the first waveguide core layer 140 is located directly above the cavity 133, and the extending direction of the cavity 133 and the extending direction of the first waveguide core layer 140 are perpendicular to each other.

The cross-sectional view of the waveguide structure 100 in the AA' direction (the extension direction of the first waveguide core layer 140) is shown in FIG. 1C. It can be seen from FIG. 1C that the cavity 133 is formed by the upper barrier layer 131, the sacrificial layer 132 and the first doped layer. A part of the upper surface of the upper barrier layer 131 is the top wall of the cavity 133, the side of the sacrificial layer 132 facing the cavity 133 is the side wall of the cavity 133, and the first doped layer 120 Part of the upper surface of the area is the bottom wall of the cavity 133. The projection of the first waveguide core layer 140 on the plane of the bottom wall of the cavity 133 is located in the bottom wall of the cavity 133. When the second doped layer 130 has one cavity 133, the sacrificial layer 132 includes two parts, as shown in FIG. 1C, when the second doped layer 130 has two or more cavities 133, the sacrificial layer 132 includes at least three parts. For example, when there are two cavities 133 in the second doped layer 130, the sacrificial layer 132 includes three parts, as shown in FIG. 1D.

The first doped layer 120 may be an N-type doped layer or a P-type doped layer. When the first doped layer 120 is an N-type doped layer, the second doped layer 130 is a P-type doped layer. When one doped layer 120 is a P-type doped layer, the second doped layer 130 is an N-type doped layer, that is, the doping types of the first doped layer 120 and the second doped layer 130 are opposite, so that the waveguide structure 100 The PNP structure or NPN structure is formed between the active optical devices that share the waveguide structure 100, the substrate 110, the first doped layer 120, and the second doped layer 130 formed on opposite sides of the cavity 133 (as shown in FIG. 2 (Shown), the PNP structure or the NPN structure is reversely cut off when the active optical device is working, which can prevent the active device from conducting conduction through the first doped layer 120 in the waveguide structure 100. Wherein, the upper barrier layer 131 and the sacrificial layer 132 have the same doping type, that is, when the second doped layer 130 is a P-type doped layer, the upper barrier layer 131 and the sacrificial layer 132 are both P-type doped layers. When the second doped layer 130 is an N-type doped layer, the upper barrier layer 131 and the sacrificial layer 132 are both N-type doped layers.

Further, the substrate 110 may be a semi-insulating (SI) substrate, and the material of the substrate 110 may be indium phosphide (InP). The waveguide core layer 140 is used to transmit optical signals, and the waveguide core layer 140 may be etched to form one or more parallel optical waveguides to transmit optical signals.

The waveguide structure 100 mainly realizes the electrical isolation between the active optical devices in the integrated optical chip through the area where the cavity 133 is located. According to the positional relationship between the upper barrier layer 131 and the cavity 133, the upper barrier layer 131 can be divided into a first part and a second part. There are two parts. The first part is the upper barrier layer 131 directly above the cavity 133, and the second part is the part directly above the sacrificial layer 132. In order to further increase the electrical isolation effect of the waveguide structure 100, the upper barrier layer 131 is located in the cavity 133. The upper part of the upper barrier layer 131 directly above, that is, the first part of the upper barrier layer, may also be implanted with target ions, and the target ions are used to increase the impedance of the upper barrier layer 131 in the part directly above the cavity 133. Wherein, the target ions may be ions such as helium ions that can increase the resistance of the blocking layer 131 on the portion directly above the cavity 133.

Since the thickness of the upper barrier layer 131 in the waveguide structure 100 can be controlled according to actual requirements (for example, 2 μm-10 μm), usually the thickness of the upper barrier layer 131 is small (may be less than 2 μm), so the energy required for ion implantation is low, which can solve The problem of poor electrical isolation caused by the limitation of ion implantation energy on the depth of ion implantation enables target ions to be implanted as far as possible into the entire thickness range of the upper barrier layer 131 located directly above the cavity 133, thereby making the cavity 133 positive. The upper barrier layer 131 above has a relatively large impedance, which can effectively isolate the electrical isolation.

In a specific implementation, the thickness of the upper barrier layer 131 directly above the cavity 133 is less than or equal to a set value, and the set value is the maximum depth that target ions can be implanted into the upper barrier layer directly above the cavity 133 to The target ions can be implanted into the entire thickness range of the upper barrier layer 131 directly above the cavity 133.

Further, the cavity 133 can be obtained by etching the sacrificial layer 132, that is, the reaction rate of the sacrificial layer 132 and the etchant is greater than the reaction rate of the upper barrier layer 131 and the etchant, so that the sacrificial layer 132 can be etched away , And the upper barrier layer 131 can be retained to form a cavity 133. The size of the cavity 133 can be controlled by the dose of the etchant and the etching time (that is, by controlling the volume of the sacrificial layer 132 etched away) The size of the cavity 133).

In a specific implementation, in order to etch the sacrificial layer 132 to form the cavity 133, it is necessary to first etch the upper barrier layer 131 to obtain an etch window. The depth of the etch window is greater than the thickness of the upper barrier layer 131 to avoid An etchant is injected into the window to etch the sacrificial layer 132. Therefore, as shown in FIGS. 3A to 3C, one or more etching windows 134 may be formed on the upper barrier layer 132, and these etching windows 134 are located Both sides of the waveguide core layer 140 or the same side. It should be noted that the embodiment of the present application does not limit the size, shape, and number of the etching window 134, and the etching window 134 may specifically be a rectangle, a rounded rectangle, a circle, or a triangle.

The material of the sacrificial layer 132 may be InGaAs, InAlAs, InAlAs, or three layers of InP, InAlAs, and InP. When the material of the sacrificial layer 132 is InGaAs or InAlAs, the material of the upper barrier layer 131 may be When the sacrificial layer 132 is composed of three layers of InP, InAlAs, and InP, the material of the upper barrier layer 131 may be InGaAs, InAlAs or InGaAsP InGaAsP.

Generally, the refractive index of the waveguide core layer 140 is greater than the refractive index of the material around the waveguide core layer 140 (for example, the second doped layer 130), forming a certain refractive index difference to confine the optical signal in the waveguide core layer 140 Transmission, reducing the leakage of optical signals. Therefore, in a scenario where the refractive index of the upper barrier layer 131 is close to the refractive index of the waveguide core layer 140 (for example, the current lower cladding layer), the second doped layer 130 may also include a lower cladding layer 135, which is located in the waveguide. Between the core layer 140 and the upper barrier layer 131, compared to the lower cladding layer 135, the upper barrier layer 131 is thinner. At this time, a three-dimensional schematic diagram of the waveguide structure 100 is shown in FIG. 4A, a cross-sectional view of the waveguide structure 100 in the AA' direction As shown in FIG. 4B, the cross-sectional view of the waveguide structure 100 in the BB' direction is as shown in FIG. 4C. Wherein, the material of the under-cladding layer 135 may be InP.

Further, the first doped layer 120 may include a buffer layer 121 and a lower barrier layer 122. The buffer layer 121 is located between the lower barrier layer 1221 and the substrate 110. At this time, a three-dimensional schematic diagram of the waveguide structure 100 is shown in FIG. 5A. The cross-sectional view of the waveguide structure 100 in the AA' direction is shown in FIG. 5B, and the cross-sectional view of the waveguide structure 10 in the BB' direction is shown in FIG. 5C. It can be seen from FIG. 5B that in the scenario where the first doped layer 120 includes the buffer layer 121 and the lower barrier layer 122, the bottom wall of the cavity 133 is a partial area of the upper surface of the lower barrier layer 122. Wherein, the buffer layer 121 is used to perform lattice matching on the substrate 110 to improve the quality of the material grown on the substrate 110. The doping types of the buffer layer 121 and the lower barrier layer 122 are the same. When the first doped layer 120 is a P-type doped layer, the doping types of the buffer layer 121 and the lower barrier layer 122 are also P-type doping. When the first doping layer 130 is an N-type doping layer, the doping types of the buffer layer 121 and the lower barrier layer 122 are also N-type doping.

The material of the buffer layer 121 is usually InP, and the material of the lower barrier layer 122 is usually the same as the material of the upper barrier layer 131, and may be InP, InGaAs, InAlAs, or the like. Therefore, the combination of materials used in the upper barrier layer 131, the sacrificial layer 132, and the lower barrier layer 122 includes but is not limited to any of the following: (1) the upper barrier layer 131 is InP, and the sacrificial layer 132 is InGaAs, The lower barrier layer 122 is InP; (2) the upper barrier layer 131 is InP, the sacrificial layer 132 is InAlAs, and the lower barrier layer 122 is InP; (3) the upper barrier layer 131 is InGaAs, and the sacrificial layer 132 is composed of InP, InAlAs, and It is composed of three layers of InP, the lower barrier layer 122 is InGaAs; (4) the upper barrier layer 131 is InAlAs, the sacrificial layer 132 is composed of InP, InAlAs and InP in sequence, and the lower barrier layer 122 is InAlAs. Wherein, when the lower barrier layer 122 is InP, the buffer layer 121 and the lower barrier layer 122 can be regarded as the same layer of material.

Further, as shown in FIG. 6, the waveguide structure 100 may further include a third doped layer 150 formed on the waveguide core layer 140. When the second doped layer 130 is an N-type doped layer, the third doped layer 150 is a P-type doped layer. When the second doped layer 130 is a P-type doped layer, the third doped layer 150 is an N-type doped layer, that is, the second doped layer 130 and the third doped layer 150 The doping type is opposite. The material of the third doped layer 150 may be InP.

Through the above solution, since the second doped layer 130 of the waveguide structure 100 has at least one cavity 133, and the thickness of the upper barrier layer 131 directly above the cavity 133 can be controlled to a smaller value according to actual requirements, The impedance of the upper barrier layer 131 directly above the cavity 133 is increased, and the current transmitted by the upper barrier layer 131 directly above the cavity 133 in the direction along which the waveguide core layer 140 extends is reduced. In addition, the first doped layer 120 and the second doped layer 130 have opposite doping types, so that the waveguide structure 100 is formed on opposite sides of the cavity 133 and shares the substrate 110 and the first doped layer of the waveguide structure 100. A PNP structure or an NPN structure is formed between the active optical device of the layer 120 and the second doped layer 130. When the active optical device is working, the PNP structure or the NPN structure is reversely cut off, further suppressing the second doping layer 130 A current that travels in the direction in which the core of the waveguide extends. Therefore, the waveguide structure 100 provided by the embodiments of the present application can effectively suppress the current transmitted by the second doped layer 130 in the extending direction of the waveguide core layer, and then can realize the integrated optical chip through the waveguide structure 100 on opposite sides of the cavity 133. The electrical isolation between the formed active optical devices.

Based on the above embodiments, the present application also provides an integrated optical chip 200. A top view is shown in FIG. 7A. The integrated optical chip 200 includes the waveguide structure 100 and the first active component 210 described in any one of the above possible embodiments. And second active component 220. As shown in FIG. 7B, the first active component 210 and the second active component 220 are disposed on the upper surface of the upper barrier layer of the waveguide structure 100, and the first active component 210 and the second active component 220 are respectively located in the cavity 133 On the two opposite sides of the first active device, just below the first active component is a part of the sacrificial layer 132, directly below the second active component 132 is another part of the sacrificial layer 132, and the sacrificial layer 132 directly below the first active component 210 The sacrificial layer 132 directly below the second active component 220 is separated by the cavity 133, that is, the sacrificial layer 132 is divided into at least two parts by the cavity 133.

Wherein, the first active component 210 includes a second waveguide core layer 211 and a fourth doped layer 212 stacked sequentially from bottom to top. The second active component 220 includes a third waveguide core layer 221 and a fourth doped layer stacked sequentially from bottom to top. The fifth doped layer 222, the second waveguide core layer 211 and the third waveguide core layer 221 are respectively connected to the first waveguide core layer 140.

The second doped layer 130 is an N-type doped layer, and the fourth doped layer 212 and the fifth doped layer 222 are both P-type doped layers; or, the second doped layer 130 is a P-type doped layer, The fourth doped layer 212 and the fifth doped layer 222 are both N-type doped layers.

Specifically, the first active component 210 and the part of the waveguide structure 100 directly below the first active component 210 (including the second doped layer 130 directly below the first active component 210, the first doped layer 120 and The substrate 110) forms the first active optical device 230, the second active component 220, and the portion of the waveguide structure 100 directly below the second active component 220 (including the second doping directly below the second active component 220). The layer 130, the first doped layer 120 and the substrate 110) form a second active optical device, that is, the first active optical device 230 and the second active optical device 240 share the substrate 110, the first doped The layer 120 and the second doped layer 130.

Furthermore, because when the integrated optical chip 200 is working, not all the active optical devices in the integrated optical chip 200 have a voltage difference between the second doped layers 130. Therefore, in order to save the cost of the integrated optical chip 200, and To reduce the processing complexity of the integrated optical chip 200, only active optical devices with a voltage difference between the second doped layers 130 during operation can be arranged on opposite sides of the cavity 133 and connected. That is to say, when the integrated optical chip 200 is working, the voltage of the first active device 230 is different from the voltage of the second active device 240, in particular, the voltage on the second doped layer 130 in the first active device 230 The voltage is different from the voltage on the second doped layer 130 in the second active device 240.

Further, the first active optical device 230 may be a modulator, and the second active optical device 240 may be a laser, an optical amplifier, or an optical detector. For example, when the first active device 230 is a modulator, as shown in FIG. 8, the modulator sequentially includes a substrate 110, a first doped layer 120, a second doped layer 130, a second waveguide core layer 211, and a first doped layer. Four doped layers 212. The second doped layer 130 is provided with a first electrode 213, and the fourth doped layer 212 is provided with a second electrode 214. The first doped layer 120 may be a P-type doped layer based on InP, and the second doped layer 130 may be an InP-based N-type doped layer, and the fourth doped layer 212 may be an InP-based P-type doped layer. When the modulator works, the voltage on the first electrode 213 is higher than the voltage on the second electrode 214, and the second waveguide core layer 211 performs electro-optic modulation based on the quantum confined stark effect (QCSE) or other photoelectric effects.

Further, in order to realize the electrical isolation of the first active optical device 230 and the second active optical device 240 in directions other than the extending direction of the first waveguide core layer 140, the first waveguide structure 100 has first The groove 250 and the second groove 260, the first groove 250 and the second groove 260 both penetrate the second doped layer 130, so that current cannot pass between the active devices except for the extending direction of the first waveguide core layer 140. The second doped layer 130 in the direction is transmitted. At this time, the top view of the integrated optical chip 200 is shown in FIG. 9A, and the cross-sectional view of the integrated optical chip 200 in the AA′ direction is shown in FIG. 9B.

Wherein, the first active optical device 230, the second active optical device 240, and the isolation device 270 are all located between the first groove 250 and the second groove 260. The isolation device 270 includes a first waveguide core layer 140, a second The doped layer 130, the portion of the first doped layer 120 directly below the second doped layer 130, and the portion of the substrate 110 directly below the second doped layer 130, as shown in FIG. 9B. In the scenario where the waveguide structure 100 includes the third doped layer 150, the isolation device 270 further includes the third doped layer 150 above the first waveguide core layer 140, that is, the isolation device 270 includes the third doped layer 150 above the first waveguide core layer 140. The doped layer 150, the first waveguide core layer 140, the second doped layer 130, the portion of the first doped layer 120 directly below the second doped layer 130, and the substrate 110 is located directly on the second doped layer 130 The lower part. The aforementioned waveguide structure 100 may be an isolation device 270.

In a specific implementation, the first groove 250 and the second groove 260 may also penetrate the first doped layer 120 on the substrate 110.

It should be noted that the embodiments of the present application do not limit the number of first active devices and the number of second active devices. Since there is no voltage difference between the plurality of first active optical devices 230 or the plurality of second active optical devices 240 in the integrated optical chip 200, the plurality of first active optical devices 230 or the plurality of second active optical devices The devices 240 may be located on the same side of the cavity 133, that is, between the plurality of first active optical devices 230 or between the plurality of second active optical devices 240 may not be electrically isolated by the cavity 133. For example, as shown in FIG. 10A, the modulator, laser, and optical amplifier included in the integrated optical chip 200 are located on opposite sides of the first cavity 133, and the modulator and the optical amplifier are located in the second cavity 133. On opposite sides; as shown in FIG. 10B, the modulator, laser, and optical amplifier included in the integrated optical chip 200, the modulator and the optical amplifier are respectively located on opposite sides of the cavity 133, the laser and the optical amplifier are located on the same side, by the integrated optical When the chip 200 is working, there is no voltage difference between the laser and the optical amplifier, so the laser and the optical amplifier do not need to be electrically isolated by the cavity 133; as shown in Figure 10C, the modulator, laser, and optical amplifier in the integrated optical chip 200 And the optical detector, the modulator and the optical amplifier are located on opposite sides of the cavity 133, and the laser, the optical detector and the optical amplifier are on the same side. When the integrated optical chip 200 works, there is no space between the laser, the optical detector and the optical amplifier. Because of the voltage difference, the laser, the photodetector and the optical amplifier can be electrically isolated without the cavity 133.

It should be understood that the integrated optical chip 200 provided by the embodiment of the present application is a complete integrated optical chip, and also has the structure of a known integrated optical chip (such as a driving circuit of an active optical device). The related structure of the optical chip involved in realizing the electrical isolation of the common doped layer of the active device in the integrated optical chip will be described, and other structures will not be repeated.

Based on the above embodiments, this application also provides a method for realizing electrical isolation between active optical devices in an integrated optical chip, that is, a method for preparing the waveguide structure 100. As shown in Figure 11, the method mainly includes the following steps:

S1101: The first doped layer 120, the second doped layer 130, and the first waveguide core layer 140 are sequentially grown on the substrate 110.

Wherein, the first waveguide core layer 140 covers a part of the upper surface of the second doped layer 130. The second doped layer 130 includes an upper barrier layer 131 and a sacrificial layer 132. The sacrificial layer 132 is located on the first doped layer 120 and above. Between the barrier layers 131; the first doped layer 120 may be an N-type doped layer or a P-type doped layer, when the first doped layer 120 is an N-type doped layer, the second doped layer 130 is a P-type Doped layer. When the first doped layer 120 is a P-type doped layer, the second doped layer 130 is an N-type doped layer, that is, the doping type of the first doped layer 120 and the second doped layer 130 in contrast.

S1102: Etching the first waveguide core layer 140 to form a waveguide trench. The depth of the waveguide groove is greater than the thickness of the first waveguide core layer 140 to expose the second doped layer 130 under the first waveguide core layer 140.

S1103: The second doped layer 130 exposed in the waveguide trench is etched, and at least one cavity 133 is formed in the second doped layer 130.

The sacrificial layer 132 remaining after etching is used to support the upper barrier layer 131, the cavity 133 penetrates the second doped layer 130 along the extending direction of the cavity 133, and the first waveguide core layer 140 is located directly above the cavity 133. The extension direction of the cavity 133 and the extension direction of the first waveguide core layer 140 are perpendicular to each other.

Further, in step S1103, etching the second doped layer 130 exposed in the waveguide trench to form at least one cavity 133 in the second doped layer 130 includes the following steps: i. Exposing the waveguide trench The upper barrier layer 131 is etched to form at least one etch window 134; wherein the depth of the etch window 134 is greater than the thickness of the upper barrier layer 131, so that the etchant can contact the sacrificial layer 132, and then to Etching is performed to form a cavity 133; ii, an etchant is added to at least one etching window to etch the sacrificial layer 132 to form at least one cavity 133. Specifically, when the second doped layer 130 exposed in the waveguide trench is etched, the area except for the etching window is protected by a mask.

After step S1103 is performed, the method further includes: implanting target ions into the upper barrier layer 131 directly above the cavity 133. Among them, the target ions are used to increase the impedance of the blocking layer 131 on the portion directly above the cavity 133.

In specific implementation, in order to make the portion of the upper barrier layer 131 directly above the cavity 133 directly below the first waveguide core layer 140 also be able to implant target ions, usually from a direction (ion The implantation angle) performs ion implantation, and selects appropriate ion implantation energy and dose according to the matching result of the implantation depth, ion implantation energy and dose, and implants target ions into the upper barrier layer 131 directly above the cavity 133.

Exemplarily, as shown in FIG. 12, when target ions are injected at the intersection point O of the upper barrier layer 131 directly below the first waveguide core layer 140 and the center line of the waveguide core layer 140 in the thickness direction at an angle α, The angle α, the width w of the waveguide core layer 140 and the ion implantation depth d satisfy the following formula:

The depth of ion implantation can be greater than or equal to

So that the upper barrier layer 131 located directly above the cavity 133 and directly below the first waveguide core layer 140 is implanted with target ions.

In summary, the embodiments of the present application provide a waveguide structure, an integrated optical chip, and an electrical isolation method. Using the solutions provided in the embodiments of the present application, electrical isolation between active optical devices in the integrated optical chip can be achieved, thereby reducing The power consumption and heat generation of the integrated optical chip ensure the normal operation of the integrated optical chip.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application also intends to include these modifications and variations.

Claims

A waveguide structure, which is characterized in that it is applied to an integrated optical chip. The waveguide structure includes a substrate, a first doped layer, a second doped layer, and a first waveguide core layer stacked in sequence from bottom to top. The first waveguide core layer covers a partial area of the upper surface of the second doped layer;

Wherein, the second doped layer includes an upper barrier layer and a sacrificial layer, the sacrificial layer is located between the upper barrier layer and the first doped layer and is used to support the upper barrier layer; The second doped layer has at least one cavity, the cavity penetrates the second doped layer along the extending direction of the cavity, the first waveguide core layer is located directly above the cavity, and the The extending direction of the cavity and the extending direction of the first waveguide core layer are perpendicular to each other;

The first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer; or, the first doped layer is a P-type doped layer, and the second doped layer is The layer is an N-type doped layer.
The waveguide structure according to claim 1, wherein the projection of the first waveguide core layer on the plane of the bottom wall of the cavity is located in the bottom wall of the cavity, wherein the cavity The bottom wall of is a partial area of the upper surface of the first doped layer.
The waveguide structure according to claim 1 or 2, wherein a part of the upper barrier layer directly above the cavity is implanted with target ions, and the target ions are used to increase the impedance of the upper barrier layer .
The waveguide structure of claim 3, wherein the thickness of the upper barrier layer is less than or equal to a set value, and the set value is the maximum depth at which the target ion can be implanted into the upper barrier layer .
The waveguide structure according to any one of claims 1 to 4, further comprising: a third doped layer, the third doped layer is located above the first waveguide core layer, wherein the The second doped layer is an N-type doped layer, and the third doped layer is a P-type doped layer; or, the second doped layer is a P-type doped layer, and the third doped layer is N-type doped layer.
The waveguide structure according to any one of claims 1-5, wherein the first doped layer comprises a buffer layer and a lower barrier layer, and the buffer layer is located between the lower barrier layer and the substrate. between;

The bottom wall of the cavity is a partial area of the upper surface of the lower barrier layer.
An integrated optical chip, characterized by comprising the waveguide structure according to any one of claims 1-6, a first active component and a second active component; wherein the upper surface of the upper barrier layer is provided with The first active component and the second active component are isolated from each other, the first active component and the second active component are respectively located on opposite sides of the cavity, and the first Immediately below the active component is a part of the sacrificial layer, and directly below the second active component is another part of the sacrificial layer;

The first active component includes a second waveguide core layer and a fourth doped layer that are sequentially stacked from bottom to top, and the second active component includes a third waveguide core layer and a fifth waveguide core layer that are stacked sequentially from bottom to top. A doped layer, wherein the second waveguide core layer and the third waveguide core layer are respectively connected to the first waveguide core layer;

The second doped layer is an N-type doped layer, and the fourth doped layer and the fifth doped layer are both P-type doped layers; or, the second doped layer is a P-type doped layer. The doped layer, the fourth doped layer and the fifth doped layer are both N-type doped layers.
8. The integrated optical chip of claim 7, wherein the first active component and the part of the waveguide structure directly below the first active component form a first active optical device;

The second active component and the portion of the waveguide structure directly below the second active component form a second active optical device.
The integrated optical chip according to claim 8, wherein a first groove and a second groove are respectively provided on both sides in the extending direction of the waveguide structure, the first groove and the second groove The grooves all penetrate the second doped layer, wherein the first active optical device, the second active optical device, and the isolation device are all located between the first groove and the second groove , The isolation device includes the second doped layer, the first waveguide core layer, a portion of the first doped layer directly below the second doped layer, and the substrate is located The part directly below the second doped layer.
9. The integrated optical chip according to claim 8 or 9, wherein when the integrated optical chip works, the voltage of the first active device is different from the voltage of the second active device.
The integrated optical chip according to any one of claims 8-10, wherein the first active optical device is a modulator, and the second active optical device is a laser, an optical amplifier, or an optical detector.
A method for realizing electrical isolation, characterized in that it is applied to an integrated optical chip, and the method includes:

A first doped layer, a second doped layer, and a first waveguide core layer are sequentially grown on a substrate; wherein the first waveguide core layer covers a partial area of the upper surface of the second doped layer, and The second doped layer includes an upper barrier layer and a sacrificial layer, the sacrificial layer is located between the first doped layer and the upper barrier layer, the first doped layer is an N-type doped layer, and the The second doped layer is a P-type doped layer; or, the first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer;

Etching the first waveguide core layer to form a waveguide trench, wherein the depth of the waveguide trench is greater than the thickness of the first waveguide core layer;

The second doped layer exposed in the waveguide trench is etched to form at least one cavity in the second doped layer; wherein the sacrificial layer remaining after etching is used to support the The above barrier layer, the cavity penetrates the second doped layer along the extending direction of the cavity, the first waveguide core layer is located directly above the cavity, and the extending direction of the cavity The extension direction of the first waveguide core layer is perpendicular to each other.
11. The method of claim 12, wherein etching the second doped layer exposed in the waveguide trench to form at least one cavity in the second doped layer comprises:

Etching the upper barrier layer exposed in the waveguide trench to form at least one etching window; wherein the depth of the etching window is greater than the thickness of the upper barrier layer;

An etchant is added to the at least one etching window to etch the sacrificial layer to form the at least one cavity.
The method of claim 12 or 13, wherein the second doped layer exposed in the waveguide trench is etched, and after at least one cavity is formed in the second doped layer ,Also includes:

Implanting target ions into the upper barrier layer located directly above the cavity; wherein the target ions are used to increase the impedance of the upper barrier layer located directly above the cavity.