CN116560114A

CN116560114A - Integrated circuit, preparation method thereof and electronic equipment

Info

Publication number: CN116560114A
Application number: CN202210099588.5A
Authority: CN
Inventors: 袁俊; 杨莉; 雷翔; 江先鑫; 胡志强
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-01-27
Filing date: 2022-01-27
Publication date: 2023-08-08

Abstract

The application discloses an integrated circuit, a preparation method thereof and electronic equipment. The integrated circuit comprises a PN junction structure, wherein the PN junction structure comprises a first P-type semiconductor region and a first N-type semiconductor region which are adjacently arranged along a first direction; the contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side, far away from the first N-type semiconductor region, of the first P-type semiconductor region relative to the reference plane; or the contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side of the first N-type semiconductor region far away from the first P-type semiconductor region relative to the reference plane; the reference plane is perpendicular to the first direction. Because the contact interface of the N region and the P region in the PN junction structure is inclined relative to the reference plane, compared with the traditional transverse PN junction structure, the area of the contact interface of the first N-type semiconductor region and the first P-type semiconductor region can be increased on the basis of not changing the whole volume of the PN junction structure, so that the range of the PN junction depletion region is enlarged.

Description

Integrated circuit, preparation method thereof and electronic equipment

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to an integrated circuit, a method for manufacturing the integrated circuit, and an electronic device.

Background

Electro-optic modulation plays an irreplaceable role in optical interconnection and optical communication systems, and electro-optic modulators are key devices for realizing electro-optic signal conversion. Conventional electro-optic modulation is implemented by changing the refractive index of a crystal by the action of an applied electric field, and the effect produced thereby is called an electro-optic effect. When the change in the refractive index of a crystal is proportional to the applied electric field, i.e. the first order of the electric field, this electro-optic effect is called a linear electro-optic effect, also called a Pokels effect, which generally occurs in crystals without a centre of symmetry.

In recent years, in order to solve bandwidth bottlenecks of electronic interconnects, optical interconnects are increasingly replacing electronic circuits to realize signal transmission between chips and inside chips. Photonic links that can be integrated on complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) chips are becoming a future research direction. As an important component in photonic links, integrable electro-optic modulators are of increasing interest. The silicon-based electro-optic modulator has the characteristics of small size, low cost, compatibility with the traditional CMOS process and the like, and is widely studied. Since silicon is a symmetrical crystal, the Pokels effect is not generated, the high-order electro-optic effect is weak, and the electro-optic modulation utilizes the plasma dispersion effect. When an electric signal is applied, the change of the concentration of free carriers in the silicon material causes the change of the refractive index of the silicon material, so that the transmission characteristic of light in the optical waveguide is changed, and the electro-optic modulation is realized through a certain optical structure, such as Mach-Zehnder-interferometer (MZI), and the like.

Taking a carrier depletion type Silicon-based electro-optic modulator as an example, the electro-optic modulator is based On a Silicon-On-Insulator (SOI) platform, and a PN junction is formed in a ridge optical waveguide of the platform by doping. When a modulation voltage is applied across the PN junction, the refractive index of the optical waveguide is adjusted depending on the free carrier dispersion effect of silicon. When a reverse bias voltage is applied across the PN junction, the width of the depletion region of the PN junction increases, causing the number of free carriers within the optical waveguide to decrease. Due to the free carrier dispersion effect, when the number of free carriers in the silicon material is reduced, the refractive index of silicon becomes large, so that the transmission spectrum of the electro-optical modulator is shifted, and the modulation function is realized. The region where the carrier concentration changes is concentrated in the depletion region near the PN junction. Thus, the overlapping area of the optical field spot and the PN junction depletion region is proportional to the modulation efficiency of the electro-optic modulator.

For the traditional transverse PN junction structure, the overlapping area of the light spot mode field and the PN depletion region is limited, so that the modulation efficiency is limited, and if the modulation efficiency is to be improved, the length of the ridge optical waveguide region needs to be increased; however, increasing the length of the ridge optical waveguide region will increase the total capacitance of the reverse biased PN junction, resulting in a limited bandwidth of the electro-optic modulator, thereby limiting the application and development of carrier-depleted silicon-based tunable electro-optic modulators in higher-rate and bandwidth optical communication chips.

Disclosure of Invention

The application provides an integrated circuit, a preparation method thereof and electronic equipment, and modulation efficiency is improved by improving overlapping area of a light spot mode field and a PN junction depletion region.

In the present application, the layer and the region prefixed with N or P means that electrons or holes are majority carriers, respectively.

In a first aspect, the present application provides an integrated circuit including a PN junction structure therein. The PN junction structure includes a first P-type semiconductor region and a first N-type semiconductor region disposed adjacently along a first direction. Taking a plane perpendicular to the first direction X as a reference plane: and the bottom edge of the contact interface between the first P-type semiconductor region and the first N-type semiconductor region is close to the reference plane, the contact interface between the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side, away from the first N-type semiconductor region, of the first P-type semiconductor region relative to the reference plane, namely, the distance between the contact interface between the first P-type semiconductor region and the first N-type semiconductor region and the reference plane Z at the top side is larger than the distance between the contact interface between the first P-type semiconductor region and the first N-type semiconductor region and the reference plane at the bottom side, and the distance between the contact interface at different positions from the bottom side to the top side and the reference plane tends to be increased.

Or, the bottom edge of the contact interface between the first P-type semiconductor region and the first N-type semiconductor region is close to the reference plane, the contact interface between the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side, away from the first P-type semiconductor region, of the first N-type semiconductor region relative to the reference plane, that is, the distance between the contact interface between the first P-type semiconductor region and the first N-type semiconductor region and the reference plane at the top side is larger than the distance between the contact interface between the first P-type semiconductor region and the first N-type semiconductor region and the reference plane at the bottom side, and the distance between the contact interface at different positions from the bottom side to the top side and the reference plane tends to increase.

Because the contact interface of the first type semiconductor region and the first N type semiconductor region in the PN junction structure is inclined relative to the reference plane, compared with the traditional transverse PN junction structure, the PN junction structure is an inclined PN junction structure, and the area of the contact interface of the first N type semiconductor region and the first P type semiconductor region can be increased on the basis of not changing the whole volume of the PN junction structure, so that the range of a PN junction depletion region is enlarged.

In the implementation, the P-type ions doped in the P-type semiconductor region may be 3-valent elements such As boron (B) or aluminum (Al), and the N-type ions doped in the N-type semiconductor region may be 5-valent elements such As phosphorus (P) or arsenic (As).

It should be noted that the contact interface between the first N-type semiconductor region and the first P-type semiconductor region may be a smooth and flat slope, or may be a slope that is not strictly defined, for example, a curved surface, which is not limited herein.

In the application, the larger the inclination angle theta of the contact interface of the first N-type semiconductor region and the first P-type semiconductor region relative to the reference plane is, the larger the area of the contact interface of the first N-type semiconductor region and the first P-type semiconductor region is, but the process difficulty is relatively large, the inclination angle theta of the contact interface of the first N-type semiconductor region and the first P-type semiconductor region relative to the reference plane is too small, and the contact interface is close to being parallel to the reference plane, so that the effect of increasing the area of the contact interface is small. Thus, exemplary, in the present application, the contact interface of the first N-type semiconductor region and the first P-type semiconductor region has an inclination angle θ with respect to the reference plane of 10 degrees or more and 80 degrees or less.

In the PN junction structure, the contact interface between the first P-type semiconductor region and the first N-type semiconductor region is inclined with respect to the reference plane toward the side of the first N-type semiconductor region away from the first P-type semiconductor region. The PN junction structure can also comprise a second P-type semiconductor region positioned on the first N-type semiconductor region, and the second P-type semiconductor region is contacted with the first P-type semiconductor region. Thereby further increasing the range of the depletion region in the PN junction structure. Illustratively, a side of the first P-type semiconductor region facing the first N-type semiconductor region is in contact with the second P-type semiconductor region.

For example, in the present application, the doping concentration of the second P-type semiconductor region may be similar to, but not limited to, the same doping concentration as that of the first P-type semiconductor region. Further, in the present application, the second P-type semiconductor region and the first P-type semiconductor region may be an integral structure.

In the PN junction structure, the contact interface between the first P-type semiconductor region and the first N-type semiconductor region is inclined toward the first P-type semiconductor region away from the first N-type semiconductor region with respect to the reference plane. The PN junction structure can also comprise a second N-type semiconductor region positioned on the first P-type semiconductor region, and the second N-type semiconductor region is contacted with the first N-type semiconductor region. Thereby further increasing the range of the depletion region in the PN junction structure.

Illustratively, a side of the first N-type semiconductor region facing the first P-type semiconductor region is in contact with the second N-type semiconductor region.

For example, in the present application, the doping concentration of the second N-type semiconductor region may be similar to, but not limited to, the same doping concentration as that of the first N-type semiconductor region.

Further, in the present application, the second N-type semiconductor region and the first N-type semiconductor region are in a unitary structure.

The integrated circuit provided by the embodiment of the application can be any electronic device and chip comprising a PN junction structure, for example, the integrated circuit is a processor or an optoelectronic modulator. An integrated circuit is schematically illustrated as an electro-optical modulator.

Illustratively, the electro-optic modulator includes a ridge-type optical waveguide, wherein the ridge-type optical waveguide includes a ridge and first and second bases on opposite sides of the ridge, respectively. The PN junction structure is arranged on the ridge. When a reverse bias voltage is applied across the PN junction, the width of the depletion region of the PN junction increases, causing a decrease in the number of free carriers within the ridge optical waveguide. Due to the free carrier dispersion effect, when the number of free carriers in the ridge part is reduced, the refractive index of the ridge part is increased, so that the transmission line of the electro-optical modulator is shifted, and the modulation function is realized.

In the electro-optical modulator, a first N-type semiconductor region of a PN junction structure is positioned on one side of a ridge portion close to a first base portion, and a first P-type semiconductor region is positioned on one side of the ridge portion close to a second base portion. When a reverse bias voltage is applied across the PN junction, the width of the depletion region of the PN junction increases, causing a decrease in the number of free carriers within the ridge optical waveguide. Due to the free carrier dispersion effect, when the number of free carriers in the ridge part is reduced, the refractive index of the ridge part is increased, so that the transmission line of the electro-optical modulator is shifted, and the modulation function is realized.

In the application, the contact interface of the first N-type semiconductor region and the first P-type semiconductor region is inclined relative to the reference plane. Compared with the traditional transverse PN junction structure, the inclined PN junction structure is formed on the ridge, the area of the contact interface between the first N-type semiconductor region and the first P-type semiconductor region can be increased on the basis that the length of the ridge-type optical waveguide is not changed, so that the cross-sectional area of the PN junction depletion region is increased, the overlapping area of the optical field spot and the PN junction depletion region is increased, and the modulation efficiency of the electro-optic modulator is improved.

Further, in the electro-optical modulator, a third N-type semiconductor region may be included in the first base, the third N-type semiconductor region having a doping concentration greater than that of the first N-type semiconductor region; the second base may include a third P-type semiconductor region therein having a doping concentration greater than the doping concentration of the first P-type semiconductor region.

In the present application, the comparison of the doping concentrations of the two regions refers only to the comparison of the concentrations of the impurities doped in the two regions, and the impurity components are not limited, that is, the impurity components may be the same or different.

In particular implementations, the electro-optic modulator may further include a fourth N-type semiconductor region and a fourth P-type semiconductor region. The fourth N-type semiconductor region is positioned on the third N-type semiconductor region, and the doping concentration of the fourth N-type semiconductor region is larger than that of the third N-type semiconductor region; the fourth P-type semiconductor region is positioned on the third P-type semiconductor region, and the doping concentration of the fourth P-type semiconductor region is larger than that of the third P-type semiconductor region. The fourth N-type semiconductor region and the fourth P-type semiconductor region are respectively used for subsequent connection with the electrode.

For example, the fourth N-type semiconductor region and the third N-type semiconductor region may be an integral structure, and the doping concentrations of the fourth N-type semiconductor region and the third N-type semiconductor region are different only by N-type ions. Similarly, the fourth P-type semiconductor region and the third P-type semiconductor region may be an integral structure, and the doping concentrations of the fourth P-type semiconductor region and the third P-type semiconductor region are different only by P-type ions.

In practice, the ridge type optical waveguide is generally formed on a semiconductor substrate having a uniform thickness, and thus the heights of the fourth N type semiconductor region, the fourth P type semiconductor region, and the ridge portion with respect to the bottom surface of the base portion are the same, which is not limited herein.

Further, the integrated circuit provided in the embodiments of the present application may be an optoelectronic chip, where the optoelectronic chip may include: the optical splitter includes an input waveguide, a splitter connected to the input waveguide, a modulation arm provided on each branch of the splitter for modulating a signal, a combiner connected to each branch of the splitter for combining the signals, and an output waveguide connected to the combiner. In the specific arrangement, the number of branches can be two, and the two branches are symmetrically arranged, namely, the two modulation arms are symmetrically arranged. When the optical fiber is particularly used, an input continuous optical signal enters from an input waveguide, is divided into two beams of light with equal power through a beam splitter, respectively passes through a modulation arm, then is combined through a beam combiner, and finally is output through an output waveguide.

Any of the above-described electro-optical modulators provided in the embodiments of the present application are disposed in the modulation arm. In practice, the arm lengths of the two modulation arms may be equal or unequal, with the purpose of unequal arm lengths to observe responses at different wavelengths. If the arm lengths are equal, the entire modulator can operate in a wider band.

In a second aspect, the present application also provides an electronic device comprising a circuit board and an integrated circuit as in the various embodiments of the first aspect, the integrated circuit being electrically connected to the circuit board. Since the principle of the electronic device for solving the problem is similar to that of the aforementioned integrated circuit, the implementation of the electronic device can be referred to the implementation of the aforementioned integrated circuit, and the repetition is omitted.

In a third aspect, the present application also provides a method for manufacturing an integrated circuit, which may include the steps of: providing a semiconductor substrate; then, N-type ions and P-type ions are respectively implanted into the semiconductor substrate to form a first P-type semiconductor region and a first N-type semiconductor region which are adjacently arranged along a first direction. The contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side, far away from the first N-type semiconductor region, of the first P-type semiconductor region relative to the reference plane; or the contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side of the first N-type semiconductor region far away from the first P-type semiconductor region relative to the reference plane; the reference plane is perpendicular to the first direction.

In one possible implementation manner, implanting N-type ions and P-type ions into a semiconductor substrate respectively to form a first P-type semiconductor region and a first N-type semiconductor region adjacently disposed along a first direction may include: performing P-type ion implantation on one side of the semiconductor substrate along a first direction to form a first P-type semiconductor region; forming a photoresist structure with gradually changed thickness by adopting a multi-gray-scale photomask, or forming a photoresist structure with inclined edge side surfaces by adjusting exposure energy and time; and performing N-type ion implantation on the other side of the semiconductor substrate along the first direction by taking the photoresist structure as an ion implantation masking layer to form a first N-type semiconductor region.

Illustratively, performing P-type ion implantation on one side of the semiconductor substrate along the first direction to form a first P-type semiconductor region may include: and performing P-type ion implantation on one side of the semiconductor substrate along the first direction and the bottom region of the semiconductor substrate to form a first P-type semiconductor region.

Optionally, after forming the first N-type semiconductor region and the first P-type semiconductor region in the semiconductor substrate, the method may further include: and performing N-type ion implantation on the region above the first P-type semiconductor region to form a second N-type semiconductor region.

In another possible implementation manner, implanting N-type ions and P-type ions into the semiconductor substrate respectively to form a first P-type semiconductor region and a first N-type semiconductor region adjacently disposed along the first direction may include: performing N-type ion implantation on one side of the semiconductor substrate along the first direction to form a first N-type semiconductor region; forming a photoresist structure with gradually changed thickness by adopting a multi-gray-scale photomask, or forming a photoresist structure with inclined edge side surfaces by adjusting exposure energy and time; and taking the photoresist structure as an ion implantation masking layer, and performing P-type ion implantation on the other side of the semiconductor substrate along the first direction to form a first P-type semiconductor region.

Illustratively, performing N-type ion implantation on one side of the semiconductor substrate along the first direction to form a first N-type semiconductor region may include: n-type ion implantation is performed on one side of the semiconductor substrate along the first direction and the bottom area of the semiconductor substrate to form a first N-type semiconductor region.

Optionally, after forming the first N-type semiconductor region and the first P-type semiconductor region in the semiconductor substrate, the method may further include: and performing P-type ion implantation on the region above the first N-type semiconductor region to form a second P-type semiconductor region.

Illustratively, when the integrated circuit is an electro-optic modulator, the semiconductor substrate may be a ridge-type optical waveguide including a ridge and first and second bases on either side of the ridge, respectively; implanting N-type ions and P-type ions, respectively, in the semiconductor substrate to form a first P-type semiconductor region and a first N-type semiconductor region disposed adjacently along the first direction may include: n-type ions and P-type ions are respectively injected into the ridge to form a first N-type semiconductor region and a first P-type semiconductor region, the first N-type semiconductor region is positioned at one side close to the first base, the first P-type semiconductor region is positioned at one side close to the second base, and the first direction is the direction that the first base points to the second base.

Further, after the N-type ions and the P-type ions are respectively implanted into the ridge portion to form the first N-type semiconductor region and the first P-type semiconductor region, the method may further include; forming a third N-type semiconductor region in the first base, wherein the doping concentration of the third N-type semiconductor region is greater than that of the first N-type semiconductor region; and forming a third P-type semiconductor region in the second base part, wherein the doping concentration of the third P-type semiconductor region is larger than that of the first P-type semiconductor region.

For example, the third N-type semiconductor region may be formed by performing N-type ion implantation on the first base portion using a conventional CMOS process, and the third P-type semiconductor region may be formed by performing P-type ion implantation on the second base portion using a conventional CMOS process.

In an implementation, after forming the third N-type semiconductor region in the first base portion, the method may further include: implanting N-type ions into a partial region of the third N-type semiconductor region to form a fourth N-type semiconductor region; after forming the third P-type semiconductor region in the second base, further comprising: and implanting P-type ions into a partial region of the third P-type semiconductor region to form a fourth P-type semiconductor region.

For example, a conventional CMOS process may be used to implant N-type ions into the end of the first base portion remote from the ridge portion to form a fourth N-type semiconductor region, such that the doping concentration of the fourth N-type semiconductor region is greater than the doping concentration of the second N-type semiconductor region. And performing P-type ion implantation on one end, far away from the ridge, of the second base part by adopting a conventional CMOS (complementary metal oxide semiconductor) process to form a fourth P-type semiconductor region, so that the doping concentration of the fourth P-type semiconductor region is greater than that of the second P-type semiconductor region.

The technical effects achieved by the second aspect and the third aspect may be described with reference to any possible design of the first aspect, and the description is not repeated here.

Drawings

FIG. 1 is a schematic structural diagram of an optoelectronic chip according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an electrical structure of an electro-optic modulator provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of an electro-optic modulator of a conventional lateral PN junction structure;

fig. 4 is a schematic structural diagram of a PN junction structure according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a PN junction structure according to another embodiment of the present application;

fig. 6 is a schematic structural diagram of a PN junction structure according to another embodiment of the present application;

fig. 7 is a schematic cross-sectional structure of a PN junction structure according to another embodiment of the present application;

fig. 8 is a schematic cross-sectional structure of a PN junction structure according to another embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of an electro-optic modulator according to one embodiment of the present application;

FIG. 10 is a schematic cross-sectional view of an electro-optic modulator according to another embodiment of the present application;

FIG. 11 is a schematic cross-sectional view of an electro-optic modulator according to another embodiment of the present application;

FIG. 12 is a schematic cross-sectional view of an electro-optic modulator according to another embodiment of the present application;

FIG. 13 is a flow chart of a method for fabricating an integrated circuit according to an embodiment of the present disclosure;

FIG. 14 is a flow chart of another method for fabricating an integrated circuit according to an embodiment of the present disclosure;

Fig. 15 is a schematic flow chart of a method for manufacturing an electro-optical modulator according to an embodiment of the present application;

fig. 16a to 16d are schematic structural views illustrating a process for manufacturing a ridge optical waveguide according to an embodiment of the present application;

fig. 17a to 17g are schematic structural diagrams illustrating a manufacturing process of an electro-optical modulator according to an embodiment of the present application;

FIGS. 18a to 18g are schematic diagrams illustrating a process for fabricating an electro-optic modulator according to another embodiment of the present disclosure;

FIGS. 19a to 19d are schematic views showing a process for manufacturing an electro-optic modulator according to an embodiment of the present application;

fig. 20a to 20d are schematic structural views illustrating a manufacturing process of another electro-optical modulator according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings.

In order to facilitate understanding of the integrated circuit provided in the embodiments of the present application, an application scenario thereof will be first described below. The integrated circuit may be used in the optoelectronic field, for example, as an optoelectronic chip. For example, referring to fig. 1, an optoelectronic chip may include: an input waveguide 11, a beam splitter 12 connected to the input waveguide 11, a modulation arm provided on each branch of the beam splitter 12 for modulating a signal, a beam combiner 13 connected to each branch of the beam splitter 12 for combining the signals, and an output waveguide 14 connected to the beam combiner 13. When the optical fiber is specifically used, an input continuous optical signal enters from an input waveguide 11, is split into two beams of light with equal power through a beam splitter 12, passes through a modulation arm respectively, then is combined through a beam combiner 13, and finally is output through an output waveguide 14. Wherein the modulation arm comprises an electro-optic modulator 10, and the electro-optic modulator 10 is a PN junction structure formed by doping a ridge optical waveguide on an SOI platform.

The electrical structure of the electro-optic modulator is shown in fig. 2 as a PN junction operating in reverse bias mode. When zero bias voltage is applied, the optical waveguide is internally provided with P-type doped ions and N-type doped ions with certain concentration; when reverse bias is applied, the depletion region expands, the built-in electric field increases, the carrier concentration in the optical waveguide becomes low, the effective refractive index of the corresponding optical waveguide becomes large, and the loss becomes small. Therefore, the phase difference of the two paths can be changed by adjusting the voltages of the two modulation arms, and the final output light intensity is further adjusted.

The current use of electro-optic modulator 10 is as shown in figure 3Lateral PN junction structure, i.e. contact interface of P-type semiconductor region (P region) and N-type semiconductor region (N region) and SiO ₂ The layer surface is vertical, and the region where the carrier concentration changes is concentrated in the depletion region (rectangular dotted line box in the figure) near the PN junction. Because the overlapping area of the light field mode spot (elliptic dotted line frame in the figure) and the PN junction depletion region is proportional to the modulation efficiency of the modulator, the overlapping area of the light spot mode field and the PN depletion region is limited, the modulation efficiency is limited, and if the modulation efficiency is to be improved, the length of the ridge optical waveguide region needs to be increased; however, increasing the length of the ridge optical waveguide region will increase the total capacitance of the reverse biased PN junction, resulting in a limited bandwidth of the electro-optic modulator, thereby limiting the application and development of the electro-optic modulator in higher rate and bandwidth optical communication chips.

Based on this, the embodiment of the application provides an integrated circuit, which improves the overlapping area of a facula mode field and a PN junction depletion region and improves the modulation efficiency by improving the depletion region range of the PN structure of a contact area increasing region of a P region and an N region in the PN structure.

The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary. It should also be understood that in the various embodiments herein below, "at least one", "one or more" means one, two or more than two. The term "and/or" is used to describe an association relationship of associated objects, meaning that there may be three relationships; for example, a and/or B may represent: a alone, a and B together, and B alone, wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

In the present application, the layer and the region prefixed with N or P means that electrons or holes are majority carriers, respectively. In addition, "+" marked with N or P indicates that the doping concentration is higher than that of the unmarked layer or region, and the greater the number of "+" indicates that the doping concentration is higher. N or P containing the same number of "+" is indicated as similar doping concentration and is not limited to the same doping concentration.

In the integrated circuit provided in the embodiment of the present application, the PN junction structure is included, referring to fig. 4 and 5, fig. 4 is a schematic structural diagram of the PN junction structure 1000 provided in one embodiment of the present application, and fig. 5 is a schematic structural diagram of the PN junction structure provided in another embodiment of the present application. The PN junction structure 1000 includes a first P-type semiconductor region 1001 (i.e., P-region) and a first N-type semiconductor region 1002 (i.e., N-region) disposed adjacent to each other along a first direction X. Taking a plane perpendicular to the first direction X as a reference plane Z:

as shown in fig. 4, the bottom edge (Z-side in the drawing) of the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 is close to the reference plane Z, and the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 is inclined toward the first P-type semiconductor region 1001 away from the first N-type semiconductor region 1002 side (x+ side in the drawing) with respect to the reference plane Z, that is, the distance between the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 at the top side (z+ side in the drawing) and the reference plane Z is greater than the distance between the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 at the bottom side (Z-side in the drawing) and the reference plane Z, and the distance between the contact interface and the reference plane Z at different positions from the bottom side (Z-side) to the top side (z+ side) tends to increase.

Alternatively, as shown in fig. 5, the bottom edge (Z-side in the drawing) of the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 is close to the reference plane Z, and the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 is inclined toward the first N-type semiconductor region 1002 away from the first P-type semiconductor region 1001 side (X-side in the drawing) with respect to the reference plane Z, that is, the distance between the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 and the reference plane Z at the top side (z+ side in the drawing) is greater than the distance between the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 and the reference plane Z at the bottom side (Z-side in the drawing), and the distance between the contact interface and the reference plane Z at different positions from the bottom side (Z-side) to the top side (z+ side) tends to increase.

It should be noted that the contact interface between the first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) may be, for example, a slope as shown in fig. 4, or may be a slope that is not strictly defined, for example, a curved surface as shown in fig. 6, which is not limited herein.

In the integrated circuit provided in the application, because the contact interface between the first P-type semiconductor region 1001 and the first N-type semiconductor region 1002 in the PN junction structure 1000 is inclined with respect to the reference plane Z, compared with the conventional lateral PN junction structure, the PN junction structure of the application is an inclined PN junction structure, and the area of the contact interface between the first N-type semiconductor region 1002 and the first P-type semiconductor region 1001 can be increased on the basis of not changing the volume of the PN junction structure 1000, thereby increasing the range of the PN junction depletion region.

In this application, the larger the inclination angle θ of the contact interface between the first N-type semiconductor region 1002 and the first P-type semiconductor region 1001 with respect to the reference plane Z, the larger the area of the contact interface between the first N-type semiconductor region 1002 and the first P-type semiconductor region 1001, but the more difficult the process, the smaller the inclination angle θ of the contact interface between the first N-type semiconductor region 1002 and the first P-type semiconductor region 1001 with respect to the reference plane Z, the contact interface is close to being parallel to the reference plane Z, so that the effect of increasing the area of the contact interface is smaller. Thus, exemplary, in the present application, the contact interface of the first N-type semiconductor region 1002 and the first P-type semiconductor region 1001 has an inclination angle θ with respect to the reference plane Z of 10 degrees or more and 80 degrees or less.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a PN junction structure 1000 according to another embodiment of the present application, in the PN junction structure 1000, a contact interface between a first P-type semiconductor region 1001 and a first N-type semiconductor region 1002 is inclined toward a side of the first N-type semiconductor region 1002 away from the first P-type semiconductor region 1001 with respect to a reference plane Z. The PN junction structure 1000 may further include a second P-type semiconductor region 1003 (i.e., a P' region) located on the first N-type semiconductor region 1002, and the second P-type semiconductor region 1003 is in contact with the first P-type semiconductor region 1001. Thereby further increasing the range of the depletion region in the PN junction structure 1000.

Illustratively, with continued reference to fig. 7, a side of the first P-type semiconductor region 1001 facing the first N-type semiconductor region 1002 is in contact with the second P-type semiconductor region 1003.

For example, in the present application, the doping concentration of the second P-type semiconductor region 1003 may be similar to, but not limited to, the doping concentration of the first P-type semiconductor region 1001.

Further, in this application, the second P-type semiconductor region 1003 and the first P-type semiconductor region 1001 may be a unitary structure.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a PN junction structure 1000 according to another embodiment of the present application, in the PN junction structure 1000, a contact interface between a first P-type semiconductor region 1001 and a first N-type semiconductor region 1002 is inclined toward a side of the first P-type semiconductor region 1001 away from the first N-type semiconductor region 1002 with respect to a reference plane Z. The PN junction structure 1000 may further include a second N-type semiconductor region 1004 (i.e., an N' region) located on the first P-type semiconductor region 1001, and the second N-type semiconductor region 1004 is in contact with the first N-type semiconductor region 1002. Thereby further increasing the range of the depletion region in the PN junction structure 1000.

Illustratively, with continued reference to fig. 8, a side of the first N-type semiconductor region 1002 facing the first P-type semiconductor region 1001 is in contact with the second N-type semiconductor region 1004.

For example, in the present application, the doping concentration of the second N-type semiconductor region 1004 may be similar to, but not limited to, the same doping concentration as the first N-type semiconductor region 1002.

Further, in the present application, the second N-type semiconductor region 1004 and the first N-type semiconductor region 1002 may be integrally formed.

The integrated circuit provided by the embodiment of the application can be any electronic device comprising a PN junction structure, for example, the integrated circuit is an optoelectronic modulator. An integrated circuit is schematically illustrated as an electro-optical modulator.

For example, referring to fig. 9-12, the electro-optic modulator 10 is formed by doping a ridge optical waveguide. Wherein the ridge optical waveguide includes a ridge portion 110 and a first base portion 111 and a second base portion 112 located on both sides of the ridge portion 110, respectively. In practice, the body of the ridge optical waveguide may be formed of a semiconductor material such as single crystal silicon, polycrystalline silicon, germanium silicon (GeSi), or indium phosphorus (InP), which is not limited herein. The PN junction structure is disposed on the ridge portion 110 of the ridge optical waveguide, that is, the ridge portion 110 of the ridge optical waveguide is doped to form the PN junction structure.

With continued reference to fig. 9-12, a first N-type semiconductor region (i.e., N-region) of the pn junction structure is located on a side of the ridge 110 proximate to the first base 111, and a first P-type semiconductor region (i.e., P-region) is located on a side of the ridge 110 proximate to the second base 112. When a reverse bias voltage is applied across the PN junction, the width of the depletion region of the PN junction increases, causing a decrease in the number of free carriers within the ridge optical waveguide. Due to the free carrier dispersion effect, when the number of free carriers in the ridge 110 is reduced, the refractive index of the ridge 110 becomes large, so that the transmission line of the electro-optical modulator is shifted, and the modulation function is realized.

Referring to fig. 9 and 10, in the present application, a contact interface between a first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) is inclined with respect to a reference plane. Compared with the traditional transverse PN junction structure, the inclined PN junction structure is formed on the ridge 110, the area of the contact interface between the first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) can be increased on the basis that the length of the ridge-type optical waveguide is not changed, so that the cross-sectional area of the PN junction depletion region is increased, the overlapping area of optical field spots and the PN junction depletion region is increased, and the modulation efficiency of the electro-optical modulator is improved.

In order to further improve the modulation efficiency of the electro-optical modulator, as shown in fig. 11, in the ridge 110, the PN junction structure may be as shown in fig. 7, and the contact interface between the first P-type semiconductor region (P-region) and the first N-type semiconductor region (N-region) is inclined with respect to the reference plane toward a side of the first N-type semiconductor region (N-region) away from the first P-type semiconductor region (P-region), the second P-type semiconductor region (P '-region) is located on the first N-type semiconductor region (N-region), and a side of the first P-type semiconductor region (P-region) facing the first N-type semiconductor region (N-region) is in contact with the second P-type semiconductor region (P' -region). Therefore, the cross-sectional area of the depletion region in the PN structure can be further increased, the overlapping area of the light field spot and the PN junction depletion region is increased, and the modulation efficiency of the electro-optical modulator is further improved.

Alternatively, as shown in fig. 12, in the ridge portion 110, the PN junction structure may be a structure as shown in fig. 8, in which a contact interface of the first P-type semiconductor region (P region) and the first N-type semiconductor region (N region) is inclined with respect to the reference plane Z toward a side of the first P-type semiconductor region (P region) away from the first N-type semiconductor region (N region). The second N-type semiconductor region (N 'region) is positioned on the first P-type semiconductor region (P region), and one side of the first N-type semiconductor region (N region) facing the first P-type semiconductor region (P region) is contacted with the second N-type semiconductor region (N' region). Therefore, the cross-sectional area of the depletion region in the PN structure can be further increased, the overlapping area of the light field spot and the PN junction depletion region is increased, and the modulation efficiency of the electro-optical modulator is further improved.

In particular implementations, in ion doping the ridge 110, the ridge 110 may be doped to extend to the first base 111 and the second base 112 in order to ensure that the ridge 110 is doped in view of process errors. Referring to fig. 11 and 12, fig. 11 is a schematic cross-sectional structure of an electro-optical modulator according to another embodiment of the present application, and fig. 12 is a schematic cross-sectional structure of an electro-optical modulator according to another embodiment of the present application. In the electro-optic modulator 10, a first N-type semiconductor region (N-region) may extend to the first base 111, and a first P-type semiconductor region (P-region) may extend to the second base 112.

With continued reference to fig. 9-12, in the electro-optic modulator 10, a third N-type semiconductor region (n+), having a doping concentration greater than that of the first N-type semiconductor region (n+), may be included in the first base 111; the second base 112 may include a third P-type semiconductor region (p+ region) therein, and the third P-type semiconductor region (p+ region) may have a doping concentration greater than that of the first P-type semiconductor region (P region).

In particular implementations, with continued reference to fig. 9-12, the electro-optic modulator 10 may further include a fourth N-type semiconductor region (n++ region) and a fourth P-type semiconductor region (p++ region). The fourth N-type semiconductor region (N++ region) is positioned on the third N-type semiconductor region (N+ region), and the doping concentration of the fourth N-type semiconductor region (N++ region) is larger than that of the third N-type semiconductor region (N+ region); the fourth P-type semiconductor region (P++ region) is located on the third P-type semiconductor region (P+ region), and the doping concentration of the fourth P-type semiconductor region (P++ region) is larger than that of the third P-type semiconductor region (P+ region). The fourth N-type semiconductor region (N++ region) and the fourth P-type semiconductor region (P++ region) are used for subsequent connection with the electrode, respectively.

For example, the fourth N-type semiconductor region (n++ region) and the third N-type semiconductor region (n+ region) may be integrally formed, and the doping concentrations of the fourth N-type semiconductor region (n++ region) and the third N-type semiconductor region (n+ region) are different only by N-type ions. Similarly, the fourth P-type semiconductor region (p++ region) and the third P-type semiconductor region (p+ region) may be integrally formed, and the doping concentrations of the fourth P-type semiconductor region (p++ region) and the third P-type semiconductor region (p+ region) are different only by P-type ions.

In practice, the ridge optical waveguide is generally formed on a semiconductor substrate having a uniform thickness, and thus the heights of the fourth N-type semiconductor region (n++ region), the fourth P-type semiconductor region (p++ region), and the ridge 110 with respect to the bottom surface of the base are the same, which is not limited herein.

In summary, compared with the traditional electro-optical modulator with a transverse PN junction structure, the electro-optical modulator provided by the embodiment of the application has the inclined PN junction structure on the ridge, so that the cross-sectional area of the depletion region of the PN junction can be increased on the basis that the length of the ridge optical waveguide is not changed, the overlapping area of the optical field spot and the depletion region of the PN junction is increased, and the modulation efficiency of the electro-optical modulator is improved. In addition, the electro-optical modulator can reduce the requirement on the length of the ridge optical waveguide, so that the total capacitance of the electro-optical modulator can be reduced, the bandwidth of the modulator can be improved, and the electro-optical modulator can be further applied to optical communication chips with higher speed and bandwidth.

Further, the integrated circuit provided in the embodiments of the present application may also be an optoelectronic chip, and referring to fig. 1, the optoelectronic chip may include: an input waveguide 11, a beam splitter 12 connected to the input waveguide 11, a modulation arm provided on each branch of the beam splitter 12 for modulating a signal, a beam combiner 13 connected to each branch of the beam splitter 12 for combining the signals, and an output waveguide 14 connected to the beam combiner 13. In the specific arrangement, the number of branches can be two, and the two branches are symmetrically arranged, namely, the two modulation arms are symmetrically arranged. When the optical fiber is specifically used, an input continuous optical signal enters from an input waveguide 11, is split into two beams of light with equal power through a beam splitter 12, passes through a modulation arm respectively, then is combined through a beam combiner 13, and finally is output through an output waveguide 14.

Wherein the modulation arm comprises any of the above-described electro-optic modulators 10 provided by embodiments of the present application. The electrical structure of the electro-optic modulator 10 is shown in fig. 2 as a PN junction operating in reverse bias mode. At zero bias, the optical waveguide has a certain concentration of P-type doping and N-type doping; when reverse bias is applied, the depletion region expands, the built-in electric field increases, the carrier concentration in the optical waveguide becomes low, the effective refractive index of the corresponding optical waveguide becomes large, and the loss becomes small. Therefore, the phase difference of the two paths can be changed by adjusting the voltages of the two modulation arms, and the final output light intensity is further adjusted.

In practice, the arm lengths of the two modulation arms may be equal or unequal, with the purpose of unequal arm lengths to observe responses at different wavelengths. If the arm lengths are equal, the entire modulator can operate in a wider band.

In this application, since the contact interface of the first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) in the electro-optical modulator is not perpendicular and not parallel to the plane in which the base (i.e., the first base or the second base) is located. In this application, the contact interface between the first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) is an inclined plane with respect to the plane of the base, so that compared with the conventional lateral PN junction structure, the inclined PN junction structure is formed on the ridge 110, and the area of the contact interface between the first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) can be increased without changing the length of the ridge optical waveguide, so that the cross-sectional area of the PN junction depletion region is increased, the overlapping area of the optical field spot and the PN junction depletion region is increased, and the modulation efficiency of the electro-optic modulator is improved. In addition, the electro-optical modulator can reduce the requirement on the length of the ridge optical waveguide, so that the total capacitance of the electro-optical modulator can be reduced, the bandwidth of the modulator can be improved, and the electro-optical modulator can be further applied to optical communication chips with higher speed and bandwidth.

Correspondingly, the embodiment of the application also provides a preparation method of the integrated circuit, which can comprise the following steps: providing a semiconductor substrate; then, N-type ions and P-type ions are respectively implanted into the semiconductor substrate to form a first P-type semiconductor region and a first N-type semiconductor region which are adjacently arranged along a first direction.

The contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side, far away from the first N-type semiconductor region, of the first P-type semiconductor region relative to the reference plane; or the contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side of the first N-type semiconductor region far away from the first P-type semiconductor region relative to the reference plane; the reference plane is perpendicular to the first direction.

In one possible implementation, as shown in fig. 13, the preparation method specifically may include the following steps:

step S101, performing P-type ion implantation on one side of the semiconductor substrate along the first direction to form a first P-type semiconductor region.

For example, a first P-type semiconductor region may be formed by performing P-type ion implantation on one side of the semiconductor substrate in the first direction and on a bottom region of the semiconductor substrate.

And S102, forming a photoresist structure with gradually changed thickness by adopting a multi-gray-scale photomask, or forming the photoresist structure with inclined edge side surfaces by adjusting exposure energy and time.

In specific implementations, the multi-Gray tone photomask may be classified into a Gray tone photomask (Gray-tone mask) and a halftone photomask (Half tone mask). The gray mask plate is used for manufacturing micro-slits with the resolution of the exposure machine, and a part of light sources are shielded by the micro-slit part to achieve the half-exposure effect. The halftone mask is a semi-transparent film for performing a half-exposure. Since the two masks can show 3 exposure levels of the full exposure part, the half exposure part and the unexposed part after 1 exposure, at least 2 kinds of photoresist can be formed after development.

And step S103, performing N-type ion implantation on the other side of the semiconductor substrate along the first direction by taking the photoresist structure as an ion implantation masking layer to form a first N-type semiconductor region.

Optionally, when step S101 is to perform P-type ion implantation on one side of the semiconductor substrate along the first direction and the bottom region of the semiconductor substrate to form the first P-type semiconductor region, after step S103, the method may further include: and performing N-type ion implantation on the region above the first P-type semiconductor region to form a second N-type semiconductor region.

In one possible implementation, as shown in fig. 14, the preparation method specifically may include the following steps:

Step S201, performing N-type ion implantation on one side of the semiconductor substrate along the first direction to form a first N-type semiconductor region.

Illustratively, an N-type ion implantation is performed on a side of the semiconductor substrate along the first direction and a bottom region of the semiconductor substrate to form a first N-type semiconductor region.

And S202, forming a photoresist structure with gradually changed thickness by adopting a multi-gray-scale photomask, or forming the photoresist structure with inclined edge side surfaces by adjusting exposure energy and time.

In step S203, the photoresist structure is used as an ion implantation masking layer, and P-type ion implantation is performed on the other side of the semiconductor substrate along the first direction to form a first P-type semiconductor region.

Optionally, when step S201 is to perform N-type ion implantation on one side of the semiconductor substrate along the first direction and the bottom region of the semiconductor substrate to form the first N-type semiconductor region, after step S203, it may further include: and performing P-type ion implantation on the region above the first N-type semiconductor region to form a second P-type semiconductor region.

The following describes in detail a preparation method provided in the present application, taking the integrated circuit as an electro-optical modulator as an example.

Referring to fig. 15, fig. 15 is a schematic flow chart of a method for manufacturing an electro-optical modulator according to an embodiment of the present application. The preparation method can comprise the following steps:

Step S301, providing a ridge optical waveguide, where the ridge optical waveguide includes a ridge portion and a first base portion and a second base portion located on two sides of the ridge portion, respectively.

Illustratively, the ridge optical waveguide may be fabricated using an SOI wafer (wafer). Of course, in implementation, the ridge optical waveguide may be formed of other semiconductor materials such as polysilicon, germanium-silicon (GeSi), or indium-phosphorus (InP). The following will schematically illustrate an SOI wafer.

In practice, SOI wafers generally include an insulating substrate, an oxide layer on the insulating substrate, and a top silicon layer on the oxide layer. Wherein the oxide layer can be SiO ₂ The thickness of the oxide layer is generally 1-3 μm, the top silicon layer is generally a P-type lightly doped layer with the thickness of 100-1000 nmMonocrystalline silicon, the doping concentration of P-type ions is generally 10 ¹⁵ ～10 ¹⁶ Individual/cm ³ 。

In this application, the top silicon layer may be a layer of N-type lightly doped monocrystalline silicon, which is not limited herein.

In the preparation of the ridge optical waveguide, as shown in fig. 16a, a thermal oxide layer 002 may be grown on the surface of an SOI wafer 001, the thickness of the thermal oxide layer 002 may be 5nm to 50n, and then a SiN layer 003 may be formed by using Low pressure chemical vapor deposition (Low-pressure Chemical Vapor Deposition, LPCVD) or the like as an auxiliary etching mask layer, wherein the thickness of the SiN layer 003 is generally 10nm to 200nm. Thereafter, as shown in fig. 16b, a pattern of the ridge optical waveguide 100 is formed in the top silicon layer by an etching process.

Alternatively, after patterning the ridge optical waveguide 100, a sidewall oxidation process may be used to improve the sidewall roughness, then a CVD process may be used to form oxide 004 to fill the etched ridge optical waveguide 100, and a planarization process may be used to planarize the surface to form the structure shown in fig. 16 c. Finally, the SiN layer 003 may be removed by dry etching and hot phosphoric acid etching, leaving the thermally oxidized layer 002 on the ridge optical waveguide 100, resulting in the structure shown in fig. 16 d.

Step S302, forming a first N-type semiconductor region and a first P-type semiconductor region which are adjacently arranged along a first direction in the ridge portion; the first direction is the direction that the first base points to the second base, the first N-type semiconductor region is located at one side close to the first base, and the first P-type semiconductor region is located at one side close to the second base.

In one embodiment, the contact interface between the first P-type semiconductor region and the first N-type semiconductor region is inclined with respect to a reference plane, which is a plane perpendicular to the first direction, toward a side of the first P-type semiconductor region away from the first N-type semiconductor region.

In another embodiment, the contact interface between the first P-type semiconductor region and the first N-type semiconductor region is inclined with respect to a reference plane, which is a plane perpendicular to the first direction, toward a side of the first N-type semiconductor region away from the first P-type semiconductor region.

In a specific implementation, the first N-type semiconductor region and the first P-type semiconductor region may be formed in the ridge portion by subjecting the ridge portion to N-type ion doping and P-type ion doping, respectively. Illustratively, the doped P-type ions may be 3-valent elements such As boron (B) or aluminum (Al), and the doped N-type ions may be 5-valent elements such As phosphorus (P-region) or arsenic (As).

In the ion doping of the ridge portion 110, in order to ensure that the ridge portion 110 is doped in consideration of process errors, the first N-type semiconductor region (N region) may extend to the first base portion 111 and the first P-type semiconductor region (P region) may extend to the second base portion 112 when the ridge portion 110 is doped.

In the specific implementation, when the ridge portion 110 is ion-doped, N-type ion doping may be performed first, followed by P-type ion doping, or P-type ion doping may be performed first, followed by N-type ion doping, which is not limited herein.

Taking P-type ion doping first and then N-type ion doping as an example, in one possible implementation method, the first N-type semiconductor region and the first P-type semiconductor region may be formed in the ridge portion in the following manner.

As shown in fig. 17a, a conventional CMOS process may be used to perform P-type ion implantation on the side of the ridge 110 near the second base 112 to form a first P-type semiconductor region (P-region).

As shown in fig. 17b, a multi-gray-scale photomask may be used to form a photoresist structure 005 having a gradually-changed thickness, and then N-type ion implantation is performed on the side of the ridge 110 near the first base 111 to form a first N-type semiconductor region (N region) by using the photoresist structure 005 as an ion implantation masking layer, so that the contact interface between the formed first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) is inclined with respect to the reference plane.

Alternatively, as shown in fig. 17c, a photoresist structure 005 having an inclined edge side is formed by adjusting exposure energy and time, and then N-type ion implantation is performed on the side of the ridge 110 near the first base 111 to form a first N-type semiconductor region (N-region) by using the photoresist structure 005 as an ion implantation mask layer, so that a contact interface between the formed first N-type semiconductor region (N-region) and the first P-type semiconductor region (P-region) is inclined with respect to a reference plane.

Alternatively, in the present application, P-type ion implantation is performed on the side of the ridge portion near the second base portion to form a first P-type semiconductor region, as shown in fig. 18a, P-type ion implantation may be performed on the side of the ridge portion 110 near the second base portion 112 and the bottom region of the ridge portion 110 to form a first P-type semiconductor region (P-region), that is, P-type ions are not implanted into the ridge portion 110 region located on the first P-type semiconductor region (P-region), so that if the body of the ridge portion 110 is an N-type doped semiconductor, a PN junction may be formed between the first P-type semiconductor region (P-region) and the ridge portion 110 region located on the first P-type semiconductor region (P-region), thereby increasing the depletion region of the PN junction. If the body of the ridge 110 is not an N-doped semiconductor, it is advantageous to subsequently perform an N-type ion implantation on the ridge 110 region located on the first P-type semiconductor region (P-region), thereby increasing the depletion region of the PN junction.

Next, as shown in fig. 18b, a first N-type semiconductor region (N region) is formed in the ridge portion 110. Thereafter, as shown in fig. 18c, a conventional CMOS process may be further used to perform N-type ion implantation on the ridge region located above the first P-type semiconductor region (P-region) to form a second N-type semiconductor region (N' -region). For example, the doping concentration of the second N-type semiconductor region (N' region) may be similar to, but not limited to, the same doping concentration as the first N-type semiconductor region (N region).

Taking the example of N-type ion doping and P-type ion doping, in one possible implementation method, the first N-type semiconductor region and the first P-type semiconductor region may be formed in the ridge in the following manner.

As shown in fig. 19a, a conventional CMOS process may be used to perform N-type ion implantation on the side of the ridge portion 110 near the first base portion 111 to form a first N-type semiconductor region (N-region).

As shown in fig. 19b, a multi-gray-scale photomask may be used to form a photoresist structure 005 having a gradually-changed thickness, and then P-type ion implantation is performed on the side of the ridge 110, which is close to the second base 112, to form a first P-type semiconductor region (P-region), so that the contact interface between the formed first N-type semiconductor region (N-region) and the first P-type semiconductor region (P-region) is inclined with respect to the reference plane.

Alternatively, as shown in fig. 19c, a photoresist structure 005 having an inclined edge side is formed by adjusting exposure energy and time, and then P-type ion implantation is performed on the side of the ridge 110 near the second base 112 using the photoresist structure 005 as an ion implantation mask layer to form a first P-type semiconductor region (P-region), so that the contact interface between the first N-type semiconductor region (N-region) and the first P-type semiconductor region (P-region) is formed to be inclined with respect to a reference plane.

Alternatively, in the present application, N-type ion implantation is performed on the side of the ridge 110 near the first base 111 to form a first N-type semiconductor region, as shown in fig. 20a, N-type ion implantation may be performed on the side of the ridge 110 near the first base 111 and the bottom region of the ridge 110 to form a first N-type semiconductor region (N region), that is, N-type ions are not implanted into the ridge 110 region located on the first N-type semiconductor region (N region), so that if the body of the ridge 110 is a P-type doped semiconductor, the first N-type semiconductor region (N region) and the ridge 110 region located on the first N-type semiconductor region (N region) may form a PN junction, thereby increasing the depletion region of the PN junction. If the ridge 110 body is not a P-doped semiconductor, a subsequent P-type ion implantation of the ridge 110 region located on the first N-type semiconductor region (N-region) is facilitated, thereby increasing the depletion region of the PN junction.

Next, as shown in fig. 20b, a first P-type semiconductor region (P-region) is formed in the ridge portion 110. Thereafter, as shown in fig. 20c, a conventional CMOS process may be further used to perform P-type ion implantation on the ridge region located above the first N-type semiconductor region (N region) to form a second P-type semiconductor region (P' region). For example, the doping concentration of the second P-type semiconductor region (P' region) may be similar to, but not limited to, the same doping concentration as the first P-type semiconductor region (P region).

In step S303, a third N-type semiconductor region is formed in the first base portion, and the doping concentration of the third N-type semiconductor region is greater than that of the first N-type semiconductor region.

As illustrated in fig. 17d, 18d, 19d and 20d, the third N-type semiconductor region (n+ region) may be formed by performing N-type ion implantation on the first base 111 using a conventional CMOS process.

Step S304, forming a third P-type semiconductor region in the second base, wherein the doping concentration of the third P-type semiconductor region is greater than that of the second P-type semiconductor region.

As illustrated in fig. 17e, 18e, 19d and 20d, the second base 112 is P-type ion implanted to form a third P-type semiconductor region (p+ region).

Further, the present application may further include:

Step S305, implanting N-type ions into a partial region of the third N-type semiconductor region to form a fourth N-type semiconductor region. As illustrated in fig. 17f, 18f, 19d and 20d, the fourth N-type semiconductor region (n++ region) may be formed by performing N-type ion implantation on the end of the first base 111 remote from the ridge 110 using a conventional CMOS process, so that the doping concentration of the fourth N-type semiconductor region (n++ region) is greater than that of the third N-type semiconductor region (n+ region).

Step S306, implanting P-type ions into a partial region of the third P-type semiconductor region to form a fourth P-type semiconductor region. For example, as shown in fig. 17g, 18g, 19d and 20d, a conventional CMOS process may be used to perform P-type ion implantation on the end of the second base 112 remote from the ridge 110 to form a fourth P-type semiconductor region (p++ region), so that the doping concentration of the fourth P-type semiconductor region (p++ region) is greater than that of the third P-type semiconductor region (p+ region).

The execution sequence of steps S103 to S106 is not limited in this application, and the sequence may be exchanged. The second N-type semiconductor region or the second P-type semiconductor region may be formed at any stage after the formation of the first N-type semiconductor region and the first P-type semiconductor region, and is not limited herein.

The electro-optical modulator prepared by the method adopts a multi-gray-scale photomask to form a photoresistance structure with gradually changed thickness, or adopts a photoresistance structure with inclined edge side surfaces formed by adjusting exposure energy and time to form inclined PN junctions on the ridge parts of the ridge-type optical waveguides, and then forms a third N-type semiconductor region (N+ region), a second P-type semiconductor region (P+ region), a fourth N-type semiconductor region (N++ region) and a fourth P-type semiconductor region (P++ region) through ion implantation by a conventional CMOS process, so that the electro-optical modulator is simple in process and good in controllability.

Accordingly, the application also provides electronic equipment, which comprises a shell, a circuit board and any one of the integrated circuits provided by the embodiment of the application, wherein the integrated circuit is connected with the circuit board. As the electronic device may be a mobile phone, a computer, a router, a switch, etc. comprising such an integrated circuit, this is not an example.

In the application, since the contact interface between the first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) in the PN junction structure is an inclined plane, the range of the depletion region can be enlarged compared with the conventional lateral PN junction structure. When the method is applied to the electro-optical modulator, an inclined PN junction structure is formed on the ridge, the area of a contact interface between the first N-type semiconductor region (N region) and the first P-type semiconductor region (P region) can be increased on the basis that the length of the ridge-type optical waveguide is not changed, so that the cross-sectional area of a PN junction depletion region is increased, the overlapping area of an optical field spot and the PN junction depletion region is increased, and the modulation efficiency of the electro-optical modulator is improved. In addition, the electro-optical modulator can reduce the requirement on the length of the ridge optical waveguide, so that the total capacitance of the electro-optical modulator can be reduced, the bandwidth of the modulator can be improved, and the electro-optical modulator can be further applied to optical communication chips with higher speed and bandwidth.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. An integrated circuit comprising a PN junction structure; the PN junction structure comprises a first P-type semiconductor region and a first N-type semiconductor region which are adjacently arranged along a first direction;

the contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined relative to a reference plane to one side of the first P-type semiconductor region away from the first N-type semiconductor region; or, the contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side of the first N-type semiconductor region away from the first P-type semiconductor region relative to the reference plane; the reference plane is perpendicular to the first direction.

2. The integrated circuit of claim 1, wherein a contact interface of the first N-type semiconductor region and the first P-type semiconductor region is tilted at an angle greater than or equal to 10 degrees and less than or equal to 80 degrees relative to the reference plane.

3. The integrated circuit of claim 1 or 2, wherein a contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined with respect to the reference plane toward a side of the first N-type semiconductor region remote from the first P-type semiconductor region;

the PN junction structure further comprises a second P-type semiconductor region located on the first N-type semiconductor region, and the second P-type semiconductor region is in contact with the first P-type semiconductor region.

4. The integrated circuit of claim 3, wherein a doping concentration of the second P-type semiconductor region is equal to a doping concentration of the first P-type semiconductor region.

5. The integrated circuit of claim 1 or 2, wherein a contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined with respect to the reference plane toward a side of the first P-type semiconductor region remote from the first N-type semiconductor region;

the PN junction structure further comprises a second N-type semiconductor region located on the first P-type semiconductor region, and the second N-type semiconductor region is in contact with the first N-type semiconductor region.

6. The integrated circuit of claim 5, wherein a doping concentration of the second N-type semiconductor region is equal to a doping concentration of the first N-type semiconductor region.

7. The integrated circuit of any of claims 1-6, further comprising a ridge optical waveguide comprising a ridge and first and second bases on either side of the ridge, respectively;

the PN junction structure is arranged on the ridge of the ridge type optical waveguide;

the first base comprises a third N-type semiconductor region, and the doping concentration of the third N-type semiconductor region is larger than that of the first N-type semiconductor region;

the second base includes a third P-type semiconductor region having a doping concentration greater than the doping concentration of the first P-type semiconductor region.

8. The integrated circuit of claim 7, wherein the first base further comprises a fourth N-type semiconductor region, the fourth N-type semiconductor region being located on the third N-type semiconductor region, and a doping concentration of the fourth N-type semiconductor region being greater than a doping concentration of the third N-type semiconductor region;

the second base portion further comprises a fourth P-type semiconductor region, the fourth P-type semiconductor region is located on the third P-type semiconductor region, and the doping concentration of the fourth P-type semiconductor region is larger than that of the third P-type semiconductor region.

9. The integrated circuit of claim 7 or 8, wherein the integrated circuit further comprises: an input waveguide, a beam splitter having a plurality of branches connected to the input waveguide, a beam combiner connected to each branch of the beam splitter for combining signals, and an output waveguide connected to the beam combiner;

each branch of the beam splitter is provided with the ridge optical waveguide for modulating signals.

10. An electronic device comprising a circuit board and an integrated circuit as claimed in any one of claims 1-9, the circuit board being electrically connected to the integrated circuit.

11. A method of manufacturing an integrated circuit, comprising:

providing a semiconductor substrate;

respectively implanting N-type ions and P-type ions into the semiconductor substrate to form a first P-type semiconductor region and a first N-type semiconductor region which are adjacently arranged along a first direction;

the contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side of the first P-type semiconductor region away from the first N-type semiconductor region relative to a reference plane; or, the contact interface of the first P-type semiconductor region and the first N-type semiconductor region is inclined towards one side of the first N-type semiconductor region away from the first P-type semiconductor region relative to the reference plane; the reference plane is perpendicular to the first direction.

12. The method of manufacturing according to claim 11, wherein implanting N-type ions and P-type ions in the semiconductor substrate respectively forms a first P-type semiconductor region and a first N-type semiconductor region adjacently disposed along a first direction, comprising:

performing P-type ion implantation on one side of the semiconductor substrate along the first direction to form a first P-type semiconductor region;

forming a photoresist structure with gradually changed thickness by adopting a multi-gray-scale photomask, or forming a photoresist structure with inclined edge side surfaces by adjusting exposure energy and time;

and taking the photoresist structure as an ion implantation masking layer, and performing N-type ion implantation on the other side of the semiconductor substrate along the first direction to form a first N-type semiconductor region.

13. The method of manufacturing according to claim 12, wherein performing P-type ion implantation on one side of the semiconductor substrate in the first direction to form a first P-type semiconductor region comprises:

and performing P-type ion implantation on one side of the semiconductor substrate along the first direction and the bottom area of the semiconductor substrate to form a first P-type semiconductor region.

14. The method of manufacturing of claim 13, further comprising, after forming the first N-type semiconductor region and the first P-type semiconductor region in the semiconductor substrate:

And performing N-type ion implantation on the region above the first P-type semiconductor region to form a second N-type semiconductor region.

15. The method of manufacturing according to claim 11, wherein implanting N-type ions and P-type ions in the semiconductor substrate respectively forms a first P-type semiconductor region and a first N-type semiconductor region adjacently disposed along a first direction, comprising:

performing N-type ion implantation on one side of the semiconductor substrate along the first direction to form a first N-type semiconductor region;

and taking the photoresist structure as an ion implantation masking layer, and performing P-type ion implantation on the other side of the semiconductor substrate along the first direction to form a first P-type semiconductor region.

16. The method of manufacturing according to claim 15, wherein performing N-type ion implantation on one side of the semiconductor substrate in the first direction to form a first N-type semiconductor region comprises:

and performing N-type ion implantation on one side of the semiconductor substrate along the first direction and the bottom area of the semiconductor substrate to form a first N-type semiconductor region.

17. The method of manufacturing of claim 16, further comprising, after forming the first N-type semiconductor region and the first P-type semiconductor region in the semiconductor substrate:

and performing P-type ion implantation on the region above the first N-type semiconductor region to form a second P-type semiconductor region.

18. The method of manufacturing according to any one of claims 11 to 17, wherein the semiconductor substrate is a ridge optical waveguide including a ridge and first and second bases on both sides of the ridge, respectively;

implanting N-type ions and P-type ions into the semiconductor substrate respectively to form a first P-type semiconductor region and a first N-type semiconductor region adjacently arranged along a first direction, comprising:

injecting N-type ions and P-type ions into the ridge to form a first N-type semiconductor region and a first P-type semiconductor region, wherein the first N-type semiconductor region is positioned at one side close to the first base, the first P-type semiconductor region is positioned at one side close to the second base, and the first direction is the direction that the first base points to the second base;

after the N-type ions and the P-type ions are respectively implanted into the ridge part to form a first N-type semiconductor region and a first P-type semiconductor region, the method further comprises the steps of;

Forming a third N-type semiconductor region in the first base, wherein the doping concentration of the third N-type semiconductor region is larger than that of the first N-type semiconductor region;

and forming a third P-type semiconductor region in the second base, wherein the doping concentration of the third P-type semiconductor region is larger than that of the first P-type semiconductor region.

19. The method of manufacturing of claim 18, further comprising, after forming a third N-type semiconductor region in the first base: implanting N-type ions into a partial region of the third N-type semiconductor region to form a fourth N-type semiconductor region;

after forming the third P-type semiconductor region in the second base, further comprising: and implanting P-type ions into a partial region of the third P-type semiconductor region to form a fourth P-type semiconductor region.