WO2021018407A1 - Synchronisation d'horloge dans des réseaux de communication par paquets - Google Patents

Synchronisation d'horloge dans des réseaux de communication par paquets Download PDF

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Publication number
WO2021018407A1
WO2021018407A1 PCT/EP2019/078206 EP2019078206W WO2021018407A1 WO 2021018407 A1 WO2021018407 A1 WO 2021018407A1 EP 2019078206 W EP2019078206 W EP 2019078206W WO 2021018407 A1 WO2021018407 A1 WO 2021018407A1
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Prior art keywords
markers
node
round
slave
trip time
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PCT/EP2019/078206
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English (en)
Inventor
Ulf PARKHOLM
Granville Manvel GOES
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Telefonaktiebolaget Lm Ericsson (Publ)
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Publication of WO2021018407A1 publication Critical patent/WO2021018407A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H04L43/0864—Round trip delays

Definitions

  • the present disclosure relates to clock synchronization in packet communication networks, in general, and in particular to method and apparatus for obtaining phase and frequency offsets for synchronizing clocks.
  • Ethernet has been proposed for the 5G fronthaul transport network between the baseband unit (BBU) pools and the remote radio heads (RRHs).
  • BBU baseband unit
  • RRHs remote radio heads
  • the advantages of adopting an Ethernet transport include the low cost of equipment, the use of a shared infrastructure with statistical multiplexing, as well as the ease of operations, administration and maintenance (OAM).
  • OFM operations, administration and maintenance
  • CPRI Common Public Radio Interface
  • eCPRI transport network should provide for high bitrates with very low latency and jitter.
  • Achieving clock synchronization between communicating nodes in a large system is a challenge.
  • the complexity of this challenge increases if the clocks are not exchanged between the nodes which usually leads to de-synchronizing. This is the case when devices (e.g., network nodes) communicate through Ethernet - there is no exchange of clocks between nodes. Instead, synchronization of clocks between Ethernet connected devices is achieved using Ethernet communication through a preamble part of the Ethernet packet.
  • PTP Precision Time Protocol
  • IEEE 1588-2002 IEEE 1588-2002 standard
  • PTP v2 IEEE 1588-2008 standard
  • the IEEE 1588-2008 protocol provides improved accuracy over the 2002 version.
  • the PTP implementation uses the Ethernet packet preambles for transmitting timestamps.
  • PTP reduces the clock synchronization error to hundreds of nanoseconds, but in some applications in 5G even more accurate synchronization is required.
  • an important requirement is that the clock synchronization error is kept to a minimum. This error corresponds to the clock phase and frequency offsets between two clocks in two Ethernet communicating nodes.
  • the disclosed solution seeks to preferably mitigate, alleviate or eliminate one or more of the disadvantages mentioned above singly or in any combination.
  • a method of obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network comprises transmitting signals to and receiving signals from the slave node, wherein the signals carry periodic markers at a physical layer.
  • the method further comprises calculating a plurality of values indicative of round-trip time based on detection at the master node of first markers in a first signal transmitted from the master node to the slave node and detection at the master node of second markers in a second signal received from the slave node and applying regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.
  • a method of obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network comprises transmitting signals to and receiving signals from the master node, wherein the signals carry periodic markers at a physical layer and calculating a plurality of values indicative of round-trip time based on detection at the slave node of second markers in a second signal transmitted from the slave node to the master node and detection at the slave node of first markers in a first signal received from the master node.
  • the method further comprises applying regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.
  • an apparatus for obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network.
  • the apparatus comprising a processing circuitry and a memory.
  • the memory contains instructions executable by the processing circuitry such that the apparatus is operative to transmit signals to and receiving signals from the slave node, wherein the signals carry periodic markers at a physical layer.
  • the apparatus is further operative to calculate a plurality of values indicative of round-trip time based on detection at the master node of first markers in a first signal transmitted from the master node to the slave node and detection at the master node of second markers in a second signal received from the slave node and apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.
  • an apparatus for obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network.
  • the apparatus comprises a processing circuitry and a memory.
  • the memory contains instructions executable by the processing circuitry such that the apparatus is operative to transmit signals to and receiving signals from the master node, wherein the signals carry periodic markers at a physical layer.
  • the apparatus is also operative to calculate a plurality of values indicative of round-trip time based on detection at the slave node of second markers in a second signal transmitted from the slave node to the master node and detection at the slave node of first markers in a first signal received from the master node and to apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.
  • a packet communications network comprising a master node and a slave node.
  • the packet communications network further comprises an apparatus for obtaining phase and frequency offsets for synchronising a slave clock at the slave node with a master clock at the master node.
  • the apparatus comprises a processing circuitry and a memory.
  • the memory contains instructions executable by the processing circuitry such that the apparatus is operative to transmit signals to and receiving signals from the slave node, wherein the signals carry periodic markers at a physical layer.
  • the apparatus is further operative to calculate a plurality of values indicative of round-trip time based on detection at the master node of first markers in a first signal transmitted from the master node to the slave node and detection at the master node of second markers in a second signal received from the slave node.
  • the apparatus is further operative to apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.
  • a packet communications network comprising a master node and a slave node.
  • the packet communications network further comprises an apparatus for obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node.
  • the apparatus comprises a processing circuitry and a memory.
  • the memory contains instructions executable by the processing circuitry such that the apparatus is operative to transmit signals to and receiving signals from the master node, wherein the signals carry periodic markers at a physical layer.
  • the apparatus is further operative to calculate a plurality of values indicative of round-trip time based on detection at the slave node of second markers in a second signal transmitted from the slave node to the master node and detection at the slave node of first markers in a first signal received from the master node.
  • the apparatus is further operative to apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.
  • the disclosed solution provides the benefit of improved accuracy of clock synchronisation in packet communications network (i.e., even further reduced clock synchronisation error). Moreover, embodiments described herein require measurements to be carried out only at one node such that transmitting timestamps is not required, which results in releasing some channel resources that would be consumed by existing techniques. Further, the disclosed solution can be implemented with existing hardware without change, and combining this solution with PTP protocol does not require any complex changes to the system.
  • FIG. 1A and FIG. IB are diagrams illustrating master and slave nodes operating in one embodiment
  • FIG. 2A is a diagram illustrating clock skew
  • FIG. 2B is a diagram illustrating phase and frequency offset
  • FIG. 3 is a flowchart illustrating a method of obtaining phase and frequency offsets for synchronizing a slave clock with a master clock in a packet communications network in one embodiment
  • FIG. 4 is a flowchart illustrating a method of obtaining phase and frequency offsets for synchronizing a slave clock with a master clock in a packet communications network in another embodiment
  • FIG. 5 and FIG. 6 are diagrams illustrating principles of RTT protocol in one embodiment
  • FIG. 7 to FIG. 9 illustrate measurements of values indicative of round-trip time in one embodiment
  • FIG. 10 and FIG. 11 illustrate details of Reed-Solomon Forward Error Correction sublayer
  • FIG. 12 to FIG. 14 illustrate hierarchy of clocks and synchronization in a communications network
  • FIG. 15 is a diagram illustrating an apparatus for obtaining phase and frequency offsets for synchronizing a slave clock with a master clock in a packet communications network in one embodiment.
  • Ethernet is used for exchange of data between devices and can also be used for connecting devices to the Internet. As mentioned earlier it has also been proposed for the 5G fronthaul transport network. Ethernet communication speeds or throughput can be up to 25 Gbps. In Ethernet-based communication, only transmit (TX) and receive (RX) data lines are exchanged between communicating nodes as illustrated in Figures 1A and IB.
  • the Ethernet node 1 transmitter (TX) to Ethernet node 2 receiver (RX) forms Link 1 and the Ethernet Node 2 TX to Ethernet Node 1 RX forms Link 2.
  • Each of the nodes have their individual clock and no exchange of clock information takes place. This may lead to clocks at the respective nodes drifting apart and eventually to clock de-synchronization.
  • clock offset There are two types of clock offset: clock skew (also known as clock phase offset) and clock jitter (also known as clock frequency offset).
  • clock phase offset both clocks have the same frequency but the phase of one clock is shifted as compared to the other as illustrated in Figure 2A.
  • a phase offset is usually caused by problems during synchronization.
  • Figure 2B illustrates clock frequency offset, in which the frequencies (or, equivalently, the periods T1 and T2) of the two clocks differ.
  • Clock frequency offset is often caused by improper clock generator circuitry, noise, or interference.
  • Embodiments of the present disclosure determine the clock synchronization error (i.e., phase and frequency offset) by determining a plurality of values indicative of round- trip time (RTT).
  • RTT round- trip time
  • an RTT protocol may be implemented along an existing protocol (e.g., PTP) as an add-on feature.
  • PTP existing protocol
  • the values indicative of round-trip time of the data exchanged between two communicating nodes are calculated.
  • a plurality of values indicative of RTT are determined based on a large number of data transactions between the nodes to be synchronized.
  • the gathered values indicative of RTT are processed using one of known mathematical models (applying regression analysis) to derive (approximate) the clock phase and frequency offset.
  • the method in one embodiment may be performed at the master node.
  • the method comprises transmitting signals to and receiving signals (in operation 302) from the slave node, wherein the signals carry periodic markers at a physical layer, which is also referred to as Layer 1 in the OSI (Open Systems Interconnection) model.
  • OSI Open Systems Interconnection
  • the method then comprises calculating, 304, a plurality of values indicative of round-trip time based on detection at the master node of first markers in a first signal transmitted from the master node to the slave node and detection at the master node of second markers in a second signal received from the slave node.
  • the method comprises applying regression analysis, 306, to the calculated values to approximate values of phase and frequency offset of the slave clock.
  • Figure 4 illustrates an embodiment of the operation of calculating the plurality of values indicative of round-trip time.
  • the master node, 102 transmits a first signal, 108, (e.g., Ethernet packet if the master and slave nodes are connected using Ethernet base links) to the slave node, 104.
  • the communication between the master, 102, and slave, 104, nodes is bidirectional, so the master node receives a second signal, 106, from the slave node.
  • the method comprises detecting (in operation 402, yes), at the master node, 102, a first marker at a physical layer of the first signal, 106.
  • the master node, 102 determines (in operation 404) a first clock value, Ti, in response to detection of said first marker. This is the time when the first marker has been detected.
  • the master node detects (in operation 406, yes) a second marker at a physical layer of the second signal, 108, and determines (in operation 408) a second clock value, T2, in response to detection of said second marker. This is the time when the second marker has been detected.
  • the operations 402 - 410 are repeated multiple times in order to obtain a set of values of RTTindicative (in operation 412, no). Once there is enough of the of RTTindicative values (operation 412, yes), the method applies one of the known mathematical models to approximate phase and frequency values using for example regression analysis (operation 306).
  • the method in its embodiments is based on using equidistant (periodic) markers and once the markers are inserted in the signals transmitted by the nodes 102 and 104 then the method may preferably use each marker (consecutive markers). However, in alternative embodiments the method does not have to use each marker inserted for calculating the RTTindicative values. If the markers are inserted periodically the method will also work if we calculate the RTTindicative values using e.g., only every second (or third, or n-th marker) as they still will be periodic.
  • FIG 7 This fluctuation of RTTindicative values is illustrated in Figure 7.
  • the top part of Figure 7 shows the periodic events used to determine the RTTindicative values and the bottom part shows a series of plots illustrating how the RTTindicative values change (fluctuate).
  • the same is illustrated in Figure 8 where different periodic events have been chosen for calculating the RTTindicative values.
  • Waveform 1 in Figure 8 illustrates a situation where the clocks at master, 102, and slave, 104, nodes are in sync.
  • the RTTindicative values in the bottom plots form a straight horizontal line meaning the values were identical.
  • the master node, 102 begins transmitting at the first clock edge
  • the slave node, 104 begins transmitting at the second.
  • Each node transmits periodically at every 4th clock edge and as can be seen the RTTindicative (RTTindicative value is calculated from the time the master, 102, transmits a frame to the time when it receives a frame from the slave, 104) which is the same for all the intervals from 1-22.
  • RTTindicative values are plotted, a straight line is produced.
  • Waveform 2 illustrates situation when the clocks at master, 102, and slave, 104, nodes are not in sync and the RTTindicative values produced a sawtooth waveform with fluctuating RTTindicative values.
  • the RTTindicative values are generated the same way as shown in waveform 1 , but the plot at the bottom is different as a result of the clocks not being synchronized. As can be seen the RTTindicative values first decrease until the 21 st transmission and then increase at the 22 nd transmission generating a sawtooth waveform.
  • Such a sawtooth waveform is illustrated in Figure 9 with about 20000 samples collected.
  • the number of samples collected is implementation specific. It may be predefined as a target value and the method continues calculating the RTTindicative values until the target is reached or there may be a time limit for obtaining the RTTindicative values.
  • the operation of calculating a plurality of values indicative of round-trip time is performed using consecutive first and second markers.
  • an RTTindicative value is calculated after determining T1 value for a first marker and then T2 value for a second marker detected immediately after the first marker for which T 1 has been determined.
  • each marker is used for calculating RTTindicative.
  • the operation of calculating a plurality of values indicative of round-trip time is performed using every n-th first and second markers. This means that not all markers will be used for calculating RTTindicative values, but instead every second first marker and every second second marker will be used to calculate the RTTindicative values. Similarly, every third, fourth, etc marker may be used. Because the markers are periodic then every n-th market is also periodic. The advantage is reduced processing load (fewer samples in the set, slower processing).
  • the periodic markers are inserted into the first and second signals with a frequency determined by the clocks to be synchronised.
  • said first markers and said second markers are independent of each other.
  • the markers are not inserted into the signal transmitted from one of the nodes in response to detection by said node of a marker in a received signal. Rather the markers are inserted as a result of operation of the node on the transmit line irrespective of operation of the receive line.
  • the RTT protocol will be implemented with the existing Ethernet protocol.
  • a value indicative of round-trip time of a single Ethernet packet in embodiments of this solution may be calculated from a Start of Frame (SoF) signal which is available during the transmission and reception of a packet.
  • SoF Start of Frame
  • the values indicative of RTT calculated from equidistant (periodic) signals transmitted in Layer 1 may be used to augment the SoF of a single ethernet frame.
  • the values of clock phase and frequency offset can be determined by applying a mathematical model to these values indicative of RTT.
  • the mathematical model uses regression analysis to the calculated values to approximate values of phase and frequency offset of the slave clock.
  • Embodiments of the present disclosure use markers (e.g., signals) periodically inserted at the physical layer of signals exchanged between master and slave node.
  • markers e.g., signals
  • some embodiments may use periodic markers purposefully inserted for the determination of the phase and frequency offsets of the slave clock, it may be particularly advantageous to use for this purpose Layer 1 periodic markers that are already present in the communication signals exchanged between master and slave node. Therefore, in one embodiment, the method of obtaining phase and frequency offsets may use Code Word Markers (CWMs) present (e.g., inserted) in Reed-Solomon Forward Error Correction (RS-FEC, defined in clause 108 of IEEE Std 802.3-2018 standard [2]) as the first and second markers. In another embodiment, the method may use Parity Symbols (PS) as the first and second markers. The Parity Symbols are also present (e.g., inserted) in the RS- FEC.
  • CWMs Code Word Markers
  • RS-FEC Reed-Solo
  • the method to determine the clock’s phase and frequency offsets may be implemented in the physical (PHY) layer of the OSI model with the help of the RS-FEC sublayer.
  • the RS-FEC sublayer, 1002 is shown in Figure 10 and illustrated in more detail in Figure 11.
  • RS-FEC sublayer operates a Codeword Marker Insertion block which inserts CWMs into transcoded blocks before they go to Reed-Solomon encoder.
  • CWMs form the first 257-bits of every 1024th RS-FEC codeword.
  • time between the beginning of successive codeword makers is 209.709919 microsecond (ps) or 4.768492 kilohertz (kHz).
  • the CWMs are present in the signal transmitted between the master, 102, and slave, 104, nodes and they are equidistant (periodic).
  • the Codeword Markers are very useful for the receiver, since the codeword marker synchronization block uses these alignment markers to obtain lock to the incoming bit stream and ensure codeword alignment.
  • the CWM insertion and removal function of RS-FEC sublayer is part of the PHY layer. The same considerations are applicable to so called rapid CWM which are together with CWM defined in IEEE 802.3by - 2018 standard, clauses 108.5.2.4 (insertion) and 108.5.3.4 (removal).
  • a CWM is detected on the transmitting channel (first marker) and a Start of Frame for Transmitter (SoF_TX) signal is asserted for one clock period in the master node, 102.
  • a Start of Frame for Receiver (SoF_RX) signal is asserted for one clock period in the master node, 102, this is shown in Figures 1A and IB.
  • the time difference between the assertion of the two signals forms the value indicative of round-trip time value of an Ethernet packet between the master, 102, and slave, 104, nodes.
  • Parity Symbols used by the RS-FEC sublayer may be used as the periodic first and second markers.
  • a Reed-Solomon Encoder block operates on the RS-FEC sublayer, 1002, and converts 514 information symbols to a codeword containing 528 symbols by appending parity symbols.
  • the codeword consists of 514 information symbols and 14 Parity Symbols (PS). Each symbol is made up of 10- bits.
  • the PS is used for correctly decoding the received codeword to extract the information symbols and correcting them if necessary. For 25 Gbps Ethernet, the time between the beginning of successive PS is 204.794843 nanosecond (ns) or 4.882935463 megahertz (MHz).
  • the Parity Symbols are present in the signal transmitted between the master, 102, and slave, 104, nodes and they are equidistant (periodic).
  • the PS help in error detection and correction in the received codeword.
  • a Detect Parity_Transmit (DP_TX) signal is asserted for one clock period.
  • a Detect Parity Receive (DP_RX) signal is asserted for one clock period, this is shown in Figures 1A and IB.
  • the time difference between the assertion of the two signals is calculated and it is the value indicative of round-trip time value of an Ethernet packet between the master, 102, and slave, 104, nodes.
  • a third clock which is faster than the master, 110, and slave, 112, clocks at the two nodes is used to check when the signals are asserted (SoF_TX and SoF_RX or DP TX and DP RX).
  • this solution can be implemented with the existing designs.
  • clocks are distributed through a network of clocks representing a hierarchy as seen in the Figure 12.
  • GM Grand Master
  • BC Boundary Clock
  • OC Ordinary Clock
  • Figure 12 displays only one BC between the GM and the OC but, there may be multiple BCs between them with each BC at a lower-level in the hierarchy synchronizing with the immediate higher-level BC.
  • the BC synchronizes to the GM clock and the OC synchronizes to the BC through the implementation of the PTP.
  • the RTT protocol described in this document may be implemented along with the existing PTP in the following scenarios to improve the system level clock synchronization:
  • the RTT protocol may be implemented between the BC and the OC as shown in Figure 13. This allows the OC to further synchronize its clock with the BC as compared to only when the PTP is executed. This will help the OC to have a tighter clock synchronization with the BC.
  • the RTT protocol may be also implemented between the GM clock and the BC, and between the BC and the OC, as seen in Figure 14.
  • the BC will be synchronized with the GM clock by implementation of the PTP and RTT protocols, thus ensuring the BC is tightly synchronized with the GM clock.
  • the OC is synchronized with the BC through implementation of the PTP and RTT protocols, which will ensure that the OC is tightly synchronized with the BC. This leads to the OC being tightly synchronized with the GM clock.
  • phase and frequency offset may be communicated to the slave node, 104, for synchronizing the slave clock, 112.
  • the GM clock may align the Tx markers it sends with an external timing source that provides precise time information.
  • this may be a global navigation satellite system (GNSS) which provides location and precise time information, for example Global Positioning System (GPS), Galileo, GLONASS or BeiDou.
  • GPS Global Positioning System
  • GLONASS GLONASS
  • BeiDou BeiDou.
  • the GM clock may derive its timing signal from a GNSS source and may then send downstream the Tx markers with timing based on the GNSS derived timing.
  • the slave clocks in the packet communications network will be synchronised using the RTT protocol to the GM and its external timing source (GNSS) by synchronising their downstream Tx ports with their upstream Rx ports as shown in Figure 14.
  • GNSS external timing source
  • the method in its embodiments has been described above from the perspective of the master node, 102. In other words, the operations of the method are performed at the master node. In alternative embodiments the method can equally be performed at the slave node 104.
  • the method comprises transmitting signals to and receiving signals from the master node, 102 (in operation 302), wherein the signals carry periodic markers at a physical layer.
  • the method also comprises calculating (in operation 304) a plurality of values indicative of round-trip time based on detection at the slave node, 104, of second markers in a second signal transmitted from the slave node, 104, to the master node, 102, and detection at the slave node, 104, of first markers in a first signal received from the master node, 102.
  • the method comprises applying regression analysis (in operation 306) to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.
  • the operation of calculating the plurality of values indicative of round- trip time comprises detecting at the slave node, 104, a second marker at a physical layer of the second signal, said second signal being for transmission from the slave node to the master node.
  • the method comprises determining, a third clock value in response to detection of said second marker.
  • the method comprises detecting at the slave node, 104, a first marker at a physical layer of the first signal, said first signal being received from the master node and determining a fourth clock value in response to detection of said first marker.
  • a value indicative of round-trip time between the slave node and the master node is calculated as a difference between said fourth clock value and said third clock value.
  • the slave node, 104 may be used for synchronizing the slave clock, 112, without transmitting them over the network.
  • Figure 15 illustrates one embodiment of an apparatus, 150, 102 or 104, which implements the method of obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network described earlier.
  • the apparatus, 150, 102 or 104 comprises a processing circuitry, 1502, and a memory, 1504.
  • the memory, 1504, contains instructions executable by the processing circuitry, 1502, such that the apparatus, 150, 102 or 104, is operative to transmit signals to and receiving signals from the slave node, wherein the signals carry periodic markers at a physical layer.
  • the apparatus, 150, 102 or 104 is also operative to calculate a plurality of values indicative of round-trip time based on detection at the master node, 102, of first markers in a first signal transmitted from the master node, 102, to the slave node, 104, and detection at the master node, 102, of second markers in a second signal received from the slave node, 104, and apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.
  • the apparatus, 150, 102 or 104 may include a processing circuitry (one or more than one processor), 1502, coupled to an interface, 1506, and to the memory 1504.
  • the apparatus, 150, 102 or 104 may comprise more than one interface.
  • one interface may be an Ethernet interface for connecting to the slave node, 104, and another interface may be provided for a network operator to perform management operations on the apparatus 150, 102 or 104.
  • the interface 1506, the processor(s) 1502, and the memory 1504 may be connected in series as illustrated in Figure 15.
  • these components 1502, 1504 and 1506 may be coupled to an internal bus system of the apparatus, 150, 102 or 104.
  • the memory 1504 may include a Read-Only- Memory (ROM), e.g., a flash ROM, a Random Access Memory (RAM), e.g., a Dynamic RAM (DRAM) or Static RAM (SRAM), a mass storage, e.g., a hard disk or solid state disk, or the like.
  • ROM Read-Only- Memory
  • RAM Random Access Memory
  • DRAM Dynamic RAM
  • SRAM Static RAM
  • the memory, 1504 may include software, 1512, and/or control parameters, 1514.
  • the memory, 1504, may include suitably configured program code to be executed by the processor(s), 1502, so as to implement the above-described method as explained above.
  • the apparatus, 150 may be implemented as a separate unit, 150, connected to the master node, 102, as illustrated in Figure 1A.
  • the apparatus may be integrated as part of the master node, 102, as illustrated in Figure IB.
  • the apparatus 105 may be a software function or a hardware component of the master node, 102.
  • the method of obtaining phase and frequency offsets for synchronising a slave clock, 112, with a master clock, 110 may be equally implemented at the slave node 104.
  • the apparatus, 150 may be implemented as a separate unit, 150, connected to the slave node, 104.
  • the apparatus, 150 may be integrated as part of the slave node, 104.
  • the apparatus 105 may be a software function or a hardware component of the slave node, 104.
  • a computer program may be provided for implementing functionalities of the apparatus, 150, 102 or 104, e.g., in the form of a physical medium storing the program code and/or other data to be stored in the memory 1504, or by making the program code available for download or by streaming.
  • the apparatus, 150, 102 or 104 may be provided as a virtual apparatus.
  • the apparatus, 150, 102 or 104 may be provided in distributed resources, such as in cloud resources.
  • the memory, 1504, processing circuitry, 1502, and physical interface(s), 1506, may be provided as functional elements.
  • the functional elements may be distributed in a logical network and not necessarily be directly physically connected.
  • the apparatus, 150, 102 or 104 may be provided as single- node devices, or as a multi-node system.
  • the apparatus, 150, 102 or 104 is further configured to carry all the other embodiments of the methods described above.
  • the methods of the present disclosure may be implemented in hardware, or as software modules running on one or more processors. The methods may also be carried out according to the instructions of a computer program, and the present disclosure also provides a computer readable medium having stored thereon a program for carrying out any of the methods described herein.
  • a computer program embodying the disclosure may be stored on a computer readable medium, or it could, for example, be in the form of a signal such as a downloadable data signal provided from an Internet website, or it could be in any other form.

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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un procédé d'obtention de décalages de phase et de fréquence pour la synchronisation d'une horloge esclave d'un nœud esclave avec une horloge maîtresse d'un nœud maître dans un réseau de communication par paquets. Le procédé mis en œuvre au niveau du nœud maître consiste à émettre des signaux vers et à recevoir des signaux en provenance du nœud esclave, les signaux transportant des marqueurs périodiques au niveau d'une couche physique. Le procédé comprend également les étapes consistant à calculer une pluralité de valeurs indiquant un temps aller-retour sur la base d'une détection au niveau du nœud maître de premiers marqueurs dans un premier signal émis du nœud maître vers le nœud esclave et d'une détection au niveau du nœud maître de seconds marqueurs dans un second signal reçu en provenance du nœud esclave et à appliquer une analyse de régression aux valeurs calculées indiquant un temps aller-retour pour approcher des valeurs de décalage de phase et de fréquence de l'horloge esclave. L'invention concerne en outre un procédé correspondant exécuté au niveau du nœud esclave. L'invention concerne également un appareil pour mettre en œuvre le procédé au niveau d'un nœud maître ou d'un nœud esclave.
PCT/EP2019/078206 2019-07-31 2019-10-17 Synchronisation d'horloge dans des réseaux de communication par paquets WO2021018407A1 (fr)

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WO2023085986A1 (fr) * 2021-11-11 2023-05-19 Telefonaktiebolaget Lm Ericsson (Publ) Procédés de synchronisation d'horloges entre des nœuds de réseau utilisant ethernet et transmettant des marqueurs de contrôle continu (fec), et nœud
CN116527192A (zh) * 2023-05-31 2023-08-01 中国科学院空间应用工程与技术中心 一种fc网络时钟同步方法及系统
WO2023241274A1 (fr) * 2022-06-17 2023-12-21 华为技术有限公司 Appareil de traitement de données ainsi que procédé et système de commutation principale et de commutation de veille

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WO2023085986A1 (fr) * 2021-11-11 2023-05-19 Telefonaktiebolaget Lm Ericsson (Publ) Procédés de synchronisation d'horloges entre des nœuds de réseau utilisant ethernet et transmettant des marqueurs de contrôle continu (fec), et nœud
WO2023241274A1 (fr) * 2022-06-17 2023-12-21 华为技术有限公司 Appareil de traitement de données ainsi que procédé et système de commutation principale et de commutation de veille
CN116527192A (zh) * 2023-05-31 2023-08-01 中国科学院空间应用工程与技术中心 一种fc网络时钟同步方法及系统

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