WO2021018180A1 - 显示基板、显示面板及显示设备 - Google Patents

显示基板、显示面板及显示设备 Download PDF

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Publication number
WO2021018180A1
WO2021018180A1 PCT/CN2020/105452 CN2020105452W WO2021018180A1 WO 2021018180 A1 WO2021018180 A1 WO 2021018180A1 CN 2020105452 W CN2020105452 W CN 2020105452W WO 2021018180 A1 WO2021018180 A1 WO 2021018180A1
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Prior art keywords
light
emitting
drive signal
pixel circuit
units
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PCT/CN2020/105452
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English (en)
French (fr)
Inventor
陈亮
王磊
肖丽
玄明花
刘冬妮
陈昊
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/271,737 priority Critical patent/US11348523B2/en
Publication of WO2021018180A1 publication Critical patent/WO2021018180A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present disclosure relates to the display field, and in particular to a display substrate, a display panel and a display device.
  • OLED Organic Light-Emitting Diode
  • the present disclosure provides a display substrate including: a plurality of pixel driving circuits; a plurality of sets of light-emitting driving signal lines, each of the plurality of sets of light-emitting driving signal lines includes a plurality of light-emitting driving signals Line; and a plurality of pixel circuit multiplexing units, respectively connected to the plurality of pixel drive circuits, the plurality of pixel circuit multiplexing units are arranged in a D ⁇ E first array, where D and E are both integers greater than 1 , Wherein each pixel circuit multiplexing unit of the plurality of pixel circuit multiplexing units includes N light-emitting units arranged in a K ⁇ H second array, wherein K, H, and N are all integers greater than 1, and The N light-emitting units are connected to a group of light-emitting drive signal lines in the plurality of groups of light-emitting drive signal lines, and each light-emitting unit of the N light-emitting units is configured to be connected
  • the drive signal from the connected pixel drive circuit is received, so that all the light-emitting units in the same row do not emit light at the same time, and all the light-emitting units in the same column do not emit light at the same time.
  • the same pixel circuit multiplexing unit The N light-emitting units inside emit light sequentially within one frame.
  • the plurality of pixel circuit multiplexing units are connected to the plurality of pixel drive circuits in a one-to-one correspondence, and the N light-emitting units in each pixel circuit multiplexing unit are connected to the plurality of The same pixel drive circuit in the pixel drive circuit.
  • each group of light-emitting drive signal lines includes N light-emitting drive signal lines; the N light-emitting drive signal lines extend in a first direction and are arranged in a second direction, and the first direction is The row direction of the first array and the second array, the second direction is the column direction of the first array and the second array; the pixel circuits in the same row in the first array are multiplexed
  • the unit is connected to a set of light-emitting drive signal lines.
  • each pixel circuit multiplexing unit includes a first light emitting unit and a second light emitting unit arranged in a column
  • the N light emitting drive signal lines include a first light emitting drive signal line and a second light emitting drive signal line.
  • a light-emitting drive signal line wherein the first light-emitting unit in the pixel circuit multiplexing unit in the i-th row and j-th column in the first array and the i-th row and j+1 column in the first array are
  • the second light-emitting unit in the pixel circuit multiplexing unit is connected to the first light-emitting drive signal line, where i and j are integers, and 1 ⁇ i ⁇ D, 1 ⁇ j ⁇ E; the i-th in the first array
  • the second light-emitting unit in the pixel circuit multiplexing unit in the row j-th column and the first light-emitting unit in the pixel circuit multiplexing unit in the i-th row and j+1 column in the first array are connected to a second light-emitting drive signal line.
  • the first driving signal line and the second driving signal line are linearly extending along the first direction, and each of the first light-emitting unit and the second light-emitting unit is connected to the The first light-emitting driving signal line or the second light-emitting driving signal line is connected.
  • the first light-emitting drive signal line is in a first zigzag shape and extends along the first direction to be combined with the first light-emitting unit and the first light-emitting unit in the pixel circuit multiplexing unit in the i-th row and j-th column.
  • the second light-emitting unit in the pixel circuit multiplexing unit in row i and column j+1 is connected;
  • the second light-emitting drive signal line is in the shape of a second zigzag line and extends in the first direction to be connected to the j-th row and i-th row.
  • the second light-emitting unit in the column pixel circuit multiplexing unit is connected to the first light-emitting unit in the pixel circuit multiplexing unit in the i-th row and j+1-th column.
  • the N is an even number greater than 2
  • the display substrate further includes multiple groups of light-emitting control lines, each pixel circuit multiplexing unit is connected to a group of grouped light-emitting control lines, wherein each group of light-emitting control lines includes M grouped light-emitting control lines,
  • the N light-emitting units in the pixel circuit multiplexing unit are divided into M groups of light-emitting units, and the pixel circuit multiplexing unit further includes M switch circuits, wherein the m-th switch circuit and the m-th group light-emitting control Line, the m-th group of light-emitting units and the pixel drive circuit are connected, and the m-th switch circuit is configured to switch the pixel under the control of the m-th group light-emitting control signal at the m-th group light-emitting control line
  • the driving current generated by the driving circuit is provided to the m-th group of light-emitting units, where M is an integer greater than 1, and m is an integer and 1 ⁇ m ⁇ M.
  • the plurality of light-emitting drive signal lines extend in the second direction and are arranged in the first direction, and the first grouped light-emitting control lines and the second grouped light-emitting control lines are in the first direction. Extending and arranged in the second direction; the pixel circuit multiplexing units located in the same column in the first array are connected to a group of light-emitting drive signal lines, and the pixel circuit multiplexing units located in the same row are connected to a group of grouped light-emitting control lines.
  • M 2
  • the M grouped light-emitting control lines include a first grouped light-emitting control line and a second grouped light-emitting control line
  • the M groups of light-emitting units include a first group of light-emitting units and a second group of light-emitting units.
  • M switch circuits include a first switch circuit and a second switch circuit
  • the first switch circuit includes a first transistor, the gate of the first transistor is connected to the first grouped light-emitting control line, the first The first pole of the transistor is connected to the pixel drive circuit, and the second pole of the first transistor is connected to the first group of light-emitting units
  • the second switch circuit includes a second transistor, and the gate of the second transistor is connected In the second grouped light-emitting control line, the first electrode of the second transistor is connected to the pixel driving circuit, and the second electrode of the second transistor is connected to the second group of light-emitting units.
  • each of the N light-emitting units includes: a third transistor, a gate of the third transistor is connected to one of a plurality of light-emitting drive signal lines, and the first transistor of the third transistor The electrode is connected to one of the plurality of pixel driving circuits; a light emitting device, the anode of the light emitting device is connected to the second electrode of the third transistor, and the cathode of the light emitting device is connected to a reference signal line.
  • the gate of the third transistor is arranged in the gate layer of the display substrate, and the first electrode and the second electrode of the third transistor are arranged in the source and drain layer of the display substrate
  • the anode of the light-emitting device is arranged in the anode layer of the display substrate, wherein the anode of the light-emitting device has a protrusion extending to one of the plurality of light-emitting drive signal lines in the anode layer, The protruding portion is connected to the second electrode of the third transistor in the source drain layer through a via hole.
  • the lengths of the protrusions of the anodes of the light emitting devices located in the same row and adjacent columns are different in the extending direction.
  • the present disclosure provides a display panel including the display substrate as described above.
  • the present disclosure provides a display device including the display panel as described above.
  • Figure 1 is a schematic diagram of a 1:2 pixel multiplexing scheme in the related art
  • Figure 2 is a schematic diagram of a pixel multiplexing scheme in related technologies
  • Figure 3 is a circuit diagram of a pixel circuit in the related art
  • FIG. 4 is a working timing diagram of the pixel circuit in the related art in the related art
  • FIG. 5 is a schematic diagram of the light emitting unit distribution of a 1:2 pixel multiplexing scheme in the related art
  • Fig. 6 is an image decomposition schematic diagram of a 1:2 pixel multiplexing scheme in the related art
  • Fig. 7 is an image decomposition schematic diagram of a 1:4 pixel multiplexing scheme in the related art
  • Fig. 8 is a structural diagram of a pixel complementary multiplexing circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a diagram of the arrangement and lighting sequence of light-emitting units according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of image decomposition according to an embodiment of the present disclosure.
  • FIG. 11 is a circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • Fig. 12 is a structural diagram of a pixel circuit multiplexing unit according to an embodiment of the present disclosure.
  • FIG. 13 is a structural diagram of a display substrate in the related art.
  • FIG. 14 is a distribution diagram of the extension part of the light-emitting unit in the anode layer in the related art
  • FIG. 15 is a distribution diagram of the extension part of the light-emitting unit in the anode layer according to an embodiment of the present disclosure
  • FIG. 16 is a diagram of the arrangement and lighting sequence of light-emitting units according to another embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of image decomposition according to another embodiment of the present disclosure.
  • FIG. 18 is a structural diagram of a pixel circuit multiplexing unit according to another embodiment of the present disclosure.
  • FIG. 19 is a working timing diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 20 is a structural diagram of a pixel circuit multiplexing unit according to another embodiment of the present disclosure.
  • FIG. 21 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 22 is a schematic diagram of image decomposition according to another embodiment of the present disclosure.
  • FIG. 23 is a structural diagram of a pixel circuit multiplexing unit according to another embodiment of the present disclosure.
  • FIG. 24 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 25 is a structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 26 is a structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a 1:2 pixel multiplexing scheme in the related art (two light-emitting units share one pixel driving circuit).
  • the image is decomposed into sub-image 1 and sub-image 2, where sub-image 1 corresponds to rows 1, 3, 5... of the image, that is, odd rows; sub-image 2 corresponds to rows 2, 4, and 4 of the image 6...lines, that is, even-numbered lines.
  • the odd-numbered rows of light-emitting units are controlled to emit light in the first half of 1 frame time, so that they are displayed as sub-image 1.
  • the even-numbered rows of light-emitting units are controlled to emit light, thereby displaying sub-image 2.
  • Sub-image 1 and sub-image 2 are superimposed into a complete image.
  • the nth row of sub-image 1 and sub-image 2 will share a pixel driving circuit, multiplexing the same EM output, and A Gate output.
  • Each sub-pixel in the nth row of sub-image 1 and sub-image 2 has a corresponding EM switch EM(n-1), EM(n-2).
  • the pixel circuit corresponding to the 1:2 multiplexing of the engine bridge technology can see 2 sub-pixels, which are 7T+1C in total, which greatly reduces the number of thin film transistors (TFTs for short).
  • Fig. 6 is an image decomposition schematic diagram of a 1:2 pixel multiplexing scheme in the related art. As shown in Fig. 6, the picture difference between the odd-line image and the even-line image after decomposition is relatively large, so when the odd-line image and the even-line image are switched between the upper and lower fields, flicker occurs in the vertical direction.
  • Fig. 7 is an image decomposition schematic diagram of a 1:4 pixel multiplexing scheme in the related art. As shown in Fig. 7, the image picture difference after image decomposition of the 1:4 pixel multiplexing scheme is larger, and the flicker will be more serious.
  • the present disclosure proposes a pixel circuit.
  • the pixel circuit 111 includes: a plurality of pixel driving circuits 11; a plurality of pixel circuit multiplexing units 12,
  • the pixel circuit multiplexing unit 12 is connected to the pixel driving circuit 11 in a one-to-one correspondence, and the pixel circuit multiplexing unit 12 is connected to the corresponding pixel driving circuit 11.
  • the pixel circuit multiplexing unit 12 includes N light-emitting units 21, wherein N/2 light-emitting units 21 are respectively located in the nth row and mth column to m+ith column, and N/2 light-emitting units 21 are respectively located in the nth column.
  • N is an even number greater than 0
  • n is an odd number
  • i is equal to N/2-1
  • all light-emitting units in the same row do not emit light at the same time
  • all light-emitting units in the same column do not emit light at the same time Glow.
  • the N light emitting units 21 of the pixel circuit multiplexing unit 12 are arranged in 2 rows, that is, the nth row (odd row) and the n+1th row (even row).
  • the nth row includes N/2
  • the n+1th row includes N/2 light-emitting units 21. All the light-emitting units 21 in the same row do not emit light at the same time, and all the light-emitting units 21 in the same column emit light at different times, and a 1:N pixel multiplexing scheme can be realized. Since N is an even number greater than 0, the embodiments of the present disclosure can implement pixel multiplexing schemes such as 1:2, 1:4, 1:6, etc.
  • the pixel driving circuit 11 includes TFTs T1, T2, T3, T4, T5 and a capacitor C1.
  • the pixel circuit multiplexing unit 12 and the pixel driving circuit 11 are connected in a one-to-one correspondence.
  • the pixel circuit multiplexing unit 12 includes N light-emitting units 21, of which N/2 light-emitting units 21 are located respectively The nth row and the mth column to the m+ith column, and the N/2 light-emitting units 21 are respectively located in the n+1th row and the mth column to the m+ith column, N is an even number greater than 0, n is an odd number, i Equal to N/2-1.
  • All the light-emitting units 21 in the same row do not emit light at the same time, and all the light-emitting units 21 in the same column do not emit light at the same time, which can realize the decomposition display of the image in the horizontal and vertical directions and reduce display flicker.
  • the N light-emitting units 21 in the same pixel circuit multiplexing unit 12 can emit light sequentially within one frame.
  • the N light-emitting units 21 adjacent to the same row can emit light sequentially within one frame.
  • multiple pixel circuit multiplexing units 12 can be arranged as shown in FIG. 9.
  • Two light-emitting units 21 in the same pixel circuit multiplexing unit emit light sequentially within one frame, and two adjacent light-emitting units 21 in the same row emit light sequentially within one frame.
  • the light-emitting units 21 with the same logo emit light at the same time (that is, the light-emitting units 21 of the logo 1 emit light at the same time, and the light-emitting units 21 of the logo 2 emit light at the same time), and the light-emitting units 21 of the logo 1 and the logo 2 emit light in sequence.
  • the display effect is shown in Figure 10, which can realize the horizontal and vertical decomposition display of the image and reduce the display flicker.
  • the pixel circuit multiplexing unit 12 also includes: 2 light-emitting drive signal lines, the 2 light-emitting drive signal lines are connected to the two light-emitting units 21 in a one-to-one correspondence; two light-emitting units 21 adjacent to the same row Connect with two light-emitting drive signal lines one-to-one.
  • the present disclosure provides a display substrate 200, including: a plurality of pixel driving circuits 11; a plurality of groups of light-emitting driving signal lines, each of the plurality of groups of light-emitting driving signal lines includes a plurality of light-emitting driving signal lines; And a plurality of pixel circuit multiplexing units 12 are connected to the plurality of pixel driving circuits 11 in a one-to-one correspondence, and the plurality of pixel circuit multiplexing units 12 are arranged in a D ⁇ E first array, where D and E are both An integer greater than 1, wherein each pixel circuit multiplexing unit 12 in the plurality of pixel circuit multiplexing units 12 includes N light-emitting units 21 arranged in a K ⁇ H second array, wherein K, H, and N are all Is an integer greater than 1, the N light-emitting units 21 are connected to one pixel drive circuit 11 of the plurality of pixel drive circuits 11, and the N light-emitting units 21 are connected to one of the multiple sets of light
  • a group of light-emitting drive signal lines are connected, and each light-emitting unit 21 of the N light-emitting units 21 is configured to receive the light-emitting drive signal from the multiple connections under the control of the light-emitting drive signal at the connected light-emitting drive signal line.
  • the drive signal of one pixel drive circuit 11 in the pixel drive circuit 11 makes all the light-emitting units 21 located in the same row not emit light at the same time, and all the light-emitting units 21 in the same column emit light at different times.
  • the N light-emitting units 21 emit light sequentially within one frame.
  • each group of light-emitting drive signal lines includes N light-emitting drive signal lines, and the N light-emitting drive signal lines extend in a first direction and are arranged in a second direction, and the first direction is the The row direction of the first array and the second array, the second direction is the column direction of the first array and the second array; the pixel circuit multiplexing units 12 in the same row in the first array Connect a set of light-emitting drive signal lines.
  • each pixel circuit multiplexing unit 12 includes a first light-emitting unit and a second light-emitting unit arranged in a column, and the N light-emitting drive signal lines include a first light-emitting drive signal line and a second light-emitting drive signal.
  • the second light-emitting unit in the circuit multiplexing unit 12 is connected to the first light-emitting drive signal line, where i and j are integers, and 1 ⁇ i ⁇ D, 1 ⁇ j ⁇ E; the i-th row in the first array
  • the second light-emitting unit in the pixel circuit multiplexing unit 12 in the j-th column and the first light-emitting unit in the i-th row and j+1 column in the first array are connected to the second light-emitting drive Signal line.
  • the pixel circuit multiplexing unit 12 located in the first row and first column of the first array includes a first light-emitting unit 211 and a second light-emitting unit 212 arranged in a column, which are multiplexed with the pixel circuit
  • the first group of light-emitting driving signal lines EMG1 corresponding to the unit 12 includes a first light-emitting driving signal line EM1 and a second light-emitting driving signal line EM2, where the first driving signal line and the second driving signal line are in the other groups of light-emitting driving signal lines
  • Other reference numerals are used for denoting in, for example, EM3 and EM4 can be respectively denoted in the second row and first column of the first array.
  • the first light-emitting unit 211 in the pixel circuit multiplexing unit 12 in the first row and the first column in the first array and the pixel circuit multiplexing unit 12 in the first row and the first column in the first array is connected to the first light-emitting drive signal line EM1; the second light-emitting unit 212 in the pixel circuit multiplexing unit 12 in the first row and the first column in the first array is The first light-emitting unit 211 in the pixel circuit multiplexing unit 12 in the first row and first column is connected to the second light-emitting drive signal line EM2.
  • a similar connection manner is adopted to connect with N light-emitting drive signal lines.
  • the first light-emitting drive signal line EM1 extends in a first zigzag shape along the first direction to be in line with the pixel circuit multiplexing unit 12 in the first row and first column.
  • the first light-emitting unit 211 is connected to the second light-emitting unit 212 in the pixel circuit multiplexing unit 12 in the first row and the first column;
  • the second light-emitting drive signal line EM2 is in a second zigzag shape and extends along the first direction , To be connected to the second light-emitting unit 212 in the pixel circuit multiplexing unit 12 in the first row and first column and the first light-emitting unit 211 in the pixel circuit multiplexing unit 12 in the first row and first column.
  • EM1 and EM2 are designed in a broken line type, and are connected to the two light-emitting units 211 and 212 in the pixel circuit multiplexing unit 12 through different layers of metal wiring, and the pixel circuits in the first row and the first column are multiplexed.
  • the first light-emitting unit 211 in the unit 12 and the first light-emitting unit 211 in the pixel circuit multiplexing unit 12 in the first row and second column are respectively one-to-one with the first light-emitting drive signal line EM1 and the second light-emitting drive signal line EM2. Corresponding connection.
  • the two light-emitting units 21 in the same pixel circuit multiplexing unit 12 can emit light sequentially within one frame, and the same row is adjacent
  • the two light-emitting units 21 emit light sequentially within one frame time, thereby realizing the decomposition display of the image in the horizontal and vertical directions, and reducing display flicker.
  • the above-mentioned design of the light-emitting drive signal line into a zigzag type can realize that the two light-emitting units 21 in the same pixel circuit multiplexing unit 12 emit light sequentially within one frame, and the two adjacent light-emitting units 21 in the same row within one frame time Glow in turn.
  • each group of light-emitting driving signal lines includes N light-emitting driving signal lines, and N is an even number greater than 2, and the N light-emitting driving signal lines in each group of light-emitting driving signal lines follow the order from the first light-emitting driving signal line.
  • FIG. 13 shows an exemplary partial film structure diagram of a display substrate in the related art.
  • the display substrate 300 includes: a base substrate 210; a gate layer 270 disposed on the base substrate 210; a source and drain layer 230 disposed on a side of the gate layer 270 away from the base substrate 210;
  • the anode layer 240 is located on the side of the source/drain layer 230 away from the base substrate 210 and is electrically connected to the source/drain layer 230 via the via hole V1;
  • the cathode layer 260 is located at The side of the anode layer 240 away from the base substrate 210;
  • the luminescent material layer 250 is located between the anode layer 240 and the cathode layer 260.
  • Fig. 14 shows a partial plan view of a display substrate used in the related art.
  • the extensions 3111 of the light-emitting units 21 located in the same row in the anode layer 240 are connected to the corresponding light-emitting drive signal lines in the same row, and the extensions 3111 of the light-emitting units 21 located in different rows in the anode layer 240 are connected to different light-emitting drive signals. line.
  • the extension 3111 of the light emitting unit 21 in the first row in the anode layer 240 is connected to the light emitting drive signal line EM1 corresponding to the first row
  • the extension 3111 of the light emitting unit 21 in the second row in the anode layer 240 is connected to the second row.
  • the light-emitting drive signal line EM2 corresponding to the row is connected. It can be seen from FIG. 14 that the extension 3111 of the anode layer 240 of each light-emitting unit has the same length in the extension direction.
  • each of the N light-emitting units includes: a third transistor, and a gate of the third transistor is connected to one of a plurality of light-emitting drive signal lines ,
  • the first electrode of the third transistor is connected to one of the plurality of pixel driving circuits;
  • a light emitting device the anode of the light emitting device is connected to the second electrode of the third transistor, and the cathode of the light emitting device is connected to a reference The signal line ELVSS.
  • the gate of the third transistor is arranged in the gate layer of the display substrate, the first electrode and the second electrode of the third transistor are arranged in the source and drain layer of the display substrate, and the light emitting device
  • the anode is disposed in the anode layer of the display substrate, wherein the anode of the light-emitting device has a protrusion 2111 extending to one of the plurality of light-emitting drive signal lines in the anode layer, and the protrusion 2111
  • the portion 2111 is connected to the second electrode of the third transistor in the source-drain layer through a via V1.
  • FIG. 15 shows a schematic plan view of a part of a display substrate according to an embodiment of the present disclosure.
  • the extension 2111 of the light-emitting unit 21 located in the odd-numbered row and even-numbered column in the anode layer 240 extends to the next row and is connected to the light-emitting drive signal line EM2 corresponding to the next row.
  • the light-emitting unit 21 located in the even-numbered row and even column in the anode layer 240 The extension portion 2111 of ⁇ 2 extends to the upper row to be connected to the light emitting drive signal line EM1 corresponding to the upper row.
  • the extension 211 of the anode layer 240 in the first row and the first column and the extension 211 of the anode layer 240 in the first row and the second column have different lengths in the extension direction. .
  • the extension 2111 of the light emitting unit 21 located in the odd rows and even columns in the anode layer 240 extends to the next row, and the extension 2111 of the light emitting unit 21 located in the even rows and even columns in the anode layer extends to the upper row ,
  • the extended portions 2111 of the anode layer in the light-emitting unit 21 can be cross-distributed, so that one of the two adjacent light-emitting units 21 in the same row is connected to the light-emitting drive signal line such as EM1 or EM2 to realize the same pixel
  • the two light-emitting units 21 in the circuit multiplexing unit 12 emit light sequentially within a frame time, and the two adjacent light-emitting units 21 in the same row emit light sequentially within a frame time, thereby realizing the image horizontal and vertical direction decomposition display, reducing the display Flashing.
  • the N light-emitting units 21 in the same pixel circuit multiplexing unit 12 emit light sequentially within one frame, and the N light-emitting units 21 adjacent to the same row emit light sequentially within one frame. , It can realize the decomposition display of the image in the horizontal and vertical directions and reduce the display flicker.
  • the present disclosure also proposes a pixel circuit 111, as shown in FIG. 8, including: a plurality of pixel drive circuits 11; a plurality of pixel circuit multiplexing units 12, the pixel circuit multiplexing unit 12 and the pixel drive circuit 11 one by one Correspondingly, the pixel circuit multiplexing unit 12 is connected to the corresponding pixel driving circuit 11.
  • the pixel circuit multiplexing unit 12 includes N light-emitting units 21, where N/2 light-emitting units 21 are respectively located in the nth row and mth column to m+ith column, and the N/2 light-emitting units 21 are respectively located in the n+1th column.
  • Row m-th column to m+i-th column, N is an even number greater than 2
  • n is an odd number
  • i is equal to N/2-1.
  • the N light emitting units 21 of the pixel circuit multiplexing unit 12 are arranged in 2 rows, that is, the nth row (odd row) and the n+1th row (even row), and the nth row includes N/2
  • the light-emitting unit 21, the n+1th row includes N/2 light-emitting units 21, all the light-emitting units 21 in the same row do not emit light at the same time, and all the light-emitting units 21 in the same column do not emit light at the same time.
  • N in the same pixel circuit multiplexing unit 12 The light-emitting units 21 emit light sequentially within one frame, and the light-emitting units 21 at corresponding positions in the pixel circuit multiplexing unit 12 in the same row emit light at the same time.
  • the N light-emitting units 21 in the same pixel circuit multiplexing unit 12 can be controlled to emit light in the order of row first and then column or other order.
  • the N/2 light-emitting units in the nth row emit light first in the order of row first and then column.
  • N/2 light-emitting units in a +1 row emit light, and N/2 light-emitting units in the same row emit light sequentially in columns, which can realize a pixel multiplexing scheme of 1:N. Since N is an even number greater than 2, the present disclosure The embodiment can realize 1:4, 1:6, ... and other pixel multiplexing schemes.
  • the units 12 can be arranged as shown in FIG. 16.
  • the four light-emitting units 21 in the same pixel circuit multiplexing unit emit light in the order of row first and then column within one frame time, and the light-emitting units 21 at corresponding positions in the pixel circuit multiplexing unit 12 in the same row emit light at the same time, as shown in FIG. 16.
  • the light-emitting units 21 with the same logo emit light at the same time (that is, the light-emitting unit 21 of the logo 1 emits light at the same time, the light-emitting unit 21 of the logo 2 emits light at the same time, the light-emitting unit 21 of the logo 3 emits light at the same time, and the light-emitting unit 21 of the logo 4 emits light at the same time), 1.
  • the light-emitting units 21 of mark 2, mark 3, and mark 4 emit light in sequence.
  • the display effect is shown in Figure 17, which can realize the horizontal and vertical decomposition display of the image and reduce the display flicker.
  • the pixel driving circuit 11 includes TFTs T1, T2, T3, T4, T5, and a capacitor C1.
  • the pixel circuit multiplexing unit 12 corresponds to the pixel drive circuit 11 one-to-one, the pixel circuit multiplexing unit 12 is connected to the corresponding pixel drive circuit 11, and the pixel circuit multiplexing unit 12 includes N The light emitting unit 21, wherein N/2 light emitting units 21 are respectively located in the nth row and mth column to m+ith column, and N/2 light emitting units 21 are respectively located in the n+1th row and mth column to m+ith column Column, N is an even number greater than 2, n is an odd number, i is equal to N/2-1, N light-emitting units 21 in the same pixel circuit multiplexing unit 12 emit light sequentially within a frame time, and pixel circuits in the same row are multiplexed
  • the light-emitting unit 21 at the corresponding position in the unit 12 emits light at the same time, which can realize the decomposition display of the image in the horizontal and vertical directions, and reduce the
  • the pixel circuit multiplexing unit 12 includes: N light-emitting drive signal lines, and the N light-emitting drive signal lines are connected to the N light-emitting units 21 in a one-to-one correspondence; corresponding positions in the pixel circuit multiplexing unit 12 in the same row
  • the light emitting unit 21 is connected to the same light emitting drive signal line.
  • a pixel circuit multiplexing unit 12 includes four light-emitting units 21, which are connected to four light-emitting drive signal lines such as EM1, EM2, EM3, and EM4. Corresponding connection.
  • the light-emitting units 21 at corresponding positions in the pixel circuit multiplexing unit 12 in the same row are connected to the same light-emitting drive signal line, and the light-emitting units 21 at the corresponding positions are arranged with one light-emitting unit 21 spaced apart.
  • the working sequence is shown in FIG. 19, so that the four light-emitting units 21 in the same pixel circuit multiplexing unit 12 can emit light sequentially within one frame.
  • a pixel circuit multiplexing unit 12 includes 6 light-emitting units 21, and 6 light-emitting drive signal lines such as EM1, EM2, EM3, EM4, EM5 Connect with EM6 one-to-one.
  • the light-emitting units 21 at corresponding positions in the pixel circuit multiplexing unit 12 in the same row are connected to the same light-emitting drive signal line, and the light-emitting units 21 at the corresponding positions are arranged with two light-emitting units 21 spaced apart.
  • the circuit diagram of the pixel circuit is shown in Figure 21, so that the six light-emitting units 21 in the same pixel circuit multiplexing unit 12 emit light sequentially within one frame time, and the light-emitting units at corresponding positions in the pixel circuit multiplexing unit 12 in the same row 21 emits light at the same time, and its display effect is shown in Figure 22, which further realizes the decomposition display of the image in the horizontal and vertical directions and reduces the display flicker.
  • the N light-emitting units 21 in the same pixel circuit multiplexing unit 12 emit light sequentially within a frame time, and the light-emitting units 21 at corresponding positions in the pixel circuit multiplexing unit 12 in the same row simultaneously Luminous, can realize the image horizontal and vertical direction decomposition display, reduce display flicker.
  • the extension 2111 of the anode layer 240 located in the i-th row and j-th column is in the extension direction
  • the length of is different from the length of the extension 2111 of the anode layer 240 located in the i-th row and j+1-th column in the extending direction.
  • the display substrate 200 further includes multiple groups of light-emitting control lines, each pixel circuit multiplexing unit 12 is connected to a group of grouped light-emitting control lines, wherein each group of light-emitting control lines includes M grouped light-emitting control lines ,
  • the N light-emitting units in the pixel circuit multiplexing unit are divided into M groups of light-emitting units, the pixel circuit multiplexing unit further includes M switch circuits, wherein the m-th switch circuit and the m-th group emit light
  • the control line, the m-th group of light-emitting units and the pixel drive circuit are connected, and the m-th switch circuit is configured to switch the m-th group light-emitting control signal under the control of the m-th group light-emitting control signal
  • the driving current generated by the pixel driving circuit is provided to the m-th group of light-emitting units, where M is an integer greater than 1, and m is an integer and 1 ⁇ m ⁇ M.
  • the M grouped light-emitting control lines include a first grouped light-emitting control line and a second grouped light-emitting control line
  • the M groups of light-emitting units are divided into a first group of light-emitting units H211 and a second group of light-emitting units H211.
  • the M switch circuits include: a first switch circuit connected to the first group light emitting control line, the first group light emitting unit H211 and the pixel drive circuit 11, the first switch The circuit is configured to provide the driving current generated by the pixel driving circuit 11 to the first group of light-emitting units H211 under the control of the first grouped light-emitting control signal at the first grouped light-emitting control line; a second switch circuit, and The second group light-emitting control line, the second group light-emitting unit H212 and the pixel drive circuit 11 are connected, and the second switch circuit is configured to control the second group light-emitting control signal at the second group light-emitting control line
  • the driving current generated by the pixel driving circuit 11 is provided to the second group of light-emitting units H212.
  • the plurality of light-emitting drive signal lines extend in the second direction and are arranged in the first direction, and the first grouped light-emitting control lines and the second grouped light-emitting control lines are in the first direction. Extend and arrange in the second direction; the pixel circuit multiplexing units 12 located in the same column in the first array are connected to a group of light-emitting drive signal lines, and the pixel circuit multiplexing units 12 located in the same row are connected to a group of grouped light-emitting control lines .
  • the first switch circuit includes a first transistor T12, a gate of the first transistor T12 is connected to the first grouped light emission control line, and a first electrode of the first transistor T12 is connected to the In the pixel driving circuit 11, the second electrode of the first transistor T12 is connected to the first group of light-emitting units H211; the second switch circuit includes a second transistor T13, and the gate of the second transistor T13 is connected to the Two groups of light-emitting control lines, the first electrode of the second transistor T13 is connected to the pixel driving circuit 11, and the second electrode of the second transistor T13 is connected to the second group of light-emitting units H212.
  • the M grouped light-emitting control lines include a first grouped light-emitting control line (EM v 1) and a second grouped light-emitting control line (EM v 2); N light-emitting control lines in the pixel circuit multiplexing unit 12
  • the unit 21 is divided into a first group of light emitting units H211 and a second group of light emitting units H212.
  • the pixel circuit multiplexing unit 12 further includes a first switch circuit and a second switch circuit.
  • the first switch circuit includes a first transistor T12, a gate of the first transistor T12 is connected to the first grouped light emission control line EMv1, and a first electrode of the first transistor T12 is connected to the pixel driving circuit 11,
  • the second electrode of the first transistor T12 is connected to the first group of light-emitting units H211;
  • the second switch circuit includes a second transistor T13, and the gate of the second transistor T13 is connected to the second grouped light-emitting control line EMv2, the first pole of the second transistor T13 is connected to the pixel driving circuit 11, and the second pole of the second transistor T13 is connected to the second group of light-emitting units H212.
  • the first transistor T12 is connected to the first grouped light-emitting control line, the first group of light-emitting units, and the pixel drive circuit 11, and the first transistor T12 is configured as the first grouped light-emitting control line EMv1.
  • the driving current generated by the pixel driving circuit 11 is provided to the first group of light emitting units H211 under the control of a grouped light emitting control signal; the second transistor T13 and the second grouped light emitting control line EMv2, the second group
  • the light emitting unit H212 is connected to the pixel driving circuit 11, and the second transistor T13 is configured to drive the pixel driving circuit 11 under the control of the second grouped light emitting control signal at the second grouped light emitting control line EMv2. Electric current is supplied to the second group of light emitting cells H212.
  • the plurality of light-emitting drive signal lines such as EM H 1, EM H 2, and EM H 3 extend in the second direction (row direction) and are arranged in the first direction (also called row light emitting Drive signal line); the first grouped light-emitting control line EMv1 and the second grouped light-emitting control line EMv2 extend in the first direction and are arranged in the second direction (column direction) (also called column light-emitting drive signal line ).
  • the pixel circuit multiplexing units (for example, including the pixel circuit multiplexing unit 12 and the pixel circuit multiplexing units in the same column) in the same column (for example, the first column) in the first array Unit) Connect the light-emitting drive signal lines EM H 1, EM H 2 and EM H 3.
  • the pixel circuit multiplexing units (for example, pixel circuit multiplexing units including the pixel circuit multiplexing unit 12 and its counterparts) located in the same row (for example, the first row) in the first array are connected to the first grouped light emitting control line ( For example, EMv1) and the second grouped lighting control line (for example, EMv2).
  • N/2 column light-emitting drive signal lines are connected to N/2 light-emitting units 21 in one-to-one correspondence, and N/2 column light-emitting drive signal lines are also connected to other N/2 light-emitting units 21 in one-to-one correspondence; pixels in the same column
  • the light emitting unit 21 at the corresponding position in the circuit multiplexing unit 12 is connected to the same column of light emitting drive signal lines.
  • the pixel circuit multiplexing unit 12 may further include: two row light-emitting drive signal lines, one of the two row light-emitting drive signal lines and the first transistor T12 The control terminal is connected, the other of the two row light-emitting drive signal lines is connected to the control terminal of the second transistor T13; the control terminal of the switch circuit in the corresponding position in the pixel circuit multiplexing unit 12 of the same row is connected to the same Row light-emitting drive signal line connection.
  • the pixel circuit multiplexing unit 12 may include a first transistor T12 as shown in FIG. 23 and FIG. 24, and three light-emitting units 21 are connected to the pixel driving circuit 11 through the first transistor T12. Connected; the second transistor T13, the other three light-emitting units 21 are connected to the pixel drive circuit 11 through the second transistor T13.
  • Three column light-emitting drive signal lines such as EM H 1, EM H 2, EM H 3 are connected to the three light-emitting units 21 in the same row one-to-one, and 3 column light-emitting drive signal lines such as EM H 1, EM H 2, The EM H 3 is also connected to the other three light-emitting units 21 in the next row in a one-to-one correspondence, and the light-emitting units 21 at corresponding positions in the pixel circuit multiplexing unit 12 in the same column are connected to the light-emitting drive signal lines in the same column;
  • Two row light-emitting drive signal lines such as EMv1, EMv2, one row light-emitting drive signal line such as EMv1 is connected to the control terminal of the first transistor T12, and the other row light-emitting drive signal line of the two row light-emitting drive signal lines, such as EMv2 and
  • the control end of the second transistor T13 is connected, and the control end of the switch circuit in the corresponding position in the pixel circuit multiplexing unit 12 in the same row is connected to the light-emitting drive signal line in the same row.
  • the six light-emitting units 21 in the same pixel circuit multiplexing unit 12 emit light sequentially within one frame, and the light-emitting units 21 at corresponding positions in the pixel circuit multiplexing unit 12 in the same row emit light at the same time.
  • the display effect is shown in FIG. 22. Display, and then realize the image horizontal and vertical direction decomposition display, reduce display flicker, and reduce the number of signal lines.
  • the N light-emitting units 21 in the same pixel circuit multiplexing unit 12 emit light sequentially within a frame time, and the light-emitting units 21 at corresponding positions in the pixel circuit multiplexing unit 12 in the same row simultaneously Luminous, can realize the image horizontal and vertical direction decomposition display, reduce display flicker.
  • an embodiment of the present disclosure further proposes a display panel 30, as shown in FIG. 25, including: a display substrate 200 as in the above-mentioned embodiment.
  • an embodiment of the present disclosure also proposes a display device 33, as shown in FIG. 26, comprising: a display panel 30 and a housing 34 as shown in the above-mentioned embodiment, which are arranged outside the display panel 30 .

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Abstract

一种显示基板（200），包括：多个像素驱动电路（11）；多组发光驱动信号线，多组发光驱动信号线中的每组发光驱动信号线包括多条发光驱动信号线；以及多个像素电路复用单元（12），与多个像素驱动电路（11）一一对应地连接，其中，每个像素电路复用单元（12）包括N个发光单元（21），N个发光单元（21）连接多个像素驱动电路（11）中的一个像素驱动电路（11），并且N个发光单元（21）与一组发光驱动信号线连接。

Description

显示基板、显示面板及显示设备
相关申请的交叉引用
本申请要求于2019年7月29日提交的、申请号为201910689209.6的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示领域，特别是涉及一种显示基板、显示面板及显示设备。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)面板具有主动发光、无视角问题、重量轻、厚度小、亮度高、发光效率高、响应速度快、动态画面质量高、使用温度范围广、可实现柔性显示、工艺简单、成本低、抗震能力强等一系列优点。由于OLED面板响应速度快，用于虚拟现实(Virtual Reality，简称VR)产品中可以有效减小眩晕感，具有巨大的应用潜力。
发明内容
在第一方面，本公开提供一种显示基板，包括：多个像素驱动电路；多组发光驱动信号线，所述多组发光驱动信号线中的每组发光驱动信号线包括多条发光驱动信号线；以及多个像素电路复用单元，分别与所述多个像素驱动电路连接，所述多个像素电路复用单元布置成D×E第一阵列，其中D和E均为大于1的整数，其中，所述多个像素电路复用单元中的每个像素电路复用单元包括布置成K×H第二阵列的N个发光单元，其中K、H和N均为大于1的整数，并且所述N个发光单元与所述多组发光驱动信号线中的一组发光驱动信号线连接，所述N个发光单元中的每个发光单元被配置为在所连接的所述发光驱动信号线处的发光驱动信号的控制下接收来自所连接的像素驱动电路的驱动信号，使得位于同一行的所有发光单元不同时发光，同一列的所有发光单元不同时发光，同一所述像素电路复用单元内的所述N个发光单元在一帧时间内依次发光。
在一些实施例中，所述多个像素电路复用单元与所述多个像素驱动电路一一对应地连接，并且所述每个像素电路复用单元中的N个发光单元连接所述多个像素驱动电 路中的同一个像素驱动电路。
在一些实施例中，所述每组发光驱动信号线包括N条发光驱动信号线；所述N条发光驱动信号线在第一方向上延伸并且在第二方向上排列，所述第一方向为所述第一阵列和所述第二阵列的行方向，所述第二方向为所述第一阵列和所述第二阵列的列方向；所述第一阵列中位于同一行的像素电路复用单元连接一组发光驱动信号线。
在一些实施例中，N＝2，每个像素电路复用单元包括布置成一列的第一发光单元和第二发光单元，所述N条发光驱动信号线包括第一发光驱动信号线和第二发光驱动信号线，其中，所述第一阵列中的第i行第j列所述像素电路复用单元中的第一发光单元和所述第一阵列中的第i行第j+1列所述像素电路复用单元中的第二发光单元连接第一发光驱动信号线，其中i和j均为整数，且1≤i≤D，1≤j≤E；所述第一阵列中的第i行第j列像素电路复用单元中的第二发光单元和所述第一阵列中的第i行第j+1列所述像素电路复用单元中的第一发光单元连接第二发光驱动信号线。
在一些实施例中，所述第一驱动信号线和第二驱动信号线均呈直线型沿第一方向延伸，所述第一发光单元和第二发光单元中的每一个经由过孔与所述第一发光驱动信号线或第二发光驱动信号线连接。
在一些实施例中，所述第一发光驱动信号线呈第一折线型沿第一方向延伸，以与所述第i行第j列像素电路复用单元中的第一发光单元和所述第i行第j+1列所述像素电路复用单元中的第二发光单元连接；所述第二发光驱动信号线呈第二折线型沿第一方向延伸，以与所述第i行第j列像素电路复用单元中的第二发光单元和所述第i行第j+1列所述像素电路复用单元中的第一发光单元连接。
在一些实施例中，所述N为大于2的偶数，每组发光驱动信号线中的N条发光驱动信号线按照从第一发光驱动信号线至第N发光驱动信号线的顺序沿所述第二方向排列；其中第二阵列中的第k行第h列发光单元与所述N条发光驱动信号线中的第n发光驱动信号线连接，其中k、h和n均为大于1的整数，1≤k≤K，1≤h≤H，其中n＝(k-1)H+h。
在一些实施例中，所述的显示基板还包括多组分组发光控制线，每个像素电路复用单元连接一组分组发光控制线，其中每组分组发光控制线包括M条分组发光控制线，所述像素电路复用单元中的所述N个发光单元分为M组发光单元，所述像素电路复用单元还包括M个开关电路，其中，第m开关电路与所述第m分组发光控制线、所述第m组发光单元和所述像素驱动电路连接，所述第m开关电路被配置为在所述第m分组 发光控制线处的第m分组发光控制信号的控制下将所述像素驱动电路产生的驱动电流提供至所述第m组发光单元，其中M是大于1的整数，m为整数且1≤m≤M。
在一些实施例中，所述多条发光驱动信号线在第二方向上延伸并且在第一方向上排列，所述第一分组发光控制线和所述第二分组发光控制线在第一方向上延伸并且在第二方向上排列；所述第一阵列中位于同一列的像素电路复用单元连接一组发光驱动信号线，位于同一行的像素电路复用单元连接一组分组发光控制线。
在一些实施例中，M＝2，所述M条分组发光控制线包括第一分组发光控制线和第二分组发光控制线，所述M组发光单元包括第一组发光单元和第二组发光单元，M个开关电路包括第一开关电路和第二开关电路，所述第一开关电路包括第一晶体管，所述第一晶体管的栅极连接所述第一分组发光控制线，所述第一晶体管的第一极连接所述像素驱动电路，所述第一晶体管的第二极连接所述第一组发光单元；所述第二开关电路包括第二晶体管，所述第二晶体管的栅极连接所述第二分组发光控制线，所述第二晶体管的第一极连接所述像素驱动电路，所述第二晶体管的第二极连接所述第二组发光单元。
在一些实施例中，所述N个发光单元中的每个发光单元包括：第三晶体管，所述第三晶体管的栅极连接多条发光驱动信号线之一，所述第三晶体管的第一极连接所述多个像素驱动电路之一；发光器件，所述发光器件的阳极连接所述第三晶体管的第二极，所述发光器件的阴极连接至参考信号线。
在一些实施例中，所述第三晶体管的栅极设置在所述显示基板的栅极层中，所述第三晶体管的第一极和第二极设置在所述显示基板的源漏层中，所述发光器件的阳极设置在所述显示基板的阳极层中，其中，所述发光器件的阳极具有在所述阳极层中向所述多条发光驱动信号线之一延伸的伸出部，所述伸出部经由过孔与源漏层中所述第三晶体管的第二极连接。
在一些实施例中，位于同一行相邻列的所述发光器件的阳极的所述伸出部在延伸方向上的长度不同。
在第二方面，本公开提供一种显示面板，包括如上所述的显示基板。
在第三方面，本公开提供一种显示设备，包括如上所述的显示面板。
附图说明
图1是相关技术中1∶2像素复用方案的示意图；
图2是相关技术中像素复用方案原理图；
图3是相关技术中像素电路的电路图；
图4是相关技术中相关技术中像素电路的工作时序图；
图5是相关技术中1∶2像素复用方案的发光单元分布示意图；
图6是相关技术中1∶2像素复用方案的图像分解示意图；
图7是相关技术中1∶4像素复用方案的图像分解示意图；
图8是根据本公开一个实施例的像素补充复用电路的结构图；
图9是根据本公开一个实施例的发光单元的排列及发光次序图；
图10是根据本公开一个实施例的图像分解示意图；
图11是根据本公开一个实施例的像素驱动电路的电路图；
图12是根据本公开一个实施例的像素电路复用单元的结构图；
图13是相关技术中显示基板的结构图；
图14是相关技术中阳极层中位于发光单元的延伸部的分布图；
图15是根据本公开一个实施例中阳极层中位于发光单元的延伸部的分布图；
图16是根据本公开另一个实施例的发光单元的排列及发光次序图；
图17是根据本公开另一个实施例的图像分解示意图；
图18是根据本公开另一个实施例的像素电路复用单元的结构图；
图19是根据本公开一个实施例的像素电路的工作时序图；
图20是根据本公开另一个实施例的像素电路复用单元的结构图；
图21是根据本公开一个实施例的像素电路的电路图；
图22是根据本公开另一个实施例的图像分解示意图；
图23是根据本公开另一个实施例的像素电路复用单元的结构图；
图24是根据本公开一个实施例的像素电路的电路图；
图25是根据本公开一个实施例的显示面板的结构图；
图26是根据本公开一个实施例的显示设备的结构图。
具体实施方式
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参 考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
下面结合附图来描述本公开实施例的像素电路、显示基板、显示面板及显示设备。像素复用方案即多个发光单元共用1个像素驱动电路。图1是相关技术中1∶2像素复用方案(两个发光单元共用1个像素驱动电路)的示意图。如图1所示，图像分解为子图像1和子图像2，其中，子图像1对应图像的第1、3、5...行，即奇数行；子图像2对应图像的第2、4、6...行，即偶数行。在1帧时间的前半帧控制奇数行发光单元发光，从而显示为子图像1。在1帧时间的后半帧控制偶数行发光单元发光，从而显示为子图像2。子图像1和子图像2叠加成完整图像。
如图2、图3、图4和图5所示，按照擎桥技术1∶2复用，子图像1和子图像2的第n行会共用一个像素驱动电路，复用同一个EM输出，同一个Gate输出。子图像1和子图像2的第n行的每个子像素都有对应的EM开关EM(n-1)、EM(n-2)。擎桥技术1∶2复用对应的像素电路可以看到2个子像素，合计为7T+1C，大大减少薄膜晶体管(Thin Film Transistor，简称TFT)的个数。
图6是相关技术中1∶2像素复用方案的图像分解示意图。如图6所示，分解后的奇数行图像和偶数行图像的画面差异较大，因此在上下半帧切换奇数行图像和偶数行图像时会在竖直方向产生闪烁。图7是相关技术中1∶4像素复用方案的图像分解示意图。如图7所示，1∶4像素复用方案图像分解后的图像画面差异更大，闪烁将更加严重。
为缓解相关技术中像素复用方案产生的显示闪烁，本公开提出了一种像素电路，如图8所示，像素电路111包括：多个像素驱动电路11；多个像素电路复用单元12，像素电路复用单元12与像素驱动电路11一一对应连接，像素电路复用单元12与对应的像素驱动电路11连接。
其中，像素电路复用单元12包括N个发光单元21，其中N/2个发光单元21分别位于第n行第m列至第m+i列，另外N/2个发光单元21分别位于第n+1行第m列至第m+i列，N为大于0的偶数，n为奇数，i等于N/2-1，同一行的所有发光单元不同时发光，同一列的所有发光单元不同时发光。
在本公开实施例中，像素电路复用单元12的N个发光单元21排列成2行，即第n 行(奇数行)和第n+1行(偶数行)，第n行包括N/2个发光单元21，第n+1行包括N/2个发光单元21。同一行的所有发光单元21不同时发光，同一列的所有发光单元21不同时发光，可实现1∶N的像素复用方案。由于N为大于0的偶数，因此本公开实施例可实现1∶2、1∶4、1∶6、......等像素复用方案。像素驱动电路11如图11所示，包括TFTT1、T2、T3、T4、T5及电容C1。
根据本公开实施例提出的像素电路111，像素电路复用单元12与像素驱动电路11一一对应连接，像素电路复用单元12包括N个发光单元21，其中N/2个发光单元21分别位于第n行第m列至第m+i列，另外N/2个发光单元21分别位于第n+1行第m列至第m+i列，N为大于0的偶数，n为奇数，i等于N/2-1。同一行的所有发光单元21不同时发光，同一列的所有发光单元21不同时发光，可实现图像横纵方向的分解显示，降低显示闪烁。
另外，在上述实施例的基础上，同一像素电路复用单元12内的N个发光单元21可在一帧时间内依次发光。
另外，在上述实施例的基础上，同一行相邻的N个发光单元21可在一帧时间内依次发光。
以N＝2为例，N＝2时，i＝0，则多个像素电路复用单元12可如图9所示排列。同一像素电路复用单元内的2个发光单元21在一帧时间内依次发光，同一行相邻的2个发光单元21在一帧时间内依次发光。如图9所示，标识相同的发光单元21同时发光(即标识1的发光单元21同时发光，标识2的发光单元21同时发光)，标识1与标识2的发光单元21依次发光。其显示效果如图10所示，可实现图像的横纵分解显示，降低显示闪烁。
另外，N等于2时，像素电路复用单元12还包括：2个发光驱动信号线，2个发光驱动信号线与2个发光单元21一一对应连接；同一行相邻的2个发光单元21与2个发光驱动信号线一一对应连接。
本公开提供了一种显示基板200，包括：多个像素驱动电路11；多组发光驱动信号线，所述多组发光驱动信号线中的每组发光驱动信号线包括多条发光驱动信号线；以及多个像素电路复用单元12，与所述多个像素驱动电路11一一对应地连接，所述多个 像素电路复用单元12布置成D×E第一阵列，其中D和E均为大于1的整数，其中，所述多个像素电路复用单元12中的每个像素电路复用单元12包括布置成K×H第二阵列的N个发光单元21，其中K、H和N均为大于1的整数，所述N个发光单元21连接所述多个像素驱动电路11中的一个像素驱动电路11，并且所述N个发光单元21与所述多组发光驱动信号线中的一组发光驱动信号线连接，所述N个发光单元21中的每个发光单元21被配置为在所连接的所述发光驱动信号线处的发光驱动信号的控制下接收来自所述多个连接的像素驱动电路11中的一个像素驱动电路11的驱动信号，使得位于同一行的所有发光单元21不同时发光，同一列的所有发光单元21不同时发光，同一所述像素电路复用单元12内的所述N个发光单元21在一帧时间内依次发光。
在一些实施例中，每组发光驱动信号线包括N条发光驱动信号线，所述N条发光驱动信号线在第一方向上延伸并且在第二方向上排列，所述第一方向为所述第一阵列和所述第二阵列的行方向，所述第二方向为所述第一阵列和所述第二阵列的列方向；所述第一阵列中位于同一行的像素电路复用单元12连接一组发光驱动信号线。
例如，N＝2，每个像素电路复用单元12包括布置成一列的第一发光单元和第二发光单元，所述N条发光驱动信号线包括第发光一驱动信号线和第二发光驱动信号线，其中，所述第一阵列中的第i行第j列所述像素电路复用单元12中的第一发光单元和所述第一阵列中的第i行第j+1列所述像素电路复用单元12中的第二发光单元连接第一发光驱动信号线，其中i和j均为整数，且1≤i≤D，1≤j≤E；所述第一阵列中的第i行第j列像素电路复用单元12中的第二发光单元和所述第一阵列中的第i行第j+1列所述像素电路复用单元12中的第一发光单元连接第二发光驱动信号线。
如图12所示，N＝2，位于第一阵列第1行第1列的像素电路复用单元12包括布置成一列的第一发光单元211和第二发光单元212，与该像素电路复用单元12对应连接的第一组发光驱动信号线EMG1包括第一发光驱动信号线EM1和第二发光驱动信号线EM2，此处第一驱动信号线和第二驱动信号线在其他组发光驱动信号线中使用其他附图标记表示，例如在第一阵列第2行第1列中可分别用EM3和EM4表示。所述第一阵列中的第1行第1列所述像素电路复用单元12中的第一发光单元211和所述第一阵列中的第1行第1列所述像素电路复用单元12中的第二发光单元212连接第一发光驱动 信号线EM1；所述第一阵列中的第1行第1列像素电路复用单元12中的第二发光单元212和所述第一阵列中的第1行第1列所述像素电路复用单元12中的第一发光单元211连接第二发光驱动信号线EM2。同理，在其他组像素电路复用单元12中采用类似的连接方式以与N条发光驱动信号线连接。
在一些实施例中，如图12所示，所述第一发光驱动信号线EM1呈第一折线型沿第一方向延伸，以与所述第1行第1列像素电路复用单元12中的第一发光单元211和所述第1行第1列所述像素电路复用单元12中的第二发光单元212连接；所述第二发光驱动信号线EM2呈第二折线型沿第一方向延伸，以与所述第1行第1列像素电路复用单元12中的第二发光单元212和所述第1行第1列所述像素电路复用单元12中的第一发光单元211连接。
例如EM1、EM2设计成折线型，通过异层金属走线，分别与像素电路复用单元12中2个发光单元211和212一一对应连接，且所述第1行第1列像素电路复用单元12中的第一发光单元211和所述第1行第2列像素电路复用单元12中的第一发光单元211分别与第一发光驱动信号线EM1和第二发光驱动信号线EM2一一对应连接。行扫描过程中仍保持同一帧时间内，先扫描奇数行，再扫描偶数行，从而可实现同一像素电路复用单元12内的2个发光单元21在一帧时间内依次发光，同一行相邻的2个发光单元21在一帧时间内依次发光，进而实现图像横纵方向的分解显示，降低显示闪烁。
上述将发光驱动信号线设计成折线型可实现同一像素电路复用单元12内的2个发光单元21在一帧时间内依次发光，且同一行相邻的2个发光单元21在一帧时间内依次发光。
在另外一些实施例中，所述每组发光驱动信号线包括N条发光驱动信号线，且N为大于2的偶数，每组发光驱动信号线中的N条发光驱动信号线按照从第一发光驱动信号线至第N发光驱动信号线的顺序沿所述第二方向排列；其中第二阵列中的第k行第h列发光单元与所述N条发光驱动信号线中的第n发光驱动信号线连接，其中k、h和n均为大于1的整数，1≤k≤K，1≤h≤H，其中n＝(k-1)H+h。
图13示出了相关技术中一种显示基板的示例性的局部的膜层结构图。其中，显示基板300包括：衬底基板210；栅极层270，设置在所述衬底基板210上；源漏极层230， 设置在栅极层270远离所述衬底基板210的一侧；阳极层240，位于所述源漏极层230的远离所述衬底基板210的一侧，并与所述源漏极层230经由过孔V1电连接；阴极层260，所述阴极层260位于阳极层240的远离所述衬底基板210的一侧；发光材料层250，位于所述阳极层240和所述阴极层260之间。
图14示出了相关技术中采用的一种显示基板的局部的平面示意图。其中，阳极层240中位于同一行的发光单元21的延伸部3111连接至同一行对应的发光驱动信号线，阳极层240中位于不同行的发光单元21的延伸部3111连接至不同的发光驱动信号线。例如，阳极层240中位于第一行的发光单元21的延伸部3111与第一行对应的发光驱动信号线EM1连接，阳极层240中位于第二行的发光单元21的延伸部3111与第二行对应的发光驱动信号线EM2连接。从图14中可以看出，每个发光单元的阳极层240的伸出部3111在延伸方向上的长度相同。
在本公开的一些实施例中，如图21所示，所述N个发光单元中的每个发光单元包括：第三晶体管，所述第三晶体管的栅极连接多条发光驱动信号线之一，所述第三晶体管的第一极连接所述多个像素驱动电路之一；发光器件，所述发光器件的阳极连接所述第三晶体管的第二极，所述发光器件的阴极连接至参考信号线ELVSS。所述第三晶体管的栅极设置在所述显示基板的栅极层中，所述第三晶体管的第一极和第二极设置在所述显示基板的源漏极层中，所述发光器件的阳极设置在所述显示基板的阳极层中，其中，所述发光器件的阳极具有在所述阳极层中向所述多条发光驱动信号线之一延伸的伸出部2111，所述伸出部2111经由过孔V1与所述源漏极层中所述第三晶体管的第二极连接。
图15示出了根据本公开实施例的一种显示基板的局部的平面示意图。其中，阳极层240中位于奇数行偶数列的发光单元21的延伸部2111延伸至下一行，以与下一行对应的发光驱动信号线EM2连接，阳极层240中位于偶数行偶数列的发光单元21的延伸部2111延伸至上一行，以与上一行对应的发光驱动信号线EM1连接。
如图15所示，第一阵列中位于第一行第一列的阳极层240的伸出部211与位于第一行第二列的阳极层240的伸出部211在延伸方向上的长度不同。
本公开实施例中，通过延伸阳极层240中位于奇数行偶数列的发光单元21的延伸 部2111延伸至下一行，以及阳极层中位于偶数行偶数列的发光单元21的延伸部2111伸至上一行，可使发光单元21中的阳极层的延伸出的延伸部2111交叉分布，从而同一行中相邻的2个发光单元21中的一个与发光驱动信号线例如EM1或EM2连接，以实现同一像素电路复用单元12内的2个发光单元21在一帧时间内依次发光，同一行相邻的2个发光单元21在一帧时间内依次发光，进而实现图像横纵方向的分解显示，降低显示闪烁。
根据本公开实施例提供的像素电路111，同一像素电路复用单元12内的N个发光单元21在一帧时间内依次发光，同一行相邻的N个发光单元21在一帧时间内依次发光，可实现图像横纵方向的分解显示，降低显示闪烁。另外，本公开还提出了一种像素电路111，如图8所示，包括：多个像素驱动电路11；多个像素电路复用单元12，像素电路复用单元12与像素驱动电路11一一对应，像素电路复用单元12与对应的像素驱动电路11连接。像素电路复用单元12包括N个发光单元21，其中N/2个发光单元21分别位于第n行第m列至第m+i列，另外N/2个发光单元21分别位于第n+1行第m列至第m+i列，N为大于2的偶数，n为奇数，i等于N/2-1。
本公开实施例中，像素电路复用单元12的N个发光单元21排列成2行，即第n行(奇数行)和第n+1行(偶数行)，第n行包括N/2个发光单元21，第n+1行包括N/2个发光单元21，同一行的所有发光单元21不同时发光，同一列的所有发光单元21不同时发光，同一像素电路复用单元12内的N个发光单元21在一帧时间内依次发光，同一行的像素电路复用单元12中相应位置的发光单元21同时发光。可控制同一像素电路复用单元12内的N个发光单元21按照先行后列的顺序或其他顺序依次发光，按照先行后列的顺序即第n行的N/2个发光单元先发光，第n+1行的N/2个发光单元后发光，且同一行内的N/2个发光单元按列依次发光，可实现1∶N的像素复用方案，由于N为大于2的偶数，因此本公开实施例可实现1∶4、1∶6、......等像素复用方案。
例如在1∶4的像素复用方案中，同一像素电路复用单元12内的N个发光单元21按照先行后列的顺序依次发光，N＝4，i＝1，则多个像素电路复用单元12可如图16所示排列。同一像素电路复用单元内的4个发光单元21在一帧时间内按照先行后列的顺序依次发光，同一行的像素电路复用单元12中相应位置的发光单元21同时发光，如图16 所示，标识相同的发光单元21同时发光(即标识1的发光单元21同时发光，标识2的发光单元21同时发光，标识3的发光单元21同时发光，标识4的发光单元21同时发光)，标识1、标识2、标识3、标识4的发光单元21依次发光。其显示效果如图17所示，可实现图像的横纵分解显示，降低显示闪烁。
像素驱动电路11如图11所示，包括TFT T1、T2、T3、T4、T5及电容C1。
根据本公开实施例提出的像素电路111，像素电路复用单元12与像素驱动电路11一一对应，像素电路复用单元12与对应的像素驱动电路11连接，像素电路复用单元12包括N个发光单元21，其中N/2个发光单元21分别位于第n行第m列至第m+i列，另外N/2个发光单元21分别位于第n+1行第m列至第m+i列，N为大于2的偶数，n为奇数，i等于N/2-1，同一像素电路复用单元12内的N个发光单元21在一帧时间内依次发光，同一行的像素电路复用单元12中相应位置的发光单元21同时发光，可实现图像横纵方向的分解显示，降低显示闪烁。
在一些实施例中，像素电路复用单元12包括：N条发光驱动信号线，N条发光驱动信号线与N个发光单元21一一对应连接；同一行的像素电路复用单元12中相应位置的发光单元21与同一发光驱动信号线连接。
例如，在1∶4的像素复用方案中，如图18所示，一个像素电路复用单元12包括四个发光单元21，与四个发光驱动信号线例如EM1、EM2、EM3和EM4一一对应连接。同一行的像素电路复用单元12中相应位置的发光单元21与同一发光驱动信号线连接，所述相应位置的发光单元21以间隔一个发光单元21的方式设置。其工作时序如图19所示，从而可实现同一像素电路复用单元12内的4个发光单元21在一帧时间内依次发光。同一行的像素电路复用单元12中相应位置的发光单元21同时发光，进而实现图像横纵方向的分解显示，降低显示闪烁。例如，在1∶6的像素复用方案中，如图20所示，一个像素电路复用单元12包括6个发光单元21，与6个发光驱动信号线例如EM1、EM2、EM3、EM4、EM5和EM6一一对应连接。同一行的像素电路复用单元12中相应位置的发光单元21与同一发光驱动信号线连接，所述相应位置的发光单元21以间隔两个发光单元21的方式设置。其像素电路的电路图如图21所示，从而实现同一像素电路复用单元12内的6个发光单元21在一帧时间内依次发光，同一行的像素电路复用单元12中 相应位置的发光单元21同时发光，其显示效果如图22所示，进而实现图像横纵方向的分解显示，降低显示闪烁。
根据本公开实施例提出的像素电路111，同一像素电路复用单元12内的N个发光单元21在一帧时间内依次发光，同一行的像素电路复用单元12中相应位置的发光单元21同时发光，可实现图像横纵方向的分解显示，降低显示闪烁。
在一些实施例中，对于1∶4和1∶6像素复用方案，如图18和图20所示，位于第i行第j列的所述阳极层240的伸出部2111在延伸方向上的长度与位于第i行第j+1列的所述阳极层240的伸出部2111在延伸方向上的长度不同。
在一些实施例中，所述显示基板200还包括多组分组发光控制线，每个像素电路复用单元12连接一组分组发光控制线，其中每组分组发光控制线包括M条分组发光控制线，所述像素电路复用单元中的所述N个发光单元分为M组发光单元，所述像素电路复用单元还包括M个开关电路，其中，第m开关电路与所述第m分组发光控制线、所述第m组发光单元和所述像素驱动电路连接，所述第m开关电路被配置为在所述第m分组发光控制线处的第m分组发光控制信号的控制下将所述像素驱动电路产生的驱动电流提供至所述第m组发光单元，其中M是大于1的整数，m为整数且1≤m≤M。
在一些实施例中，M＝2，所述M条分组发光控制线包括第一分组发光控制线和第二分组发光控制线，所述M组发光单元分为第一组发光单元H211和第二组发光单元H212，所述M个开关电路包括：第一开关电路，与所述第一分组发光控制线、所述第一组发光单元H211和所述像素驱动电路11连接，所述第一开关电路被配置为在第一分组发光控制线处的第一分组发光控制信号的控制下将所述像素驱动电路11产生的驱动电流提供至所述第一组发光单元H211；第二开关电路，与所述第二分组发光控制线、所述第二组发光单元H212和所述像素驱动电路11连接，第二开关电路被配置为在第二分组发光控制线处的第二分组发光控制信号的控制下将所述像素驱动电路11产生的驱动电流提供至所述第二组发光单元H212。
在一些实施例中，所述多条发光驱动信号线在第二方向上延伸并且在第一方向上排列，所述第一分组发光控制线和所述第二分组发光控制线在第一方向上延伸并且在第二方向上排列；所述第一阵列中位于同一列的像素电路复用单元12连接一组发光驱 动信号线，位于同一行的像素电路复用单元12连接一组分组发光控制线。
在一些实施例中，所述第一开关电路包括第一晶体管T12，所述第一晶体管T12的栅极连接所述第一分组发光控制线，所述第一晶体管T12的第一极连接所述像素驱动电路11，所述第一晶体管T12的第二极连接所述第一组发光单元H211；所述第二开关电路包括第二晶体管T13，所述第二晶体管T13的栅极连接所述第二分组发光控制线，所述第二晶体管T13的第一极连接所述像素驱动电路11，所述第二晶体管T13的第二极连接所述第二组发光单元H212。
如图24所示，M条分组发光控制线包括第一分组发光控制线(EM v1)和第二分组发光控制线(EM v2)；所述像素电路复用单元12中的N个发光单元21分为第一组发光单元H211和第二组发光单元H212。
如图24所示，所述像素电路复用单元12还包括第一开关电路和第二开关电路。
所述第一开关电路包括第一晶体管T12，所述第一晶体管T12的栅极连接所述第一分组发光控制线EMv1，所述第一晶体管T12的第一极连接所述像素驱动电路11，所述第一晶体管T12的第二极连接所述第一组发光单元H211；所述第二开关电路包括第二晶体管T13，所述第二晶体管T13的栅极连接所述第二分组发光控制线EMv2，所述第二晶体管T13的第一极连接所述像素驱动电路11，所述第二晶体管T13的第二极连接所述第二组发光单元H212。
第一晶体管T12与所述第一分组发光控制线、所述第一组发光单元和所述像素驱动电路11连接，所述第一晶体管T12被配置为在第一分组发光控制线EMv1处的第一分组发光控制信号的控制下将所述像素驱动电路11产生的驱动电流提供至所述第一组发光单元H211；第二晶体管T13与所述第二分组发光控制线EMv2、所述第二组发光单元H212和所述像素驱动电路11连接，所述第二晶体管T13被配置为在第二分组发光控制线EMv2处的第二分组发光控制信号的控制下将所述像素驱动电路11产生的驱动电流提供至所述第二组发光单元H212。
如图23所示，所述多条发光驱动信号线，例如EM H1、EM H2和EM H3在第二方向(行方向)上延伸并且在第一方向上排列(也称作行发光驱动信号线)；所述第一分组发光控制线EMv1和所述第二分组发光控制线EMv2在第一方向上延伸并且在第二方向 (列方向)上排列(也称作列发光驱动信号线)。
在一些实施例中，如图23所示，所述第一阵列中位于同一列(例如第一列)的像素电路复用单元(例如包括像素电路复用单元12及其同列的像素电路复用单元)连接发光驱动信号线EM H1、EM H2和EM H3。所述第一阵列中位于同一行(例如第一行)的像素电路复用单元(例如包括像素电路复用单元12及其同行的像素电路复用单元)连接所述第一分组发光控制线(例如EMv1)和所述第二分组发光控制线(例如EMv2)。
N/2个列发光驱动信号线与N/2个发光单元21一一对应连接，N/2个列发光驱动信号线还与另外N/2个发光单元21一一对应连接；同一列的像素电路复用单元12中相应位置的发光单元21与同一列发光驱动信号线连接。
另外，作为另一种可行的实施方式，像素电路复用单元12还可包括：2个行发光驱动信号线，2个行发光驱动信号线中的一个行发光驱动信号线与第一晶体管T12的控制端连接，2个行发光驱动信号线中的另一个行发光驱动信号线与第二晶体管T13的控制端连接；同一行的像素电路复用单元12中相应位置的开关电路的控制端与同一行发光驱动信号线连接。
在一些实施例中，例如N＝6时，像素电路复用单元12可如图23、图24所示，包括：第一晶体管T12，3个发光单元21通过第一晶体管T12与像素驱动电路11连接；第二晶体管T13，另外3个发光单元21通过第二晶体管T13与像素驱动电路11连接。
3个列发光驱动信号线例如EM H1、EM H2、EM H3与同一行中的3个发光单元21一一对应连接，3个列发光驱动信号线例如EM H1、EM H2、EM H3还与下一行中的另外3个发光单元21一一对应连接，同一列的像素电路复用单元12中相应位置的发光单元21与同一列发光驱动信号线连接；
2个行发光驱动信号线例如EMv1、EMv2中的一个行发光驱动信号线例如EMv1与第一晶体管T12的控制端连接，2个行发光驱动信号线中的另一个行发光驱动信号线例如EMv2与第二晶体管T13的控制端连接，同一行的像素电路复用单元12中相应位置的开关电路的控制端与同一行发光驱动信号线连接。从而实现同一像素电路复用单元12内的6个发光单元21在一帧时间内依次发光，同一行的像素电路复用单元12中相应位置的发光单元21同时发光，其显示效果如图22所示，进而实现图像横纵方向的 分解显示，降低显示闪烁，并减少信号线数量。
根据本公开实施例提出的像素电路111，同一像素电路复用单元12内的N个发光单元21在一帧时间内依次发光，同一行的像素电路复用单元12中相应位置的发光单元21同时发光，可实现图像横纵方向的分解显示，降低显示闪烁。
为了实现上述实施例，本公开实施例还提出一种显示面板30，如图25所示，包括：如上述实施例的显示基板200。
为了实现上述实施例，本公开实施例还提出一种显示设备33，如图26所示，包括：如上述实施例所示的显示面板30和壳体34，设置在所述显示面板30的外部。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、或“一些示例”等的描述意指结合该实施例或示例描述的特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必针对的是相同的实施例或示例。而且，描述的特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (15)

  1. 一种显示基板，包括：
    多个像素驱动电路；
    多组发光驱动信号线，所述多组发光驱动信号线中的每组发光驱动信号线包括多条发光驱动信号线；以及
    多个像素电路复用单元，分别与所述多个像素驱动电路连接，所述多个像素电路复用单元布置成D×E第一阵列，其中D和E均为大于1的整数，
    其中，所述多个像素电路复用单元中的每个像素电路复用单元包括布置成K×H第二阵列的N个发光单元，其中K、H和N均为大于1的整数，并且所述N个发光单元与所述多组发光驱动信号线中的一组发光驱动信号线连接，所述N个发光单元中的每个发光单元被配置为在所连接的所述发光驱动信号线处的发光驱动信号的控制下接收来自所连接的像素驱动电路的驱动信号，使得位于同一行的所有发光单元不同时发光，同一列的所有发光单元不同时发光，同一所述像素电路复用单元内的所述N个发光单元在一帧时间内依次发光。
  2. 根据权利要求1所述的显示基板，其中，所述多个像素电路复用单元与所述多个像素驱动电路一一对应地连接，并且所述每个像素电路复用单元中的N个发光单元连接所述多个像素驱动电路中的同一个像素驱动电路。
  3. 根据权利要求2所述的显示基板，其中，所述每组发光驱动信号线包括N条发光驱动信号线；
    所述N条发光驱动信号线在第一方向上延伸并且在第二方向上排列，所述第一方向为所述第一阵列和所述第二阵列的行方向，所述第二方向为所述第一阵列和所述第二阵列的列方向；
    所述第一阵列中位于同一行的像素电路复用单元连接一组发光驱动信号线。
  4. 根据权利要求3所述的显示基板，其中，N＝2，每个像素电路复用单元包括布置成一列的第一发光单元和第二发光单元，所述N条发光驱动信号线包括第一发光驱动信号线和第二发光驱动信号线，其中，
    所述第一阵列中的第i行第j列所述像素电路复用单元中的第一发光单元和所述第一阵列中的第i行第j+1列所述像素电路复用单元中的第二发光单元连接第一发光驱动 信号线，其中i和j均为整数，且1≤i≤D，1≤j≤E；
    所述第一阵列中的第i行第j列像素电路复用单元中的第二发光单元和所述第一阵列中的第i行第j+1列所述像素电路复用单元中的第一发光单元连接第二发光驱动信号线。
  5. 根据权利要求4所述的显示基板，其中，所述第一发光驱动信号线和第二发光驱动信号线均呈直线型沿第一方向延伸，所述第一发光单元和第二发光单元中的每一个经由过孔与所述第一发光驱动信号线或第二发光驱动信号线连接。
  6. 根据权利要求4所述的显示基板，其中，
    所述第一发光驱动信号线呈第一折线型沿第一方向延伸，以与所述第i行第j列像素电路复用单元中的第一发光单元和所述第i行第j+1列所述像素电路复用单元中的第二发光单元连接；
    所述第二发光驱动信号线呈第二折线型沿第一方向延伸，以与所述第i行第j列像素电路复用单元中的第二发光单元和所述第i行第j+1列所述像素电路复用单元中的第一发光单元连接。
  7. 根据权利要求3所述的显示基板，其中，所述N为大于2的偶数，每组发光驱动信号线中的N条发光驱动信号线按照从第一发光驱动信号线至第N发光驱动信号线的顺序沿所述第二方向排列；
    其中第二阵列中的第k行第h列发光单元与所述N条发光驱动信号线中的第n发光驱动信号线连接，其中k、h和n均为大于1的整数，1≤k≤K，1≤h≤H，其中n＝(k-1)H+h。
  8. 根据权利要求2所述的显示基板，还包括多组分组发光控制线，每个像素电路复用单元连接一组分组发光控制线，其中每组分组发光控制线包括M条分组发光控制线，所述像素电路复用单元中的所述N个发光单元分为M组发光单元，所述像素电路复用单元还包括M个开关电路，其中，第m开关电路与所述第m分组发光控制线、所述第m组发光单元和所述像素驱动电路连接，所述第m开关电路被配置为在所述第m分组发光控制线处的第m分组发光控制信号的控制下将所述像素驱动电路产生的驱动电流提供至所述第m组发光单元，其中M是大于1的整数，m为整数且1≤m≤M。
  9. 根据权利要求8所述的显示基板，其中，
    所述多条发光驱动信号线在第二方向上延伸并且在第一方向上排列，所述M条分组发光控制线在第一方向上延伸并且在第二方向上排列；
    所述第一阵列中位于同一列的像素电路复用单元连接一组发光驱动信号线，位于同一行的像素电路复用单元连接一组分组发光控制线。
  10. 根据权利要求8或9所述的显示基板，其中，M＝2，所述M条分组发光控制线包括第一分组发光控制线和第二分组发光控制线，所述M组发光单元包括第一组发光单元和第二组发光单元，M个开关电路包括第一开关电路和第二开关电路，
    所述第一开关电路包括第一晶体管，所述第一晶体管的栅极连接所述第一分组发光控制线，所述第一晶体管的第一极连接所述像素驱动电路，所述第一晶体管的第二极连接所述第一组发光单元；
    所述第二开关电路包括第二晶体管，所述第二晶体管的栅极连接所述第二分组发光控制线，所述第二晶体管的第一极连接所述像素驱动电路，所述第二晶体管的第二极连接所述第二组发光单元。
  11. 根据权利要求1至10中任一项权利要求所述的显示基板，其中，所述N个发光单元中的每个发光单元包括：
    第三晶体管，所述第三晶体管的栅极连接多条发光驱动信号线之一，所述第三晶体管的第一极连接所述多个像素驱动电路之一；
    发光器件，所述发光器件的阳极连接所述第三晶体管的第二极，所述发光器件的阴极连接至参考信号线。
  12. 根据权利要求11所述的显示基板，其中，所述第三晶体管的栅极设置在所述显示基板的栅极层中，所述第三晶体管的第一极和第二极设置在所述显示基板的源漏层中，所述发光器件的阳极设置在所述显示基板的阳极层中，其中，
    所述发光器件的阳极具有在所述阳极层中向所述多条发光驱动信号线之一延伸的伸出部，所述伸出部经由过孔与源漏层中所述第三晶体管的第二极连接。
  13. 根据权利要求12所述的显示基板，其中，位于同一行相邻列的所述发光器件的阳极的所述伸出部在延伸方向上的长度不同。
  14. 一种显示面板，包括如权利要求1-13任一项所述的显示基板。
  15. 一种显示设备，包括如权利要求14所述的显示面板。
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