WO2021017499A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2021017499A1
WO2021017499A1 PCT/CN2020/080940 CN2020080940W WO2021017499A1 WO 2021017499 A1 WO2021017499 A1 WO 2021017499A1 CN 2020080940 W CN2020080940 W CN 2020080940W WO 2021017499 A1 WO2021017499 A1 WO 2021017499A1
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Prior art keywords
light
emitting device
substrate
layer
display panel
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PCT/CN2020/080940
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English (en)
French (fr)
Inventor
田文亚
郭恩卿
王程功
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成都辰显光电有限公司
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Priority to KR1020227002704A priority Critical patent/KR20220027177A/ko
Publication of WO2021017499A1 publication Critical patent/WO2021017499A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages

Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a display panel and a manufacturing method thereof.
  • Silicon-based microdisplay technology combines the display with monocrystalline silicon integrated circuits.
  • the display panel using silicon-based microdisplay technology has the advantages of higher display resolution, large viewing angle, fast response speed, high brightness, and low power consumption. This makes silicon Microdisplay technology has broad application prospects in increasing the size and definition of image display, reducing the number of system chips to reduce the cost of the system and the space volume of products.
  • silicon-based microscopic technology can be applied to military, medical, aerospace and Various fields such as electronic consumption.
  • the laser stripping of the light-emitting chip and the welding process of the light-emitting chip and the backplane will greatly reduce the production yield of the display panel, and for the display panel using silicon-based micro-display technology, the light-emitting chip achieves flip-chip alignment with high accuracy
  • the welding technology is extremely difficult, which further reduces the production yield of the display panel, and it is difficult to use the quantum dot color conversion technology in the related technology to realize the color display of the display panel.
  • the present application provides a display panel and a manufacturing method thereof, which reduces the influence of the laser lift-off process and the bonding process on the production yield of the display panel, reduces the difficulty of bonding and alignment during mass transfer, and realizes the display panel, for example, Color display of micro display panel.
  • the present application provides a display panel, including:
  • the light-emitting color of the device is different;
  • the first light emitting device and the second light emitting device are epitaxially grown on the substrate, and the third light emitting device is bonded to the substrate.
  • the present application also provides a manufacturing method of a display panel for manufacturing the display panel described in any embodiment of the present application, and the manufacturing method includes:
  • the third light-emitting device is bonded on the substrate and the temporary substrate is peeled off.
  • the present application provides a display panel and a manufacturing method thereof.
  • the display panel includes a substrate and a plurality of first light-emitting devices, a plurality of second light-emitting devices, and a plurality of third light-emitting devices on the substrate.
  • the first light-emitting device The second light-emitting device and the second light-emitting device are epitaxially grown on the substrate, and the third light-emitting device is bonded on the substrate, which reduces the influence of the laser lift-off process and the bonding process on the production yield of the display panel, and reduces the bonding during mass transfer It is difficult to align the display panel, especially the color display of the micro display panel.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a top view structure of a display panel provided by an embodiment of the application.
  • FIG. 3 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the application
  • 4 to 14 are schematic cross-sectional structural diagrams corresponding to the steps in FIG. 3.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the application
  • FIG. 2 is a schematic top view structure of a display panel provided by an embodiment of the application. 1 and 2
  • the display panel includes a substrate 10 and a plurality of first light emitting devices 1, a plurality of second light emitting devices 2 and a plurality of third light emitting devices 3 on the substrate 10.
  • the second light-emitting device 2 and the third light-emitting device 3 have different light-emitting colors.
  • the first light-emitting device 1 and the second light-emitting device 2 are epitaxially grown on the substrate 10, and the third light-emitting device 3 is bonded to the substrate 10.
  • the first light-emitting device 1 can be set as a blue light-emitting device
  • the second light-emitting device 2 is a green light-emitting device
  • the third light-emitting device 3 is a red light-emitting device
  • the first light-emitting device can be epitaxially grown on the substrate 10. 1 and the second light-emitting device 2, namely the blue light-emitting device and the green light-emitting device
  • the third light-emitting device 3, namely the red light-emitting device is epitaxially grown on another substrate, and then the third light-emitting device is connected by flip-chip bonding technology 3. That is, the red light emitting device is bonded on the substrate 10 on which the first light emitting device 1 and the second light emitting device 2, namely the blue light emitting device and the green light emitting device are grown.
  • the display panel may be a silicon-based micro display panel, and the light-emitting device may be a Micro LED.
  • the silicon-based micro display panel when the silicon-based micro display panel is manufactured, if the silicon-based micro display panel includes three-color light-emitting devices, one batch transfer is required Light-emitting devices of the same color can be manufactured by using three laser stripping and bonding techniques to complete the display panel. However, the laser stripping of the light-emitting device and the welding process of the light-emitting device and the backplane will damage the light-emitting device and greatly reduce the display The production yield of the panel.
  • the size of light-emitting devices is extremely small, which makes it extremely difficult to achieve high-precision flip-chip soldering technology for light-emitting devices, that is, it is extremely difficult to align the light-emitting devices, which further reduces the display panel’s Production yield.
  • the display panel by setting the display panel to include a substrate 10 and a plurality of first light emitting devices 1, a plurality of second light emitting devices 2 and a plurality of third light emitting devices 3 on the substrate 10, the first light emitting device 1 and the second light-emitting device 2 are epitaxially grown on the substrate 10, and the third light-emitting device 3 is bonded to the substrate 10, eliminating the need for laser lift-off and bonding processes for the first light-emitting device 1 and the second light-emitting device 2. This reduces the probability of damage to the light-emitting device by the laser lift-off process and the bonding process, and improves the production yield of the display panel.
  • the related technologies for color display of display panels include quantum dot color conversion technology, that is, quantum dots of different colors are doped in the film to achieve color display, but for high-resolution display panels, such as silicon-based micro
  • quantum dot color conversion technology that is, quantum dots of different colors are doped in the film to achieve color display, but for high-resolution display panels, such as silicon-based micro
  • the size of the display panel and the light-emitting device is extremely small, and it is difficult to use the quantum dot color conversion technology in the related art to realize color display.
  • the first light-emitting device 1 and the second light-emitting device 2 can be epitaxially grown on the substrate 10
  • the third light-emitting device 3 can be epitaxially grown on another temporary substrate. Therefore, multiple quantum well layers of different colors can be used to make Different light-emitting devices emit light of different colors, thereby realizing the color display of a display panel, such as a silicon-based microdisplay panel.
  • the first light-emitting device 1 and the second light-emitting device 2 may share the N-type semiconductor layer 4, for example, the first light-emitting device 1 and the second light-emitting device may be provided on the substrate 10. 2.
  • a patterned N-type semiconductor layer 4 is formed on the position of the blue light-emitting device and the green light-emitting device.
  • the pattern The formed N-type semiconductor layer 4 covers the position on the substrate 10 where the first light-emitting device 1 and the second light-emitting device 2 are required, and exposes the position where the third light-emitting device 3 is required on the substrate 10, such as a red light-emitting device.
  • adjacent first light-emitting devices 1 and second light-emitting devices 2 can be set to share the cathode structure 5, all the cathode structures 5 form a grid structure, and the cathode structure 5 is located in the N-type semiconductor In the layer 4, the N-type semiconductor layer 4 includes a channel region a located between the adjacent first light-emitting device 1 and the second light-emitting device 2. Along the direction perpendicular to the display panel, the cathode structure 5 is arranged corresponding to the channel region a .
  • the first light-emitting device 1 and the second light-emitting device 2 for example, a blue light-emitting device and a green light-emitting device share a cathode structure 5, and the cathode structure 5 of the two is located in the N-type semiconductor layer 4 shared by both
  • the N-type semiconductor layer 4 includes a channel region a located between the adjacent first light-emitting device 1 and the second light-emitting device 2, and the channel region a has an electron doping concentration relative to other positions of the N-type semiconductor layer 4 It is smaller to form a channel region a, and the cathode structure 5 is arranged corresponding to the channel region a to realize the transmission of electrons to the light-emitting functional layer 6 so that the first light-emitting device 1 and the second light-emitting device 2 emit light.
  • a grid-like structure formed by the cathode structure 5 corresponding to the first light-emitting device 1 and the second light-emitting device 2 may be arranged to be electrically connected to the driving chip through the cathode signal line around the non-display area, so as to realize the driving chip to the first light-emitting device.
  • the transmission of the cathode signal of 1 and the second light emitting device 2 makes the first light emitting device 1 and the second light emitting device 2 emit light.
  • setting the adjacent first light-emitting device 1 and second light-emitting device 2 to share the cathode structure 5 also simplifies the manufacturing process of display panels, such as silicon-based microdisplay panels, and improves the utilization of cathode materials in the light-emitting devices.
  • the light-emitting functional layer 6 of each light-emitting device may be located between the N-type semiconductor layer 4 and the P-type semiconductor layer 7, for example, a first light-emitting device 1 and a second light-emitting device may be provided.
  • 2 is a Micro LED with a front-mounted structure
  • the third light-emitting device 3 is a vertical Micro LED.
  • the light-emitting function layer 6 is located between the N-type semiconductor layer 4 and the P-type semiconductor layer 7, and the anode structure 8 of the light-emitting device is located on the P-type semiconductor.
  • Layer 7 is on the side facing away from the light-emitting functional layer 6, and the cathode structure 5 is located on the side of the light-emitting functional layer 6 facing away from the P-type semiconductor layer 7, that is, the anode structure 8 and the cathode structure 5 of each light-emitting device are located on the side of the light-emitting functional layer 6.
  • the size of the light-emitting device is extremely small.
  • the anode structure 8 and the cathode structure 5 are located on the same side of the light-emitting functional layer 6, which will make the anode structure 8 and the cathode of the light-emitting device
  • the structure 5 is easy to short circuit, which affects the normal display of the display panel.
  • the anode structure 8 and the cathode structure 5 of each light emitting device are located on both sides of the light emitting function layer 6, which effectively avoids the short circuit of the anode structure 8 and the cathode structure 5 of the light emitting device. Display abnormal problems.
  • the anode structure 8 of the first light-emitting device 1 and the anode structure 8 of the second light-emitting device 2 are both located on the side of the light-emitting function layer 6 facing away from the substrate 10, and the third light-emitting device The anode structure 8 of the device 3 is located on the side of the light-emitting functional layer 6 facing the substrate 10.
  • the display panel further includes a plurality of pixel driving circuits 9 located in the substrate 10, the anode structure 8 of the first light-emitting device 1, and the second light-emitting device
  • the anode structure 8 of 2 and the anode structure 8 of the third light-emitting device 3 are electrically connected to the corresponding pixel driving circuit 9.
  • the anode structure 8 of the first light-emitting device 1 and the anode structure 8 of the second light-emitting device 2 are both located on the side of the light-emitting functional layer 6 facing away from the substrate 10, and the light-emitting functional layer of each light-emitting device 6 is located between the N-type semiconductor layer 4 and the P-type semiconductor layer 7, then the cathode structure 5 of the first light-emitting device 1 and the cathode structure 5 of the second light-emitting device 2 are both located on the side of the light-emitting functional layer 6 facing the substrate 10.
  • the first light-emitting device 1 and the second light-emitting device 2 share the cathode structure 5 and all the cathode structures 5 form a grid-like structure.
  • the grid-like cathode structure 5 is electrically connected to the cathode signal line in the non-display area.
  • the first light-emitting device 1 and The cathode structure 5 of the second light-emitting device 2 receives the cathode signal, the anode structure 8 of the first light-emitting device 1 and the anode structure 8 of the second light-emitting device 2 are electrically connected to the corresponding pixel driving circuit 9 located in the substrate 10.
  • the driving circuit 9 provides anode signals to the first light emitting device 1 and the second light emitting device 2 to realize active driving of the first light emitting device 1 and the second light emitting device 2.
  • the anode structure 8 of the third light-emitting device 3 is located on the side of the light-emitting functional layer 6 facing the substrate 10, and the light-emitting functional layer 6 of each light-emitting device is located between the N-type semiconductor layer 4 and the P-type semiconductor layer 7, then the third The cathode structure 5 of the light emitting device 3 is located on the side of the light emitting function layer 6 facing away from the substrate 10, and the cathode structure 5 of the third light emitting device 3 is electrically connected to the cathode layer 11 located on the side of the third light emitting device 3 facing away from the substrate 10
  • the cathode layer 11 can be connected to the cathode signal line in the non-display area, and the driving chip transmits the cathode signal to the cathode layer 11 through the cathode signal line.
  • the cathode structure 5 of the third light-emitting device 3 receives the cathode signal.
  • the third light-emitting device 3 The anode structure 8 is electrically connected to a corresponding pixel driving circuit 9 located in the substrate 10, and the pixel driving circuit provides an anode signal to the third light-emitting device 3 to realize active driving of the third light-emitting device 3.
  • the area a0 between the adjacent first light-emitting device 1 and the second light-emitting device 2 may be provided with a pixel drive circuit 9 corresponding to the first light-emitting device 1, and corresponding to the second light-emitting device 1.
  • the pixel drive circuit 91 can be set to be electrically connected to the first light-emitting device 1.
  • the pixel driving circuit 92 is electrically connected to the second light emitting device 2, and the pixel driving circuit 93 is electrically connected to the third light emitting device 3.
  • the surface of the substrate 10 used for epitaxial growth of the first light-emitting device 1 and the second light-emitting device 2 can be etched into the first crystal orientation.
  • the first crystal orientation can be, for example, the 111 crystal orientation.
  • the surface of the substrate 10 without the first light-emitting device 1 and the second light-emitting device 2 can maintain the second crystal orientation.
  • the second crystal orientation can be, for example, 100 crystal orientation. This part of the surface is shown in FIG. Shown as a plane, the pixel driving circuit 9 can be set in the area where the substrate 10 with 100 crystal orientation is located, so that the first light-emitting device 1 and the second light-emitting device 2 are epitaxially grown in the area where the substrate 10 with the 111 crystal orientation is not affected.
  • the area a0 between the adjacent first light-emitting device 1 and the second light-emitting device 2 is fully utilized to make the corresponding pixel driving circuit 9, so that The first light emitting device 1, the second light emitting device 2 and the third light emitting device 3 are easily connected with the corresponding pixel driving circuit 9 to realize active driving of the first light emitting device 1, the second light emitting device 2 and the third light emitting device 3 .
  • the display panel further includes an insulating layer 12 covering the first light emitting device 1 and the second light emitting device 2, and covering the first light emitting device 1, the second light emitting device 2 and the third light emitting device.
  • the planarization layer 13 of the device 3, the anode structure 8 of the first light-emitting device 1 and the anode structure 8 of the second light-emitting device 2 pass through the insulating layer 12 and pass through part of the planarization layer 13, the insulating layer 12, and part of the substrate 10.
  • the hole is electrically connected to the corresponding pixel driving circuit 9.
  • the anode structure 8 of the third light emitting device 3 is electrically connected to the corresponding pixel driving circuit 9 through the through hole penetrating the insulating layer 12 and part of the substrate 10.
  • the cathode of the third light emitting device 3 The structure 5 is electrically connected to the cathode layer 11 on the side of the third light-emitting device 3 facing away from the substrate 10 through a through hole penetrating part of the planarization layer 13.
  • the light-emitting device includes a light-emitting functional layer 6 and an N-type semiconductor layer 4 and a P-type semiconductor layer 7 located on both sides of the light-emitting functional layer 6, an anode structure 8 and a cathode structure 5, the insulating layer 12 here.
  • the layer 13 covering the first light emitting device 1, the second light emitting device 2 and the third light emitting device 3 can also be understood as flattening the N-type semiconductor layer covering at least the first light emitting device 1, the second light emitting device 2 and the third light emitting device 3. 4. Light-emitting functional layer 6 and P-type semiconductor layer 7.
  • Holes can be punched at the position where the insulating layer 12 covers the first light emitting device 1 and the second light emitting device 2 to expose the anode structure 8 of the first light emitting device 1 and the anode structure 8 of the second light emitting device 2, and then partially planarize
  • the layer 13, the insulating layer 12, and part of the substrate 10 are punched to make wires connecting the anode structure 8 of the first light-emitting device 1, the anode structure 8 of the second light-emitting device 2 and the corresponding pixel driving circuit 9, as shown in FIG.
  • the anode structure 8 penetrates the insulating layer 12 and is electrically connected to the corresponding pixel drive circuit 9 through the through holes that penetrate part of the planarization layer 13, the insulating layer 12 and part of the substrate 10, so as to realize the connection of the pixel drive circuit 9 to the first light-emitting device 1
  • the anode structure 8 and the anode structure 8 of the second light emitting device 2 transmit anode signals.
  • FIG. 1 exemplarily shows the wire connecting the anode structure 8 of the first light-emitting device 1 and the anode structure 8 of the second light-emitting device 2 with the corresponding pixel driving circuit 9 in an arc. It can be understood that the wire The process is compatible with the current semiconductor manufacturing process.
  • a hole may be punched in the insulating layer 12 corresponding to the area a0 between the adjacent first light emitting device 1 and the second light emitting device 2 to expose the anode structure 8 on the substrate 10 for bonding the third light emitting device 3
  • the bonding pad 17 of the substrate 10 corresponds to the area a0 between the adjacent first light-emitting device 1 and the second light-emitting device 2 to form a bonding pad 17 penetrating the insulating layer 12, and the bonding pad 17 is bonded
  • the anode structure 8 of the third light-emitting device 3 is combined, and the bonding pad 17 is electrically connected to the pixel driving circuit 9 corresponding to the third light-emitting device 3 through a through hole penetrating part of the substrate 10, that is, the anode structure 8 of the third light-emitting device 3
  • the pixel driving circuit 9 is implemented to transmit the ano
  • a hole may be punched in the area of the planarization layer 13 corresponding to the third light-emitting device 3 to expose the cathode structure 5 of the third light-emitting device 3.
  • the third light-emitting device 3 is provided with a cathode layer 11 on the side facing away from the substrate 10.
  • the cathode layer 11 receives the cathode signal transmitted by the cathode signal line.
  • the cathode structure 5 of the third light-emitting device 3 is electrically connected to the cathode layer 11 on the side of the third light-emitting device 3 facing away from the substrate 10 through the through hole penetrating part of the planarization layer 13. Connected, the cathode structure 5 of the third light emitting device 3 receives the cathode signal.
  • the display panel includes a plurality of pixel drive circuits 9, the pixel drive circuit 9 is a digital drive circuit, the digital drive circuit uses a digital signal to drive the light-emitting device to emit light, which is adjusted by controlling the light-emitting time of the light-emitting device
  • the light-emitting brightness of the light-emitting device avoids the problems of susceptibility to interference of analog signals and low grayscale value adjustment accuracy in the use of analog driving circuits
  • the digital driving circuit does not include a capacitor structure, which is beneficial to reduce the area occupied by the pixel driving circuit, especially For the silicon-based micro display panel, it is beneficial to improve the resolution of the display panel.
  • the digital driving circuit may adopt a static random access memory (SRAM) circuit to realize the active driving of the display panel.
  • SRAM static random access memory
  • FIG. 1 only exemplarily substitutes one thin film transistor for one pixel drive circuit 9, and does not represent the actual number of thin film transistors in the pixel drive circuit 9.
  • the embodiment of the present application has an impact on the thin film transistors included in the pixel drive circuit 9 The specific number is not limited.
  • the drawings illustrated in the embodiments of the present application only exemplarily show the size of each element, and do not represent the actual size of each element.
  • FIG. 3 is a schematic flow chart of a method for manufacturing a display panel provided by an embodiment of the application.
  • the manufacturing method is used to manufacture the display panel of the foregoing embodiment, as shown in FIG.
  • the manufacturing method of the display panel includes steps S101 to S104.
  • step S101 a substrate is provided.
  • a substrate 10 is provided.
  • the substrate 10 may be a silicon-based substrate 10.
  • step S102 the first light emitting device and the second light emitting device are epitaxially grown on the substrate.
  • the first crystal orientation can be etched on the surface of the substrate 10 corresponding to the first area a1.
  • the first area a1 is the area where the first light emitting device 1 and the second light emitting device 2 are located.
  • the area a1 where the first light-emitting device 1 and the second light-emitting device 2 need to be formed on a 4-inch or 8-inch silicon-based wafer with a 100 crystal orientation is imaged and etched with a 111 crystal orientation, that is, the first crystal. to.
  • an N-type semiconductor layer 4 is formed on the substrate 10 in a region corresponding to the first region a1.
  • the first light-emitting device 1 and the second light-emitting device 2 share the N-type semiconductor layer 4.
  • An N-type semiconductor layer 4 is formed on the bottom 10 corresponding to the first light-emitting device 1 and the second light-emitting device 2 area.
  • the N-type semiconductor layer 4 forms a grid structure as shown in FIG. 2.
  • a mask 18 can be used to A metal-organic chemical vapor deposition (Metal-organic Chemical Vapor DeP osition, MOCVD) chamber grows a buffer layer composed of ALN (aluminum nitride) material or GAN (gallium nitride) material (not shown in the figure) and N-type semiconductor
  • the layer 4 for example, an N-GaN layer, that is, an N-type gallium nitride layer, can form the first light-emitting device 1 and the first light-emitting device 1 and the N-type semiconductor layer 4 of the first light-emitting device 1 and the second light-emitting device 2
  • the light-emitting functional layer 6 of the first light-emitting device 1 is formed in a partial area of the N-type semiconductor layer 4.
  • the light-emitting functional layer 6 of the first light-emitting device 1 is a multiple quantum well layer, and the first light-emitting The device 1 may be a blue light-emitting device, for example, and another mask 19 may be used to grow the light-emitting function layer 6 of the first light-emitting device 1, that is, a blue multi-quantum well layer. Nitrogen can be used as a carrier gas in this process.
  • the light-emitting functional layer 6 of the second light-emitting device 2 is formed in another part of the N-type semiconductor layer 4.
  • the light-emitting functional layer 6 of the second light-emitting device 2 is a multiple quantum well layer, and the second
  • the light-emitting device 2 may be a green light-emitting device, and the mask 19 for growing the first light-emitting device 1 can be used to continue to grow the light-emitting functional layer 6 of the second light-emitting device 2, that is, the green light multiple quantum well layer. It is also possible to use nitrogen as the carrier gas.
  • a P-type semiconductor layer 7 is formed on the light-emitting functional layer 6 of the first light-emitting device 1 and the light-emitting functional layer 6 of the second light-emitting device 2, for example, in the light-emitting function of the first light-emitting device 1.
  • the functional layer 6 and the light-emitting functional layer 6 of the second light-emitting device 2 are respectively grown on the P-type GaN layer, and then the ITO current spreading layer 16 can be continuously grown to form the P-type of the first light-emitting device 1 and the second light-emitting device 2 respectively.
  • the ITO current spreading layer 16 is beneficial to improve the uniformity of the carrier distribution in the light-emitting functional layer 6, and optimize the light-emitting effect of the light-emitting device.
  • the P-type semiconductor layer 7 and the ITO current spreading layer 16 can share a mask Plate 20 is formed.
  • the mask 20 is removed, and the entire silicon oxide insulating layer 12 is grown to cover the first light-emitting device 1 and the second light-emitting device 2 grown before .
  • a pixel drive circuit 9 can be fabricated on the 100 crystal plane of the substrate 10 by using a semiconductor process.
  • the pixel drive circuit 9 can be a capacitorless digital drive circuit, for example
  • the SRAM driving circuit and the pixel driving circuit 9 can be implemented on the limited space of the silicon-based backplane.
  • the insulating layer 12 and part of the substrate 10 can be etched to form a groove corresponding to the area between the adjacent first light-emitting device 1 and the second light-emitting device 2.
  • the semiconductor manufacturing process of thin film transistors is used to form the corresponding pixel driving circuit 9 in the groove, and finally the structure shown in FIG. 11 is formed.
  • a hole can be opened at the position where the insulating layer 12 covers the first light emitting device 1 and the second light emitting device 2, and the anode structure of the first light emitting device 1 and the second light emitting device 2 can be fabricated by a deposition process 8.
  • the material constituting the anode structure 8 may include chromium platinum, and the insulating layer 12 between the adjacent first light emitting device 1 and the second light emitting device 2 is etched at the same time, so as to reserve for bonding the third light emitting device 3, For example, the bonding pad 17 of the anode structure 8 of the red light-emitting device.
  • step S103 a third light emitting device is epitaxially grown on the temporary substrate.
  • the temporary substrate 14 may be, for example, a GaAs substrate.
  • a third light-emitting device 3 such as a red light-emitting device, is epitaxially grown.
  • a second light-emitting device is formed on the temporary substrate 14.
  • the light-emitting functional layer 6 is a red light quantum well layer, which is beneficial to realize the color display of the display panel, and especially solves the problem of micro The display panel is difficult to realize the problem of color display.
  • step S104 the third light emitting device is bonded on the substrate and the temporary substrate is peeled off.
  • the third light-emitting device 3 fabricated on the temporary substrate 14 is correspondingly attached to the driving backplane, that is, the substrate 10, and the third light-emitting device 3 is flip-chip bonded. After bonding, the temporary substrate 14 is peeled off, as shown in FIG. 14.
  • a planarization layer 13 is fabricated on a backplane containing pixels, and the anode structure 8 of the first light-emitting device 1 and the second light-emitting device 2 is electrically connected to the pixel driving circuit 9 on the backplane, and the flatness
  • the cathode layer 11 is formed on the side of the chemical layer 13 facing away from the substrate 10.
  • the cathode structure 5 of the third light-emitting device 3 is electrically connected to the cathode layer 11.
  • the cathode layer 11 may be a transparent cathode layer 11, and finally attached above the cathode layer 11.
  • the cover is packaged, and the cover 15 may be a glass cover.

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Abstract

本申请公开了一种显示面板及其制作方法，显示面板包括衬底以及位于衬底上的多个第一发光器件、多个第二发光器件和多个第三发光器件，第一发光器件、第二发光器件和第三发光器件的发光颜色不同；第一发光器件和第二发光器件外延生长于衬底上，第三发光器件键合于衬底上。

Description

显示面板及其制作方法
本申请要求在2019年07月26日提交中国专利局、申请号为201910683283.7的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种显示面板及其制作方法。
背景技术
硅基微显技术即将显示器与单晶硅集成电路结合，使用硅基微显技术的显示面板具有显示分辨率较高、视角大、响应速度快、亮度高以及功耗低等优点，这使得硅基微显技术在增加图像显示尺寸和清晰度，减少系统芯片数量以降低系统的成本和产品的空间体积方面具有广阔的应用前景，目前硅基微显技术可应用于军事、医学、航空航天以及电子消费等各个领域。
然而，发光芯片的激光剥离以及发光芯片与背板的焊接过程均会极大地降低显示面板的制作良率，且针对使用硅基微显技术的显示面板，发光芯片实现高对准精度的倒装焊接技术的难度极大，进一步降低了显示面板的制作良率，且很难利用相关技术中的量子点色转换技术实现显示面板的彩色化显示。
发明内容
本申请提供一种显示面板及其制作方法，降低了激光剥离工艺和键合工艺对显示面板制作良率的影响，降低了巨量转移时的键合对位难度，实现了显示面板，例如是微显示面板的彩色化显示。
在一实施例中，本申请提供了一种显示面板，包括：
衬底以及位于所述衬底上的多个第一发光器件、多个第二发光器件和多个第三发光器件，所述第一发光器件、所述第二发光器件和所述第三发光器件的发光颜色不同；
所述第一发光器件和所述第二发光器件外延生长于所述衬底上，所述第三发光器件键合于所述衬底上。
在另一实施例中，本申请还提供了一种显示面板的制作方法，用于制作本 申请任一实施例所述的显示面板，所述制作方法包括：
提供衬底；
在所述衬底上外延生长所述第一发光器件和所述第二发光器件；
在临时衬底上外延生长所述第三发光器件；
将所述第三发光器件键合在所述衬底上并剥离所述临时衬底。
本申请提供了一种显示面板及其制作方法，设置显示面板包括衬底以及位于衬底上的多个第一发光器件、多个第二发光器件和多个第三发光器件，第一发光器件和第二发光器件外延生长于衬底上，第三发光器件键合于衬底上，降低了激光剥离工艺和键合工艺对显示面板制作良率的影响，降低了巨量转移时的键合对位难度，实现了显示面板，尤其是微显示面板的彩色化显示。
附图概述
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1为本申请实施例提供的一种显示面板的剖面结构示意图；
图2为本申请实施例提供的一种显示面板的俯视结构示意图；
图3为本申请实施例提供的一种显示面板的制作方法的流程示意图；
图4至图14为对应图3中各步骤的剖面结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。贯穿本说明书中，相同或相似的附图标号代表相同或相似的结构、元件或流程。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
图1为本申请实施例提供的一种显示面板的剖面结构示意图，图2为本申请实施例提供的一种显示面板的俯视结构示意图。结合图1和图2，显示面板包括衬底10以及位于衬底10上的多个第一发光器件1、多个第二发光器件2和多个第三发光器件3，第一发光器件1、第二发光器件2和第三发光器件3的发光颜色不同，第一发光器件1和第二发光器件2外延生长于衬底10上，第三发光 器件3键合于衬底10上。
可选地，可以设置第一发光器件1为蓝色发光器件，第二发光器件2为绿色发光器件，第三发光器件3为红色发光器件，可以在衬底10上外延生长出第一发光器件1和第二发光器件2，即蓝色发光器件和绿色发光器件，在另外的衬底上外延生长出第三发光器件3，即红色发光器件，再采用倒装键合技术将第三发光器件3，即红色发光器件键合在生长有第一发光器件1和第二发光器件2，即蓝色发光器件和绿色发光器件的衬底10上。
可选地，显示面板可以为硅基微显示面板，发光器件可以为Micro LED，目前在制作硅基微显示面板时，如果硅基微显示面板包括三种颜色的发光器件，则需要一次批量转移同一种颜色的发光器件，采用三次激光剥离和键合技术才能完成显示面板的制作，但是对发光器件的激光剥离以及发光器件与背板的焊接的过程会算损伤发光器件，极大地降低了显示面板的制作良率。另外，针对硅基微显示面板，发光器件的尺寸极小，使得发光器件实现高对准精度的倒装焊接技术的难度极大，即发光器件的对位难度极大，进一步降低了显示面板的制作良率。
结合图1和图2，通过设置显示面板包括衬底10以及位于衬底10上的多个第一发光器件1、多个第二发光器件2和多个第三发光器件3，第一发光器件1和第二发光器件2外延生长于衬底10上，第三发光器件3键合于衬底10上，省掉了第一发光器件1和第二发光器件2的激光剥离和键合工艺，进而降低了激光剥离工艺和键合工艺损伤发光器件的概率，提高了显示面板的制作良率，另外，相对于采用三次键合对位，仅需在转移第三发光器件3时进行键合对位，尤其针对高分辨率的显示面板，例如硅基微显示面板，大大降低了巨量转移时的键合对位难度，进一步提高了显示面板的制作良率。
另外，显示面板实现彩色化显示的相关技术包括量子点色转换技术，即在膜层中掺杂有不同颜色的量子点，进而实现彩色显示，但是针对高分辨率的显示面板，例如硅基微显示面板，发光器件的尺寸极小，很难利用相关技术中的量子点色转换技术实现彩色化显示。本申请实施例可以在衬底10上外延生长第一发光器件1和第二发光器件2，在另外的临时衬底上外延生长第三发光器件3，因此可以利用不同颜色的多量子阱层使得不同发光器件发出不同颜色的光线，进而实现显示面板，例如硅基微显示面板的彩色化显示。
可选地，结合图1和图2，可以设置第一发光器件1与第二发光器件2共用 N型半导体层4，例如可以在衬底10上需设置第一发光器件1和第二发光器件2，例如蓝色发光器件和绿色发光器件的位置上形成一层图案化的N型半导体层4，以第一发光器件1、第二发光器件2和第三发光器件3矩阵排列为例，图案化的N型半导体层4覆盖衬底10上需设置第一发光器件1和第二发光器件2的位置，露出衬底10上需设置第三发光器件3，如红色发光器件的位置，这样第一发光器件1和第二发光器件2，例如蓝色发光器件和绿色发光器件共用N型半导体层4，简化了显示面板，例如硅基微显示面板的制作工艺，提高了发光器件中N型半导体材料的利用率。
可选地，结合图1和图2，可以设置相邻的第一发光器件1和第二发光器件2共用阴极结构5，所有的阴极结构5形成网格状结构，阴极结构5位于N型半导体层4中，N型半导体层4包括位于相邻的第一发光器件1和第二发光器件2之间的沟道区a，沿垂直于显示面板的方向，阴极结构5对应沟道区a设置。
结合图1和图2，第一发光器件1和第二发光器件2，例如蓝色发光器件和绿色发光器件共用阴极结构5，且二者的阴极结构5位于二者共用的N型半导体层4中，N型半导体层4包括位于相邻的第一发光器件1和第二发光器件2之间的沟道区a，该沟道区a相对于N型半导体层4其它位置的电子掺杂浓度较小，形成沟道区a，将阴极结构5对应沟道区a设置，以实现电子向发光功能层6的传输，使得第一发光器件1和第二发光器件2发光。另外，可以设置对应第一发光器件1和第二发光器件2的阴极结构5形成的网格状结构在围绕非显示区通过阴极信号线与驱动芯片电连接，进而实现驱动芯片向第一发光器件1和第二发光器件2的阴极信号的传输，使得第一发光器件1和第二发光器件2发光。另外，设置相邻的第一发光器件1和第二发光器件2共用阴极结构5，同样简化了显示面板，例如硅基微显示面板的制作工艺，提高了发光器件中阴极材料的利用率。
可选地，结合图1和图2，可以设置每个发光器件的发光功能层6位于N型半导体层4和P型半导体层7之间，例如可以设置第一发光器件1和第二发光器件2为正装结构的Micro LED，第三发光器件3为垂直型的Micro LED，发光功能层6位于N型半导体层4和P型半导体层7之间，则发光器件的阳极结构8位于P型半导体层7背向发光功能层6的一侧，阴极结构5位于发光功能层6背向P型半导体层7的一侧，即每个发光器件的阳极结构8和阴极结构5位于发光功能层6的两侧，针对高分辨率的显示面板，例如硅基微显示面板， 发光器件的尺寸极小，阳极结构8和阴极结构5位于发光功能层6的同侧会使得发光器件的阳极结构8和阴极结构5容易短路，影响显示面板的正常显示，设置每个发光器件的阳极结构8和阴极结构5位于发光功能层6的两侧，有效避免了发光器件的阳极结构8和阴极结构5短路导致的显示异常的问题。
可选地，结合图1和图2，可以设置第一发光器件1的阳极结构8和第二发光器件2的阳极结构8均位于发光功能层6背向衬底10的一侧，第三发光器件3的阳极结构8位于发光功能层6面向衬底10的一侧，显示面板还包括位于衬底10中的多个像素驱动电路9，第一发光器件1的阳极结构8、第二发光器件2的阳极结构8和第三发光器件3的阳极结构8与对应的像素驱动电路9电连接。
结合图1和图2，第一发光器件1的阳极结构8和第二发光器件2的阳极结构8均位于发光功能层6背向衬底10的一侧，且每个发光器件的发光功能层6位于N型半导体层4和P型半导体层7之间，则第一发光器件1的阴极结构5和第二发光器件2的阴极结构5均位于发光功能层6面向衬底10的一侧，第一发光器件1和第二发光器件2共用阴极结构5且所有阴极结构5形成网格状结构，网格状的阴极结构5在非显示区与阴极信号线电连接，第一发光器件1和第二发光器件2的阴极结构5接收到阴极信号，第一发光器件1的阳极结构8与第二发光器件2的阳极结构8与位于衬底10中的对应的像素驱动电路9电连接，像素驱动电路9向第一发光器件1和第二发光器件2提供阳极信号，实现对第一发光器件1以及第二发光器件2的有源驱动。
第三发光器件3的阳极结构8位于发光功能层6面向衬底10的一侧，且每个发光器件的发光功能层6位于N型半导体层4和P型半导体层7之间，则第三发光器件3的阴极结构5位于发光功能层6背向衬底10的一侧，第三发光器件3的阴极结构5与位于第三发光器件3背向衬底10一侧的阴极层11电连接，阴极层11可以在非显示区连接阴极信号线，驱动芯片通过阴极信号线向阴极层11传输阴极信号，第三发光器件3的阴极结构5接收到阴极信号，另外，第三发光器件3的阳极结构8与位于衬底10中对应的像素驱动电路9电连接，像素驱动线路向第三发光器件3提供阳极信号，实现对第三发光器件3的有源驱动。
可选地，结合图1和图2，相邻的第一发光器件1和第二发光器件2之间的区域a0可以设置有对应该第一发光器件1的像素驱动电路9、对应该第二发光器件2的像素驱动电路9，以及对应位于该第一发光器件1和该第二发光器件2之间的第三发光器件3的像素驱动电路9。
结合图1和图2，以第一发光器件1、第二发光器件2和第三发光器件3矩阵排列为例，可以对应相邻的第一发光器件1和第二发光器件2之间的区域a0的衬底10中设置三个像素驱动电路9，以第一发光器件1、第二发光器件2和第三发光器件3为例，可以设置像素驱动电路91与第一发光器件1电连接，像素驱动电路92与第二发光器件2电连接，像素驱动电路93与第三发光器件3电连接。
可选地，衬底10上用于外延生长第一发光器件1和第二发光器件2的表面可以腐蚀出第一晶向，第一晶向例如可以是111晶向，该部分表面如图1所示呈锯齿状，衬底10上未设置第一发光器件1和第二发光器件2的表面可以保持第二晶向，第二晶向例如可以是100晶向，该部分表面如图1所示为平面，则可以将像素驱动电路9均设置100晶向的衬底10所在区域，这样在不影响111晶向的衬底10所在区域外延生长第一发光器件1和第二发光器件2以实现第一发光器件1与第二发光器件2的单片集成的同时，充分利用了相邻的第一发光器件1与第二发光器件2之间的区域a0制作对应的像素驱动电路9，使得第一发光器件1、第二发光器件2和第三发光器件3易于与对应的像素驱动电路9连接以实现对第一发光器件1、第二发光器件2和第三发光器件3的有源驱动。
可选地，结合图1和图2，可以设置显示面板还包括覆盖第一发光器件1和第二发光器件2的绝缘层12以及覆盖第一发光器件1、第二发光器件2和第三发光器件3的平坦化层13，第一发光器件1的阳极结构8和第二发光器件2的阳极结构8贯穿绝缘层12且通过贯穿部分平坦化层13、绝缘层12和部分衬底10的通孔与对应的像素驱动电路9电连接，第三发光器件3的阳极结构8通过贯穿绝缘层12和部分衬底10的通孔与对应的像素驱动电路9电连接，第三发光器件3的阴极结构5通过贯穿部分平坦化层13的通孔与位于第三发光器件3背向衬底10一侧的阴极层11电连接。
结合图1和图2，发光器件包括发光功能层6以及位于发光功能层6两侧的N型半导体层4和P型半导体层7以及阳极结构8和阴极结构5，这里所说的绝缘层12覆盖第一发光器件1和第二发光器件2，为绝缘层12至少覆盖第一发光器件1以及第二发光器件2的N型半导体层4、发光功能层6和P型半导体层7，平坦化层13覆盖第一发光器件1、第二发光器件2和第三发光器件3同样可以理解为平坦化至少覆盖第一发光器件1、第二发光器件2和第三发光器件3的N型半导体层4、发光功能层6和P型半导体层7。
可以在绝缘层12覆盖第一发光器件1和第二发光器件2的位置上打孔以露出第一发光器件1的阳极结构8和第二发光器件2的阳极结构8，再通过对部分平坦化层13、绝缘层12以及部分衬底10进行打孔以制作连接第一发光器件1的阳极结构8、第二发光器件2的阳极结构8与对应的像素驱动电路9的导线，即图1中所示连接第一发光器件1的阳极结构8、第二发光器件2的阳极结构8与对应的像素驱动电路9的弧线，也即第一发光器件1的阳极结构8和第二发光器件2的阳极结构8贯穿绝缘层12且通过贯穿部分平坦化层13、绝缘层12和部分衬底10的通孔与对应的像素驱动电路9电连接，实现像素驱动电路9向第一发光器件1的阳极结构8和第二发光器件2的阳极结构8传输阳极信号。
需要说明的是，图1示例性地以弧线表示连接第一发光器件1的阳极结构8、第二发光器件2的阳极结构8与对应的像素驱动电路9的导线，可以理解的是，导线的工艺是兼容目前的半导体制作工艺的。
可选地，可以在绝缘层12对应相邻的第一发光器件1和第二发光器件2之间的区域a0打孔以露出衬底10上用于键合第三发光器件3的阳极结构8的键合焊盘17，即在衬底10对应相邻的第一发光器件1和第二发光器件2之间的区域a0形成贯穿绝缘层12的键合焊盘17，键合焊盘17键合第三发光器件3的阳极结构8，键合焊盘17通过贯穿部分衬底10的通孔与对应第三发光器件3的像素驱动电路9电连接，即第三发光器件3的阳极结构8通过贯穿绝缘层12和部分衬底10的通孔与对应的像素驱动电路9电连接，实现了像素驱动电路9向第三发光器件3的阳极结构8传输阳极信号。
可选地，可以在平坦化层13对应第三发光器件3的区域打孔以露出第三发光器件3的阴极结构5，第三发光器件3背向衬底10一侧设置有阴极层11，阴极层11接收阴极信号线传输的阴极信号，第三发光器件3的阴极结构5通过贯穿部分平坦化层13的通孔与位于第三发光器件3背向衬底10一侧的阴极层11电连接，第三发光器件3的阴极结构5接收到阴极信号。
可选地，结合图1和图2，显示面板包括多个像素驱动电路9，像素驱动电路9为数字驱动电路，数字驱动电路采用数字信号驱动发光器件发光，通过控制发光器件的发光时间来调节发光器件的发光亮度，避免了采用模拟驱动电路存在的模拟信号易受干扰以及灰阶值调节精度低的问题，且数字驱动电路不包括电容结构，有利于减小像素驱动电路所占面积，尤其针对硅基微显示面板，有利于提高显示面板的分辨率，数字驱动电路例如可以采用静态随机存取存储 器(Static Random Access Memory，SRAM)电路以实现显示面板的有源驱动。
需要说明的是，图1仅示例性地以一个薄膜晶体管代一个像素驱动电路9，不代表像素驱动电路9中薄膜晶体管的实际数量，本申请实施例对像素驱动电路9中包含的薄膜晶体管的具体数量不作限定。另外需要说明的是，本申请实施例示附图只是示例性的表示各元件的大小，并不代表各元件的实际尺寸。
本申请实施例还提供了一种显示面板的制作方法，图3为本申请实施例提供的一种显示面板的制作方法的流程示意图，该制作方法用于制作上述实施例的显示面板，如图3所示，显示面板的制作方法包括步骤S101至步骤S104。
在步骤S101中，提供衬底。
结合图1、图2和图4，提供衬底10，示例性地，衬底10可以为硅基衬底10。
在步骤S102中，在衬底上外延生长第一发光器件和第二发光器件。
结合图1、图2和图5，可以在衬底10对应第一区域a1的表面腐蚀出第一晶向，第一区域a1为第一发光器件1和第二发光器件2所在区域，例如可以在4英寸或8英寸的硅基晶向为100晶向的晶圆上需要形成第一发光器件1和第二发光器件2的区域a1采用湿法图像化腐蚀出111晶向，即第一晶向。
结合图1、图2和图6，在衬底10上对应第一区域a1的区域形成N型半导体层4，第一发光器件1和第二发光器件2共用N型半导体层4，可以在衬底10上对应第一发光器件1和第二发光器件2的区域形成N型半导体层4，N型半导体层4形成如图2所示的网格状结构，例如可以使用一块掩膜版18在金属有机化合物化学气相沉积(Metal-organic Chemical Vapor DeP osition，MOCVD)腔室内生长ALN(氮化铝)材料或GAN(氮化镓)材料构成的缓冲层(图中未示出)以及N型半导体层4，例如为N-GaN层，即N型氮化镓层，可以在形成第一发光器件1与第二发光器件2的N型半导体层4时形成网格状的第一发光器件1和第二发光器件2的阴极结构5。
结合图1、图2和图7，在N型半导体层4的部分区域形成第一发光器件1的发光功能层6，第一发光器件1的发光功能层6为多量子阱层，第一发光器件1例如可以为蓝色发光器件，则可以采用另一个掩膜版19生长第一发光器件1的发光功能层6，即蓝光多量子阱层，此过程可以使用氮气作为载气。
结合图1、图2和图8，在N型半导体层4的另外部分区域形成第二发光器件2的发光功能层6，第二发光器件2的发光功能层6为多量子阱层，第二发光 器件2例如可以为绿色发光器件，则可以采用生长第一发光器件1的掩膜版19移位后继续生长第二发光器件2的发光功能层6，即绿光多量子阱层，此过程同样可以使用氮气作为载气。
结合图1、图2和图9，在第一发光器件1的发光功能层6和第二发光器件2的发光功能层6上分别形成P型半导体层7，例如在第一发光器件1的发光功能层6和第二发光器件2的发光功能层6上分别生长P型的GaN层，之后还可以继续生长ITO电流扩展层16，分别形成于第一发光器件1和第二发光器件2的P型半导体层7上方，ITO电流扩展层16有利于提高载流子在发光功能层6中分布的均匀性，优化发光器件的发光效果，P型半导体层7和ITO电流扩展层16可以共用掩膜版20形成。
结合图1、图2和图10，形成ITO电流扩展层16之后，去除掩膜版20，生长整层的氧化硅绝缘层12，包覆之前生长的第一发光器件1和第二发光器件2。
结合图1、图2和图11，形成上述绝缘层12之后，可以在衬底10的100晶面上利用半导体工艺制作像素驱动电路9，像素驱动电路9可以是无电容的数字驱动电路，例如SRAM驱动电路，像素驱动电路9可以在硅基背板有限的空间上完成。示例性地，可以在制作完绝缘层12之后，对应相邻的第一发光器件1和第二发光器件2之间的区域，可以刻蚀绝缘层12与部分衬底10以形成凹槽，在凹槽内利用薄膜晶体管的半导体制作工艺形成对应的像素驱动电路9，最终形成如图11所示的结构。
结合图1、图2和图12，可以在绝缘层12覆盖第一发光器件1和第二发光器件2的位置开孔，采用沉积工艺制作第一发光器件1和第二发光器件2的阳极结构8，构成阳极结构8的材料可以包括铬铂金，同时刻蚀相邻第一发光器件1和第二发光器件2之间的绝缘层12，以预留出用于键合第三发光器件3，例如红色发光器件的阳极结构8的键合焊盘17。
在步骤S103中，在临时衬底上外延生长第三发光器件。
结合图1、图2和图13，临时衬底14例如可以是GaAs衬底，在临时衬底14上外延生长第三发光器件3，例如红色发光器件，例如在临时衬底14上依次形成第三发光器件3的N型半导体层4、发光功能层6、P型半导体层7以及阳极结构8，发光功能层6为红光量子阱层，有利于实现显示面板的彩色化显示，尤其解决了微显示面板难以实现彩色化显示的问题。
在步骤S104中，将第三发光器件键合在衬底上并剥离临时衬底。
结合图1、图2和图13，将在临时衬底14上制作好的第三发光器件3与驱动背板，即衬底10对应贴合，倒装键合第三发光器件3，倒装键合后剥离临时衬底14，如图14所示。
结合图1和图2，在含有像素的背板上制作平坦化层13，将第一发光器件1和第二发光器件2的阳极结构8与背板上的像素驱动电路9电连接，在平坦化层13背向衬底10的一侧形成阴极层11，第三发光器件3的阴极结构5与阴极层11电连接，阴极层11可以为透明阴极层11，最后在阴极层11上方贴附盖板封装，盖板15可以是玻璃盖板。

Claims (13)

  1. 一种显示面板，包括：
    衬底；
    位于所述衬底上的多个第一发光器件、多个第二发光器件和多个第三发光器件，所述第一发光器件、所述第二发光器件和所述第三发光器件的发光颜色不同；
    所述第一发光器件和所述第二发光器件外延生长于所述衬底上，所述第三发光器件键合于所述衬底上。
  2. 根据权利要求1所述的显示面板，其中，所述第一发光器件与所述第二发光器件共用N型半导体层。
  3. 根据权利要求2所述的显示面板，其中，相邻的所述第一发光器件和所述第二发光器件共用阴极结构，所有的所述阴极结构形成网格状结构。
  4. 根据权利要求3所述的显示面板，其中，所述阴极结构位于所述N型半导体层中，所述N型半导体层包括位于相邻的所述第一发光器件和所述第二发光器件之间的沟道区，沿垂直于所述显示面板所在平面的方向，所述阴极结构对应所述沟道区设置。
  5. 根据权利要求1-4任一项所述的显示面板，其中，每个发光器件的发光功能层位于N型半导体层和P型半导体层之间。
  6. 根据权利要求5所述的显示面板，其中，所述第一发光器件的阳极结构和所述第二发光器件的阳极结构均位于所述发光功能层背向所述衬底的一侧，所述第三发光器件的阳极结构位于所述发光功能层面向所述衬底的一侧。
  7. 根据权利要求6所述的显示面板，还包括：
    位于所述衬底中的多个像素驱动电路，所述第一发光器件的阳极结构、所述第二发光器件的阳极结构和所述第三发光器件的阳极结构与对应的所述像素驱动电路电连接，所述第三发光器件的阴极结构与位于所述第三发光器件背向所述衬底一侧的阴极层电连接。
  8. 根据权利要求7所述的显示面板，其中，相邻的所述第一发光器件和所述第二发光器件之间的区域设置有对应所述第一发光器件的像素驱动电路、对应所述第二发光器件的像素驱动电路、以及对应位于所述第一发光器件和所述第二发光器件之间的所述第三发光器件的像素驱动电路。
  9. 根据权利要求8所述的显示面板，还包括：
    覆盖所述第一发光器件和所述第二发光器件的绝缘层以及覆盖所述第一发 光器件、所述第二发光器件和所述第三发光器件的平坦化层；
    所述第一发光器件的阳极结构和所述第二发光器件的阳极结构贯穿所述绝缘层且通过贯穿部分所述平坦化层、所述绝缘层和部分所述衬底的通孔与对应的所述像素驱动电路电连接；
    所述第三发光器件的阳极结构通过贯穿所述绝缘层和部分所述衬底的通孔与对应的所述像素驱动电路电连接，所述第三发光器件的阴极结构通过贯穿部分所述平坦化层的通孔与所述阴极层电连接。
  10. 根据权利要求1所述的显示面板，还包括：
    多个像素驱动电路，所述像素驱动电路为数字驱动电路。
  11. 一种显示面板的制作方法，用于制作如权利要求1-10任一项所述的显示面板，其中，所述制作方法包括：
    提供衬底；
    在所述衬底上外延生长所述第一发光器件和所述第二发光器件；
    在临时衬底上外延生长所述第三发光器件；
    将所述第三发光器件键合在所述衬底上并剥离所述临时衬底。
  12. 根据权利要求11所述的方法，其中，所述在所述衬底上外延生长所述第一发光器件和所述第二发光器件包括：
    在所述衬底对应第一区域的表面腐蚀出第一晶向；其中，所述第一区域为所述第一发光器件和所述第二发光器件所在区域；
    在所述衬底上对应所述第一区域的区域形成N型半导体层；
    在所述N型半导体层的部分区域形成所述第一发光器件的发光功能层；
    在所述N型半导体层的部分区域形成所述第二发光器件的发光功能层；
    在所述第一发光器件的发光功能层和所述第二发光器件的发光功能层上分别形成P型半导体层。
  13. 根据权利要求12所述的方法，其中，所述第一发光器件的发光功能层为多量子阱层，所述第二发光器件的发光功能层为多量子阱层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115236910A (zh) * 2022-09-23 2022-10-25 惠科股份有限公司 显示面板及显示装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416243B (zh) * 2019-07-26 2021-11-12 成都辰显光电有限公司 一种显示面板及其制作方法
CN113745259B (zh) * 2020-05-29 2024-02-27 成都辰显光电有限公司 发光二极管显示面板及其制备方法
CN114420720B (zh) * 2022-03-29 2022-06-17 季华实验室 一种MicroLED显示面板制作方法及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140159065A1 (en) * 2012-12-11 2014-06-12 LuxVue Technology Corporation Stabilization structure including sacrificial release layer and staging cavity
CN104934456A (zh) * 2014-03-20 2015-09-23 联想(北京)有限公司 发光装置
CN107919414A (zh) * 2017-12-04 2018-04-17 歌尔股份有限公司 微发光二极管转移的方法、制造方法、装置和电子设备
CN109742200A (zh) * 2019-01-11 2019-05-10 京东方科技集团股份有限公司 一种显示面板的制备方法、显示面板及显示装置
WO2019103566A1 (en) * 2017-11-27 2019-05-31 Seoul Viosys Co., Ltd. Led unit for display and display apparatus having the same
CN110416243A (zh) * 2019-07-26 2019-11-05 云谷（固安）科技有限公司 一种显示面板及其制作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1649514B1 (en) * 2003-07-30 2014-01-01 Panasonic Corporation Semiconductor light emitting device, light emitting module, and lighting apparatus
CN101859757B (zh) * 2009-04-07 2014-04-09 裕星企业有限公司 堆栈发光二极管芯片结构及其制造方法
US9455242B2 (en) * 2010-09-06 2016-09-27 Epistar Corporation Semiconductor optoelectronic device
CN103066178B (zh) * 2012-12-29 2015-07-29 映瑞光电科技(上海)有限公司 一种倒装光子晶体led芯片及其制造方法
CN105489727B (zh) * 2016-01-18 2018-06-19 厦门市三安光电科技有限公司 倒装led芯片的键合电极结构及制作方法
CN107017319A (zh) * 2017-05-23 2017-08-04 深圳市华星光电技术有限公司 彩色微发光二极管阵列基板的制作方法
CN107946417B (zh) * 2017-11-29 2019-09-03 北京工业大学 一种全色微型led阵列垂直外延制备方法
CN108538878A (zh) * 2018-07-11 2018-09-14 大连德豪光电科技有限公司 微发光二极管基板及其制备方法、显示装置
CN109860092B (zh) * 2019-01-02 2020-10-02 南京中电熊猫液晶显示科技有限公司 一种微型发光二极管巨量转移的方法及显示器
CN109873060B (zh) * 2019-04-18 2020-11-13 广东省半导体产业技术研究院 一种微发光二极管阵列制作方法
CN109994579B (zh) * 2019-04-30 2020-12-25 成都辰显光电有限公司 微型led显示面板的制备方法和微型led显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140159065A1 (en) * 2012-12-11 2014-06-12 LuxVue Technology Corporation Stabilization structure including sacrificial release layer and staging cavity
CN104934456A (zh) * 2014-03-20 2015-09-23 联想(北京)有限公司 发光装置
WO2019103566A1 (en) * 2017-11-27 2019-05-31 Seoul Viosys Co., Ltd. Led unit for display and display apparatus having the same
CN107919414A (zh) * 2017-12-04 2018-04-17 歌尔股份有限公司 微发光二极管转移的方法、制造方法、装置和电子设备
CN109742200A (zh) * 2019-01-11 2019-05-10 京东方科技集团股份有限公司 一种显示面板的制备方法、显示面板及显示装置
CN110416243A (zh) * 2019-07-26 2019-11-05 云谷（固安）科技有限公司 一种显示面板及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115236910A (zh) * 2022-09-23 2022-10-25 惠科股份有限公司 显示面板及显示装置
US11916053B1 (en) 2022-09-23 2024-02-27 HKC Corporation Limited Display panel and display device

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