WO2021017412A1

WO2021017412A1 - Phased array beam control device and control method therefor

Info

Publication number: WO2021017412A1
Application number: PCT/CN2020/070260
Authority: WO
Inventors: 包晓军; 刘远曦; 李琳; 刘会涛; 王育才; 刘航; 黄辉
Original assignee: 珠海纳睿达科技有限公司
Priority date: 2019-07-30
Filing date: 2020-01-03
Publication date: 2021-02-04
Also published as: CN110471334A; CN110471334B

Abstract

A phased array beam control device, a firmware upgrade method, and a radar. The phased array beam control device comprises a first FPGA module (10) used for processing phase data of a beam in real time; a second FPGA module (20) used for outputting corresponding instructions to a plurality of radio frequency receiving and transmitting components according to the data processed by the first FPGA module (10); a clock and synchronous signal module (30) used for generating a clock signal and synchronizing same to the first FPGA module (10) and the second FPGA module (20); a first DDR module (60) used for storing process data generated by the first FPGA module (10); a FLASH module (50) used for storing and loading the required configuration information; and a power supply module (40) used for supplying power to the first FPGA module (10) and the second FPGA module (20). A single phased array beam control device consisting of the first FPGA module (10) and the second FPGA module (20) can achieve logic control of the plurality of radio frequency receiving and transmitting components, and reduce the number of beam control devices, thereby reducing the system hardware cost.

Description

Phased array beam control device and control method thereof

Technical field

The present invention relates to the technical field of signal processing, in particular to a phased array beam control device and a control method thereof.

Background technique

The beam control devices of phased array radar usually include centralized and distributed. Among them, centralized refers to the unified operation of the amplitude and phase of each array unit of the phased array by a set of beam control devices. After the calculation is completed, the phase is shifted. The data of the receiver and the attenuator is distributed to each antenna array unit, the amount of hardware equipment is small, and the cost is low, but the computing time will increase with the increase of the antenna unit, which affects the speed of beam scanning. Distributed means that the entire array antenna is divided into multiple sub-arrays. Each sub-array is controlled by a beam control device. Each beam control device only calculates the phase shift of the radio frequency transmitting and receiving components in the sub-array, thereby reducing the calculation time and meeting the beam requirements. However, the increase in the number of beam control devices required will lead to increased costs, decreased reliability, and a large amount of debugging and maintenance work.

Summary of the invention

The purpose of the present invention is to solve at least one of the technical problems existing in the prior art, and provide a phased array beam control device and control method thereof, which can control multiple radio frequency transceiver components through a single beam control device, reducing beam control devices Therefore, the system hardware cost is reduced.

The first aspect of the present invention provides a phased array beam control device, including:

The first FPGA module is used to process the phase data of the beam;

The second FPGA module is interactively connected to the first FPGA module, and is configured to output corresponding instructions to multiple radio frequency transceiver components according to the phase data processed by the first FPGA module;

A clock and synchronization signal module, the output ports of the clock and synchronization signal modules are respectively connected to the input ports of the first FPGA module and the second FPGA module, and are used to generate a clock signal and synchronize to the first FPGA module And the second FPGA module;

A first DDR module, interactively connected with the first FPGA module, and used for storing process data generated by the first FPGA module;

The FLASH module is interactively connected with the first FPGA module 10 and is used to store configuration information required for loading;

A power supply module, where the power output ports of the power supply module are respectively connected to the power input ports of the first FPGA module and the second FPGA module, and are used to supply power to the first FPGA module and the second FPGA module.

The above-mentioned phased array beam control device has at least the following beneficial effects: the first FPGA module is used to process the phase data of the beam in real time, and the second FPGA module is used to perform multi-processing based on the data processed by the first FPGA module. Each radio frequency transceiver component outputs corresponding instructions. A single phased array beam control device composed of the above-mentioned first FPGA module and second FPGA module can simultaneously realize the logical control of multiple radio frequency transceiver components, reducing the number of beam control devices , Thereby reducing the cost of system hardware.

The phased array beam control device according to the first aspect of the present invention further includes:

The PHY module is interactively connected to the first FPGA module and the external network, and is used to implement data exchange between the first FPGA module and the external network;

The first DDR module is also used to buffer the control data received by the PHY module;

The FLASH module is also used to store the upgrade data received by the PHY module. The PHY module is set on the device to receive data from the external network, and can receive the control data or upgrade data transmitted by the external network, such as the control data or upgrade data transmitted by the Ethernet, which can realize the remote control or remote upgrade of the control device, and improve the operation and operation of the control device. Convenience of maintenance.

According to the phased array beam control device according to the first aspect of the present invention, the first FPGA module is also used to monitor the status of multiple radio frequency transceiver components. The first FPGA module monitors the status of the radio frequency transceiver components by collecting data in real time, and can discover the faulty radio frequency transceiver components in time, so as to perform timely maintenance on the malfunctioning radio frequency transceiver components.

According to the phased array beam control device according to the first aspect of the present invention, the first FPGA module includes:

processor;

A clock module for generating a clock signal for use by the processor;

The first register module is used to latch variable data generated by the processor;

The first high-speed serdes interface module is used to implement communication between the first FPGA module and the second FPGA module;

The reset module is used to reset the processor. The structure of the first FPGA module is only used to realize the calculation and processing of data, which can effectively increase the speed of calculation, thereby increasing the beam scanning speed of the whole machine.

According to the phased array beam control device according to the first aspect of the present invention, the processor includes:

The MAC module is used to receive TCP protocol message information and process phase data according to the message information;

The second DDR module is used to control the first DDR module and store temporary data generated by the MAC module;

Timer module, used to generate timing interrupt signal;

The interrupt module is used to uniformly manage the interrupt signals generated by the timer module according to different priorities;

SPI module, used to communicate with external FLASH chip;

ENVM module, used to store application data and upgrade data;

IIC module, used to monitor the status of multiple radio frequency transceiver components;

The MAC module, the second DDR module, the timer module, the interrupt module 112, the SPI module, the ENVM module, and the IIC module are interactively connected.

According to the phased array beam control device according to the first aspect of the present invention, the second FPGA module includes:

The second high-speed serdes interface module is used to implement communication between the second FPGA module 20 and the first FPGA module;

The FIFO module is used to store the amplitude and phase data output from the second high-speed serdes interface module, and manage the data output from the second high-speed serdes interface module according to the principle of first in, first out;

The second register module is used to store variable data;

Synchronization signal module, used to output synchronization signals;

The scheduler module is used to sample the synchronization signal to form various control logics, read the amplitude and phase information stored in the FIFO module, and output the information to the corresponding control pin through the output module 25;

Output module, used to allocate control signal pins. The architecture of the second FPGA module is only used to implement the data processed by the first FPGA module and output corresponding instructions to the radio frequency transceiver component, which can effectively improve the control efficiency of the radio frequency transceiver component by the control device.

According to the phased array beam control device according to the first aspect of the present invention, the first FPGA module and the second FPGA module are connected through a serdes serial interface. The serdes serial interface is a high-speed serial interface. The serdes serial interface is connected between the first FPGA module and the second FPGA module to achieve high-speed wave-controlled data transmission.

The second aspect of the present invention provides a control method applied to the above-mentioned phased array beam control device, including the following steps:

The first FPGA module processes the phase data of the beam;

The second FPGA module outputs corresponding instructions to multiple radio frequency transceiver components according to the phase data processed by the first FPGA module.

The firmware upgrade method according to the second aspect of the present invention has at least the following beneficial effects: the first FPGA module is used to process the phase data of the beam in real time, and the second FPGA module is used to perform data processing based on the data processed by the first FPGA module. Multiple radio frequency transceiver components output corresponding instructions. A single phased array beam control device composed of the above-mentioned first FPGA module and second FPGA module 20 can simultaneously realize the logical control of multiple radio frequency transceiver components, reducing beam control devices Therefore, the system hardware cost is reduced.

The control method according to the second aspect of the present invention further includes the following steps:

Remotely transfer firmware via Ethernet;

PHY module receives the firmware transmitted by Ethernet;

Store the firmware to the FLASH module, and set the firmware update flag to 1;

Reset and restart the first FPGA module, and load an upgrade program;

Read the firmware update flag bit of the FLASH module, and if the flag bit is 1, copy the new version firmware to the corresponding address bit in the first FPGA module to overwrite the old firmware;

Set the firmware update flag bit of the FLASH module to 0;

Reset the first FPGA module. The above firmware upgrade method can realize the remote upgrade of the phased array beam control device of the first aspect of the present invention, avoids the tedious operation of on-site upgrade and maintenance, and improves maintenance efficiency.

Store the executable program of the second FPGA module transmitted by Ethernet in the first DDR module;

The first FPGA module loads the executable program into the second FPGA module.

Description of the drawings

The present invention will be further described below with reference to the drawings and embodiments.

Figure 1 is a schematic structural diagram of a phased array beam control device according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a first FPGA module according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a second FPGA module according to an embodiment of the present invention;

4 is a flowchart of a control method applied to the aforementioned phased array beam control device according to an embodiment of the present invention;

Fig. 5 is a firmware upgrade flowchart of an embodiment of the present invention.

Detailed ways

This section will describe the specific embodiments of the present invention in detail. The preferred embodiments of the present invention are shown in the drawings. The function of the drawings is to supplement the description of the text part of the manual with graphics, so that people can intuitively and vividly understand the text. Each technical feature and overall technical solution of the invention cannot be understood as a limitation on the protection scope of the present invention.

In the description of the present invention, it should be understood that the orientation description involved, for example, the orientation or positional relationship indicated by up, down, front, back, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and only In order to facilitate the description of the present invention and simplify the description, it does not indicate or imply that the pointed device or element must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

In the description of the present invention, several meanings are one or more, multiple meanings are two or more, greater than, less than, exceeding, etc. are understood to not include the number, and above, below, and within are understood to include the number. If it is described that the first and second are only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly specifying the number of the indicated technical features or implicitly specifying the order of the indicated technical features relationship.

In the description of the present invention, unless otherwise clearly defined, terms such as setting, installation, and connection should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meaning of the above terms in the present invention in combination with the specific content of the technical solution.

1, a phased array beam control device is provided, including:

The first FPGA module 10 is used to process the phase data of the beam;

The second FPGA module 20 is interactively connected with the first FPGA module 10, and is configured to output corresponding instructions to multiple radio frequency transceiver components according to the phase data processed by the first FPGA module 10;

The clock and synchronization signal module 30. The output ports of the clock and synchronization signal module 30 are respectively connected to the input ports of the first FPGA module 10 and the second FPGA module 20, and are used to generate clock signals and synchronize them to the first FPGA module 10 and the second FPGA module. FPGA module 20;

The first DDR module 60 is interactively connected with the first FPGA module 10, and is used to store process data generated by the first FPGA module 10;

The FLASH module 50 is interactively connected with the first FPGA module 10 and is used to store configuration information required for loading;

The power supply module 40, the power output port of the power supply module 40 is respectively connected to the power input port of the first FPGA module 10 and the second FPGA module 20, and is used for power supply of the first FPGA module 10 and the second FPGA module 20.

The first FPGA module 10 is used to process the phase data of the beam in real time, and the second FPGA module 20 is used to output corresponding instructions to multiple radio frequency transceiver components according to the data processed by the first FPGA module 10. The single phased array beam control device composed of 10 and the second FPGA module 20 can simultaneously realize the logical control of multiple radio frequency transceiver components, reducing the number of beam control devices, thereby reducing the system hardware cost.

Further, it also includes:

The PHY module 70 is respectively interactively connected with the first FPGA module 10 and the external network, and is used to implement data exchange between the first FPGA module 10 and the external network;

The first DDR module 60 is also used to buffer the control data received by the PHY module 70;

The FLASH module 50 is also used to store the upgrade data received by the PHY module 70. The PHY module 70 is provided on the device to receive data from the external network, and can receive control data or upgrade data transmitted from the external network, such as Ethernet, to realize remote control or remote upgrade of the control device, and improve the operation of the control device. And ease of maintenance.

Further, the first FPGA module 10 is also used to monitor the status of multiple radio frequency transceiver components. The first FPGA module 10 monitors the status of the radio frequency transceiver components by collecting data in real time, and can discover the faulty radio frequency transceiver components in time, so as to perform timely maintenance on the faulty radio frequency transceiver components.

2, the first FPGA module 10 includes:

Processor 11;

The clock module 13 is used to generate a clock signal for the processor 11 to use;

The first register module 14 is used to latch variable data generated by the processor 11;

The first high-speed serdes interface module 15 is used to implement communication between the first FPGA module 10 and the second FPGA module 20;

The reset module is used to reset the processor 11. Among them, the aforementioned first high-speed serdes interface module 15 is preferably a JESD204B module. The structure of the first FPGA module 10 is only used to implement calculation processing of data, which can effectively increase the speed of calculation, thereby increasing the beam scanning speed of the whole machine.

Further, the processor 11 is a Cortex-M3 processor 11, including:

The MAC module 111 is used to receive TCP protocol message information and process phase data according to the message information;

The second DDR module 113 is used to control the first DDR module 60 and store temporary data generated by the MAC module 111;

The timer module 114 is used to generate a timing interrupt signal;

The interrupt module 112 is used to uniformly manage the interrupt signals generated by the timer module 114 according to different priorities;

The SPI module 116 is used to communicate with an external FLASH chip;

ENVM module 117, used to store application data and upgrade data;

The IIC module 115 is used to monitor the status of multiple radio frequency transceiver components.

The MAC module 111, the second DDR module 113, the timer module 114, the interrupt module 112, the SPI module 116, the ENVM module 117, and the IIC module 115 are mutually connected. Among them, after the monitoring data is collected, the monitoring data of each radio frequency transmitting and receiving component is transmitted back to the control center in time via Ethernet, which is convenient for subsequent maintenance. In the embodiment of the present invention, the first FPGA module 10 serves as the main control module of the entire control device. It can be understood that, in addition to the above-mentioned functions, it can also be used for the complete functions of the control device. To realize network communication, amplitude and phase calculation, data dynamic buffering, configuration parameter storage, online upgrade, and program loading of the second FPGA module 20.

3, the second FPGA module 20 includes:

The second high-speed serdes interface module 22 is used to implement communication between the second FPGA module 20 and the first FPGA module 10;

The FIFO module 23 is configured to store the amplitude and phase data output from the second high-speed serdes interface module 22, and manage the data output from the second high-speed serdes interface module 22 according to the principle of first-in first-out;

The second register module 21 is used to store variable data;

The synchronization signal module 26 is used to output a synchronization signal;

The scheduler module 24 is used to sample the synchronization signal to form various control logics, read the amplitude and phase information stored in the FIFO module 23, and output the information to the corresponding control pins through the output module 25;

The output module 25 is used to allocate control signal pins. The architecture of the second FPGA module 20 is only used to implement the data processed by the first FPGA module 10 and output corresponding instructions to the radio frequency transceiver component, which can effectively improve the control efficiency of the control device on the radio frequency transceiver component. In the embodiment of the present invention, the above-mentioned second high-speed serdes interface module 22 is specifically a JESD204B module, which is a communication module between the first FPGA and the second FPGA, and realizes high-speed and reliable communication between the two FPGA modules. The JESD204B module Contains JESD204B-PHY unit, JESD204B transmitting unit, JESD204B receiving unit, the first FPGA module 10 sends the amplitude and phase data after the calculation is completed to the second FPGA module 20 through the JESD204B module, and finally the amplitude and phase data is transmitted through the second FPGA module 20 Set to the corresponding radio frequency transmitting and receiving components in the form of control signals to realize beam control.

Specifically, in the embodiment of the present invention, the above-mentioned architecture can realize the phase control of 8 radio frequency transceiver units by one beam control device, which effectively reduces the number of beam control devices. For example, when the phased array radar has 64 radio frequency transceiver units, the traditional distributed beam control device needs 64, and the dual FPGA architecture adopting the embodiment of the present invention only needs 8 to realize the 64 radio frequency transceiver units. Real-time control greatly reduces the number of beam control devices, thereby reducing system hardware costs.

Further, the first FPGA module 10 and the second FPGA module 20 are connected through a serdes serial interface. The serdes serial interface is a high-speed serial interface, and the first FPGA module 10 and the second FPGA module 20 are connected through the serdes serial interface to realize high-speed transmission of wave-controlled data. Specifically, the two FPGA modules are connected through a high-speed serdes bus, and the JESD204B protocol is used for reliable data transmission. The rate of a single serdes bus can reach 5 Gbps, realizing high-speed data transmission.

4, an embodiment of the present invention also provides a method for using the above-mentioned phased array beam steering device, including the following steps:

Step S10: the first FPGA module 10 processes the phase data of the beam;

Step S10: The second FPGA module 20 outputs corresponding instructions to multiple radio frequency transceiver components according to the phase data processed by the first FPGA module 10. The first FPGA module 10 is used to process the phase data of the beam in real time, and the second FPGA module 20 is used to output corresponding instructions to multiple radio frequency transceiver components according to the data processed by the first FPGA module 10. The single phased array beam control device composed of the FPGA module 10 and the second FPGA module 20 can simultaneously realize the logical control of multiple radio frequency transceiver components, reducing the number of beam control devices, thereby reducing the system hardware cost.

Referring to FIG. 5, further, it further includes the following steps:

Step S100: remotely transmit the firmware via Ethernet;

Step S200: the PHY module 70 receives the firmware transmitted by the Ethernet;

Step S300: Store the firmware in the FLASH module, and set the firmware update flag to 1;

Step S400: reset and restart the first FPGA module 10, and load an upgrade program;

Step S500: Read the firmware update flag bit of the FLASH module, and if the flag bit is 1, copy the new version firmware to the corresponding address bit in the first FPGA module 10 to overwrite the old firmware;

Step S600: Set the firmware update flag bit of the FLASH module to 0;

Step S700: Reset the first FPGA module 10.

The above firmware upgrade method can realize the remote upgrade of the phased array beam control device of the first aspect of the present invention, avoids the tedious operation of on-site upgrade and maintenance, and improves maintenance efficiency.

Further, it also includes the following steps:

Step S1000: the executable program of the second FPGA module transmitted by Ethernet is stored in the first DDR module 60;

Step S2000: the first FPGA module 10 loads the executable program into the second FPGA module 20.

Specifically, when it is necessary to remotely upgrade the program of the first FPGA module 10 online, the new version of the firmware is first sent from the control center to the FLASH module 50 in the beam control device through the gigabit network and stored in the FLASH module 50. Set the firmware update flag bit to 1, and then the first FPGA module 10 performs a reset and restart operation. During the restart process, a section of the upgrade program in the ENVM module 117 is loaded. After the upgrade program is loaded, the firmware update flag bit of the FLASH module 50 is read, if it is 1 It indicates that the firmware update is required. The upgrade program executes the copy task, and copies the new version firmware in the FLASH module 50 to the corresponding address bit of the application program in the ENVM module 117. After overwriting the old firmware, update the firmware in the FLASH module 50 The flag position is 0, and finally the first FPGA module 10 is reset to complete the entire online upgrade process. In the first FPGA module 10, the JTAG pins of the second FPGA module 20 are simulated with general-purpose input and output pins, and C language programming is performed in the Cortex-M3 of the first FPGA module 10 to realize the first FPGA module 10 to the second FPGA module 20 The executable program of the second FPGA module 20 is sent from the control center via the network to the DDR for storage, and then the JTAG pin simulated in the first FPGA module 10 is used to load the second FPGA module 20.

The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above-mentioned embodiments. Within the scope of knowledge possessed by those of ordinary skill in the technical field, various implementations can be made without departing from the purpose of the present invention. Kind of change.

Claims

A phased array beam control device, characterized in that it comprises:

The first FPGA module is used to process the phase data of the beam;

The second FPGA module is interactively connected to the first FPGA module, and is configured to output corresponding instructions to multiple radio frequency transceiver components according to the phase data processed by the first FPGA module;

A clock and synchronization signal module, the output ports of the clock and synchronization signal modules are respectively connected to the input ports of the first FPGA module and the second FPGA module, and are used to generate a clock signal and synchronize to the first FPGA module And the second FPGA module;

A first DDR module, interactively connected with the first FPGA module, and used to store process data generated by the first FPGA module;

The FLASH module is interactively connected with the first FPGA module and is used to store configuration information required for loading;

A power supply module, where the power output ports of the power supply module are respectively connected to the power input ports of the first FPGA module and the second FPGA module, and are used to supply power to the first FPGA module and the second FPGA module.
The phased array beam control device according to claim 1, further comprising:

The PHY module is interactively connected to the first FPGA module and the external network, and is used to implement data exchange between the first FPGA module and the external network;

The first DDR module is also used to buffer the control data received by the PHY module;

The FLASH module is also used to store the upgrade data received by the PHY module.
The phased array beam control device according to claim 1, characterized in that:

The first FPGA module is also used to monitor the status of multiple radio frequency transceiver components.
The phased array beam control device according to claim 1, wherein the first FPGA module comprises:

processor;

A clock module for generating a clock signal for use by the processor;

The first register module is used to latch variable data generated by the processor;

The first high-speed serdes interface module is used to implement communication between the first FPGA module and the second FPGA module;

The reset module is used to reset the processor.
The phased array beam control device according to claim 4, wherein the processor comprises:

The MAC module is used to receive TCP protocol message information and process phase data according to the message information;

The second DDR module is used to control the first DDR module and store temporary data generated by the MAC module;

Timer module, used to generate timing interrupt signal;

The interrupt module is used to uniformly manage the interrupt signals generated by the timer module according to different priorities;

SPI module, used to communicate with external FLASH chip;

ENVM module, used to store application data and upgrade data;

IIC module, used to monitor the status of multiple radio frequency transceiver components;

The MAC module, the second DDR module, the timer module, the interrupt module, the SPI module, the ENVM module and the IIC module are interactively connected.
The phased array beam control device according to claim 1, wherein the second FPGA module comprises:

The second high-speed serdes interface module is used to implement communication between the second FPGA module and the first FPGA module;

The FIFO module is used to store the amplitude and phase data output from the second high-speed serdes interface module, and manage the data output from the second high-speed serdes interface module according to the principle of first in, first out;

The second register module is used to store variable data;

Synchronization signal module, used to output synchronization signals;

The scheduler module is used to sample the synchronization signal to form various control logics, read the amplitude and phase information stored in the FIFO module, and output the information to the corresponding control pin through the output module;

Output module, used to allocate control signal pins.
The phased array beam control device according to claim 1, wherein the first FPGA module (10) and the second FPGA module are connected through a serdes serial interface.
A control method applied to the phased array beam control device according to any one of claims 1-7, characterized in that it comprises the following steps:

The first FPGA module processes the phase data of the beam;

The second FPGA module outputs corresponding instructions to multiple radio frequency transceiver components according to the phase data processed by the first FPGA module.
The control method according to claim 8, characterized in that it further comprises the following steps:

Remotely transfer firmware via Ethernet;

PHY module receives the firmware transmitted by Ethernet;

Store the firmware to the FLASH module, and set the firmware update flag to 1;

Reset and restart the first FPGA module, and load an upgrade program;

Read the firmware update flag bit of the FLASH module, and if the flag bit is 1, copy the new version firmware to the corresponding address bit in the first FPGA module to overwrite the old firmware;

Set the firmware update flag bit of the FLASH module to 0;

Reset the first FPGA module.
The control method according to claim 9, characterized in that it further comprises the following steps:

Store the executable program of the second FPGA module transmitted by Ethernet in the first DDR module;

The first FPGA module loads the executable program into the second FPGA module.