WO2021017180A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2021017180A1
WO2021017180A1 PCT/CN2019/111188 CN2019111188W WO2021017180A1 WO 2021017180 A1 WO2021017180 A1 WO 2021017180A1 CN 2019111188 W CN2019111188 W CN 2019111188W WO 2021017180 A1 WO2021017180 A1 WO 2021017180A1
Authority
WO
WIPO (PCT)
Prior art keywords
retaining wall
display area
hole structure
stress buffer
array substrate
Prior art date
Application number
PCT/CN2019/111188
Other languages
English (en)
French (fr)
Inventor
杨杰
张明
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/625,740 priority Critical patent/US11152438B2/en
Publication of WO2021017180A1 publication Critical patent/WO2021017180A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80517—Multilayers, e.g. transparent multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and a display panel.
  • OLEDs Organic light-emitting diodes
  • the organic light-emitting layer in commonly used OLED mostly uses IJP (ink jet printing, inkjet printing) is completed, the ink droplets have the advantages of low viscosity, good fluidity, and good flatness.
  • IJP ink jet printing, inkjet printing
  • the ink droplets have the advantages of low viscosity, good fluidity, and good flatness.
  • some retaining walls must be set to limit the printing range, because the retaining walls mainly limit the ink
  • the purpose of the drop printing range is generally a closed graphic surrounding the product.
  • the film interface at the barrier wall is numerous and there are undulations, the stress is easy to concentrate at the location of the barrier wall, resulting in shedding and separation between the film layers, which mainly occurs in the ITO/Ag/ITO in the anode layer between.
  • the present invention provides an array substrate and a display panel. By providing openings in the anode layer at the barrier wall, the stress on the anode layer at the barrier wall is reduced, and the film layer at the barrier wall is prevented from falling off, thereby affecting the display Technical issues.
  • the present invention provides an array substrate, including: a display area and a non-display area surrounding the display area;
  • the array substrate includes:
  • the anode layer is arranged on the substrate;
  • the first retaining wall is arranged on the anode layer and surrounds the display area
  • the anode layer is provided with a first stress buffer area corresponding to the first retaining wall, and a first pore structure penetrating the anode layer is provided in the first stress buffer area.
  • the first stress buffer area is arranged around the display area, and at least one end of the first retaining wall close to the display area is located in the first stress buffer area.
  • the distance between the boundary of the first stress buffer zone on the side close to the display area and the first retaining wall is greater than 10 microns.
  • the array substrate further includes a second retaining wall disposed on the anode layer, and a second stress buffer corresponding to the second retaining wall, and the second A second hole structure is arranged in the stress buffer zone;
  • the second retaining wall is arranged around the display area and is located on a side of the first retaining wall close to the display area.
  • the second stress buffer zone is arranged around the display area, and the second retaining wall is located in the second stress buffer zone.
  • the distance between the two boundaries of the second stress buffer zone and the second retaining wall is greater than 10 microns.
  • both the first hole structure and the second hole structure include: a plurality of through holes that surround the display area and are spaced apart from each other.
  • the through hole includes a plurality of continuous or discontinuous sub-through holes in a direction away from the display area.
  • the structures of the through holes of the first hole structure and the through holes of the second hole structure are the same or different.
  • a display panel comprising an array substrate, and an organic light emitting layer and a thin film encapsulation layer sequentially arranged on the array substrate;
  • the array substrate includes a display area and a non-display area surrounding the display area;
  • the array substrate includes:
  • the anode layer is arranged on the substrate;
  • the first retaining wall is arranged on the anode layer and surrounds the display area
  • the anode layer is provided with a first stress buffer area corresponding to the first retaining wall, and a first pore structure penetrating the anode layer is provided in the first stress buffer area.
  • the first stress buffer area is arranged around the display area, and at least one end of the first retaining wall close to the display area is located in the first stress buffer area.
  • the distance between the boundary of the first stress buffer zone on the side close to the display area and the first retaining wall is greater than 10 microns.
  • the array substrate further includes a second retaining wall disposed on the anode layer, and a second stress buffer corresponding to the second retaining wall, and the second A second hole structure is arranged in the stress buffer zone;
  • the second retaining wall is arranged around the display area and is located on a side of the first retaining wall close to the display area.
  • the second stress buffer zone is arranged around the display area, and the second retaining wall is located in the second stress buffer zone.
  • the distance between the two boundaries of the second stress buffer zone and the second retaining wall is greater than 10 microns.
  • both the first hole structure and the second hole structure include: a plurality of through holes that surround the display area and are spaced apart from each other.
  • the through hole includes a plurality of continuous or discontinuous sub-through holes in a direction away from the display area.
  • the structures of the through holes of the first hole structure and the through holes of the second hole structure are the same or different.
  • the height of the first retaining wall is greater than the height of the second retaining wall.
  • the first hole structure covered by the first retaining wall is filled with the same material as the first retaining wall;
  • the second hole structure covered by the second retaining wall is filled with the same material as the second retaining wall.
  • the present invention reduces the stress on the anode layer at the retaining wall by arranging the pore structure in the anode layer at the retaining wall, thereby preventing the excessive stress from causing the metal layer in the anode layer and the conductive film Shedding and separation.
  • FIG. 1A is a schematic structural diagram of an array substrate provided by an embodiment of the present invention.
  • FIG. 1B is a schematic plan view of an array substrate provided by an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of another array substrate structure provided by an embodiment of the present invention.
  • FIG. 3 is a schematic plan view of a hole structure provided by an embodiment of the present invention.
  • Fig. 4 is a schematic plan view of another hole structure provided by an embodiment of the present invention.
  • Fig. 5 is a schematic plan view of another hole structure provided by an embodiment of the present invention.
  • Fig. 6 is a schematic plan view of another hole structure provided by an embodiment of the present invention.
  • FIG. 7 is a schematic plan view of another hole structure provided by an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of another display panel provided by an embodiment of the present invention.
  • the present invention is directed to the existing array substrate and display panel. Due to the large undulations at the retaining wall, the anode layer suffers a greater stress at the retaining wall, so that the anode layer can be peeled off. Solve the defect.
  • the present invention provides an array substrate, including: a display area and a non-display area surrounding the display area;
  • the array substrate includes:
  • the anode layer is arranged on the substrate;
  • the first retaining wall is arranged on the anode layer and surrounds the display area
  • the anode layer is provided with a first stress buffer area corresponding to the first retaining wall, and a first pore structure penetrating the anode layer is provided in the first stress buffer area.
  • FIGS. 1A and 1B it is an array substrate provided by an embodiment of the present invention, wherein the array substrate includes a substrate 105, an anode layer 104 disposed on the substrate 105, and an anode layer 104 disposed on the substrate 105.
  • the first retaining wall 101 on the anode layer 104, and the first retaining wall 101 is arranged around the display area 108 of the substrate 105.
  • the anode layer 104 includes conductive films 1041, 1043 and metal layers 1042 alternately disposed, and the first conductive film 1041 and the second conductive film 1043 are respectively disposed on both sides of the metal layer 1042.
  • a first stress buffer 106 corresponding to the first retaining wall 101 is provided on the anode layer 104, and a first hole penetrating the anode layer 104 is provided in the first stress buffer 106 Structure 1031.
  • the first hole structure 1031 penetrates the first conductive film 1041, the metal layer 1042, and the second conductive film 1043.
  • the array substrate has many membrane interfaces and undulations at the position where the retaining wall is provided, so that the stress is easy to concentrate at the position of the retaining wall, causing the film to fall off, and mainly occurs in the anode layer.
  • this embodiment provides a buffer area for stress by providing a hole structure in the anode layer at the retaining wall, reducing the stress on the anode layer at the retaining wall, thereby preventing the anode layer from being The conductive film and the metal layer fall off and separate.
  • the material of the first conductive film 1041 and the second conductive film 1043 includes indium tin oxide (ITO), and the material of the metal layer 1042 includes silver.
  • ITO indium tin oxide
  • the first stress buffer zone 106 is arranged around the display area 108, and at least one end of the first retaining wall 101 close to the display area 108 is located at the first stress Buffer 106.
  • the side of the first retaining wall 101 close to the display area 108 is located in the first stress buffer zone 106, that is, part of the first retaining wall 101 is located in the In the first stress buffer zone 106; in the second case, all the first retaining walls 101 are located in the first stress buffer zone 106.
  • the orthographic projection area of the first retaining wall 101 on the metal layer 104 is equal to or smaller than the area of the first stress buffer zone 106.
  • the distance between the boundary of the first stress buffer zone 106 on the side close to the display area 108 and the first retaining wall 101 is greater than 10 microns.
  • first hole structure 1031 is arranged in the first stress buffer zone 106, there are three situations where the first hole structure 1031 is arranged.
  • the first hole structure 1031 is shown in FIG. 1A, a part of the first hole structure 1031 is covered by the first retaining wall 101, and a part of the first hole structure 1031 is provided in the place.
  • the first retaining wall 101 is outside the orthographic projection area on the metal layer 104.
  • part of the first hole structure 1031 is disposed at one end of the first retaining wall 101 close to the display area 108 .
  • the first hole structure 1031 is only arranged outside the orthographic projection area of the first retaining wall 101 on the metal layer 104.
  • the array substrate further includes a second retaining wall 102 disposed on the anode layer 104, and a second stress buffer 107 corresponding to the second retaining wall 102, and A second hole structure 1032 is provided in the second stress buffer zone 107.
  • the second retaining wall 102 is arranged around the display area 108 and is located on the side of the first retaining wall 101 close to the display area 108.
  • the second stress buffer zone 107 is arranged around the display area 108, and the second retaining wall 102 is located in the second stress buffer zone 107.
  • the orthographic projection area of the second retaining wall 102 on the metal layer 104 is smaller than the area of the second stress buffer zone 107.
  • the distance between the two boundaries of the second stress buffer zone 107 and the second retaining wall 102 is greater than 10 microns.
  • the second hole structure 1032 is as shown in FIG. 1A, part of the second hole structure 1032 is covered by the second retaining wall 102, and some of the second hole structure 1032 is provided in the place. The two ends of the second retaining wall 102 are described.
  • the second hole structure 1032 is only provided at both ends of the second retaining wall 102.
  • the height of the first retaining wall 101 is greater than the height of the second retaining wall 102, which can not only enhance the restriction of the retaining wall on the film layer prepared in its enclosure, but also enhance the intrusion of water vapor The preventive effect.
  • the first hole structure 1031 covered by the first retaining wall 101 is filled with the same material as the first retaining wall 101
  • the second hole structure 1032 covered by the second retaining wall 102 The inside is filled with the same material as the second retaining wall 102.
  • the material of the first retaining wall 101 and the second retaining wall 102 includes organic materials such as polyimide.
  • the adhesion between the retaining wall and the anode layer can be increased, and the adhesion strength between the film layers in the array substrate can be improved.
  • both the first hole structure 1031 and the second hole structure 1032 include a plurality of through holes that surround the display area 108 and are spaced apart from each other.
  • the through hole includes a plurality of continuous or discontinuous sub through holes in a direction away from the display area 108.
  • the through hole may be a continuous through hole in a direction away from the display area 108 or a discontinuous through hole in a direction away from the display area 108.
  • the first hole structure 1031 is located in the first stress buffer zone 106, and the second hole structure 1032 is located in the second stress buffer zone 107, all surrounding the display area 108, and the first The one hole structure 1031 and the second hole structure 1032 are both through holes spaced apart from each other in the direction surrounding the display area 108.
  • the through holes of the first hole structure 1031 and the second hole structure 1032 have the same or different structures, that is, the designs of the first hole structure 1031 and the second hole structure 1032 can be the same or different. It can be different.
  • the widths of the first hole structure 1031 and the second hole structure 1032 are both 1 to 1000 micrometers, and the first hole structure 1031 and the second hole structure 1032 are located around the display area 108 The spacing in the direction is greater than 10 microns.
  • the shape of the first hole structure 1031 and the second hole structure 1032 includes a rectangle or a circle. For details, see the following embodiments.
  • the first hole structure 1031 is a continuous through hole in the first stress buffer zone 106 in a direction away from the display area 108, and the second hole structure 1032 is under the second stress In the buffer zone 107, there are discontinuous through holes in the direction away from the display area 108.
  • the array substrate includes a substrate 205, an anode layer 204 disposed on the substrate 205, and a first retaining wall 201 and a second retaining wall 202 disposed on the anode layer 204, and The first retaining wall 201 and the second retaining wall 202 are arranged around the display area 208 of the substrate 205, and the second retaining wall 202 is located on the side of the first retaining wall 201 close to the display area 208 .
  • the anode layer 204 includes conductive films 2041, 2043 and metal layers 2042 alternately disposed, and the first conductive film 2041 and the second conductive film 2043 are respectively disposed on both sides of the metal layer 2042.
  • the anode layer 204 is provided with a first stress buffer 206 corresponding to the first retaining wall 201, and a first hole penetrating the anode layer 204 is provided in the first stress buffer 206 Structure 2031.
  • the anode layer 204 is also provided with a second stress buffer 207 corresponding to the second retaining wall 202, and a second pore structure penetrating the anode layer 204 is provided in the second stress buffer 207 2032.
  • first hole structure 2031 and the second hole structure 2032 penetrate the first conductive film 2041, the metal layer 2042, and the second conductive film 2043.
  • the material of the first conductive film 2041 and the second conductive film 2043 includes indium tin oxide (ITO), and the material of the metal layer 2042 includes silver.
  • ITO indium tin oxide
  • the first hole structure 2031 covered by the first retaining wall 201 is filled with the same material as the first retaining wall 201, and the second hole covered by the second retaining wall 202
  • the structure 2032 is filled with the same material as the second retaining wall 202.
  • the material of the first retaining wall 201 and the second retaining wall 202 includes organic materials such as polyimide.
  • the adhesion between the retaining wall and the anode layer can be increased, and the adhesion strength between the film layers in the array substrate can be improved.
  • the first hole structure 2031 in the first stress buffer zone 206 and the second hole structure 2032 in the second stress buffer zone 207 are both through holes that surround the display area 208 and are spaced apart from each other.
  • the first hole structure 2031 in the first stress buffer zone 206 and the second hole structure 2032 in the second stress buffer zone 207 are continuous through holes in a direction away from the display area 208.
  • the anode layer at the retaining wall is provided with a hole structure penetrating the anode layer to provide a stress buffer area, which reduces the stress on the anode layer at the retaining wall and prevents electrical conduction in the anode layer. Falling off between the film layer and the metal layer.
  • FIG. 3 it is a schematic plan view of the hole structure provided by this embodiment, and FIG. 3 shows only a part of the array substrate structure for illustration.
  • the anode layer 304 disposed on the substrate, the first retaining wall 301 disposed on the anode layer 304, and the first stress corresponding to the first retaining wall 301
  • a buffer zone 306 a second retaining wall 302 disposed on the anode layer 304, a second stress buffer zone 307 corresponding to the second retaining wall 302, and a second stress buffer zone 307 disposed in the first stress buffer zone 306 at the same time
  • the first hole structure 3031 and the second hole structure 3032 are both arranged around the display area 308 and are arranged at intervals in the direction surrounding the display area 308.
  • the first hole structure 3031 and the second hole structure 3032 are both arranged in parallel along a direction away from the display area 308, and the first hole structure 3031 is located far away from the first stress buffer zone 306.
  • the direction of the display area 308 is a continuous through hole
  • the second hole structure 3032 is a discontinuous through hole in the direction away from the display area 308 in the second stress buffer area 307.
  • the first hole structure 3031 is a rectangular through hole, and part of the first hole structure 3031 is located on the first retaining wall 301 close to the display area One end of 308 and the other part of the first hole structure 3031 are covered by the first retaining wall 301.
  • the second hole structure 3032 is a rectangular through hole, and part of the second hole structure 3032 is located at both ends of the second retaining wall 302, and another part of the second hole
  • the structure 3032 is covered by the second retaining wall 302, wherein the part of the second hole structure 3032 covered by the second retaining wall 302 is a discontinuous through hole in a direction away from the display area 308 .
  • a hole structure is provided to reduce the stress of the anode layer at the retaining wall, so as to prevent the conductive film in the anode layer from falling off between the metal layer.
  • FIG. 4 it is a schematic plan view of the hole structure provided by this embodiment, and FIG. 4 shows only a part of the array substrate structure for illustration.
  • the anode layer 404 disposed on the substrate, the first retaining wall 401 disposed on the anode layer 404, and the first stress corresponding to the first retaining wall 401 A buffer zone 406, a second retaining wall 402 arranged on the anode layer 404, a second stress buffer zone 407 corresponding to the second retaining wall 402, and a second stress buffer zone 407 arranged in the first stress buffer zone 406
  • the first hole structure 4031 and the second hole structure 4032 are both arranged around the display area 408, and are arranged at intervals in the direction surrounding the display area 408.
  • the first hole structure 4031 and the second hole structure 4032 are arranged at a certain angle with the direction away from the display area 408.
  • the first hole structure 4031 is in the first stress buffer zone 406.
  • the inner edge is a continuous through hole in the direction away from the display area 408, and the second hole structure 4032 is a discontinuous through hole in the second stress buffer area 407 in the direction away from the display area 408.
  • the first hole structure 4031 is a rectangular through hole, and part of the first hole structure 4031 is located in the first retaining wall 401 close to the display area One end of 408 and the other part of the first hole structure 4031 are covered by the first retaining wall 401.
  • the second hole structure 4032 is a rectangular through hole, and part of the second hole structure 4032 is located at both ends of the second retaining wall 402, and another part of the second hole
  • the structure 4032 is covered by the second retaining wall 402, wherein the part of the second hole structure 4032 covered by the second retaining wall 402 is a discontinuous through hole in a direction away from the display area 408 .
  • a hole structure is provided to reduce the stress of the anode layer at the retaining wall, so as to prevent the conductive film in the anode layer from falling off between the metal layer.
  • FIG. 5 it is a schematic plan view of the hole structure provided by this embodiment, and the structure shown in FIG. 5 is only part of the array substrate structure for illustration.
  • the anode layer 504 provided on the substrate including the array substrate as described above, the anode layer 504 provided on the substrate, the first retaining wall 501 provided on the anode layer 504, the first stress corresponding to the first retaining wall 501 A buffer zone 506, a second retaining wall 502 arranged on the anode layer 504, a second stress buffer zone 507 corresponding to the second retaining wall 502, and simultaneously arranged in the first stress buffer zone 506
  • the first hole structure 5031 and the second hole structure 5032 are both arranged around the display area 508 and are arranged at intervals in the direction surrounding the display area 508.
  • the first hole structure 5031 and the second hole structure 5032 are arranged in parallel along a direction away from the display area 508, and the first hole structure 5031 is located away from the inner edge of the first stress buffer zone 506.
  • the direction of the display area 508 is a continuous through hole
  • the second hole structure 5032 is a continuous through hole in the direction away from the display area 508 in the second stress buffer zone 507.
  • the first hole structure 5031 is a rectangular through hole, and part of the first hole structure 5031 is located on the first retaining wall 501 close to the display area One end of 508 and the other part of the first hole structure 5031 are covered by the first retaining wall 501.
  • the second hole structure 5032 is a rectangular through hole, and part of the second hole structure 5032 is located at both ends of the second retaining wall 502, and another part of the second hole
  • the structure 5032 is covered by the second retaining wall 502, wherein a part of the second hole structure 5032 covered by the second retaining wall 502 is a continuous through hole in a direction away from the display area 508.
  • a hole structure is provided to reduce the stress of the anode layer at the retaining wall, so as to prevent the conductive film in the anode layer from falling off between the metal layer.
  • FIG. 6 it is a schematic plan view of the hole structure provided by this embodiment, and FIG. 6 shows only part of the array substrate structure for illustration.
  • the first hole structure 6031 and the second hole structure 6032 are both arranged around the display area 608 and are arranged at intervals in the direction surrounding the display area 608.
  • the first hole structure 6031 and the second hole structure 6032 are arranged in parallel along a direction away from the display area 608, and the first hole structure 6031 is located away from the inner edge of the first stress buffer zone 606.
  • the direction of the display area 608 is a discontinuous through hole
  • the second hole structure 6032 is a discontinuous through hole in the direction away from the display area 608 in the second stress buffer area 607.
  • the first hole structure 6031 in the first stress buffer zone 606, is a rectangular through hole, and part of the first hole structure 6031 is located on the first retaining wall 601 close to the display area
  • One end of 608 the other part of the first hole structure 6031 is covered by the first retaining wall 601, and the part of the first hole structure 6031 covered by the first retaining wall 601 is along the distance away from the display
  • the direction of the area 608 is a discontinuous through hole.
  • the second hole structure 6032 is a rectangular through hole, and part of the second hole structure 6032 is located at both ends of the second retaining wall 602, and another part of the second hole
  • the structure 6032 is covered by the second retaining wall 602, wherein a part of the second hole structure 6032 covered by the second retaining wall 602 is a discontinuous through hole in a direction away from the display area 608 .
  • a hole structure is provided to reduce the stress of the anode layer at the retaining wall, so as to prevent the conductive film in the anode layer from falling off between the metal layer.
  • FIG. 7 it is a schematic plan view of the hole structure provided in this embodiment, and the structure shown in FIG. 7 is only part of the array substrate structure for illustration.
  • the array substrate as described above, the anode layer 704 provided on the substrate, the first retaining wall 701 provided on the anode layer 704, and the first stress corresponding to the first retaining wall 701
  • the first hole structure 7031 and the second hole structure 7032 are both arranged around the display area 708, and are arranged at intervals in the direction surrounding the display area 708.
  • the first hole structure 7031 and the second hole structure 7032 are arranged in parallel along a direction away from the display area 708, and the first hole structure 7031 is located away from the inner edge of the first stress buffer zone 706.
  • the direction of the display area 708 is a discontinuous through hole
  • the second hole structure 7032 is a discontinuous through hole in the direction away from the display area 708 in the second stress buffer zone 707.
  • the first hole structure 7031 is a circular through hole, and part of the first hole structure 7031 is located on the first retaining wall 701 close to the display At one end of the area 708, the other part of the first hole structure 7031 is covered by the first retaining wall 701, and the part of the second hole structure 7032 covered by the first retaining wall 701 is along the distance away from the The direction of the display area 708 is a discontinuous through hole.
  • the second hole structure 7032 is a circular through hole, and part of the second hole structure 7032 is located at both ends of the second retaining wall 702, and another part of the second hole structure 7032
  • the hole structure 7032 is covered by the second retaining wall 702, wherein the part of the second hole structure 7032 covered by the second retaining wall 702 is discontinuous in the direction away from the display area 708 hole.
  • a hole structure is provided to reduce the stress of the anode layer at the retaining wall, so as to prevent the conductive film in the anode layer from falling off between the metal layer.
  • the shape of the hole structure is not limited to rectangle and circle, nor is it limited to whether the shape of the hole structure in the first stress buffer zone and the second stress buffer zone are the same.
  • An embodiment of the present invention also provides a display panel.
  • the display panel includes the above-mentioned array substrate, an organic light-emitting layer 806 and an encapsulation film disposed on the array substrate.
  • the array substrate includes a substrate 805, an anode layer 804 disposed on the substrate 805, a first barrier wall 801 and a second barrier wall 802 disposed on the anode layer 804, and the anode layer 804 The first hole structure 8031 and the second hole structure 8032.
  • the organic light-emitting layer 806 is disposed on the anode layer 804, and the organic light-emitting layer 806 covers the display area and stops at the second retaining wall 802.
  • the organic light-emitting layer 806 is provided with the thin-film encapsulation layer, and the thin-film encapsulation layer includes a first inorganic layer 807, an organic layer 808, and a second inorganic layer 809 that are stacked, wherein the first inorganic layer 807 And the second inorganic layer 809 covers the display area, the first retaining wall 801 and the second retaining wall 802, and the organic layer 808 covers the display area and the second retaining wall 802 and stops at all Mentioned first retaining wall 801.
  • the display panel includes the above-mentioned array substrate, an organic light-emitting layer 906 and an encapsulation film disposed on the array substrate.
  • the array substrate includes a substrate 905, an anode layer 904 disposed on the substrate 905, a first retaining wall 901 and a second retaining wall 902 disposed on the anode layer 904, and the anode layer 904 passing through The first hole structure 9031 and the second hole structure 9032.
  • the organic light emitting layer 906 is provided on the anode layer 904, and the organic light emitting layer 906 covers the display area and stops at the second retaining wall 902.
  • the thin-film encapsulation layer is disposed on the organic light-emitting layer 906, and the thin-film encapsulation layer includes a first inorganic layer 907, an organic layer 908, and a second inorganic layer 909 that are stacked, wherein the first inorganic layer 907 And the second inorganic layer 8909 covers the display area, the first retaining wall 901, and the second retaining wall 902, and the organic layer 908 only covers the display area and ends at the second retaining wall 802.
  • the display panel provided by the present invention provides a hole structure in the anode layer to buffer the stress of the anode layer at the retaining wall, so as to reduce the risk of film peeling of the anode layer.

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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Abstract

一种阵列基板及显示面板，阵列基板包括基板以及设置于基板上的阳极层（104、204、304、404、504、604、704、804、904），且阳极层（104、204、304、404、504、604、704、804、904）上设置有环绕阵列基板的显示区的第一挡墙（101、201、301、401、501、601、701、801、901），以及与第一挡墙（101、201、301、401、501、601、701、801、901）相对应的第一应力缓冲区（106、206、306、406、506、606、706），且第一应力缓冲区（106、206、306、406、506、606、706）内设置有贯穿阳极层（104、204、304、404、504、604、704、804、904）的第一孔结构（1031、2031、3031、4031、5031、6031、7031、8031、9031）。

Description

阵列基板及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
 背景技术
有机发光二极管(OLED)具有自发光、高对比、广视角、低功耗、可弯折等优点受到了广泛的关注，柔性OLED也因为其可挠曲，轻薄的特点逐渐占领市场。
目前常用OLED中的有机发光层多采用IJP(ink jet printing，喷墨打印)完成，墨滴具有粘度低，流动性好，平坦性好的优点，同时也因为流动性好，必须设置一些限定其打印范围的挡墙，因为挡墙主要起到限定墨滴打印范围的目的，所以一般为围绕产品的封闭图形。
因为挡墙处的膜层界面多且存在起伏，使得应力易在挡墙的位置集中，导致膜层间的脱落、分离，且主要发生在阳极层中的ITO/Ag/ITO之间。
 技术问题
在显示面板中，因为挡墙处的膜层界面多且存在起伏，使得应力易在挡墙的位置集中，导致膜层间的脱落、分离，且主要发生在阳极层中的ITO/Ag/ITO之间。
 技术解决方案
本发明提供一种阵列基板及显示面板，通过在挡墙处的阳极层中设置开孔，从而减小阳极层在挡墙处所受的应力，防止挡墙处的膜层脱落，进而影响显示的技术问题。
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种阵列基板，其包括：显示区和围绕所述显示区的非显示区；
所述阵列基板包括：
基板；
阳极层，设置于所述基板上；
第一挡墙，设置在所述阳极层上且环绕所述显示区设置；
其中，所述阳极层上设有与所述第一挡墙相对应的第一应力缓冲区，且所述第一应力缓冲区内设置有贯穿所述阳极层的第一孔结构。
根据本发明的一种实施例，所述第一应力缓冲区围绕所述显示区设置，且至少所述第一挡墙靠近所述显示区的一端位于所述第一应力缓冲区内。
根据本发明的一种实施例，所述第一应力缓冲区靠近所述显示区一侧的边界距离所述第一挡墙的距离大于10微米。
根据本发明的一种实施例，所述阵列基板还包括设置于所述阳极层上的第二挡墙，以及与所述第二挡墙相对应的第二应力缓冲区，且所述第二应力缓冲区内设置有第二孔结构；
其中，所述第二挡墙围绕所述显示区设置，并位于所述第一挡墙靠近所述显示区的一侧。
根据本发明的一种实施例，所述第二应力缓冲区围绕所述显示区设置，且所述第二挡墙位于所述第二应力缓冲区内。
根据本发明的一种实施例，所述第二应力缓冲区的两边界距离所述第二挡墙的距离均大于10微米。
根据本发明的一种实施例，所述第一孔结构和所述第二孔结构均包括：多个环绕所述显示区且相互间隔的通孔。
根据本发明的一种实施例，所述通孔包括沿远离所述显示区方向上，多个连续或不连续的子通孔。
根据本发明的一种实施例，所述第一孔结构的通孔与所述第二孔结构的通孔的结构相同或不相同。
一种显示面板，所述显示面板包括阵列基板，以及依次设置于所述阵列基板上的有机发光层和薄膜封装层；
所述阵列基板包括显示区和围绕所述显示区的非显示区；
所述阵列基板包括：
基板；
阳极层，设置于所述基板上；
第一挡墙，设置在所述阳极层上且环绕所述显示区设置；
其中，所述阳极层上设有与所述第一挡墙相对应的第一应力缓冲区，且所述第一应力缓冲区内设置有贯穿所述阳极层的第一孔结构。
根据本发明的一种实施例，所述第一应力缓冲区环绕所述显示区设置，且至少所述第一挡墙靠近所述显示区的一端位于所述第一应力缓冲区内。
根据本发明的一种实施例，所述第一应力缓冲区靠近所述显示区一侧的边界距离所述第一挡墙的距离大于10微米。
根据本发明的一种实施例，所述阵列基板还包括设置于所述阳极层上的第二挡墙，以及与所述第二挡墙相对应的第二应力缓冲区，且所述第二应力缓冲区内设置有第二孔结构；
其中，所述第二挡墙环绕所述显示区设置，并位于所述第一挡墙靠近所述显示区的一侧。
根据本发明的一种实施例，所述第二应力缓冲区环绕所述显示区设置，且所述第二挡墙位于所述第二应力缓冲区内。
根据本发明的一种实施例，所述第二应力缓冲区的两边界距离所述第二挡墙的距离均大于10微米。
根据本发明的一种实施例，所述第一孔结构和所述第二孔结构均包括：多个环绕所述显示区且相互间隔的通孔。
根据本发明的一种实施例，所述通孔包括沿远离所述显示区方向上，多个连续或不连续的子通孔。
根据本发明的一种实施例，所述第一孔结构的通孔与所述第二孔结构的通孔的结构相同或不相同。
根据本发明的一种实施例，所述第一挡墙的高度大于所述第二挡墙的高度。
根据本发明的一种实施例，所述第一挡墙所覆盖的所述第一孔结构内，填充有与所述第一挡墙相同的材料；
所述第二挡墙所覆盖的所述第二孔结构内，填充有与所述第二挡墙相同的材料。
 有益效果
本发明通过在挡墙处的阳极层中设置孔结构，减小了阳极层在挡墙处所受的应力，从而防止了因应力过大而导致阳极层中的金属层与导电薄膜之间的脱落与分离。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A为本发明实施例提供的一种阵列基板结构示意图。
图1B为本发明实施例提供的阵列基板平面示意图。
图2为本发明实施例提供的另一种阵列基板结构示意图。
图3为本发明实施例提供的一种孔结构平面示意图。
图4为本发明实施例提供的另一种孔结构平面示意图。
图5为本发明实施例提供的另一种孔结构平面示意图。
图6为本发明实施例提供的另一种孔结构平面示意图。
图7为本发明实施例提供的另一种孔结构平面示意图。
图8为本发明实施例提供的一种显示面板结构示意图。
图9为本发明实施例提供的另一种显示面板结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的阵列基板及显示面板，因挡墙处具有较大的起伏，导致阳极层在挡墙处所受的应力较大，以使阳极层发生膜层剥离现象，本实施例能够解决该缺陷。
本发明提供一种阵列基板，其包括：显示区和围绕所述显示区的非显示区；
所述阵列基板包括：
基板；
阳极层，设置于所述基板上；
第一挡墙，设置在所述阳极层上且环绕所述显示区设置；
其中，所述阳极层上设有与所述第一挡墙相对应的第一应力缓冲区，且所述第一应力缓冲区内设置有贯穿所述阳极层的第一孔结构。
具体地，如图1A、1B所示，为本发明一种实施例所提供的阵列基板，其中，所述阵列基板包括基板105，设置于所述基板105上的阳极层104，以及设置于所述阳极层104上的第一挡墙101，且所述第一挡墙101环绕所述基板105的显示区108设置。
其中，所述阳极层104包括交替设置导电薄膜1041、1043以及金属层1042，且第一导电薄膜1041以及第二导电薄膜1043分别设置于所述金属层1042的两侧。
另外，所述阳极层104上设置有与所述第一挡墙101相对应的第一应力缓冲区106，且所述第一应力缓冲区106内设置有贯穿所述阳极层104的第一孔结构1031。
即所述第一孔结构1031贯穿所述第一导电薄膜1041、所述金属层1042以及所述第二导电薄膜1043。
在实施应用中，所述阵列基板在设置有挡墙的位置膜层界面多且存在起伏，使得应力易在挡墙的位置集中，使得膜层之间发生脱落，且主要发生在阳极层中的导电薄膜与金属层之间，本实施例通过在挡墙处的阳极层中设置孔结构，给应力提供缓冲区域，减小了阳极层在挡墙处所受的应力，从而防止了阳极层中的导电薄膜与金属层之间脱落与分离。
且所述第一导电薄膜1041以及所述第二导电薄膜1043的材质包括氧化铟锡（ITO），所述金属层1042的材质包括银。
进一步地，如图1A、1B所示，所述第一应力缓冲区106环绕所述显示区108设置，且至少所述第一挡墙101靠近所述显示区108的一端位于所述第一应力缓冲区106内。
则有两种情况，第一种情况，所述第一挡墙101靠近所述显示区108的一侧位于所述第一应力缓冲区106内，即部分所述第一挡墙101位于所述第一应力缓冲区106内；第二种情况，全部所述第一挡墙101位于所述第一应力缓冲区106内。
若为第二种情况，则所述第一挡墙101在所述金属层104上的正投影面积等于或小于所述第一应力缓冲区106的面积。
且所述第一应力缓冲区106靠近所述显示区108一侧的边界距离所述第一挡墙101的距离大于10微米。
需要注意的是，所述第一应力缓冲区106内设置有所述第一孔结构1031，则所述第一孔结构1031设置的位置有三种情况。
第一种情况，所述第一孔结构1031如图1A所示，部分所述第一孔结构1031被所述第一挡墙101所覆盖，还有部分所述第一孔结构1031设置于所述第一挡墙101在所述金属层104上的正投影区域之外，本实施例中，部分所述第一孔结构1031设置于所述第一挡墙101靠近所述显示区108的一端。
第二情况，所述第一孔结构1031仅设置于所述第一挡墙101在所述金属层104上的正投影区域之外。
第三种情况，全部所述第一孔结构1031被所述第一挡墙101所覆盖。
其中，第二、第三种情况图中并未显示，后续实施例仅以第一种情况作详述。
另外，在本实施例中，所述阵列基板还包括设置于所述阳极层104上的第二挡墙102，以及与所述第二挡墙102相对应的第二应力缓冲区107，且所述第二应力缓冲区107内设置有第二孔结构1032。
其中，所述第二挡墙102环绕所述显示区108设置，并位于所述第一挡墙101靠近所述显示区108的一侧。
且所述第二应力缓冲区107环绕所述显示区108设置，所述第二挡墙102位于所述第二应力缓冲区107内。
所述第二挡墙102在所述金属层104上的正投影面积小于所述第二应力缓冲区107的面积。
则所述第二应力缓冲区107的两边界距离所述第二挡墙102的距离均大于10微米。
需要注意的是，所述第二应力缓冲区107内设置有所述第二孔结构1032，则所述第二孔结构1032设置的位置有三种情况。
第一种情况，所述第二孔结构1032如图1A所示，部分所述第二孔结构1032被所述第二挡墙102所覆盖，还有部分所述第二孔结构1032设置于所述第二挡墙102的两端。
第二情况，所述第二孔结构1032仅设置于所述第二挡墙102的两端。
第三种情况，全部所述第二孔结构1032被所述第二挡墙102所覆盖。
其中，第二、第三种情况图中并未显示，后续实施例仅以第一种情况作详述。
在本实施例中，所述第一挡墙101的高度大于所述第二挡墙102的高度，既可以加强挡墙对制备于其包围内的膜层的限制作用，也可以加强对水汽侵入的防范作用。
同时，所述第一挡墙101所覆盖所述第一孔结构1031内填充有与所述第一挡墙101相同的材料，所述第二挡墙102所覆盖的所述第二孔结构1032内填充有与所述第二挡墙102相同的材料。
且所述第一挡墙101以及所述第二挡墙102的材质包括聚酰亚胺等有机材料。
本实施例通过在孔结构内填充与挡墙相同的材料，可以增加挡墙与阳极层之间的粘合力，提高阵列基板中膜层之间粘接强度。
在本实施例中，所述第一孔结构1031和所述第二孔结构1032均包括：多个环绕所述显示区108且相互间隔的通孔。
且所述通孔包括沿远离所述显示区108方向上，多个连续或不连续的子通孔。
即所述通孔可为沿远离所述显示区108方向上的连续通孔，也可为沿远离所述显示区108方向上的不连续通孔。
所述第一孔结构1031在所述第一应力缓冲区106内，所述第二孔结构1032在所述第二应力缓冲区107内，均为环绕所述显示区108设置，且所述第一孔结构1031以及所述第二孔结构1032均为沿环绕所述显示区108的方向上相互间隔的通孔。
且所述第一孔结构1031的通孔与所述第二孔结构1032的通孔的结构相同或不相同，即所述第一孔结构1031与所述第二孔结构1032的设计可以相同也可以不相同。
其中，所述第一孔结构1031以及所述第二孔结构1032的宽度均为1至1000微米，且所述第一孔结构1031以及所述第二孔结构1032在环绕所述显示区108的方向上的间距均大于10微米。
且所述第一孔结构1031以及所述第二孔结构1032的形状包括矩形或圆形，具体情况见后面的实施例。
如图1A所示，所述第一孔结构1031在所述第一应力缓冲区106内，沿远离所述显示区108的方向上为连续通孔，所述第二孔结构1032在第二应力缓冲区107内，沿远离所述显示区108的方向上为不连续通孔。
如图2所示，所述阵列基板包括基板205，设置于所述基板205上的阳极层204，以及设置于所述阳极层204上的第一挡墙201以及第二挡墙202，且所述第一挡墙201以及所述第二挡墙202环绕所述基板205的显示区208设置，且所述第二挡墙202位于所述第一挡墙201靠近所述显示区208的一侧。
其中，所述阳极层204包括交替设置导电薄膜2041、2043以及金属层2042，且第一导电薄膜2041以及第二导电薄膜2043分别设置于所述金属层2042的两侧。
另外，所述阳极层204上设置有与所述第一挡墙201相对应的第一应力缓冲区206，且所述第一应力缓冲区206内设置有贯穿所述阳极层204的第一孔结构2031。
所述阳极层204上还设置有与所述第二挡墙202相对应的第二应力缓冲区207，且所述第二应力缓冲区207内设置有贯穿所述阳极层204的第二孔结构2032。
即所述第一孔结构2031以及所述第二孔结构2032贯穿所述第一导电薄膜2041、所述金属层2042以及所述第二导电薄膜2043。
且所述第一导电薄膜2041以及所述第二导电薄膜2043的材质包括氧化铟锡（ITO），所述金属层2042的材质包括银。
同时，所述第一挡墙201所覆盖的所述第一孔结构2031内填充有与所述第一挡墙201相同材质的材料，所述第二挡墙202所覆盖的所述第二孔结构2032内填充有与所述第二挡墙202相同材质的材料。
且所述第一挡墙201以及所述第二挡墙202的材质包括聚酰亚胺等有机材料。
本实施例通过在孔结构内填充与挡墙相同的材料，可以增加挡墙与阳极层之间的粘合力，提高阵列基板中膜层之间的粘接强度。
所述第一孔结构2031在所述第一应力缓冲区206内以及所述第二孔结构2032在第二应力缓冲区207内，均为环绕所述显示区208并相互间隔的通孔。
所述第一孔结构2031在所述第一应力缓冲区206内以及所述第二孔结构2032在第二应力缓冲区207内，沿远离所述显示区208的方向上均为连续通孔。
综上，本实施例通过在挡墙处的阳极层中设置贯穿阳极层的孔结构，以提供缓冲应力的区域，减小了阳极层在挡墙处所受到的应力，防止了阳极层中的导电膜层以及金属层之间的脱落。
下面结合具体的实施例来详述金属层中孔结构的分布设置情况。
实施例一
如图3所示，为本实施例所提供的孔结构平面示意图，且图3所示仅为部分阵列基板结构以作说明。
其中，包括如上所述的阵列基板，设置于所述基板上的阳极层304，设置于所述阳极层304上的第一挡墙301，与所述第一挡墙301相对应的第一应力缓冲区306，设置于所述阳极层304上的第二挡墙302，与所述第二挡墙302相对应的第二应力缓冲区307，以及同时设置于所述第一应力缓冲区306内的第一孔结构3031和所述第二应力缓冲区307内的第二孔结构3032。
所述第一孔结构3031以及所述第二孔结构3032均为环绕所述显示区308设置，且在环绕所述显示区308的方向上相互间隔设置。
所述第一孔结构3031以及所述第二孔结构3032均沿远离所述显示区308的方向上平行设置，且所述第一孔结构3031在所述第一应力缓冲区306内沿远离所述显示区308的方向上为连续通孔，所述第二孔结构3032在所述第二应力缓冲区307内沿远离所述显示区308的方向上为不连续通孔。
在本实施例中，所述第一应力缓冲区306内，所述第一孔结构3031为矩形通孔，且部分所述第一孔结构3031位于所述第一挡墙301靠近所述显示区308的一端，另一部分所述第一孔结构3031被所述第一挡墙301所覆盖。
所述第二应力缓冲区307内，所述第二孔结构3032为矩形通孔，且部分所述第二孔结构3032位于所述第二挡墙302的两端，另一部分所述第二孔结构3032被所述第二挡墙302所覆盖，其中，被所述第二挡墙302所覆盖的部分所述第二孔结构3032为沿远离所述显示区308的方向上为不连续通孔。
本实施例通过设置孔结构以减小阳极层在挡墙处所受到的应力，以防止阳极层中的导电薄膜与金属层之间的脱落。
实施例二
如图4所示，为本实施例所提供的孔结构平面示意图，且图4所示仅为部分阵列基板结构以作说明。
其中，包括如上所述的阵列基板，设置于所述基板上的阳极层404，设置于所述阳极层404上的第一挡墙401，与所述第一挡墙401相对应的第一应力缓冲区406，设置于所述阳极层404上的第二挡墙402，与所述第二挡墙402相对应的第二应力缓冲区407，以及同时设置于所述第一应力缓冲区406内的第一孔结构4031和所述第二应力缓冲区407内的第二孔结构4032。
所述第一孔结构4031以及所述第二孔结构4032均为环绕所述显示区408设置，且在环绕所述显示区408的方向上相互间隔设置。
所述第一孔结构4031以及所述第二孔结构4032的设置方向均与沿远离所述显示区408的方向有一定夹角，所述第一孔结构4031在所述第一应力缓冲区406内沿远离所述显示区408的方向上为连续通孔，所述第二孔结构4032在所述第二应力缓冲区407内沿远离所述显示区408的方向上为不连续通孔。
在本实施例中，所述第一应力缓冲区406内，所述第一孔结构4031为矩形通孔，且部分所述第一孔结构4031位于所述第一挡墙401靠近所述显示区408的一端，另一部分所述第一孔结构4031被所述第一挡墙401所覆盖。
所述第二应力缓冲区407内，所述第二孔结构4032为矩形通孔，且部分所述第二孔结构4032位于所述第二挡墙402的两端，另一部分所述第二孔结构4032被所述第二挡墙402所覆盖，其中，被所述第二挡墙402所覆盖的部分所述第二孔结构4032为沿远离所述显示区408的方向上为不连续通孔。
本实施例通过设置孔结构以减小阳极层在挡墙处所受到的应力，以防止阳极层中的导电薄膜与金属层之间的脱落。
实施例三
如图5所示，为本实施例所提供的孔结构平面示意图，且图5所示仅为部分阵列基板结构以作说明。
其中，包括如上所述的阵列基板，设置于所述基板上的阳极层504，设置于所述阳极层504上的第一挡墙501，与所述第一挡墙501相对应的第一应力缓冲区506，设置于所述阳极层504上的第二挡墙502，与所述第二挡墙502相对应的第二应力缓冲区507，以及同时设置于所述第一应力缓冲区506内的第一孔结构5031和所述第二应力缓冲区507内的第二孔结构5032。
所述第一孔结构5031以及所述第二孔结构5032均为环绕所述显示区508设置，且在环绕所述显示区508的方向上相互间隔设置。
所述第一孔结构5031以及所述第二孔结构5032均沿远离所述显示区508的方向上平行设置，所述第一孔结构5031在所述第一应力缓冲区506内沿远离所述显示区508的方向上为连续通孔，所述第二孔结构5032在所述第二应力缓冲区507内沿远离所述显示区508的方向上为连续通孔。
在本实施例中，所述第一应力缓冲区506内，所述第一孔结构5031为矩形通孔，且部分所述第一孔结构5031位于所述第一挡墙501靠近所述显示区508的一端，另一部分所述第一孔结构5031被所述第一挡墙501所覆盖。
所述第二应力缓冲区507内，所述第二孔结构5032为矩形通孔，且部分所述第二孔结构5032位于所述第二挡墙502的两端，另一部分所述第二孔结构5032被所述第二挡墙502所覆盖，其中，被所述第二挡墙502所覆盖的部分所述第二孔结构5032为沿远离所述显示区508的方向上为连续通孔。
本实施例通过设置孔结构以减小阳极层在挡墙处所受到的应力，以防止阳极层中的导电薄膜与金属层之间的脱落。
实施例四
如图6所示，为本实施例所提供的孔结构平面示意图，且图6所示仅为部分阵列基板结构以作说明。
其中，包括如上所述的阵列基板，设置于所述基板上的阳极层604，设置于所述阳极层604上的第一挡墙601，与所述第一挡墙601相对应的第一应力缓冲区606，设置于所述阳极层604上的第二挡墙602，与所述第二挡墙602相对应的第二应力缓冲区607，以及同时设置于所述第一应力缓冲区606内的第一孔结构6031和所述第二应力缓冲区607内的第二孔结构6032。
所述第一孔结构6031以及所述第二孔结构6032均为环绕所述显示区608设置，且在环绕所述显示区608的方向上相互间隔设置。
所述第一孔结构6031以及所述第二孔结构6032均沿远离所述显示区608的方向上平行设置，所述第一孔结构6031在所述第一应力缓冲区606内沿远离所述显示区608的方向上为不连续通孔，所述第二孔结构6032在所述第二应力缓冲区607内沿远离所述显示区608的方向上为不连续通孔。
在本实施例中，所述第一应力缓冲区606内，所述第一孔结构6031为矩形通孔，且部分所述第一孔结构6031位于所述第一挡墙601靠近所述显示区608的一端，另一部分所述第一孔结构6031被所述第一挡墙601所覆盖，且被所述第一挡墙601所覆盖的部分所述第一孔结构6031为沿远离所述显示区608的方向上为不连续通孔。
所述第二应力缓冲区607内，所述第二孔结构6032为矩形通孔，且部分所述第二孔结构6032位于所述第二挡墙602的两端，另一部分所述第二孔结构6032被所述第二挡墙602所覆盖，其中，被所述第二挡墙602所覆盖的部分所述第二孔结构6032为沿远离所述显示区608的方向上为不连续通孔。
本实施例通过设置孔结构以减小阳极层在挡墙处所受到的应力，以防止阳极层中的导电薄膜与金属层之间的脱落。
实施例五
如图7所示，为本实施例所提供的孔结构平面示意图，且图7所示仅为部分阵列基板结构以作说明。
其中，包括如上所述的阵列基板，设置于所述基板上的阳极层704，设置于所述阳极层704上的第一挡墙701，与所述第一挡墙701相对应的第一应力缓冲区706，设置于所述阳极层704上的第二挡墙702，与所述第二挡墙702相对应的第二应力缓冲区707，以及同时设置于所述第一应力缓冲区706内的第一孔结构7031和所述第二应力缓冲区707内的第二孔结构7032。
所述第一孔结构7031以及所述第二孔结构7032均为环绕所述显示区708设置，且在环绕所述显示区708的方向上相互间隔设置。
所述第一孔结构7031以及所述第二孔结构7032均沿远离所述显示区708的方向上平行设置，所述第一孔结构7031在所述第一应力缓冲区706内沿远离所述显示区708的方向上为不连续通孔，所述第二孔结构7032在所述第二应力缓冲区707内沿远离所述显示区708的方向上为不连续通孔。
在本实施例中，所述第一应力缓冲区706内，所述第一孔结构7031为圆形通孔，且部分所述第一孔结构7031位于所述第一挡墙701靠近所述显示区708的一端，另一部分所述第一孔结构7031被所述第一挡墙701所覆盖，且被所述第一挡墙701所覆盖的部分所述第二孔结构7032为沿远离所述显示区708的方向上为不连续通孔。
所述第二应力缓冲区707内，所述第二孔结构7032为圆形通孔，且部分所述第二孔结构7032位于所述第二挡墙702的两端，另一部分所述第二孔结构7032被所述第二挡墙702所覆盖，其中，被所述第二挡墙702所覆盖的部分所述第二孔结构7032为沿远离所述显示区708的方向上为不连续通孔。
本实施例通过设置孔结构以减小阳极层在挡墙处所受到的应力，以防止阳极层中的导电薄膜与金属层之间的脱落。
以上需要注意的是，孔结构的形状不限于矩形以及圆形，也不限于第一应力缓冲区以及第二应力缓冲区内的孔结构形状是否相同。
本发明实施例还提供一种显示面板，如图8所示，所述显示面板包括上述阵列基板以及设置于所述阵列基板上有机发光层806以及封装薄膜。
其中，所述阵列基板包括基板805，设置于所述基板805上的阳极层804，设置于所述阳极层804上的第一挡墙801和第二挡墙802，以及贯穿所述阳极层804的第一孔结构8031以及第二孔结构8032。
且所述阳极层804上设置有所述有机发光层806，且所述有机发光层806覆盖所述显示区并止于所述第二挡墙802。
所述有机发光层806上设置有所述薄膜封装层，且所述薄膜封装层包括层叠设置的第一无机层807、有机层808以及第二无机层809，其中，所述第一无机层807以及所述第二无机层809覆盖所述显示区、所述第一挡墙801以及所述第二挡墙802，所述有机层808覆盖所述显示区以及第二挡墙802并止于所述第一挡墙801。
在本发明的另一实施例中，如图9所示，所述显示面板包括上述阵列基板以及设置于所述阵列基板上有机发光层906以及封装薄膜。
其中，所述阵列基板包括基板905，设置于所述基板905上的阳极层904，设置于所述阳极层904上的第一挡墙901和第二挡墙902，以及贯穿所述阳极层904的第一孔结构9031以及第二孔结构9032。
且所述阳极层904上设置有所述有机发光906，且所述有机发光层906覆盖所述显示区并止于所述第二挡墙902。
所述有机发光层906上设置有所述薄膜封装层，且所述薄膜封装层包括层叠设置的第一无机层907、有机层908以及第二无机层909，其中，所述第一无机层907以及所述第二无机层8909覆盖所述显示区、所述第一挡墙901以及所述第二挡墙902，所述有机层908仅覆盖所述显示区并止于所述第二挡墙802。
综上所述，本发明所提供的显示面板通过在阳极层中设置孔结构，以缓冲阳极层在挡墙处所受到的应力，以减小阳极层发生膜层剥离的风险。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：显示区和围绕所述显示区的非显示区；
    所述阵列基板包括：
    基板；
    阳极层，设置于所述基板上；
    第一挡墙，设置在所述阳极层上且环绕所述显示区设置；
    其中，所述阳极层上设有与所述第一挡墙相对应的第一应力缓冲区，且所述第一应力缓冲区内设置有贯穿所述阳极层的第一孔结构。
  2. 根据权利要求1所述的阵列基板，其中，所述第一应力缓冲区环绕所述显示区设置，且至少所述第一挡墙靠近所述显示区的一端位于所述第一应力缓冲区内。
  3. 根据权利要求2所述的阵列基板，其中，所述第一应力缓冲区靠近所述显示区一侧的边界距离所述第一挡墙的距离大于10微米。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括设置于所述阳极层上的第二挡墙，以及与所述第二挡墙相对应的第二应力缓冲区，且所述第二应力缓冲区内设置有第二孔结构；
    其中，所述第二挡墙环绕所述显示区设置，并位于所述第一挡墙靠近所述显示区的一侧。
  5. 根据权利要求4所述的阵列基板，其中，所述第二应力缓冲区环绕所述显示区设置，且所述第二挡墙位于所述第二应力缓冲区内。
  6. 根据权利要求5所述的阵列基板，其中，所述第二应力缓冲区的两边界距离所述第二挡墙的距离均大于10微米。
  7. 根据权利要求4所述的阵列基板，其中，所述第一孔结构和所述第二孔结构均包括：多个环绕所述显示区且相互间隔的通孔。
  8. 根据权利要求7所述的阵列基板，其中，所述通孔包括沿远离所述显示区方向上，多个连续或不连续的子通孔。
  9. 根据权利要求8所述的阵列基板，其中，所述第一孔结构的通孔与所述第二孔结构的通孔的结构相同或不相同。
  10. 一种显示面板，所述显示面板包括阵列基板，以及依次设置于所述阵列基板上的有机发光层和薄膜封装层；
    所述阵列基板包括显示区和围绕所述显示区的非显示区；
    所述阵列基板包括：
    基板；
    阳极层，设置于所述基板上；
    第一挡墙，设置在所述阳极层上且环绕所述显示区设置；
    其中，所述阳极层上设有与所述第一挡墙相对应的第一应力缓冲区，且所述第一应力缓冲区内设置有贯穿所述阳极层的第一孔结构。
  11. 根据权利要求10所述的显示面板，其中，所述第一应力缓冲区环绕所述显示区设置，且至少所述第一挡墙靠近所述显示区的一端位于所述第一应力缓冲区内。
  12. 根据权利要求11所述的显示面板，其中，所述第一应力缓冲区靠近所述显示区一侧的边界距离所述第一挡墙的距离大于10微米。
  13. 根据权利要求10所述的显示面板，其中，所述阵列基板还包括设置于所述阳极层上的第二挡墙，以及与所述第二挡墙相对应的第二应力缓冲区，且所述第二应力缓冲区内设置有第二孔结构；
    其中，所述第二挡墙环绕所述显示区设置，并位于所述第一挡墙靠近所述显示区的一侧。
  14. 根据权利要求13所述的显示面板，其中，所述第二应力缓冲区环绕所述显示区设置，且所述第二挡墙位于所述第二应力缓冲区内。
  15. 根据权利要求14所述的显示面板，其中，所述第二应力缓冲区的两边界距离所述第二挡墙的距离均大于10微米。
  16. 根据权利要求13所述的显示面板，其中，所述第一孔结构和所述第二孔结构均包括：多个环绕所述显示区且相互间隔的通孔。
  17. 根据权利要求16所述的显示面板，其中，所述通孔包括沿远离所述显示区方向上，多个连续或不连续的子通孔。
  18. 根据权利要求17所述的显示面板，其中，所述第一孔结构的通孔与所述第二孔结构的通孔的结构相同或不相同。
  19. 根据权利要求13所述的显示面板，其中，所述第一挡墙的高度大于所述第二挡墙的高度。
  20. 根据权利要求13所述的显示面板，其中，所述第一挡墙所覆盖的所述第一孔结构内，填充有与所述第一挡墙相同的材料；
    所述第二挡墙所覆盖的所述第二孔结构内，填充有与所述第二挡墙相同的材料。
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