WO2021016993A1 - 电容检测电路、检测芯片及电子设备 - Google Patents

电容检测电路、检测芯片及电子设备 Download PDF

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Publication number
WO2021016993A1
WO2021016993A1 PCT/CN2019/098900 CN2019098900W WO2021016993A1 WO 2021016993 A1 WO2021016993 A1 WO 2021016993A1 CN 2019098900 W CN2019098900 W CN 2019098900W WO 2021016993 A1 WO2021016993 A1 WO 2021016993A1
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Prior art keywords
module
capacitor
switch unit
terminal
voltage
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PCT/CN2019/098900
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English (en)
French (fr)
Inventor
蒋宏
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深圳市汇顶科技股份有限公司
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Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2019/098900 priority Critical patent/WO2021016993A1/zh
Priority to EP19917529.0A priority patent/EP3798809B1/en
Priority to CN201980001400.5A priority patent/CN112602047B/zh
Priority to US17/010,809 priority patent/US11687197B2/en
Publication of WO2021016993A1 publication Critical patent/WO2021016993A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/945—Proximity switches
    • H03K17/955—Proximity switches using a capacitive detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/960705—Safety of capacitive touch and proximity switches, e.g. increasing reliability, fail-safe
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/96071—Capacitive touch switches characterised by the detection principle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/96071—Capacitive touch switches characterised by the detection principle
    • H03K2217/960725—Charge-transfer

Definitions

  • the embodiments of the present application relate to the technical field of capacitance detection, and in particular to capacitance detection circuits, detection chips, and electronic equipment.
  • Capacitance detection technology is widely used in electronic equipment to realize human-computer interaction.
  • the capacitive touch screen on electronic equipment can realize the touch function through capacitance detection; another example is the capacitance detection module on the headset, which can realize automatic Check whether the user is wearing a headset.
  • this is only an exemplary description.
  • self-capacitance in the capacitance detection process, when there is no human body approaching or touching, there is self-capacitance between the detection electrode and circuit ground. When the human body approaches or touches the detection electrode, the capacitance between the detection electrode and the circuit ground will change. Large, determine the user's related operations by detecting the amount of capacitance change.
  • embodiments of the present application provide a capacitance detection circuit, a detection chip, and an electronic device to overcome or alleviate the technical defects in the prior art.
  • an embodiment of the present application provides a capacitance detection circuit, including: a first driving module, a conversion module, a processing module, and a control module; the first driving module is used to charge the first capacitor to be tested; the conversion module is used To perform charge conversion processing on the first capacitor to be measured to generate an output voltage, the conversion module includes a first suppression module, and the control module is used to control the first suppression module to generate an output voltage when the conversion module generates an output voltage.
  • the interference signal is suppressed, and the second frequency is greater than the first frequency; the processing module is used to determine the capacitance change of the first capacitor to be measured before and after being affected by the external electric field according to the output voltage.
  • an embodiment of the present application provides a detection chip, which is characterized by including the capacitance detection circuit as described in any one of the embodiments of the first aspect.
  • an embodiment of the present application provides an electronic device, which is characterized by including the detection chip as described in the second aspect.
  • the capacitance detection circuit, detection chip, and electronic equipment of the embodiments of the present application suppress interference signals that are less than the first frequency or greater than the second frequency when the output voltage is generated by the conversion module through the first suppression module, thereby reducing the influence of the interference signal , Improve the sensitivity and accuracy of capacitance detection.
  • FIG. 1 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application
  • FIG. 2 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 3 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of an amplitude-frequency characteristic provided by an embodiment of the application.
  • FIG. 5 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 5a is a structural diagram of a capacitance detection circuit provided by an embodiment of the present application.
  • 5b is a structural diagram of a capacitance detection circuit provided by an embodiment of the present application.
  • FIG. 6 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 7 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 8 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 9 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 10 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 11 is a control sequence diagram provided by an embodiment of the application.
  • FIG. 12 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 13 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 14 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 15 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 16 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • FIG. 17 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit provided in the embodiments of the present application can be applied to self-capacitance detection and mutual capacitance detection. For this reason, the following embodiments first describe the capacitance detection circuit applied to self-capacitance detection, and then the capacitance detection during mutual capacitance detection The circuit connection is explained.
  • Example 1 Capacitance detection circuit when applied to self-capacitance detection ( Figure 1- Figure 14)
  • FIG. 1 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 includes: a first driving module 11, a conversion module 12, and a processing module 13 And the control module 14; the first driving module 11 is used to charge the first capacitance Cx to be measured; the conversion module 12 is used to charge the first capacitance to be measured to generate an output voltage, the conversion module 12 includes a first suppression module 121.
  • the control module 14 is used to control the first suppression module 121 to suppress interference signals that are less than the first frequency or greater than the second frequency when the conversion module 12 generates an output voltage, and the second frequency is greater than the first frequency; the processing module 13 is used to Determine the capacitance change before and after the first capacitance to be measured is affected by the external electric field according to the output voltage.
  • the first driving module 11 charges the first capacitance to be measured
  • the conversion module 12 performs charge conversion processing on the first capacitance to be measured to generate an output voltage
  • the conversion module 12 performs charge transfer on the first capacitance to be measured.
  • the conversion process generates an output voltage.
  • the first suppression module 121 suppresses signals that are less than the first frequency or greater than the second frequency.
  • FIG. 2 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 further includes a third switch unit 15, and the third switch unit 15 is connected to the first driving module 11 and the conversion module 12
  • the third switch unit 15 When the third switch unit 15 is turned off, the first driving module 11 charges the first capacitor to be tested, and when the third switch unit 15 is closed, the conversion module 12 charges the first capacitor to be tested The conversion process generates an output voltage.
  • the third switch unit 15 when the third switch unit 15 is closed, it is the charge transfer stage.
  • the third switch unit 15 can be a single-pole single-throw switch. When the third switch unit 15 is connected to the first capacitor to be measured and the conversion module 12, It is the charge transfer stage.
  • FIG. 1 the third switch unit 15 is connected to the first capacitor to be measured and the conversion module 12, It is the charge transfer stage.
  • the first driving module 11 will also be equipped with a switch, and during the charging phase, the first driving module is connected. Module 11 and the first capacitance to be measured, at this time, the third switch unit 15 is turned off; in the charge transfer phase, the switch of the first driving module 11 is turned off, so that the first driving module 11 and the first capacitance to be measured are disconnected, At this time, the third switch unit 15 is closed.
  • this is only an exemplary description, which does not mean that the application is limited to this.
  • the conversion module 12 has a first input terminal and a second input terminal, the first input terminal of the conversion module 12 is electrically connected to the first driving module 11, and the second input terminal is connected to Common mode voltage and/or connection with other circuits that can equivalently generate common mode voltage.
  • the conversion module 12 may include a differential amplifier, and the differential amplifier may be a single-ended differential amplifier 122 or a double-ended differential amplifier 123.
  • the conversion module 12 includes a single-ended differential amplifier 122.
  • the double-ended differential amplifier 123 the case of the double-ended differential amplifier 123:
  • the first input terminal of the conversion module 12 Is the inverting input terminal of the single-ended differential amplifier 122
  • the second input terminal of the conversion module 12 is the non-inverting input terminal of the single-ended differential amplifier 122
  • the first driving module 11 is electrically connected to the inverting input terminal of the single-ended differential amplifier 122
  • the non-inverted input terminal of the single-ended differential amplifier 122 is connected to the common mode voltage
  • the output terminal of the single-ended differential amplifier 122 is electrically connected to the processing module 13; both ends of the first suppression module 121 are respectively connected to the reverse of the single-ended differential amplifier 122 Phase input and output.
  • the conversion module 12 includes a single-ended differential amplifier 122 as an example for description.
  • the first suppression module 121 includes a first switch unit 1211, a first capacitor 1212, and a second capacitor 1213; the first terminal and the second terminal of the first switch unit 1211 are respectively connected to the inverting input terminal and the output terminal of the single-ended differential amplifier 122
  • the first capacitor 1212 can be connected to the first end of the first switch unit 1211 and the second end of the first switch unit 1211 through the third end of the first switch unit 1211, and the second end of the first capacitor 1212 is grounded, Two ends of the second capacitor 1213 are respectively connected to the inverting input terminal and the output terminal of the single-ended differential amplifier 122.
  • the control module 14 is used to control the first switch unit 1211 to switch back and forth between the first terminal and the second terminal, so that the third terminal of the first switch unit 1211 is connected with the first terminal or the third terminal is connected.
  • the terminal is connected to the second terminal, and the switching frequency of the first switch unit 1211 is greater than twice the driving frequency (that is, the driving frequency of the first driving module 11), so as to suppress the electrical signal less than the first frequency.
  • the control module 14 controls the first switch unit 1211 to switch back and forth between the first terminal and the second terminal, so that the third terminal of the first switch unit 1211 is connected to the first terminal or the third terminal is connected to the The second end is connected, and the second capacitor 1213 is reset.
  • the driving frequency (that is, the driving frequency of the first driving module 11) refers to the switching frequency at which the third switch unit 15 is connected and disconnected.
  • the first suppression module 121 suppresses electrical signals less than the first frequency mainly for interference signals generated by the power supply.
  • the interference signals generated by the power supply are within 50 Hz. Therefore, the first frequency can be 50 Hz.
  • this is just an example. Sexual description.
  • the first switch unit 1211 may include a single-pole double-throw switch, which is switched back and forth between the first end and the second end, so that the third end of the first switch unit 1211 communicates with the first end or the third end communicates with the second end, Alternatively, the first switch unit 1211 may include two single-pole single-throw switches, one single-pole single-throw switch is closed, and the other single-pole single-throw switch is opened, that is, the two single-pole single-throw switches are alternately closed and opened to function as a single-pole double-throw switch. The function of the switch. Of course, this is only an exemplary description, which does not mean that the application is limited to this.
  • the switching frequency of the unit 1211, Cr is the capacitance value of the first capacitor 1212.
  • the combination of the second capacitor 1213 with the first switch unit 1211 and the first capacitor 1212 adds a zero point F 0 to the capacitance detection circuit 10, and this zero point can be directly used as the first frequency, as shown in FIG. 4, 4
  • the amplifier (single-ended differential amplifier 122 or double-ended differential amplifier 123) has a main pole Fc, and the main pole can be directly used as the second frequency. The higher the frequency after the main pole, the lower the gain, which makes the capacitance detection circuit 10 work
  • the frequency band is between F 0 and Fc, that is, interference signals smaller than the first frequency and larger than the second frequency are suppressed.
  • the relationship that the switching frequency of the first switching unit 1211 is greater than twice the power supply frequency must be satisfied.
  • the first driving module 11 includes a fourth switch unit 112, and the control module 14 further uses The fourth switch unit 112 is controlled to be in the first closed state so that the first drive module 11 charges the first capacitor to be measured; specifically, because the fourth switch unit 112 is in the first closed state, the The first terminal is connected to the first voltage (Vcc) through the fourth switch unit 112, and the second terminal of the first capacitor to be measured is connected to the second voltage (such as gnd). The first voltage is greater than the second voltage, thereby realizing the The capacitor under test is charged.
  • FIG. 5a is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the fourth switch unit 112 includes a fourth switch K 4 , the fourth switch K 4 is a single-pole single-throw switch, and the fourth switch K One end of 4 is connected to the first voltage (Vcc), and the other end of the fourth switch K 4 is connected to the first capacitor to be measured.
  • Vcc first voltage
  • gnd second voltage
  • control module 14 is further configured to control the fourth switch unit 112 to be in the second closed state to discharge the first capacitance to be measured; specifically, since the fourth switch unit 112 is in the second closed state, the first to be measured
  • the first terminal of the capacitor is connected to the third voltage (Vss) through the fourth switch unit 112, and the second terminal of the first capacitor to be tested is connected to the second voltage.
  • the second voltage is greater than the third voltage, so that the first capacitor to be tested Discharge.
  • the fourth switch unit 112 may include a single-pole double-throw switch, and two closed states are realized by connecting two connecting ends, or the fourth switch unit 112 may include two single-pole single-throw switches, the first single-pole single-throw switch is closed, The second single-pole single-throw switch is opened to the first closed state, the first single-pole single-throw switch is opened, and the second single-pole single throw switch is closed to the second closed state.
  • this is only an exemplary description, which does not mean that the application is limited to this.
  • the fourth switch unit 112 includes a fifth switch K 51 , the fifth switch K 51 is a single-pole double-throw switch, and the fifth switch K a first access terminal 51 of a first voltage, the second terminal of the third voltage of the fifth switching access K 51, K terminal of the fifth switch 51 and a third capacitor connected to the first test, the fifth switch 51 in the K
  • the fourth switch unit 112 is in the first closed state, and both ends of the first capacitor to be tested are connected to the first voltage (Vcc) and the second voltage (such as gnd), respectively, to realize the A capacitor to be tested is charged;
  • the fourth switch unit 112 is in the second closed state, and both ends of the first capacitor to be tested are connected to a second voltage (such as gnd) and the third voltage (Vss) to discharge the first
  • the first application scenario will be described in detail with reference to the capacitance detection circuit shown in FIGS. 3 and 5, and the circuit structure will be described in detail with reference to the capacitance detection circuit shown in FIG. 6, and FIG. 6 is an implementation of this application.
  • the example provides a structure diagram of a capacitance detection circuit.
  • the first switch unit 1211 may include a first switch K 1 ;
  • the third switch unit 15 is K 3 ;
  • the fourth switch unit 112 may include a fourth switch K 4 , and may also include a fifth switch K 51 .
  • the capacitance detection circuit 10 is a self-capacitance detection circuit
  • the differential amplifier included in the conversion module 12 is a single-ended differential amplifier 122.
  • the first driving module 11 includes a fourth switch K 4 and a fifth switch K 51. The first terminal of the fourth switch K 4 is electrically connected to the first terminal of the first capacitor Cx to be measured.
  • the terminal is grounded (the ground voltage is the second voltage), the second terminal of the fourth switch K 4 is electrically connected to the third terminal of the fifth switch, the first terminal of the fifth switch K 51 is connected to the first voltage Vcc, the fifth switch The second terminal of K 51 is connected to the third voltage Vss; among them, the fourth switch K 4 is closed and the first terminal and the third terminal of the fifth switch K 51 are connected, and the first capacitor to be measured is connected to the first voltage Vcc.
  • the fourth switch unit 112 is in the first closed state; the fourth switch K 4 is closed and the second end and the third end of the fifth switch K 51 are connected, and the first capacitor to be measured is connected to the third voltage Vss. At this time, The fourth switch unit 112 is in the second closed state.
  • the third switch unit 15K 3 Two ends of the third switch unit 15K 3 are electrically connected to the first end of the first capacitor to be measured and the inverting input end of the single-ended differential amplifier 122 respectively.
  • the non-inverting input terminal of the single-ended differential amplifier 122 is connected to the common mode voltage Vcm, and the output terminal of the single-ended differential amplifier 122 (that is, the first output terminal of the single-ended differential amplifier 122) is connected to the processing module 13.
  • the first suppression module 121, a first suppression module 121, a first switch K 1 of the first and second ends are respectively connected to the inverting input terminal and an output terminal of the single-terminal of the differential amplifier 122, a first capacitor 1212 through the first a third terminal of the switch K 1 may be connected to a first terminal of a first switch and a first switch K 1 K 1 of the second terminal, respectively, a first capacitor 1212C r a second end, the second of the two capacitor 1213C f
  • the terminals are respectively connected to the inverting input terminal and the output terminal of the single-ended differential amplifier 122.
  • the double-ended differential amplifier 123 has a non-inverting input terminal, an inverting input terminal, a first output terminal, and a second output terminal.
  • the first input terminal of the conversion module 12 is the inverting input terminal of the double-ended differential amplifier 123
  • the second input terminal of the conversion module 12 is the non-inverting input terminal of the double-ended differential amplifier 123
  • the first driving module 11 and the double-ended differential amplifier 123 The inverting input terminal of the amplifier 123 is electrically connected, the non-inverting input terminal of the double-ended differential amplifier 123 is connected to the common mode voltage, and the first output terminal and the second output terminal of the double-ended differential amplifier 123 are electrically connected to the processing module 13;
  • Two ends of a suppression module 121 are respectively connected to the inverting input terminal and the first output terminal of the double-ended differential amplifier 123.
  • the input and output of the double-ended differential amplifier 123 may be connected to only one first suppression module 121.
  • the double-ended differential amplifier 123 is equivalent to a single-ended differential amplifier 122, and the input of the double-ended differential amplifier 123
  • the first suppression module 122 and the second suppression module 124 are configured at the same time as the output terminal and the output terminal.
  • the dynamic range of the detection circuit is relatively large, and a relatively large gain can be achieved, thereby improving the sensitivity of detection.
  • FIG. 7 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the conversion module 12 includes a double-ended differential amplifier 123 as an example for description.
  • the conversion module 12 also includes a second suppression module 124. Two ends of the second suppression module 124 are respectively connected to the non-inverting input terminal and the second output terminal of the double-ended differential amplifier 123.
  • the control module 14 is used to control the second suppression module 124 in When the conversion module 12 generates the output voltage, it suppresses interference signals that are less than the first frequency or greater than the second frequency, and the second frequency is greater than the first frequency.
  • the second suppression module 124 includes a second switch unit 1241, a third capacitor 1242, and a fourth capacitor 1243; the first terminal of the second switch unit 1241 And the second terminal are respectively connected to the non-inverting input terminal and the second output terminal of the double-ended differential amplifier 123, and the two ends of the fourth capacitor 1243 are respectively connected to the first terminal of the second switch unit 1241 and the second switch unit 1241.
  • the first end of the third capacitor 1242 is electrically connected to the third end of the second switch unit 1241, and the second end of the third capacitor 1242 is grounded; the control module 14 is used to control the second switch unit 1241 to connect to the first end Switch back and forth between the second terminals so that the third terminal of the second switch is connected to the first terminal or the third terminal is connected to the second terminal.
  • the switching frequency of the second switch unit 1241 is greater than twice the driving frequency, so that the The electrical signal of the first frequency is suppressed.
  • the principle of the second suppression module 124 is the same as that of the first suppression module 121, and will not be repeated here.
  • the specific structures of the second suppression module 124 and the first suppression module 121 may be different.
  • the driving frequency in the self-capacitance detection circuit is the switching frequency at which the switch in the second driving module is connected or disconnected, or the driving frequency in the mutual capacitance detection circuit is the second driving frequency.
  • the power frequency of the module is the switching frequency at which the switch in the second driving module is connected or disconnected, or the driving frequency in the mutual capacitance detection circuit is the second driving frequency.
  • the second switch unit 1241 may include a single-pole double-throw switch, which is switched back and forth between the first end and the second end, so that the third end of the two switch units is connected to the first end or the third end is connected to the second end, or,
  • the second switch unit 1241 may include two single-pole single-throw switches, one single-pole single-throw switch is closed, one single-pole single-throw switch is opened, and alternately closed and opened to function as a single-pole double-throw switch.
  • this is only an exemplary description, which does not mean that the application is limited to this.
  • FIG. 8 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the second application scenario is described in detail in conjunction with the capacitance detection circuit shown in FIG. 7 above, referring to the capacitance shown in FIG.
  • the detection circuit describes the circuit structure in detail.
  • the first switch unit 1211 may include a first switch K 1 ;
  • the second switch unit 1241 may include a second switch K 2 ;
  • the third switch unit 15 is K 3 ;
  • the fourth switch unit 112 may include a fourth switch K 4 may also include a fifth switch K 51 .
  • the capacitance detection circuit 10 is a self-capacitance detection circuit, and the differential amplifier included in the conversion module 12 is a double-ended differential amplifier 123.
  • the capacitance detection circuit 10, the first driving module 11 and the first suppression module 121 provided in this embodiment are the same as those in the fourth embodiment, and will not be repeated here.
  • the conversion module 12 in this embodiment also includes a second suppression module.
  • the first terminal and the second terminal of the second switch K 2 are respectively connected to the non-inverting input terminal and the second output terminal of the double-ended differential amplifier 123, and both ends of the fourth capacitor 1243C f a second terminal respectively connected to the first terminal of the second switch K 2 and K 2 of the second switch, the third capacitor 1242C r a first end electrically connected to the third terminal of the second switching unit 1241, a third capacitor 1242C r The second terminal is grounded.
  • the capacitance values of the first capacitor 1212 and the third capacitor 1242 are the same as C r
  • the capacitance values of the second capacitor 1213 and the fourth capacitor 1243 are the same as C f .
  • the capacitance detection circuit 10 shown in FIG. 6 and FIG. 8 is suitable for the case where the self-capacitance of the first capacitor Cx to be measured is small, because the self-capacitance is small and the impact on detection is small.
  • FIG. 9 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 further includes a first cancellation module 16;
  • the module 14 is also used to control the first canceling module 16 to charge the first canceling capacitor, and to control the first canceling capacitor to charge or discharge the first capacitor to be measured to achieve charge cancellation.
  • the first cancellation module 16 includes a fifth switch unit 161, and the control module 14 is further configured to control the fifth switch unit 161 to be in the first closed state and form The charging branch is used to allow the cancellation module to charge the first cancellation capacitor; the control module 14 is also used to control the fifth switch unit 161 to be in the second closed state to form a cancellation branch so that the first cancellation capacitor Cc performs the charging on the first capacitor under test. Charging or discharging realizes charge cancellation.
  • the fifth switch unit 161 may include two single-pole double-throw switches, and three closed states are realized by the switching of the two single-pole double-throw switches.
  • this is only an exemplary description, which does not mean that the application is limited to this.
  • both ends of the first cancellation capacitor are connected to the fourth voltage and the fifth voltage respectively, and the fifth voltage is higher than the fourth voltage. Voltage. At this time, the first cancellation capacitor is charged.
  • the first end of the first cancellation capacitor is electrically connected to the first end of the first capacitor under test through the fifth switch unit 161.
  • the second end of the first cancellation capacitor is connected to the sixth voltage or the seventh voltage through the fifth switch unit 161, and the sixth voltage is lower than the second voltage connected to the second end of the capacitor under test.
  • a capacitor to be tested is discharged to achieve charge offset, and the seventh voltage is higher than the second voltage connected to the second end of the capacitor to be tested. At this time, the first capacitor to be tested is charged to achieve charge offset.
  • the charge on the first capacitor under test is transferred to the first cancellation capacitor.
  • first cancellation capacitor charges the capacitor under test to achieve charge cancellation, first The charge transfer on the offset capacitor to the first capacitor under test, the charge transfer during the offset process, is to eliminate the influence caused by the existence of the basic capacitance of the first capacitor under test, which is different from the charge transfer in the charge transfer stage.
  • the capacitance detection circuit 10 based on self-capacitance detection shown in FIG. 3, combined with the structure of the first drive module 11 shown in the capacitance detection circuit 10 shown in FIG. 5, and the capacitance detection circuit 10 shown in FIG.
  • the illustrated structure of the first cancellation module 16 describes the working timing of the capacitance detection circuit 10. According to the first voltage or the second voltage of the first capacitor to be measured, the capacitance detection circuit 10 is divided into a positive process and a negative process:
  • the third switch unit 15 is turned off, the fourth switch unit 112 is in the first closed state, the first capacitor under test is connected to the first voltage, and the first driving module 11 responds to the first capacitor under test.
  • the fifth switch unit 161 is in the first closed state, the fourth voltage and the fifth voltage are respectively connected to both ends of the first cancellation capacitor to form a charging branch, and the first cancellation capacitor is charged to the fifth voltage;
  • the third switch unit 15 is still off, the fourth switch unit 112 is off, and the fifth switch unit 161 is in the second closed state.
  • the first cancellation capacitor discharges the first capacitor to be measured to achieve charge cancellation , Part of the charge of the first capacitor under test is transferred to the first cancellation capacitor; in the third stage, the third switch unit 15 is closed, the first capacitor under test and the conversion module 12 are connected, the fourth switch unit 112 is off, and the fifth switch unit 161 is in the second closed state, the conversion module 12 performs charge conversion processing on the first capacitor under test to generate an output voltage, and the processing module 13 determines the capacitance change of the first capacitor under test according to the output voltage of the transfer module.
  • the third switch unit 15 is opened, the fourth switch unit 112 is in the second closed state, the first capacitor to be measured is discharged to the third voltage, and the fifth switch unit 161 is in the first closed state.
  • Both ends of the first cancellation capacitor are connected to the fourth voltage and the fifth voltage to form a charging branch, and the first cancellation capacitor is charged to the fifth voltage; in the second stage, the third switch unit 15 is still turned off, and the fourth switch unit 112 is open, and the fifth switch unit 161 is in the second closed state.
  • the first cancellation capacitor charges the first capacitor to be tested to achieve charge cancellation, and part of the charge of the first cancellation capacitor is transferred to the first capacitor to be tested.
  • a capacitor under test is charged to the seventh voltage; in the third stage, the third switch unit 15 is closed, the first capacitor under test is connected to the conversion module 12, the fourth switch unit 112 is off, and the fifth switch unit 161 is in the third closed state. State, the conversion module 12 performs charge conversion processing on the first capacitor to be measured to generate an output voltage, and the processing module 13 determines the capacitance change of the first capacitor to be measured according to the output voltage of the transfer module.
  • the first cancellation capacitor can discharge or charge the first capacitor under test to the common mode voltage Vcm; if there is no finger close, the capacitance value Cx of the first capacitor under test will not change.
  • the output of the conversion module 12 will not change (zero); if an object is close to the first capacitor to be measured, Cx will change, denoted as Cx+ ⁇ C, where ⁇ C is caused by the object being close to the first capacitor to be measured.
  • the capacitance change amount because the first capacitance to be measured becomes larger, the output of the conversion module 12 will change (not zero) during the third-stage detection process.
  • the capacitance detection circuit 10 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 is a self-capacitance detection circuit
  • the differential amplifier included in the conversion module 12 is a single-ended differential amplifier 122.
  • FIG. 10 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 is a self-capacitance detection circuit
  • the differential amplifier included in the conversion module 12 is a single-ended differential amplifier 122.
  • the first switch unit 1211 may include a first switch K 1 ; the second switch unit 1241 may include a second switch K 2 ; the third switch unit 15 is K 3 ; and the fourth switch unit 112 may include a fourth switch K 4 may also include a fifth switch K 51 ; the fifth switch unit 161 may include three fifth switches K 52 , K 53 and K 54 , and may also include two sixth switches K 61 and K 62 ; seventh The switch unit 171 may include a seventh switch K 7 , and may also include an eighth switch K 81 .
  • the capacitance detection circuit in FIG. 10 includes a first driving module 11, a conversion module 12, a first suppression module 121 and a first cancellation module 16.
  • the first driving module 11, the conversion module 12, and the first suppression module 121 are the same as those in the fourth embodiment.
  • the fifth switch unit 161 includes three fifth switches K 52 , K 53 and K 54 , and two sixth switches K 61 and K 62 ; in this embodiment, the fourth voltage and the sixth voltage are both Vss, and the fifth voltage and the seventh voltage are both Vcc.
  • the fifth switch K 52 can connect the first terminal with the third terminal or connect the second terminal with the third terminal by switching between the first terminal and the second terminal.
  • the first terminal of the fifth switch K 52 is connected to Vss.
  • the third terminal of the fifth switch 52 is connected to the sixth switch K K a first end 61, a second end connected to the sixth switch of the first 61 K measured capacitor Cx
  • the third end of the sixth switch K 61 is electrically connected to the first end of the first cancellation capacitor Cc
  • the sixth switch K 61 can connect the first end and the third end by switching between the first end and the second end or the second and third terminals communicate with the second terminal of the first offset capacitance Cc is electrically connected to the third terminal of the sixth switch K 62, K 62 through the sixth switch of the first and second ends handover may be
  • the first terminal and the third terminal are connected or the second terminal and the third terminal are connected
  • the first terminal of the sixth switch K 62 and the third terminal of the fifth switch K 53 are electrically connected
  • the first terminal of the sixth switch K 62 It is electrically connected to the third terminal of the fifth switch K 54 .
  • the fifth switch K 53 can connect the first terminal and the third terminal or connect the second terminal and the third terminal by switching between the first terminal and the second terminal, and the fifth switch K 54 can connect the first terminal and the second terminal. Switching can connect the first terminal and the third terminal or connect the second terminal and the third terminal.
  • the first terminal of the fifth switch K 53 is connected to Vcc
  • the second terminal of the fifth switch K 53 is connected to Vss
  • the second terminal of the fifth switch K 53 is connected to Vss.
  • the first end of the switch K 54 is connected to Vss
  • the second end of the fifth switch K 54 is connected to Vss.
  • the fifth switch (K 52 , K 53 and K 54 ) are all switched to the first end, the respective first and third ends are connected, and the sixth switch (K 61 and K 62 ) are all switched to The first end connects the respective first end and third end.
  • the fifth switch unit 161 is in the first closed state; the fifth switches (K 52 , K 53 and K 54 ) are all switched to the first end, Connect the respective first end and the third end, the sixth switch (K 61 and K 62 ) are switched to the second end, and the respective second end and third end are connected, at this time, the fifth switch unit 161 is in The second closed state; the fifth switch (K 52 , K 53 and K 54 ) are all switched to the second end, the respective first and third ends are connected, and the sixth switch (K 61 and K 62 ) are all switched to At the first end, the respective first end and third end are connected.
  • the fifth switch unit 161 is in the first closed state; the fifth switches (K 52 , K 53 and K 54 ) are all switched to the second end, Connect the respective first end and third end, the sixth switch (K 61 and K 62 ) are switched to the second end, and the respective second end and third end are connected. At this time, the fifth switch unit 161 is in The second closed state.
  • FIG. 11 is a control sequence diagram provided by an embodiment of the application. According to the Vcc or Vss of the first capacitor to be tested, the capacitance detection circuit 10 is divided into a positive process and a negative process:
  • the conversion module 12 performs charge conversion processing on the first capacitor Cx to be measured to generate an output voltage.
  • the conversion module 12 performs charge conversion processing on the first capacitor Cx to be measured to generate an output voltage.
  • the switching frequency of the first switch unit 1211 is greater than twice the power frequency, so as to suppress signals that are less than the first frequency or greater than the second frequency.
  • the capacitance detection circuit is self-contained circuit
  • the power supply frequency refers to the third switching unit 15 and the communication frequency is switched off
  • the third switch 16 is turned off or the communication unit 4 is controlled by the fourth switch K
  • the first A switch unit 1211 is the first switch K 1
  • the switching frequency of the first switch unit 1211 is greater than twice the power supply frequency means that the first switch K 1 is between the first terminal and the second terminal
  • the frequency of switching between is greater than twice the switching frequency of on and off of the fourth switch K 4 .
  • FIG. 12 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 is a self-capacitance detection circuit
  • the conversion module 12 includes a differential amplifier It is a double-ended differential amplifier 123.
  • the capacitance detection circuit 10 in this embodiment includes a first driving module 11, a conversion module 12, a first suppression module 121, a first cancellation module 16 and a second suppression module 124.
  • the first driving module 11, the conversion module 12, the first suppression module 121, and the first cancellation module 16 are the same as those in the sixth embodiment, and will not be repeated here.
  • the second switch K 2 The first terminal and the second terminal are respectively connected to the non-inverting input terminal and the second output terminal of the double-ended differential amplifier 123, and the two ends of the fourth capacitor 1243C f are respectively connected to the first terminal and the second switch of the second switch K 2 K 2 of the second end, the third capacitor 1242C r a first terminal and a third terminal electrically connected to the second switching unit 1241, a third capacitor second terminal of 1242C r.
  • the capacitance values of the first capacitor 1212 and the third capacitor 1242 are the same as C r
  • the capacitance values of the second capacitor 1213 and the fourth capacitor 1243 are the same as C f .
  • the capacitance detection circuit 10 described in the sixth and seventh embodiments is suitable for the case where the self-capacitance of the first capacitance to be measured is large, because the self-capacitance of the first capacitance to be measured is large, and therefore, has a greater impact on capacitance detection.
  • the first cancellation module 16 to cancel the self-capacitance of the first capacitance to be measured, the change ⁇ C of the first capacitance to be measured when the object approaches can be detected more accurately.
  • FIG. 13 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 further includes a second driving module 17.
  • the second drive module 17 is electrically connected to the second input terminal of the conversion module 12.
  • the control module 14 is also used to charge the second capacitor under test by controlling the second drive module 17; the conversion module 12 is used to charge the second capacitor under test. Charge conversion processing to generate output voltage.
  • the capacitance detection circuit 10 further includes a sixth switch unit 18, and the sixth switch unit 18 is connected to the second drive module 17 and the second drive module 12 Between the input terminals, when the sixth switch unit 18 is closed, the conversion module 12 performs charge conversion processing on the second capacitor to be measured to generate an output voltage.
  • the second drive module 17 includes a seventh switch unit 171, and the control module 14 is further configured to control the seventh switch unit 171 to be in the first closed state so that the second drive module 17 responds to the second standby.
  • the seventh switch unit 171 is in the first closed state
  • the first terminal of the second capacitor to be tested is connected to the eighth voltage through the seventh switch unit 171
  • the second terminal of the second capacitor to be tested is connected to the Nine voltage, the eighth voltage is greater than the ninth voltage.
  • control module 14 is further configured to control the seventh switch unit 171 to be in the second closed state to discharge the second capacitance to be measured; when the seventh switch unit 171 is in the second closed state, the first capacitance of the second capacitance to be measured
  • the terminal is connected to the tenth voltage through the seventh switch unit 171, and the second terminal of the second capacitor to be measured is connected to the ninth voltage, which is greater than the tenth voltage.
  • the principle and structure of the second driving module 17 are the same as those of the first driving module 11, and will not be repeated here.
  • FIG. 14 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 further includes a second cancellation module 19;
  • the module 14 is also used to control the second canceling module 19 to charge the second canceling capacitor, and to control the second canceling capacitor to charge or discharge the second capacitor to be measured to achieve charge cancellation.
  • the second cancellation module 19 includes an eighth switch unit 191, and the control module 14 is further configured to control the eighth switch unit 191 to be in the first closed state and form a charging branch so that the cancellation module can contact the second The second cancellation capacitor is charged; the control module 14 is also used to control the eighth switch unit 191 to be in a second closed state to form a cancellation branch so that the second cancellation capacitor charges or discharges the second capacitor to be measured to achieve charge cancellation.
  • both ends of the second cancellation capacitor are connected to the eleventh voltage and the twelfth voltage, and the twelfth voltage is higher than the eleventh voltage.
  • the eighth switch unit 191 when the eighth switch unit 191 is in the second closed state, the first end of the second cancellation capacitor is electrically connected to the first end of the second capacitor to be measured through the eighth switch unit 191, and the second end of the second cancellation capacitor
  • the thirteenth voltage or the fourteenth voltage is connected through the eighth switch unit 191.
  • the thirteenth voltage is lower than the ninth voltage connected to the second end of the second capacitor under test, and the fourteenth voltage is higher than the second voltage under test. Measure the ninth voltage connected to the second end of the capacitance.
  • the principle and structure of the second cancellation module 19 are the same as those of the first cancellation module 16, and will not be repeated here.
  • the capacitance detection circuit, detection chip, and electronic equipment of the embodiments of the present application suppress interference signals that are less than the first frequency or greater than the second frequency when the output voltage is generated by the conversion module 12 through the first suppression module 121, thereby reducing the interference signals The influence of this improves the sensitivity and accuracy of capacitance detection.
  • Example 2 Capacitance detection circuit when applied to self-capacitance detection ( Figure 15-17)
  • FIG. 15 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 includes: a first drive module 11, a first suppression module 121, and a conversion The module 12, the processing module 13, and the control module 14; the first driving module 11 is used to charge the first capacitance Cx to be measured; the conversion module 12 is used to perform charge conversion processing on the first capacitance to be measured to generate an output voltage, the control module 14 is used to control the first suppression module 121 to suppress interference signals less than the first frequency or greater than the second frequency when the conversion module 12 generates the output voltage, and the second frequency is greater than the first frequency; the processing module 13 is used to determine according to the output voltage The capacitance change before and after the first capacitance to be measured is affected by the external electric field.
  • the first driving module 11 charges the first capacitance to be measured
  • the conversion module 12 performs charge conversion processing on the first capacitance to be measured to generate an output voltage
  • the conversion module 12 performs charge transfer on the first capacitance to be measured.
  • the conversion process generates an output voltage.
  • the first suppression module 121 suppresses signals that are less than the first frequency or greater than the second frequency.
  • the first driving module 11 includes an excitation power supply 111Vtx, and the excitation power supply 111 is electrically connected to the first input terminal of the conversion module 12 through a first capacitor to be measured.
  • the excitation power supply 111 in the first driving module 11 charges the first capacitance to be measured, and the first capacitance to be measured transfers the charge to the conversion module 12.
  • the overall capacitance in the circuit becomes smaller, and the charge transferred from the first capacitance to be measured to the transfer module becomes less, and the output voltage of the transfer module decreases.
  • the driving frequency refers to the frequency of the excitation power source 111.
  • the first suppression module 121 suppresses electrical signals less than the first frequency mainly for interference signals generated by the power supply.
  • the interference signals generated by the power supply are within 50 Hz. Therefore, the first frequency can be 50 Hz.
  • the first cancellation capacitor used in the cancellation module is preferably a capacitor with a constant capacitance, and its capacitance does not change with changes in the external environment, such as being affected by pressure, temperature, or humidity.
  • the capacitance detection circuit 10 is a mutual capacitance detection circuit
  • the differential amplifier included in the conversion module 12 is a single-ended differential amplifier 122.
  • the first terminal of the first capacitor Cx to be tested is connected to the excitation power supply 111Vtx
  • the second terminal of the first capacitor Cx to be tested is connected to the inverting input terminal of the single-ended differential amplifier 122
  • the non-inverting input terminal of the single-ended differential amplifier 122 is connected to
  • the output terminal of the single-ended differential amplifier 122 (that is, the first output terminal of the single-ended differential amplifier 122) is connected to the processing module 13.
  • the first suppression module 121, a first switch K 1 of the first and second ends are respectively connected to the inverting input terminal and an output terminal of the single-terminal of the differential amplifier 122, a first capacitor 1212 through the third switch K 1 is a first ends respectively connected to the first switch and a first terminal of a first switch K 1 K 1 of the second terminal of the first capacitor 1212C r a second end, the ends of the second capacitor 1213C f are connected to single-ended differential The inverting input terminal and output terminal of the amplifier 122.
  • FIG. 17 is a structural diagram of a capacitance detection circuit provided by an embodiment of the application.
  • the capacitance detection circuit 10 is a mutual capacitance detection circuit
  • the differential amplifier included in the conversion module 12 is a double-ended Differential amplifier 123.
  • the first terminal of the first capacitor Cx to be tested is connected to the excitation power supply 111Vtx
  • the second terminal of the first capacitor Cx to be tested is connected to the inverting input terminal of the double-ended differential amplifier 123
  • the non-inverting input terminal of the double-ended differential amplifier 123 is connected to The common mode voltage Vcm
  • the first output terminal and the second output terminal of the double-ended differential amplifier 123 are connected to the processing module 13.
  • the first terminal and the second terminal of the first switch K 1 are respectively connected to the inverting input terminal and the first output terminal of the double-ended differential amplifier 123, and the first capacitor 1212 passes through the first switch K 1 the third terminal may be connected at a first terminal of a first switch and a first switch K 1 K 1 of the second terminal of the first capacitor 1212C r a second end, the ends of the second capacitor are respectively connected to 1213C f bis The inverting input terminal and the first output terminal of the terminal differential amplifier 123.
  • the first terminal and the second terminal of the second switch K 2 are respectively connected to the non-inverting input terminal and the second output terminal of the double-ended differential amplifier 123, and the two ends of the fourth capacitor 1243C f are respectively connected to a second switch K 2 a first end and a second end of the second switch K 2, the third capacitor 1242C r a first terminal and a third terminal electrically connected to the second switching unit 1241, the second and third capacitor 1242C r The terminal is grounded.
  • the capacitance values of the first capacitor 1212 and the third capacitor 1242 are the same as C r
  • the capacitance values of the second capacitor 1213 and the fourth capacitor 1243 are the same as C f .
  • the embodiment of the present application provides a detection chip, which includes the capacitance detection circuit 10 as described in any one of the first embodiment and the second embodiment.
  • the embodiment of the present application provides an electronic device including the detection chip as described in the third embodiment.
  • the capacitance detection circuit, detection chip, and electronic equipment of the embodiments of the present application suppress interference signals that are less than the first frequency or greater than the second frequency when the output voltage is generated by the conversion module through the first suppression module, thereby reducing the influence of the interference signal , Improve the sensitivity and accuracy of capacitance detection.
  • the electronic devices in the embodiments of this application exist in various forms, including but not limited to:
  • Mobile communication equipment This type of equipment is characterized by mobile communication functions, and its main goal is to provide voice and data communications.
  • Such terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones.
  • Ultra-mobile personal computer equipment This type of equipment belongs to the category of personal computers, has calculation and processing functions, and generally also has mobile Internet features.
  • Such terminals include: PDA, MID and UMPC devices, such as iPad.
  • Portable entertainment equipment This type of equipment can display and play multimedia content.
  • Such devices include: audio, video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.
  • Server A device that provides computing services.
  • the composition of a server includes a processor 810, hard disk, memory, system bus, etc.
  • the server is similar to a general computer architecture, but because it needs to provide highly reliable services, it has High requirements in terms of performance, reliability, security, scalability, and manageability.
  • a programmable logic device Programmable Logic Device, PLD
  • FPGA Field Programmable Gate Array
  • HDL Hardware Description Language
  • ABEL Advanced Boolean Expression Language
  • AHDL Altera Hardware Description Language
  • HDCal JHDL
  • Lava Lava
  • Lola MyHDL
  • PALASM RHDL
  • Verilog Verilog
  • the controller can be implemented in any suitable manner.
  • the controller can take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program codes (such as software or firmware) executable by the (micro)processor. , Logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers and embedded microcontrollers.
  • controllers include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicon Labs C8051F320, the memory controller can also be implemented as a part of the memory control logic.
  • controller in addition to implementing the controller in a purely computer-readable program code manner, it is entirely possible to program the method steps to make the controller use logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded The same function can be realized in the form of a microcontroller, etc. Therefore, such a controller can be regarded as a hardware component, and the devices included in it for implementing various functions can also be regarded as a structure within the hardware component. Or even, the device for realizing various functions can be regarded as both a software module for realizing the method and a structure within a hardware component.
  • a typical implementation device is a computer.
  • the computer may be, for example, a personal computer, a laptop computer, a cell phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or Any combination of these devices.
  • the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing functions specified in a flow or multiple flows in the flowchart and/or a block or multiple blocks in the block diagram.
  • the computing device includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.
  • processors CPU
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • the memory may include non-permanent memory in computer readable media, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.
  • RAM random access memory
  • ROM read-only memory
  • flash RAM flash memory
  • Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology.
  • the information can be computer-readable instructions, data structures, program modules, or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.
  • this application can be provided as methods, systems, or computer program products. Therefore, this application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • This application may be described in the general context of computer-executable instructions executed by a computer, such as a program module.
  • program modules include routines, programs, objects, components, data structures, etc. that perform specific transactions or implement specific abstract data types.
  • This application can also be practiced in distributed computing environments. In these distributed computing environments, remote processing devices connected through a communication network execute transactions.
  • program modules can be located in local and remote computer storage media including storage devices.

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Abstract

一种电容检测电路、检测芯片及电子设备，电容检测电路(10)包括：第一驱动模块(11)、转换模块(12)、处理模块(13)以及控制模块(14)；第一驱动模块(11)用于对第一待测电容进行充电；转换模块(12)用于对第一待测电容进行电荷转化处理以生成输出电压，转换模块(12)包括第一抑制模块(121)，控制模块(14)用于控制第一抑制模块(121)在转换模块(12)生成输出电压时对小于第一频率或者大于第二频率的干扰信号进行抑制，第二频率大于第一频率；处理模块(13)用于根据输出电压确定第一待测电容被外加电场影响前后的电容变化量。电容检测电路(10)对小于第一频率或者大于第二频率的干扰信号进行抑制，减少了干扰信号的影响，提高了电容检测的灵敏度和精确度。

Description

电容检测电路、检测芯片及电子设备 技术领域
本申请实施例涉及电容检测技术领域，尤其涉及电容检测电路、检测芯片及电子设备。
背景技术
电容检测技术广泛应用于电子设备上，能够实现人机交互功能，例如，电子设备上的电容触控屏，能够通过电容检测实现触控功能；又如，耳机上的电容检测模块，能够实现自动检测用户是否佩戴耳机。当然，此处只是示例性说明。对于自电容来说，电容检测过程中，当没有人体靠近或触摸时，检测电极和电路地之间存在自电容，当人体靠近或触摸检测电极时，检测电极和电路地之间的电容会变大，通过检测电容的变化量来确定用户的相关操作。
但是在一些应用场景中，由于在检测过程中一些干扰信号尤其低频干扰信号的存在，导致电容检测的灵敏度和精确度较低，不能准确判定用户的相关操作。
发明内容
有鉴于此，本申请实施例提供一种电容检测电路、检测芯片及电子设备，用以克服或者缓解现有技术中的技术缺陷。
第一方面，本申请实施例提供了一种电容检测电路，包括：第一驱动模块、转换模块、处理模块以及控制模块；第一驱动模块用于对第一待测电容进行充电；转换模块用于对第一待测电容进行电荷转化处理以生成输出电压，转换模块包括第一抑制模块，控制模块用于控制第一抑制模块转换模块生成输出电压时对小于第一频率或者大于第二频率的干扰信号进行抑制，第二频率大于第一频率；处理模块用于根据输出电压确定第一待测电容被外加电场影响前后的电容变化量。
第二方面，本申请实施例提供了一种检测芯片，其特征在于，包括如第一方面的任意一个实施例中所描述的电容检测电路。
第三方面，本申请实施例提供了一种电子设备，其特征在于，包括如第二方面所描述的检测芯片。
本申请实施例的电容检测电路、检测芯片及电子设备，通过第一抑制模块在转换模块生成输出电压时，对小于第一频率或者大于第二频率的干扰信号进行抑制，减少了干扰信号的影响，提高了电容检测的灵敏度和精确度。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为本申请实施例提供的一种电容检测电路的结构图；
图2为本申请实施例提供的一种电容检测电路的结构图；
图3为本申请实施例提供的一种电容检测电路的结构图；
图4为本申请实施例提供的一种幅频特性示意图；
图5为本申请实施例提供的一种电容检测电路的结构图；
图5a是本申请实施例提供的一种电容检测电路的结构图；
图5b是本申请实施例提供的一种电容检测电路的结构图；
图6为本申请实施例提供的一种电容检测电路的结构图；
图7为本申请实施例提供的一种电容检测电路的结构图；
图8为本申请实施例提供的一种电容检测电路的结构图；
图9为本申请实施例提供的一种电容检测电路的结构图；
图10为本申请实施例提供的一种电容检测电路的结构图；
图11为本申请实施例提供的一种控制时序图；
图12为本申请实施例提供的一种电容检测电路的结构图；
图13为本申请实施例提供的一种电容检测电路的结构图；
图14为本申请实施例提供的一种电容检测电路的结构图；
图15为本申请实施例提供的一种电容检测电路的结构图；
图16为本申请实施例提供的一种电容检测电路的结构图；
图17为本申请实施例提供的一种电容检测电路的结构图。
具体实施方式
实施本申请实施例的任一技术方案必不一定需要同时达到以上的所有优点。
为了使本领域的人员更好地理解本申请实施例中的技术方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请实施例一部分实施例，而不是全部的实施例。基于本申请实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本申请实施例保护的范围。
下面结合本申请实施例附图进一步说明本申请实施例具体实现。
本申请实施例提供的电容检测电路可应用到自容检测和互容检测，为此，以下实施例中首先对应用到自容检测的电容检测电路进行说明，再对互容检测时的电容检测电路连接进行说明。
实施例一、应用到自容检测时的电容检测电路情形(图1-图14)
如图1所示，图1为本申请实施例提供的一种电容检测电路的结构图，如图1所示，该电容检测电路10包括：第一驱动模块11、转换模块12、处理模块13以及控制模块14；第一驱动模块11用于对第一待测电容Cx进行充电；转换模块12用于对第一待测电容进行电荷转化处理以生成输出电压，转换模块12包括第一抑制模块121，控制模块14用于控制第一抑制模块121在转换模块12生成输出电压时对小于第一频率或者大于第二频率的干扰信号进行抑制，第二频率大于第一频率；处理模块13用于根据输出电压确定第一待测电容被外加电场影响前后的电容变化量。
电容检测电路10工作时，第一驱动模块11对第一待测电容充电，转换模块12对第一待测电容进行电荷转化处理生成输出电压，转换模块12对第一待测电容转移的电荷进行转化处理生成输出电压，此时，第一抑制模块121对小于第一频率或者大于第二频率的信号进行抑制。在有对象接近第一待测电容时，第一待测电容的电容大小发生变化，此时，第一待测电容向转移模块转移的电荷发生变化，转移模块输出的输出电压就会发生变化，以此可以检测出有对象接近第一待测电容。
图2为本申请实施例提供的一种电容检测电路的结构图，图2中，电容检测电路10还包括第三开关单元15，第三开关单元15连接在第一驱动模块11和转换模块12的第一输入端之间，第三开关单元15断开时，第一驱动模块11对第一待测电容进行充电，第三开关单元15闭合时，转换模块12对第一待测电容进行电荷转化处理生成输出电压。在自容检测电路中，第三开关单元15闭合时为电荷转移阶段，第三开关单元15可以是一个单刀单掷开关，当第三开关单元15连通第一待测电容和转换模块12时，为电荷转移阶段。图2中，以第三开关单元15控制第一待测电容和转换模块12连通或断开为例，通常情况下，第一驱动模块11也会配置一个开关，在充电阶段，连通第一驱动模块11和第一待测电容，此时，第三开关单元15断开；在电荷转移阶段，第一驱动模块11的开关断开，使得第一驱动模块11和第一待测电容断开，此时第三开关单元15闭合。当然，此处只是示例性说明，并不代表本申请局限于此。
可选地，在本申请的一个实施例中，转换模块12具有第一输入端和第二输入端，转换模块12的第一输入端与第一驱动模块11电连接，第二输入端接入共模电压和/或与可等效产生共模电压的其他电路连接。具体地，转换模块12可以包括一个差分放大器，差分放大器可以是单端差分放大器122或者双端差分放大器123，此处，列举两个具体的应用场景分别对转换模块12分别包括单端差分放大器122和双端差分放大器123的情形进行说明：
图3为本申请实施例提供的一种电容检测电路的结构图，可选地，在第一个应用场景中，以转化模块包括单端差分放大器122为例，转换模块12的第一输入端为单端差分放大器122的反相输入端，转换模块12的第二输入端为单端差分放大器122的正相输入端，第一驱动模块11与单端差分放大器122的反相输入端电连接，单端差分放大器122的正相输入端接入共模电压，单端差分放大器122的输出端与处理模块13电连接；第一抑制模块121的两端分别连接在单端差分放大器122的反相输入端和输出端。
如图3所示，以转换模块12包括单端差分放大器122为例进行说明。第一抑制模块121包括第一开关单元1211、第一电容1212和第二电容1213；第一开关单元1211的第一端和第二端分别连接在单端差分放大器122的反相输入端和输出端，第一电容1212通过第一开关单元1211的第三端可分别连接在第一开关单元1211的第一端和第一开关单元1211的第二端，第一电容1212的第二端接地，第二电容1213的两端分别连接在单端差分放大器122的反相输入端和输出端。
在进行电荷转移过程中，控制模块14用于控制第一开关单元1211在第一端和第二端之间来回切换，以使第一开关单元1211的第三端与第一端连通或者第三端与第二端连通，第一开关单元1211切换的频率大于两倍的驱动频率(即第一驱动模块11的驱动频率)，以对小于第一频率的电信号进行抑制。而在电荷转移完成之后，控制模块14控制第一开关单元1211在第一端和第二端之间来回切换，以使第一开关单元1211的第三端与第一端连通或者第三端与第二端连通，对第二电容1213进行复位处理。此处，需要说明的是，在自容电路中，驱动频率(即第一驱动模块11的驱动频率)指得是第三开关单元15连通和断开的切换频率。第一抑制模块121对小于第一频率的电信号进行抑制主要是针对电源产生的干扰信号，通常，电源产生的干扰信号在50Hz以内，因此，第一频率可以为50Hz，当然，此处只是示例性说明。
第一开关单元1211可以包括一个单刀双掷开关，在第一端和第二端来回切换，以 使第一开关单元1211的第三端与第一端连通或者第三端与第二端连通，或者，第一开关单元1211可以包括两个单刀单掷开关，一个单刀单掷开关闭合，另外一个单刀单掷开关断开，即两个单刀单掷开关交替闭合断开从而起到一个单刀双掷开关的功能。当然，此处只是示例性说明，并不代表本申请局限于此。
第一开关单元1211在第一端和第二端来回切换，和第一电容1212可以组成一个具有电阻特性的电路，其等效电阻R＝1/(F×Cr)，其中F为第一开关单元1211的切换频率，Cr为第一电容1212的电容值。第二电容1213和第一开关单元1211以及第一电容1212相结合的方式，为电容检测电路10增加了一个零点F 0，而该零点可以直接做为第一频率，如图4所示，图4为本申请实施例提供的一种幅频特性示意图，零点之前的信号随着频率降低增益降低，零点之后的幅频响应是平坦的，零点之前的信号随着频率降低增益降低，又因为差分放大器(单端差分放大器122或双端差分放大器123)具有主极点Fc，而该主极点可以直接作为第二频率，主极点之后频率越高，增益随之降低，从而使得电容检测电路10的工作频段在F 0和Fc之间，也就是对小于第一频率和大于第二频率的干扰信号进行抑制。
可选地，为了提高电容检测电路10的灵敏度，可以提高电容检测电路10的增益，例如，减小第二电容1213的电容值C f，C f的值越小容抗越大，增益越高；或者，减小第一电容1212的电容值Cr，根据R＝1/(F×Cr)，Cr的值越小，等效阻抗越高，增益越高；或者，减小第一开关单元1211的切换频率，第一开关单元1211的切换频率越低，等效阻抗越大，增益越高，当然，还需要满足第一开关单元1211的切换频率大于2倍的电源频率这个关系。
图5为本申请实施例提供的一种电容检测电路的结构图，结合图2所示的电容检测电路10，图5中，第一驱动模块11包括第四开关单元112，控制模块14进一步用于控制第四开关单元112处于第一闭合状态以使第一驱动模块11对第一待测电容进行充电；具体地，由于第四开关单元112处于第一闭合状态时，第一待测电容的第一端通过第四开关单元112接入第一电压(Vcc)，第一待测电容的第二端接入第二电压(如gnd)，第一电压大于第二电压，从而实现对第一待测电容进行充电。
图5a为本申请实施例提供的一种电容检测电路的结构图，图5a中，第四开关单元112包括一个第四开关K 4，第四开关K 4为单刀单掷开关，第四开关K 4的一端接入第一电压(Vcc)，第四开关K 4的另一端连接第一待测电容。在第四开关K 4闭合时，第四开关单元112处于第一闭合状态，此时第一待测电容的两端分别接入第一电压(Vcc)和第二电压(如gnd)，实现对第一待测电容充电。
可选地，控制模块14进一步用于控制第四开关单元112处于第二闭合状态以使第一待测电容放电；具体地，由于第四开关单元112处于第二闭合状态时，第一待测电容的第一端通过第四开关单元112接入第三电压(Vss)，第一待测电容的第二端接入第二电压，第二电压大于第三电压，从而使第一待测电容放电。在第四开关单元112有两种闭合状态时，能够抵消相关性高的噪声，主要是电路中的低频噪声，从而显著提高信噪比。
第四开关单元112可以包括一个单刀双掷开关，通过连接两个连接端实现两种闭合状态，或者，第四开关单元112可以包括两个单刀单掷开关，第一个单刀单掷开关闭合，第二个单刀单掷开关断开为第一闭合状态，第一个单刀单掷开关断开，第二个单刀单掷 开关闭合为第二闭合状态。当然，此处只是示例性说明，并不代表本申请局限于此。
图5b是本申请实施例提供的一种电容检测电路的结构图，图5b中，第四开关单元112包括一个第五开关K 51，第五开关K 51是单刀双掷开关，第五开关K 51的第一端接入第一电压，第五开关K 51的第二端接入第三电压，第五开关K 51的第三端与第一待测电容连接，在第五开关K 51的第一端和第三端连通时，第四开关单元112处于第一闭合状态，第一待测电容的两端分别接入第一电压(Vcc)和第二电压(如gnd)，实现对第一待测电容充电；在第五开关K 51的第二端和第三端连通时，第四开关单元112处于第二闭合状态，第一待测电容的两端分别接入第二电压(如gnd)和第三电压(Vss)，实现对第一待测电容放电。
此处，结合上述图3和图5所示的电容检测电路，对第一个应用场景进行详细说明，参照图6所示，的电容检测电路对电路结构进行详细说明，图6为本申请实施例提供的一种电容检测电路的结构图。图6中，第一开关单元1211可以包括第一开关K 1；第三开关单元15为K 3；第四开关单元112可以包括一个第四开关K 4，还可以包括一个第五开关K 51。
如图6所示，电容检测电路10为自容检测电路，转换模块12包含的差分放大器为单端差分放大器122。第一驱动模块11包括第四开关K 4和第五开关K 51，第四开关K 4的第一端与第一待测电容Cx的第一端电连接，第一待测电容Cx的第二端接地(接地电压为第二电压)，第四开关K 4的第二端与第五开关的第三端电连接，第五开关K 51的第一端接入第一电压Vcc，第五开关K 51的第二端接入第三电压Vss；其中，第四开关K 4闭合且第五开关K 51的第一端和第三端连接，第一待测电容接入第一电压Vcc，此时，第四开关单元112为第一闭合状态；第四开关K 4闭合且第五开关K 51的第二端和第三端连接，第一待测电容接入第三电压Vss，此时，第四开关单元112为第二闭合状态。第三开关单元15K 3的两端分别与第一待测电容的第一端和单端差分放大器122的反相输入端电连接。单端差分放大器122的正相输入端接入共模电压Vcm，单端差分放大器122的输出端(即单端差分放大器122的第一输出端)连接处理模块13。第一抑制模块121中，第一抑制模块121中，第一开关K 1的第一端和第二端分别连接在单端差分放大器122的反相输入端和输出端，第一电容1212通过第一开关K 1的第三端可分别连接在第一开关K 1的第一端和第一开关K 1的第二端，第一电容1212C r的第二端接地，第二电容1213C f的两端分别连接在单端差分放大器122的反相输入端和输出端。
可选地，在第二个应用场景中，以转换模块12包括双端差分放大器123为例，双端差分放大器123具有正相输入端、反相输入端、第一输出端和第二输出端，转换模块12的第一输入端为双端差分放大器123的反相输入端，转换模块12的第二输入端为双端差分放大器123的正相输入端，第一驱动模块11与双端差分放大器123的反相输入端电连接，双端差分放大器123的正相输入端接入共模电压，双端差分放大器123的第一输出端和第二输出端均与处理模块13电连接；第一抑制模块121的两端分别连接在双端差分放大器123的反相输入端和第一输出端。
在一个示例中,双端差分放大器123的输入端和输出端可以只连接一个第一抑制模块121，此时，双端差分放大器123相当于一个单端差分放大器122，双端差分放大器123的输入端和输出端同时配置第一抑制模块122和第二抑制模块124，此时，检测电路的动态范围较大，且可以实现较大的增益，从而提高检测的灵敏度。
图7为本申请实施例提供的一种电容检测电路的结构图，如图7所示，转换模块12分别包括双端差分放大器123为例进行说明。转换模块12还包括第二抑制模块124，第二抑制模块124的两端分别连接在双端差分放大器123的正相输入端和第二输出端，控制模块14用于控制第二抑制模块124在转换模块12生成输出电压时对小于第一频率或者大于第二频率的干扰信号进行抑制，第二频率大于第一频率。
可选地，如图7所示，在本申请的一个实施例中，第二抑制模块124包括第二开关单元1241、第三电容1242和第四电容1243；第二开关单元1241的第一端和第二端分别连接在双端差分放大器123的正相输入端和第二输出端，第四电容1243的两端分别连接在第二开关单元1241的第一端和第二开关单元1241的第二端，第三电容1242的第一端与第二开关单元1241的第三端电连接，第三电容1242的第二端接地；控制模块14用于控制第二开关单元1241在第一端和第二端之间来回切换，以使第二开关的第三端与第一端连通或者第三端与第二端连通，第二开关单元1241切换的频率大于两倍的驱动频率，以对小于第一频率的电信号进行抑制。第二抑制模块124与第一抑制模块121的原理相同，此处不再赘述。但是，需要说明的是，在其他应用场景中，第二抑制模块124与第一抑制模块121的具体结构可以不同。可选地，在本申请的一个实施例中，在自容检测电路中驱动频率为第二驱动模块内开关连通或断开的切换频率，或者，在互容检测电路中驱动频率为第二驱动模块的电源频率。
第二开关单元1241可以包括一个单刀双掷开关，在第一端和第二端来回切换，以使二开关单元的第三端与第一端连通或者第三端与第二端连通，或者，第二开关单元1241可以包括两个单刀单掷开关，一个单刀单掷开关闭合，一个单刀单掷开关断开，交替闭合断开从而起到一个单刀双掷开关的功能。当然，此处只是示例性说明，并不代表本申请局限于此。
图8为本申请实施例提供的一种电容检测电路的结构图，此处，结合上述图7所示的电容检测电路，对第二个应用场景进行详细说明，参照图8所示，的电容检测电路对电路结构进行详细说明。图8中，第一开关单元1211可以包括第一开关K 1；第二开关单元1241可以包括第二开关K 2；第三开关单元15为K 3；第四开关单元112可以包括一个第四开关K 4，还可以包括一个第五开关K 51。
图8中，电容检测电路10为自容检测电路，转换模块12包含的差分放大器为双端差分放大器123。本实施例中所提供的电容检测电路10，第一驱动模块11和第一抑制模块121与实施例四中的相同，此处不再赘述，本实施例中的转换模块12还包括第二抑制模块124，第二抑制模块124中，第二开关K 2的第一端和第二端分别连接在双端差分放大器123的正相输入端和第二输出端，第四电容1243C f的两端分别连接在第二开关K 2的第一端和第二开关K 2的第二端，第三电容1242C r的第一端与第二开关单元1241的第三端电连接，第三电容1242C r的第二端接地。本实施例中，第一电容1212和第三电容1242的电容值同为C r，第二电容1213和第四电容1243的电容值同为C f。
需要说明的是，图6和图8所示的电容检测电路10，适用于第一待测电容Cx的自电容较小的情况下，因为自电容较小，对检测影响较小。
图9为本申请实施例提供的一种电容检测电路的结构图，可选地，在本申请的一个实施例中，如图9所示，电容检测电路10还包括第一抵消模块16；控制模块14还用于控制第一抵消模块16对第一抵消电容进行充电，以及控制第一抵消电容对第一待测电容 进行充电或放电实现电荷抵消。
可选地，在本申请的一个实施例中，如图9所示，第一抵消模块16包括第五开关单元161，控制模块14进一步用于控制第五开关单元161处于第一闭合状态并形成充电支路以使抵消模块对第一抵消电容进行充电；控制模块14还用于控制第五开关单元161处于第二闭合状态形成抵消支路以使第一抵消电容Cc对第一待测电容进行充电或放电实现电荷抵消。
第五开关单元161可以包括两个单刀双掷开关，通过两个单刀双掷开关的切换实现三种闭合状态，当然，此处只是示例性说明，并不代表本申请局限于此。
可选地，在本申请的一个实施例中，第五开关单元161处于第一闭合状态时，第一抵消电容的两端分别接入第四电压和第五电压，第五电压高于第四电压。此时，实现对第一抵消电容充电。
可选地，在本申请的一个实施例中，第五开关单元161处于第二闭合状态时，第一抵消电容的第一端通过第五开关单元161与第一待测电容的第一端电连接，第一抵消电容的第二端通过第五开关单元161接入第六电压或第七电压，第六电压低于待测电容的第二端接入的第二电压，此时，对第一待测电容放电实现电荷抵消，第七电压高于待测电容的第二端接入的第二电压，此时，对第一待测电容充电实现电荷抵消。
需要说明的是，在第一抵消电容对待测电容放电实现电荷抵消时，第一待测电容上的电荷向第一抵消电容转移，在第一抵消电容对待测电容充电实现电荷抵消时，第一抵消电容上的电荷向第一待测电容转移，抵消过程中的电荷转移，是要消除第一待测电容基础电容量的存在而导致的影响，与电荷转移阶段的电荷转移不同。
基于图3所示的自容检测的电容检测电路10，结合图5所示的电容检测电路10中所示出的第一驱动模块11的结构，以及图9所示的电容检测电路10中所示出的第一抵消模块16的结构，对电容检测电路10的工作时序进行说明。根据第一待测电容接入第一电压或第二电压，将电容检测电路10分为正过程和负过程：
对于正过程，在第一阶段，第三开关单元15断开，第四开关单元112处于第一闭合状态，第一待测电容接入第一电压，第一驱动模块11对第一待测电容充电至第一电压，第五开关单元161处于第一闭合状态，第一抵消电容两端分别接入第四电压和第五电压形成充电支路，第一抵消电容被充电至第五电压；在第二阶段，第三开关单元15依旧断开，第四开关单元112断开，第五开关单元161处于第二闭合状态，此时，第一抵消电容对第一待测电容进行放电实现电荷抵消，第一待测电容的部分电荷向第一抵消电容转移；第三阶段，第三开关单元15闭合，第一待测电容和转换模块12连通，第四开关单元112断开，第五开关单元161处于第二闭合状态，转换模块12对第一待测电容进行电荷转化处理生成输出电压，处理模块13根据转移模块的输出电压确定第一待测电容的电容变化量。
对于负过程，在第一阶段，第三开关单元15断开，第四开关单元112处于第二闭合状态，第一待测电容放电至第三电压，第五开关单元161处于第一闭合状态，第一抵消电容两端分别接入第四电压和第五电压形成充电支路，第一抵消电容被充电至第五电压；在第二阶段，第三开关单元15依旧断开，第四开关单元112断开，第五开关单元161处于第二闭合状态，此时，第一抵消电容对第一待测电容进行充电实现电荷抵消，第一抵消电容的部分电荷向第一待测电容转移，第一待测电容被充电至第七电压；第三阶段， 第三开关单元15闭合，第一待测电容和转换模块12连通，第四开关单元112断开，第五开关单元161处于第三闭合状态，转换模块12对第一待测电容进行电荷转化处理生成输出电压，处理模块13根据转移模块的输出电压确定第一待测电容的电容变化量。
结合正过程和负过程，第一抵消电容可以将第一待测电容放电或充电到共模电压Vcm；如果没有手指靠近，第一待测电容的电容值Cx不会发生变化，在第三阶段，转换模块12的输出不会发生变化(为零)；若有对象靠近第一待测电容时，Cx会发生变化，记为Cx+△C，其中△C为对象靠近第一待测电容造成的电容改变量，由于第一待测电容变大，在第三阶段检测过程中，转换模块12的输出会发生变化(不为零)。
图10为本申请实施例提供的一种电容检测电路的结构图，在本实施例中，电容检测电路10为自容检测电路，转换模块12包含的差分放大器为单端差分放大器122。图10中，第一开关单元1211可以包括第一开关K 1；第二开关单元1241可以包括第二开关K 2；第三开关单元15为K 3；第四开关单元112可以包括一个第四开关K 4，还可以包括一个第五开关K 51；第五开关单元161可以包括三个第五开关K 52，K 53和K 54，还可以包括两个第六开关K 61和K 62；第七开关单元171可以包括一个第七开关K 7，还可以包括一个第八开关K 81。
图10中的电容检测电路包括第一驱动模块11、转换模块12、第一抑制模块121和第一抵消模块16。其中，第一驱动模块11、转换模块12和第一抑制模块121与实施例四中的相同，第一抵消模块16中，第五开关单元161包括三个第五开关K 52，K 53和K 54，以及两个第六开关K 61和K 62；本实施例中，第四电压和第六电压同为Vss，第五电压和第七电压同为Vcc。第五开关K 52通过在第一端和第二端切换可以将第一端和第三端连通或者将第二端和第三端连通，第五开关K 52的第一端接入Vss，第五开关K 52的第二端接入Vcc，第五开关K 52的第三端连接第六开关K 61的第一端，第六开关K 61的第二端连接第一待测电容Cx的第一端，第六开关K 61的第三端和第一抵消电容Cc的第一端电连接，第六开关K 61通过在第一端和第二端切换可以将第一端和第三端连通或者将第二端和第三端连通，第一抵消电容Cc的第二端与第六开关K 62的第三端电连接，第六开关K 62通过在第一端和第二端切换可以将第一端和第三端连通或者将第二端和第三端连通，第六开关K 62的第一端和第五开关K 53的第三端电连接，第六开关K 62的第一端和第五开关K 54的第三端电连接。第五开关K 53通过在第一端和第二端切换可以将第一端和第三端连通或者将第二端和第三端连通，第五开关K 54通过在第一端和第二端切换可以将第一端和第三端连通或者将第二端和第三端连通，第五开关K 53的第一端接入Vcc，第五开关K 53的第二端接入Vss，第五开关K 54的第一端接入Vss，第五开关K 54的第二端接入Vss。
需要说明的是，第五开关(K 52，K 53和K 54)都切换到第一端，将各自的第一端和第三端连通，第六开关(K 61和K 62)都切换到第一端，将各自的第一端和第三端连通，此时，第五开关单元161处于第一闭合状态；第五开关(K 52，K 53和K 54)都切换到第一端，将各自的第一端和第三端连通，第六开关(K 61和K 62)都切换到第二端，将各自的第二端和第三端连通，此时，第五开关单元161处于第二闭合状态；第五开关(K 52，K 53和K 54)都切换到第二端，将各自的第一端和第三端连通，第六开关(K 61和K 62)都切换到第一端，将各自的第一端和第三端连通，此时，第五开关单元161处于第一闭合状态；第五开关(K 52，K 53和K 54)都切换到第二端，将各自的第一端和第三端连通，第六开关(K 61和K 62)都切换到第二端，将各自的第二端和第三端连通，此时，第五开关单元161 处于第二闭合状态。
结合图11，图11为本申请实施例提供的一种控制时序图，根据第一待测电容接入Vcc或Vss，将电容检测电路10分为正过程和负过程：
对于正过程，对应图11中的T 1时段，正过程中所有的第五开关(K 51，K 52，K 53和K 54)都切换到第一端，将各自的第一端和第三端连通，第一开关K 1和第二开关K 2周期性连通断开，对于第一阶段(图11中的t 1时段)，即充电阶段，第三开关单元15K 3断开，第四开关K 4处于闭合状态，此时，第一待测电容Cx被充电至Vcc，第六开关(K 61和K 62)都切换到第一端，将各自的第一端和第三端连通，第一抵消电容Cc被充电；对于第二阶段(图11中的t 2时段)，即抵消阶段，第三开关单元15K 3断开，第四开关K 4处于断开状态，第六开关(K 61和K 62)都切换到第二端，将各自的第二端和第三端连通，此时，第一抵消电容Cc对第一待测电容Cx进行放电实现电荷抵消；对于第三阶段(图11中的t 3时段)，即电荷转移阶段，第三开关单元15K 3连通，第四开关K 4处于断开状态，第六开关(K 61和K 62)都切换到第二端，将各自的第二端和第三端连通，此时，转换模块12对第一待测电容Cx进行电荷转化处理生成输出电压。
对于负过程，对应图11中的T 2时段，负过程中所有的第五开关(K 51，K 52，K 53和K 54)都切换到第二端，将各自的第二端和第三端连通，第一开关K 1和第二开关K 2周期性连通断开，对于第一阶段(图11中的t 4时段)，即放电阶段，第三开关单元15K 3断开，第四开关K 4处于闭合状态，此时，第一待测电容Cx放电至Vss，第六开关(K 61和K 62)都切换到第一端，将各自的第一端和第三端连通，第一抵消电容Cc被充电；对于第二阶段(图11中的t 5时段)，即充电阶段，第三开关单元15K 3断开，第四开关K 4处于断开状态，第六开关(K 61和K 62)都切换到第二端，将各自的第二端和第三端连通，此时，第一抵消电容Cc对第一待测电容Cx进行充电实现电荷抵消；对于第三阶段(图11中的t 6时段)，即电荷转移阶段，第三开关单元15K 3连通，第四开关K 4处于断开状态，第六开关(K 61和K 62)都切换到第二端，将各自的第二端和第三端连通，此时，转换模块12对第一待测电容Cx进行电荷转化处理生成输出电压。
需要说明的是，第一开关单元1211切换的频率大于两倍的电源频率，以实现对小于第一频率或大于第二频率的信号进行抑制。在实施例六中，电容检测电路为自容电路，电源频指的是第三开关单元15连通和断开的切换频率，第三开关16单元连通或断开由第四开关K 4控制，第一开关单元1211为第一开关K 1，因此，在本实施例中，第一开关单元1211切换的频率大于两倍的电源频率指的是第一开关K 1在第一端和第二端之间切换的频率大于两倍的第四开关K 4的连通和断开的切换频率。
图12为本申请实施例提供的一种电容检测电路的结构图，差分放大器为双端差分放大器时，如图12所示，电容检测电路10为自容检测电路，转换模块12包含的差分放大器为双端差分放大器123。本实施例中的电容检测电路10包括第一驱动模块11、转换模块12、第一抑制模块121、第一抵消模块16和第二抑制模块124。其中，第一驱动模块11、转换模块12、第一抑制模块121和第一抵消模块16与实施例六中的相同，此处不再赘述，第二抑制模块124中，第二开关K 2的第一端和第二端分别连接在双端差分放大器123的正相输入端和第二输出端，第四电容1243C f的两端分别连接在第二开关K 2的第一端和第二开关K 2的第二端，第三电容1242C r的第一端与第二开关单元1241的第三端电连接，第三电容1242C r的第二端接地。本实施例中，第一电容1212和第三电容 1242的电容值同为C r，第二电容1213和第四电容1243的电容值同为C f。
实施例六和实施例七所描述的电容检测电路10适用于第一待测电容的自电容较大的情况，因为第一待测电容的自电容较大，因此，对电容检测影响较大，通过第一抵消模块16，将第一待测电容的自电容抵消掉，就可以更加准确地检测到对象接近时第一待测电容的变化量ΔC。
图13为本申请实施例提供的一种电容检测电路的结构图，可选地，在本申请的一个实施例中，如图13所示，电容检测电路10还包括第二驱动模块17，第二驱动模块17与转换模块12的第二输入端电连接，控制模块14还用于通过控制第二驱动模块17对第二待测电容进行充电；转换模块12用于对第二待测电容进行电荷转化处理以生成输出电压。
可选地，在本申请的一个实施例中，如图13所示，电容检测电路10还包括第六开关单元18，第六开关单元18连接在第二驱动模块17和转换模块12的第二输入端之间，第六开关单元18闭合时，转换模块12对第二待测电容进行电荷转化处理生成输出电压。
可选地，如图13所示，第二驱动模块17包括第七开关单元171，控制模块14进一步用于控制第七开关单元171处于第一闭合状态以使第二驱动模块17对第二待测电容进行充电；第七开关单元171处于第一闭合状态时，第二待测电容的第一端通过第七开关单元171接入第八电压，第二待测电容的第二端接入第九电压，第八电压大于第九电压。
可选地，控制模块14进一步用于控制第七开关单元171处于第二闭合状态以使第二待测电容放电；第七开关单元171处于第二闭合状态时，第二待测电容的第一端通过第七开关单元171接入第十电压，第二待测电容的第二端接入第九电压，第九电压大于第十电压。第二驱动模块17的原理和结构于第一驱动模块11相同，此处不再赘述。
图14为本申请实施例提供的一种电容检测电路的结构图，可选地，在本申请的一个实施例中，如图14所示，电容检测电路10还包括第二抵消模块19；控制模块14还用于控制第二抵消模块19对第二抵消电容进行充电，控制第二抵消电容对第二待测电容进行充电或放电实现电荷抵消。
可选地，如图14所示，第二抵消模块19包括第八开关单元191，控制模块14进一步用于控制第八开关单元191处于第一闭合状态并形成充电支路以使抵消模块对第二抵消电容进行充电；控制模块14还用于控制第八开关单元191处于第二闭合状态形成抵消支路以使第二抵消电容对第二待测电容进行充电或放电实现电荷抵消。
可选地，第八开关单元191处于第一闭合状态时，第二抵消电容的两端分别接入第十一电压和第十二电压，第十二电压高于第十一电压。
可选地，第八开关单元191处于第二闭合状态时，第二抵消电容的第一端通过第八开关单元191与第二待测电容的第一端电连接，第二抵消电容的第二端通过第八开关单元191接入第十三电压或第十四电压，第十三电压低于第二待测电容的第二端接入的第九电压，第十四电压高于第二待测电容的第二端接入的第九电压。第二抵消模块19的原理和结构与第一抵消模块16相同，此处不再赘述。
本申请实施例的电容检测电路、检测芯片及电子设备，通过第一抑制模块121在转换模块12生成输出电压时，对小于第一频率或者大于第二频率的干扰信号进行抑制，减少了干扰信号的影响，提高了电容检测的灵敏度和精确度。
实施例二、应用到自容检测时的电容检测电路情形(图15-图17)
如图15所示，图15为本申请实施例提供的一种电容检测电路的结构图，如图15所示，该电容检测电路10包括：第一驱动模块11、第一抑制模块121、转换模块12、处理模块13以及控制模块14；第一驱动模块11用于对第一待测电容Cx进行充电；转换模块12用于对第一待测电容进行电荷转化处理以生成输出电压，控制模块14用于控制第一抑制模块121在转换模块12生成输出电压时对小于第一频率或者大于第二频率的干扰信号进行抑制，第二频率大于第一频率；处理模块13用于根据输出电压确定第一待测电容被外加电场影响前后的电容变化量。
电容检测电路10工作时，第一驱动模块11对第一待测电容充电，转换模块12对第一待测电容进行电荷转化处理生成输出电压，转换模块12对第一待测电容转移的电荷进行转化处理生成输出电压，此时，第一抑制模块121对小于第一频率或者大于第二频率的信号进行抑制。在有对象接近第一待测电容时，第一待测电容的电容大小发生变化，此时，第一待测电容向转移模块转移的电荷发生变化，转移模块输出的输出电压就会发生变化，以此可以检测出有对象接近第一待测电容。
如图15所示，第一驱动模块11包括激励电源111Vtx，激励电源111通过第一待测电容与转换模块12的第一输入端电连接。在互容检测电路中，第一驱动模块11中的激励电源111向第一待测电容充电，第一待测电容向转换模块12转移电荷，在有可产生外加电场的对象接近第一待测电容时，电路中的整体电容变小，第一待测电容向转移模块转移的电荷变少，转移模块的输出电压就会减小。
此处，需要说明的是，在互容电路中，驱动频率指的是激励电源111的频率。第一抑制模块121对小于第一频率的电信号进行抑制主要是针对电源产生的干扰信号，通常，电源产生的干扰信号在50Hz以内，因此，第一频率可以为50Hz，当然，此处只是示例性说明。
在上述涉及到抵消处理的实施例中，尤其适用于自电容检测时，由于自电容具有较大的基础电容量而导致在有外加电场影响时检测到自电容变化较小的情形，通过上述抵消处理，即可消除自电容的基础电容量的影响，使得转换模块的输出尽可能反映由于外加电场而导致的电容量变化，从而进一步提高检测的灵敏度和精确度。上述实施例中，抵消模块中使用的第一抵消电容优选具有恒定电容量的电容，其电容量不随外界环境的变化而变化，比如受压、温度或者湿度等影响。
图16为本申请实施例提供的一种电容检测电路的结构图，如图16所示，电容检测电路10为互容检测电路，转换模块12包含的差分放大器为单端差分放大器122。第一待测电容Cx的第一端接入激励电源111Vtx，第一待测电容Cx的第二端连接单端差分放大器122的反相输入端，单端差分放大器122的正相输入端接入共模电压Vcm，单端差分放大器122的输出端(即单端差分放大器122的第一输出端)连接处理模块13。第一抑制模块121中，第一开关K 1的第一端和第二端分别连接在单端差分放大器122的反相输入端和输出端，第一电容1212通过第一开关K 1的第三端可分别连接在第一开关K 1的第一端和第一开关K 1的第二端，第一电容1212C r的第二端接地，第二电容1213C f的两端分别连接在单端差分放大器122的反相输入端和输出端。
图17为本申请实施例提供的一种电容检测电路的结构图，如图17所示，在本实施例中，电容检测电路10为互容检测电路，转换模块12包含的差分放大器为双端差分放 大器123。第一待测电容Cx的第一端接入激励电源111Vtx，第一待测电容Cx的第二端连接双端差分放大器123的反相输入端，双端差分放大器123的正相输入端接入共模电压Vcm，双端差分放大器123的第一输出端和第二输出端连接处理模块13。第一抑制模块121中，第一开关K 1的第一端和第二端分别连接在双端差分放大器123的反相输入端和第一输出端，第一电容1212通过第一开关K 1的第三端可分别连接在第一开关K 1的第一端和第一开关K 1的第二端，第一电容1212C r的第二端接地，第二电容1213C f的两端分别连接在双端差分放大器123的反相输入端和第一输出端。第二抑制模块124中，第二开关K 2的第一端和第二端分别连接在双端差分放大器123的正相输入端和第二输出端，第四电容1243C f的两端分别连接在第二开关K 2的第一端和第二开关K 2的第二端，第三电容1242C r的第一端与第二开关单元1241的第三端电连接，第三电容1242C r的第二端接地。本实施例中，第一电容1212和第三电容1242的电容值同为C r，第二电容1213和第四电容1243的电容值同为C f。
实施例三、
本申请实施例提供了一种检测芯片，包括如实施例一和实施例二中任意一个实施例中所描述的电容检测电路10。
实施例四、
本申请实施例提供了一种电子设备，包括如实施例三中所描述的检测芯片。
本申请实施例的电容检测电路、检测芯片及电子设备，通过第一抑制模块在转换模块生成输出电压时，对小于第一频率或者大于第二频率的干扰信号进行抑制，减少了干扰信号的影响，提高了电容检测的灵敏度和精确度。
上述产品可执行本申请实施例所提供的方法，具备执行方法相应的功能模块和有益效果。未在本实施例中详尽描述的技术细节，可参见本申请实施例所提供的方法。
本申请实施例的电子设备以多种形式存在，包括但不限于:
(1)移动通信设备:这类设备的特点是具备移动通信功能，并且以提供话音、数据通信为主要目标。这类终端包括:智能手机(例如iPhone)、多媒体手机、功能性手机，以及低端手机等。
(2)超移动个人计算机设备:这类设备属于个人计算机的范畴，有计算和处理功能，一般也具备移动上网特性。这类终端包括:PDA、MID和UMPC设备等，例如iPad。
(3)便携式娱乐设备:这类设备可以显示和播放多媒体内容。该类设备包括:音频、视频播放器(例如iPod)，掌上游戏机，电子书，以及智能玩具和便携式车载导航设备。
(4)服务器:提供计算服务的设备，服务器的构成包括处理器810、硬盘、内存、系统总线等，服务器和通用的计算机架构类似，但是由于需要提供高可靠的服务，因此在处理能力、稳定性、可靠性、安全性、可扩展性、可管理性等方面要求较高。
(5)其他具有数据交互功能的电子装置。
至此，已经对本主题的特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下，在权利要求书中记载的动作可以按照不同的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序，以实现期望的结果。在某些实施方式中，多任务处理和并行处理可以是有利的。
在20世纪90年代，对于一个技术的改进可以很明显地区分是硬件上的改进(例如，对二极管、晶体管、开关等电路结构的改进)还是软件上的改进(对于方法流程的改进)。 然而，随着技术的发展，当今的很多方法流程的改进已经可以视为硬件电路结构的直接改进。设计人员几乎都通过将改进的方法流程编程到硬件电路中来得到相应的硬件电路结构。因此，不能说一个方法流程的改进就不能用硬件实体模块来实现。例如，可编程逻辑器件(Programmable Logic Device,PLD)(例如现场可编程门阵列(Field Programmable Gate Array，FPGA))就是这样一种集成电路，其逻辑功能由用户对器件编程来确定。由设计人员自行编程来把一个数字系统“集成”在一片PLD上，而不需要请芯片制造厂商来设计和制作专用的集成电路芯片。而且，如今，取代手工地制作集成电路芯片，这种编程也多半改用“逻辑编译器(logic compiler)”软件来实现，它与程序开发撰写时所用的软件编译器相类似，而要编译之前的原始代码也得用特定的编程语言来撰写，此称之为硬件描述语言(Hardware Description Language，HDL)，而HDL也并非仅有一种，而是有许多种，如ABEL(Advanced Boolean Expression Language)、AHDL(Altera Hardware Description Language)、Confluence、CUPL(Cornell University Programming Language)、HDCal、JHDL(Java Hardware Description Language)、Lava、Lola、MyHDL、PALASM、RHDL(Ruby Hardware Description Language)等，目前最普遍使用的是VHDL(Very-High-Speed Integrated Circuit Hardware Description Language)与Verilog。本领域技术人员也应该清楚，只需要将方法流程用上述几种硬件描述语言稍作逻辑编程并编程到集成电路中，就可以很容易得到实现该逻辑方法流程的硬件电路。
控制器可以按任何适当的方式实现，例如，控制器可以采取例如微处理器或处理器以及存储可由该(微)处理器执行的计算机可读程序代码(例如软件或固件)的计算机可读介质、逻辑门、开关、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑控制器和嵌入微控制器的形式，控制器的例子包括但不限于以下微控制器：ARC 625D、Atmel AT91SAM、Microchip PIC18F26K20以及Silicone Labs C8051F320，存储器控制器还可以被实现为存储器的控制逻辑的一部分。本领域技术人员也知道，除了以纯计算机可读程序代码方式实现控制器以外，完全可以通过将方法步骤进行逻辑编程来使得控制器以逻辑门、开关、专用集成电路、可编程逻辑控制器和嵌入微控制器等的形式来实现相同功能。因此这种控制器可以被认为是一种硬件部件，而对其内包括的用于实现各种功能的装置也可以视为硬件部件内的结构。或者甚至，可以将用于实现各种功能的装置视为既可以是实现方法的软件模块又可以是硬件部件内的结构。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机。具体的，计算机例如可以为个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任何设备的组合。
为了描述的方便，描述以上装置时以功能分为各种单元分别描述。当然，在实施本申请时可以把各单元的功能在同一个或多个软件和/或硬件中实现。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在一个典型的配置中，计算设备包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本领域技术人员应明白，本申请的实施例可提供为方法、系统或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请可以在由计算机执行的计算机可执行指令的一般上下文中描述，例如程序模 块。一般地，程序模块包括执行特定事务或实现特定抽象数据类型的例程、程序、对象、组件、数据结构等等。也可以在分布式计算环境中实践本申请，在这些分布式计算环境中，由通过通信网络而被连接的远程处理设备来执行事务。在分布式计算环境中，程序模块可以位于包括存储设备在内的本地和远程计算机存储介质中。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (27)

  1. 一种电容检测电路，其特征在于，包括：第一驱动模块、转换模块、处理模块以及控制模块；所述第一驱动模块用于对第一待测电容进行充电；所述转换模块用于对所述第一待测电容进行电荷转化处理以生成输出电压，所述转换模块包括第一抑制模块，所述控制模块用于控制所述第一抑制模块在所述转换模块生成所述输出电压时对小于第一频率或者大于第二频率的干扰信号进行抑制，所述第二频率大于所述第一频率；所述处理模块用于根据所述输出电压确定所述第一待测电容被外加电场影响前后的电容变化量。
  2. 根据权利要求1所述的电路，其特征在于，所述转换模块具有第一输入端和第二输入端，所述转换模块的第一输入端与所述第一驱动模块电连接，所述第二输入端接入共模电压和/或与可等效产生共模电压的其他电路连接。
  3. 根据权利要求2所述的电路，其特征在于，所述转化模块包括单端差分放大器，所述转换模块的第一输入端为所述单端差分放大器的反相输入端，所述转换模块的第二输入端为所述单端差分放大器的正相输入端，所述第一驱动模块与所述单端差分放大器的反相输入端电连接，所述单端差分放大器的正相输入端接入共模电压，所述单端差分放大器的输出端与所述处理模块电连接；所述第一抑制模块的两端分别连接在所述单端差分放大器的反相输入端和输出端。
  4. 根据权利要求3所述的电路，其特征在于，所述第一抑制模块包括第一开关单元、第一电容和第二电容；所述第一开关单元的第一端和第二端分别连接在所述单端差分放大器的反相输入端和输出端，所述第一电容通过所述第一开关单元的第三端可分别连接在所述第一开关单元的第一端和所述第一开关单元的第二端，所述第一电容的第二端接地，所述第二电容的两端分别连接在所述单端差分放大器的反相输入端和输出端；所述控制模块用于控制所述第一开关单元在第一端和第二端之间来回切换，以使所述第一开关单元的第三端与第一端连通或者第三端与第二端连通，所述第一开关单元切换的频率大于两倍的驱动频率，以对小于第一频率的电信号进行抑制。
  5. 根据权利要求4所述的电路，其特征在于，在自容检测电路中所述驱动频率为所述第一驱动模块内开关连通或断开的切换频率，或者，在互容检测电路中所述驱动频率为所述第一驱动模块的电源频率。
  6. 根据权利要求2所述的电路，其特征在于，所述转化模块包括双端差分放大器，所述双端差分放大器具有正相输入端、反相输入端、第一输出端和第二输出端，所述转换模块的第一输入端为所述双端差分放大器的反相输入端，所述转换模块的第二输入端为所述双端差分放大器的正相输入端，所述第一驱动模块与所述双端差分放大器的反相输入端电连接，所述双端差分放大器的正相输入端接入共模电压，所述双端差分放大器的第一输出端和第二输出端均与所述处理模块电连接；所述第一抑制模块的两端分别连接在所述双端差分放大器的反相输入端和第一输出端。
  7. 根据权利要求6所述的电路，其特征在于，所述转换模块还包括第二抑制模块，所述第二抑制模块的两端分别连接在所述双端差分放大器的正相输入端和第二输出端，所述控制模块用于控制所述第二抑制模块在所述转换模块生成所述输出电压时对小于所述第一频率或者大于所述第二频率的干扰信号进行抑制，所述第二频率大于所述第一频率。
  8. 根据权利要求6所述的电路，其特征在于，所述第二抑制模块包括第二开关单元、第三电容和第四电容；所述第二开关单元的第一端和第二端分别连接在所述双端差分放大器的正相输入端和第二输出端，所述第四电容的两端分别连接在所述第二开关单元的第一端和所述第二开关单元的第二端，所述第三电容的第一端与所述第二开关单元的第三端电连接，所述第三电容的第二端接地；所述控制模块用于控制所述第二开关单元在第一端和第二端之间来回切换，以使所述第二开关单元的第三端与第一端连通或者第三端与第二端连通，所述第二开关单元切换的频率大于两倍的驱动频率，以对小于第一频率的电信号进行抑制。
  9. 根据权利要求8所述的电路，其特征在于，在自容检测电路中所述驱动频率为第二驱动模块内开关连通或断开的切换频率，或者，在互容检测电路中所述驱动频率为第二驱动模块的电源频率。
  10. 根据权利要求2所述的电路，其特征在于，所述第一驱动模块包括激励电源，所述激励电源通过所述第一待测电容与所述转换模块的第一输入端电连接。
  11. 根据权利要求2所述的电路，其特征在于，所述电容检测电路还包括第三开关单元，所述第三开关单元连接在所述第一驱动模块和所述转换模块的第一输入端之间，所述第三开关单元闭合时，所述转换模块对所述第一待测电容进行电荷转化处理生成输出电压。
  12. 根据权利要求1所述的电路，其特征在于，所述第一驱动模块包括第四开关单元，所述控制模块进一步用于控制第四开关单元处于第一闭合状态以使所述第一驱动模块对所述第一待测电容进行充电；所述第四开关单元处于第一闭合状态时，所述第一待测电容的第一端通过所述第四开关单元接入第一电压，所述第一待测电容的第二端接入第二电压，所述第一电压大于所述第二电压。
  13. 根据权利要求12所述的电路，其特征在于，所述控制模块进一步用于控制第四开关单元处于第二闭合状态以使所述第一待测电容放电；所述第四开关单元处于第二闭合状态时，所述第一待测电容的第一端通过所述第四开关单元接入第三电压，所述第一待测电容的第二端接入所述第二电压，所述第二电压大于所述第三电压。
  14. 根据权利要求11所述的电路，其特征在于，所述电容检测电路还包括第一抵消模块；所述控制模块还用于控制所述第一抵消模块对第一抵消电容进行充电，以及控制所述第一抵消电容对所述第一待测电容进行充电或放电实现电荷抵消。
  15. 根据权利要求14所述的电路，其特征在于，所述第一抵消模块包括第五开关单元，所述控制模块进一步用于控制所述第五开关单元处于第一闭合状态并形成充电支路以使所述抵消模块对所述第一抵消电容进行充电；所述控制模块还用于控制所述第五开关单元处于第二闭合状态形成抵消支路以使所述第一抵消电容对所述第一待测电容进行充电或放电实现电荷抵消。
  16. 根据权利要求15所述的电路，其特征在于，所述第五开关单元处于所述第一闭合状态时，所述第一抵消电容的两端分别接入第四电压和第五电压，所述第五电压高于所述第四电压。
  17. 根据权利要求15所述的电路，其特征在于，所述第五开关单元处于所述第二闭合状态时，所述第一抵消电容的第一端通过所述第五开关单元与所述第一待测电容的第 一端电连接，所述第一抵消电容的第二端通过所述第五开关单元接入第六电压或第七电压，所述第六电压低于所述待测电容的第二端接入的第二电压，所述第七电压高于所述待测电容的第二端接入的第二电压。
  18. 根据权利要求2所述的电路，其特征在于，所述电容检测电路还包括第二驱动模块，所述第二驱动模块与所述转换模块的第二输入端电连接，所述控制模块还用于通过控制所述第二驱动模块对第二待测电容进行充电；所述转换模块用于对所述第二待测电容进行电荷转化处理以生成输出电压。
  19. 根据权利要求18所述的电路，其特征在于，所述电容检测电路还包括第六开关单元，所述第六开关单元连接在所述第二驱动模块和所述转换模块的第二输入端之间，所述第六开关单元闭合时，所述转换模块对所述第二待测电容进行电荷转化处理生成输出电压。
  20. 根据权利要求19所述的电路，其特征在于，所述第二驱动模块包括第七开关单元，所述控制模块进一步用于控制第七开关单元处于第一闭合状态以使所述第二驱动模块对所述第二待测电容进行充电；所述第七开关单元处于第一闭合状态时，所述第二待测电容的第一端通过所述第七开关单元接入第八电压，所述第二待测电容的第二端接入第九电压，所述第八电压大于所述第九电压。
  21. 根据权利要求20所述的电路，其特征在于，所述控制模块进一步用于控制第七开关单元处于第二闭合状态以使所述第二待测电容放电；所述第七开关单元处于第二闭合状态时，所述第二待测电容的第一端通过所述第七开关单元接入第十电压，所述第二待测电容的第二端接入所述第九电压，所述第九电压大于所述第十电压。
  22. 根据权利要求21所述的电路，其特征在于，所述电容检测电路还包括第二抵消模块；所述控制模块还用于控制所述第二抵消模块对第二抵消电容进行充电，以及控制所述第一第二抵消电容对所述第二待测电容进行充电或放电实现电荷抵消。
  23. 根据权利要求22所述的电路，其特征在于，所述第二抵消模块包括第八开关单元，所述控制模块进一步用于控制所述第八开关单元处于第一闭合状态并形成充电支路以使所述抵消模块对所述第二抵消电容进行充电；所述控制模块还用于控制所述第八开关单元处于第二闭合状态形成抵消支路以使所述第二抵消电容对所述第二待测电容进行充电或放电实现电荷抵消。
  24. 根据权利要求23所述的电路，其特征在于，所述第八开关单元处于所述第一闭合状态时，所述第二抵消电容的两端分别接入第十一电压和第十二电压，所述第十二电压高于所述第十一电压。
  25. 根据权利要求23所述的电路，其特征在于，所述第八开关单元处于所述第二闭合状态时，所述第二抵消电容的第一端通过所述第八开关单元与所述第二待测电容的第一端电连接，所述第二抵消电容的第二端通过所述第八开关单元接入第十三电压或第十四电压，所述第十三电压低于所述第二待测电容的第二端接入的第九电压，所述第十四电压高于所述第二待测电容的第二端接入的第九电压。
  26. 一种检测芯片，其特征在于，包括如权利要求1-25任一项所述的电容检测电路。
  27. 一种电子设备，其特征在于，包括：如权利要求26所述的检测芯片。
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