WO2018132963A1 - 检测电容的装置、电子设备和检测压力的装置 - Google Patents

检测电容的装置、电子设备和检测压力的装置 Download PDF

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Publication number
WO2018132963A1
WO2018132963A1 PCT/CN2017/071490 CN2017071490W WO2018132963A1 WO 2018132963 A1 WO2018132963 A1 WO 2018132963A1 CN 2017071490 W CN2017071490 W CN 2017071490W WO 2018132963 A1 WO2018132963 A1 WO 2018132963A1
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Prior art keywords
switch
capacitor
tested
capacitance
operational amplifier
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PCT/CN2017/071490
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English (en)
French (fr)
Inventor
冯林
蒋宏
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201780003129.XA priority Critical patent/CN108124474B/zh
Priority to EP17849895.2A priority patent/EP3379271B1/en
Priority to PCT/CN2017/071490 priority patent/WO2018132963A1/zh
Priority to US15/925,768 priority patent/US10788380B2/en
Publication of WO2018132963A1 publication Critical patent/WO2018132963A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/14—Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators
    • G01L1/142—Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators using capacitors
    • G01L1/144—Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators using capacitors with associated circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0414—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0447—Position sensing using the local deformation of sensor cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/261—Amplifier which being suitable for instrumentation applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45116—Feedback coupled to the input of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45138—Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45156—At least one capacitor being added at the input of a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45514—Indexing scheme relating to differential amplifiers the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC

Definitions

  • the present invention relates to the field of information technology, and more particularly to a device for detecting capacitance, an electronic device, and a device for detecting pressure.
  • capacitive sensors to detect external physical signals.
  • capacitive touch screen capacitive force sensor
  • capacitive displacement sensor capacitive displacement sensor
  • capacitance detection technology detects the capacitance change of the capacitor by the capacitance detection technology to detect the corresponding signal to be tested.
  • the accuracy of the sensed capacitance determines the accuracy of the signal detection. Therefore, how to improve the accuracy of the detection capacitance has become a technical problem to be solved.
  • Embodiments of the present invention provide a device for detecting capacitance, an electronic device, and a device for detecting pressure, which can improve the accuracy of capacitance detection.
  • an apparatus for detecting capacitance comprising:
  • the coding circuit 110 is configured to periodically charge and discharge the at least one capacitor to be tested;
  • a conversion circuit 120 configured to convert a capacitance signal of the at least one capacitor to be tested into a voltage signal
  • the cancellation circuit 130 is configured to cancel the initial capacitance of the at least one capacitor to be tested, so that the voltage signal is associated with the capacitance change of the at least one capacitor to be tested.
  • the device for detecting capacitance is capable of detecting a small capacitance change, and can improve the accuracy of capacitance detection.
  • At least one capacitor to be tested includes a first capacitor 101 to be tested
  • the differential mode signal of the voltage signal at different times output by the conversion circuit 120 represents the change in capacitance of the first capacitor 101 to be tested.
  • the coding circuit 110 includes a first switch 111, a second switch 112, a third switch 113, and a first DC voltage source 115;
  • One end of the first to-be-tested capacitor 101 is connected to the first through the third switch 113 and the first switch 111 A DC voltage source 115, and one end of the first capacitor 101 to be tested is grounded through the third switch 113 and the second switch 112, and the other end of the first capacitor 101 to be tested is grounded.
  • the conversion circuit 120 includes a fourth switch 121, a fifth switch 122, a first feedback capacitor 123, and a first operational amplifier 124;
  • the fourth switch 121 is connected between one end of the first capacitor 101 to be tested and an inverting input terminal of the first operational amplifier 124;
  • the first feedback capacitor 123 is coupled between the inverting input and the output of the first operational amplifier 124;
  • the fifth switch 122 is connected between the inverting input terminal and the output terminal of the first operational amplifier 124;
  • a common mode voltage Vcm is input to the non-inverting input of the first operational amplifier 124.
  • the cancellation circuit 130 includes a first adjustable capacitor 131, a sixth switch 132, a seventh switch 133, an eighth switch 134, a ninth switch 135, and a second DC voltage source 139;
  • One end of the first adjustable capacitor 131 is connected to the second DC voltage source 139 through the sixth switch 132, and one end of the first adjustable capacitor 131 is grounded through the seventh switch 133, and the other end of the first adjustable capacitor 131 is connected to An inverting input of the first operational amplifier 124;
  • the eighth switch 134 and the ninth switch 135 are used to change the switching control signals that control the sixth switch 132 and the seventh switch 133.
  • the device for detecting capacitance of the embodiment of the present invention has strong low frequency common mode noise and 1/f noise suppression capability by using the working timing of positive and negative coding.
  • the at least one capacitor to be tested includes a first capacitor to be tested 101 and a second capacitor to be tested 102;
  • the differential signal of the voltage signal corresponding to the first to-be-tested capacitor 101 and the second to-be-tested capacitor 102 outputted by the conversion circuit 120 represents the capacitance change of the first to-be-tested capacitor 101 and the second to-be-tested capacitor 102.
  • the coding circuit 110 includes a first switch 111, a second switch 112, a third switch 113, a tenth switch 114, and a first DC voltage source 115;
  • One end of the first capacitor 101 to be tested is connected to the first DC voltage source 115 through the third switch 113 and the first switch 111, and one end of the first capacitor 101 to be tested is grounded through the third switch 113 and the second switch 112. The other end of the capacitor 101 to be tested is grounded;
  • One end of the second capacitor to be tested 102 is connected to the first through the tenth switch 114 and the first switch 111.
  • a DC voltage source 115, and one end of the second capacitor to be tested 102 is grounded through the tenth switch 114 and the second switch 112, and the other end of the second capacitor to be tested 102 is grounded.
  • the conversion circuit 120 includes a fourth switch 121, a fifth switch 122, a first feedback capacitor 123, a first operational amplifier 124, an eleventh switch 125, a twelfth switch 126, and a second feedback capacitor. 127 and a second operational amplifier 128;
  • the fourth switch 121 is connected between one end of the first capacitor 101 to be tested and an inverting input terminal of the first operational amplifier 124;
  • the first feedback capacitor 123 is coupled between the inverting input and the output of the first operational amplifier 124;
  • the fifth switch 122 is connected between the inverting input terminal and the output terminal of the first operational amplifier 124;
  • the eleventh switch 125 is connected between one end of the second capacitor under test 102 and an inverting input terminal of the second operational amplifier 128;
  • a second feedback capacitor 127 is coupled between the inverting input and the output of the second operational amplifier 128;
  • the twelfth switch 126 is connected between the inverting input terminal and the output terminal of the second operational amplifier 128;
  • the common mode voltage Vcm is input to the same input terminals of the first operational amplifier 124 and the second operational amplifier 128.
  • the cancellation circuit 130 includes a first adjustable capacitor 131, a sixth switch 132, a seventh switch 133, an eighth switch 134, a ninth switch 135, a second adjustable capacitor 136, and a thirteenth switch. 137, a fourteenth switch 138 and a second DC voltage source 139;
  • One end of the first adjustable capacitor 131 is connected to the second DC voltage source 139 through the sixth switch 132, and one end of the first adjustable capacitor 131 is grounded through the seventh switch 133, and the other end of the first adjustable capacitor 131 is connected to An inverting input of the first operational amplifier 124;
  • One end of the second adjustable capacitor 136 is connected to the second DC voltage source 139 through the thirteenth switch 137, and one end of the second adjustable capacitor 136 is grounded through the fourteenth switch 138, and the other end of the second adjustable capacitor 136 Connected to the inverting input of the second operational amplifier 128;
  • the eighth switch 134 and the ninth switch 135 are used to change the switching control signals that control the sixth switch 132, the seventh switch 133, the thirteenth switch 137, and the fourteenth switch 138.
  • the apparatus further includes:
  • the programmable gain amplifier 140 is configured to output a differential signal according to a voltage signal corresponding to the first to-be-tested capacitor 101 and the second to-be-tested capacitor 102.
  • the output voltages of the first DC voltage source 115 and the second DC voltage source 139 are equal.
  • the output voltage is twice the common mode voltage Vcm.
  • the first capacitor to be tested and the second capacitor to be tested are capacitors in the differential capacitance sensor.
  • the device for detecting capacitance of the embodiment of the present invention has a strong temperature drift suppression capability.
  • an electronic device comprising the device for detecting capacitance in the first aspect or any of the possible implementations of the first aspect.
  • a device for detecting a pressure comprising the device for detecting capacitance in the first aspect or any of the possible implementations of the first aspect, wherein the pressure detecting device is to be detected by a pressure associated with the detecting Capacitor device The capacitance change of the capacitor to be tested to be detected.
  • Figure 1 is a schematic illustration of an apparatus for detecting capacitance in accordance with one embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an apparatus for detecting a capacitance according to another embodiment of the present invention.
  • Fig. 3 is a timing chart showing the operation of the apparatus for detecting capacitance according to an embodiment of the present invention.
  • FIGS. 4a-4c are schematic views of a differential capacitance pressure sensor in accordance with an embodiment of the present invention.
  • Figure 5 is a schematic illustration of an apparatus for detecting capacitance in accordance with yet another embodiment of the present invention.
  • the technical solutions of the embodiments of the present invention can be applied to various devices that use touch, such as an active pen, a capacitive pen, a mobile terminal, a computer, a home appliance, and the like.
  • the device for detecting capacitance in the embodiment of the present invention may be disposed in various touch devices for detecting a touch capacitor, that is, a capacitance change of the capacitor to be tested, thereby detecting a pressure change caused by the touch.
  • the capacitance change of the capacitor to be tested can be either a relative value or an absolute value.
  • the capacitance change of the capacitor to be tested is the absolute value of its capacitance.
  • a capacitor may also be referred to simply as a “capacitor”. Accordingly, the capacitance of a capacitor may also be referred to as a capacitance value.
  • the capacitance of a capacitor and a capacitor will be described as an example.
  • Fig. 1 is a schematic view showing an apparatus for detecting a capacitance according to an embodiment of the present invention.
  • the apparatus may include a coding circuit 110, a conversion circuit 120, and a cancellation circuit 130.
  • the coding circuit 110 is configured to periodically charge and discharge the at least one capacitor to be tested.
  • the coding circuit 110 can also be referred to as a drive circuit.
  • the charge and discharge of the capacitor to be tested can be realized by switching.
  • the conversion circuit 120 is configured to convert the capacitance signal of the at least one capacitor to be tested into a voltage signal.
  • the conversion circuit 120 is a capacitance/voltage (C/V) conversion circuit.
  • the capacitance signal can be converted into a voltage signal by an operational amplifier and a feedback circuit.
  • the cancellation circuit 130 is configured to cancel the initial capacitance of the at least one capacitor to be tested, so that the voltage signal is associated with the capacitance change of the at least one capacitor to be tested.
  • the initial capacitance (including parasitic capacitance) of the capacitor to be tested is cancelled by the cancellation circuit 130.
  • the output is Zero, thereby causing the output signal of the conversion circuit 120 to correlate with the capacitance change of the capacitor to be tested.
  • the offset value is used to set the initial value to zero, which improves the dynamic range of capacitance detection.
  • the at least one capacitor to be tested includes a first capacitor to be tested
  • the differential mode signal of the voltage signal at different times output by the conversion circuit 120 represents the capacitance change of the first capacitor to be tested.
  • the differential mode signal of the voltage signal at different times outputted by the conversion circuit 120 reflects the capacitance change of the one capacitor to be tested.
  • FIG. 2 is a schematic diagram showing a specific implementation of an apparatus for detecting capacitance according to an embodiment of the present invention.
  • FIG. 2 is only an example and is not intended to limit the scope of the embodiments of the present invention.
  • the coding circuit 110 of FIG. 1 may include a first switch 111, a second switch 112, a third switch 113, and a first DC voltage source 115.
  • One end of the first capacitor 101 to be tested is connected to the first DC voltage source 115 through the third switch 113 and the first switch 111, and the terminal is grounded through the third switch 113 and the second switch 112, and the first capacitor 101 to be tested is further One end is grounded.
  • the first switch 111 is controlled by a first switch control signal (denoted as PNSW) and the second switch 112 is inverted by a PNSW signal.
  • Control, the third switch 113 is controlled by a second switch control signal (denoted as SW).
  • the first switch 111 and the third switch 113 are in communication, and when the second switch 112 is turned off, the first capacitor 101 to be tested is charged by the first DC voltage source 115.
  • the output voltage of the first DC voltage source 115 can be expressed as Vdc.
  • the second switch 112 is in communication with the third switch 113.
  • the first switch 111 is turned off, the first capacitor 101 to be tested is discharged.
  • the conversion circuit 120 of FIG. 1 may include a fourth switch 121, a fifth switch 122, a first feedback capacitor 123, and a first operational amplifier 124.
  • the fourth switch 121 passes the inverted signal of the SW Control, the fifth switch 122 is controlled by the SW.
  • the fourth switch 121 is connected between one end of the first capacitor 101 to be tested and an inverting input terminal of the first operational amplifier 124;
  • the first feedback capacitor 123 is coupled between the inverting input and the output of the first operational amplifier 124;
  • the fifth switch 122 is connected between the inverting input terminal and the output terminal of the first operational amplifier 124;
  • a common mode voltage Vcm is input to the non-inverting input of the first operational amplifier 124.
  • the cancellation circuit 130 of FIG. 1 may include a first adjustable capacitor 131, a sixth switch 132, a seventh switch 133, an eighth switch 134, a ninth switch 135, and a second DC voltage source 139.
  • the output voltages of the second DC voltage source 139 and the first DC voltage source 115 are equal, that is, both are Vdc.
  • the eighth switch 134 is controlled by the PNSW, and the ninth switch 135 is inverted by the PNSW signal.
  • Control the sixth switch 132 is controlled by the third switch control signal CSW, and the seventh switch 133 is passed through the inverted signal of the CSW. control.
  • One end of the first adjustable capacitor 131 is connected to the second DC voltage source 139 through the sixth switch 132, and the end is grounded through the seventh switch 133, and the other end of the first adjustable capacitor 131 is connected to the opposite of the first operational amplifier 124. To the input;
  • the eighth switch 134 and the ninth switch 135 are used to change the switching control signals that control the sixth switch 132 and the seventh switch 133.
  • CSW and They are the switching control signals of the sixth switch 132 and the seventh switch 133, respectively.
  • the eighth switch 134 is connected, when the ninth switch 135 is turned off, the CSW is equal to the SW; the eighth switch 134 is turned off, and when the ninth switch 135 is connected, the CSW is equal to By CSW and
  • the sixth switch 132 and the seventh switch 133 are separately controlled.
  • first switch control signal PNSW and the second switch control signal SW in FIG. 2 may adopt a signal as shown in FIG.
  • a complete capacitance detection cycle consists of t1, t2, t3, and t4.
  • the detection timing is a positive and negative coding timing.
  • T1 the first switch 111, the third switch 113, the eighth switch 134, the sixth switch 132, and the fifth switch 122 are closed, and the second switch 112, the fourth switch 121, the ninth switch 135, and the seventh switch 133 are off. Turning on, at this moment, the DC voltage Vdc is positively charged to the first capacitor 101 to be tested.
  • T2 the second switch 112, the third switch 113, the ninth switch 135, the sixth switch 132, and the fifth switch 122 are turned off, and the first switch 111, the fourth switch 121, the eighth switch 134, and the seventh switch 133 are turned off. Closing, at this moment, the charge on the first capacitor 101 to be tested is transferred to the first feedback capacitor 123 and the first adjustable capacitor 131. At this point the Vout output is:
  • C1 represents the capacitance of the first capacitor 101 to be tested
  • Cfb represents the capacitance of the first adjustable capacitor 131
  • Cc represents the capacitance of the first feedback capacitor 123.
  • T3 the second switch 112, the third switch 113, the ninth switch 135, the seventh switch 133, and the fifth switch 122 are closed, and the first switch 111, the fourth switch 121, the eighth switch 134, and the sixth switch 132 are off. Turning on, at this moment, the first capacitor 101 to be tested is shorted to ground, and the first adjustable capacitor 131 is reversely charged.
  • T4 the first switch 111, the third switch 113, the eighth switch 134, the seventh switch 133, and the fifth switch 122 are turned off, and the second switch 112, the fourth switch 121, the ninth switch 135, and the sixth switch 132 Closing, at this moment, the charge on the first feedback capacitor 123 and the first adjustable capacitor 131 is transferred to the first capacitor 101 to be tested.
  • the Vout output is:
  • the post-sampling circuit can sample the Vout output at t2 and t4 and subtract it to get the differential mode signal size:
  • the initial capacitance C1 0 is completely cancelled out, thereby outputting the differential mode signal size:
  • ⁇ C represents a change in the capacitance of the first capacitor 101 to be tested.
  • the device for detecting capacitance of the embodiment of the present invention has strong low-frequency common mode noise and 1/f noise (also referred to as flicker noise) suppression capability by using the working timing of positive and negative coding. That is to say, the device for detecting capacitance according to the embodiment of the present invention can improve the anti-interference performance, and thus can be detected when the capacitance to be tested changes slightly. Therefore, the device for detecting capacitance according to the embodiment of the present invention can detect a small capacitance change, and can improve the accuracy of capacitance detection.
  • the above-mentioned cancellation circuit of the embodiment of the present invention can completely cancel the initial capacitance and has high cancellation efficiency.
  • the at least one capacitor to be tested includes a first capacitor to be tested and a second capacitor to be tested;
  • the differential signal of the voltage signal corresponding to the first to-be-tested capacitor and the second to-be-measured capacitor outputted by the conversion circuit 120 represents a change in capacitance of the first capacitor to be tested and the second capacitor to be tested.
  • the differential signals of the voltage signals corresponding to the two capacitors to be tested outputted by the conversion circuit 120 reflect the capacitance changes of the two capacitors to be tested.
  • the capacitance of one of the capacitors to be tested may be changed, the capacitance of the capacitor to be tested is not changed, and the capacitance that does not change may be a standard.
  • the capacitor; the first capacitor to be tested and the second capacitor to be tested may also constitute a differential capacitance sensor, that is, two capacitors in the differential capacitance sensor.
  • the differential capacitance sensor can be a differential capacitance pressure sensor.
  • Figures 4a-4c show schematic diagrams of three differential capacitance pressure sensors, respectively. As shown in Figures 4a-4c, applying pressure to the differential capacitance pressure sensor will cause the intermediate electrode sheet to deform or displace, causing the capacitance C1 to increase and C2 to decrease, forming a differential ⁇ C.
  • ⁇ C is the sum of the changes in C1 and C2.
  • FIG. 5 is a schematic diagram showing another specific implementation of the apparatus for detecting capacitance according to an embodiment of the present invention.
  • FIG. 5 is only an example and is not intended to limit the scope of the embodiments of the present invention.
  • the coding circuit 110 in FIG. 1 may include a first switch 111 and a second switch. 112.
  • the first switch 111 is controlled by the first switch control signal PNSW, and the second switch 112 is inverted by the PNSW signal. Control, the third switch 113 and the tenth switch 114 are controlled by the second switch control signal SW.
  • One end of the first capacitor 101 to be tested is connected to the first DC voltage source 115 through the third switch 113 and the first switch 111, and the terminal is grounded through the third switch 113 and the second switch 112, and the first capacitor 101 to be tested is further One end is grounded.
  • One end of the second capacitor to be tested 102 is connected to the first DC voltage source 115 through the tenth switch 114 and the first switch 111, and the terminal is grounded through the tenth switch 114 and the second switch 112, and the second capacitor 102 to be tested is further One end is grounded.
  • the first switch 111, the third switch 113 and the tenth switch 114 are connected, and when the second switch 112 is turned off, the first to-be-tested capacitor 101 and the second to-be-tested capacitor 102 are charged by the first DC voltage source 115;
  • the second switch 112, the third switch 113 and the tenth switch 114 are in communication.
  • the first switch 111 is turned off, the first to-be-tested capacitor 101 and the second to-be-tested capacitor 102 are discharged.
  • the conversion circuit 120 in FIG. 1 may include a fourth switch 121, a fifth switch 122, a first feedback capacitor 123, a first operational amplifier 124, an eleventh switch 125, a twelfth switch 126, and a Two feedback capacitors 127 and a second operational amplifier 128.
  • the fourth switch 121 and the eleventh switch 125 pass the inverted signal of the SW Control, the fifth switch 122 and the twelfth switch 126 are controlled by SW.
  • the fourth switch 121 is connected between one end of the first capacitor 101 to be tested and an inverting input terminal of the first operational amplifier 124;
  • the first feedback capacitor 123 is coupled between the inverting input and the output of the first operational amplifier 124;
  • the fifth switch 122 is connected between the inverting input terminal and the output terminal of the first operational amplifier 124;
  • the eleventh switch 125 is connected between one end of the second capacitor under test 102 and an inverting input terminal of the second operational amplifier 128;
  • a second feedback capacitor 127 is coupled between the inverting input and the output of the second operational amplifier 128;
  • the twelfth switch 126 is connected between the inverting input terminal and the output terminal of the second operational amplifier 128;
  • the common mode voltage Vcm is input to the same input terminals of the first operational amplifier 124 and the second operational amplifier 128.
  • the cancellation circuit 130 of FIG. 1 includes a first adjustable capacitor 131, a sixth switch 132, a seventh switch 133, an eighth switch 134, a ninth switch 135, a second adjustable capacitor 136, and a tenth.
  • the eighth switch 134 is controlled by the PNSW, and the ninth switch 135 is inverted by the PNSW signal.
  • Control, the sixth switch 132 and the thirteenth switch 137 are controlled by the switch control signal CSW, and the seventh switch 133 and the fourteenth switch 138 pass the inverted signal of the CSW. control.
  • One end of the first adjustable capacitor 131 is connected to the second DC voltage source 139 through the sixth switch 132, and the end is grounded through the seventh switch 133, and the other end of the first adjustable capacitor 131 is connected to the opposite of the first operational amplifier 124. To the input;
  • One end of the second adjustable capacitor 136 is connected to the second DC voltage source 139 through the thirteenth switch 137, and the terminal is grounded through the fourteenth switch 138, and the other end of the second adjustable capacitor 136 is connected to the second operational amplifier 128. Inverting input;
  • the eighth switch 134 and the ninth switch 135 are used to change the switching control signals that control the sixth switch 132, the seventh switch 133, the thirteenth switch 137, and the fourteenth switch 138.
  • the first switch control signal PNSW and the second switch control signal SW in FIG. 5 may adopt a signal as shown in FIG.
  • the operation timing of the circuit in FIG. 5 can be the same as that of FIG. 2.
  • the device shown in Figure 5 can be used with a pressure sensor.
  • the first to-be-tested capacitor 101 and the second to-be-tested capacitor 102 may be two of the pressure sensors, for example, C1 and C2 in Figs. 4a-4c.
  • the change in capacitance of the first capacitor under test 101 and the second capacitor to be tested 102 can be detected by the device shown in FIG. 5, thereby obtaining a change in pressure.
  • the differential output voltage can be made zero by adjusting the capacitances of the first tunable capacitor 131 and the second tunable capacitor 136.
  • the output differential voltage is:
  • ⁇ C represents the sum of the amounts of change of the first capacitor under test 101 and the second capacitor to be tested 102. That is, the output differential voltage can represent the change in capacitance of the two capacitors to be tested.
  • the apparatus may further include:
  • a programmable gain amplifier 140 for using the first capacitor 101 to be tested and the second capacitor to be tested
  • the voltage signal corresponding to the device 102 outputs a differential signal.
  • the programmable gain amplifier 140 outputs a differential signal and stabilizes the common mode voltage of the differential output.
  • the device for detecting capacitance of the embodiment of the present invention has a strong temperature drift suppression capability.
  • the circuit output may be integrated multiple times to effectively improve the system noise ratio and improve the detection accuracy, especially for the case where the capacitance of the capacitor to be tested is a small capacitance of fF to pF.
  • an analog integration scheme may be employed, that is, adding a first-order integration circuit or changing the detection circuit timing to increase the number of integrations of the C/V conversion circuit, and then performing analog-to-digital converter (ADC) sampling.
  • a digital integration scheme can also be used, that is, the detection circuit output is directly sent to the ADC for sampling, and then the sampled data is integrated by the digital processor.
  • the device for detecting capacitance adopts the working timing of positive and negative coding, can effectively suppress low frequency noise and 1/f noise; adopts a differential structure, has temperature drift suppression capability, and zero drift suppression capability;
  • the switch capacitor circuit composed of the switch and the capacitor controlled by the switch control signal has low power consumption; thereby enabling the device to have a high signal to noise ratio, facilitating integration of integrated circuits (ICs), and having a high Detection sensitivity, which can detect the capacitance of the fF level.
  • An embodiment of the present invention further provides an electronic device, which may include the device for detecting capacitance according to the embodiment of the present invention.
  • the embodiment of the present invention further provides a device for detecting pressure, which may include the device for detecting capacitance according to the embodiment of the present invention, wherein the device for detecting pressure is associated with a pressure associated with the detecting capacitor.
  • the detected capacitance change of the capacitor to be tested.
  • the device for detecting the pressure may be a pressure sensor, and the pressure sensor may be disposed in the stylus, but the embodiment of the present invention is not limited thereto.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

一种检测电容的装置、电子设备和检测压力的装置。该检测电容的装置包括：打码电路（110），用于对至少一个待测电容器周期性充放电；变换电路（120），用于将该至少一个待测电容器的电容信号转换为电压信号；抵消电路（130），用于抵消该至少一个待测电容器的初始电容，以使该电压信号关联该至少一个待测电容器的电容变化。该检测电容的装置，能够提高抗干扰性能，提高电容检测的精确度。

Description

检测电容的装置、电子设备和检测压力的装置 技术领域
本发明涉及信息技术领域，并且更具体地，涉及一种检测电容的装置、电子设备和检测压力的装置。
背景技术
随着信息技术的发展，越来越多的电子设备采用电容式传感器检测外界物理信号。如电容式触摸屏，电容式力传感器，电容式位移传感器等。实现电容传感器的一种关键技术是电容检测技术，通过电容检测技术检测电容器的电容变化以检测相应待测信号。
检测电容的精确度，决定了信号检测的精确度。因此，如何提高检测电容的精确度，成为亟待解决的一个技术问题。
发明内容
本发明实施例提供了一种检测电容的装置、电子设备和检测压力的装置，能够提高电容检测的精确度。
第一方面，提供了一种检测电容的装置，包括：
打码电路110，用于对至少一个待测电容器周期性充放电；
变换电路120，用于将至少一个待测电容器的电容信号转换为电压信号；
抵消电路130，用于抵消至少一个待测电容器的初始电容，以使电压信号关联至少一个待测电容器的电容变化。
本发明实施例的检测电容的装置能够检测出微小电容变化，能够提高电容检测的精确度。
在一些可能的实现方式中，至少一个待测电容器包括第一待测电容器101；
变换电路120输出的不同时刻的电压信号的差模信号表示第一待测电容器101的电容变化。
在一些可能的实现方式中，打码电路110包括第一开关111、第二开关112、第三开关113和第一直流电压源115；
第一待测电容器101的一端通过第三开关113和第一开关111连接至第 一直流电压源115，且第一待测电容器101的一端，通过第三开关113和第二开关112接地，第一待测电容器101的另一端接地。
在一些可能的实现方式中，变换电路120包括第四开关121、第五开关122、第一反馈电容器123和第一运算放大器124；
第四开关121连接于第一待测电容器101的一端和第一运算放大器124的反向输入端之间；
第一反馈电容器123连接于第一运算放大器124的反向输入端和输出端之间；
第五开关122连接于第一运算放大器124的反向输入端和输出端之间；
第一运算放大器124的同向输入端输入共模电压Vcm。
在一些可能的实现方式中，抵消电路130包括第一可调电容器131、第六开关132、第七开关133、第八开关134、第九开关135和第二直流电压源139；
第一可调电容器131的一端通过第六开关132连接至第二直流电压源139，且该第一可调电容器131的一端通过第七开关133接地，第一可调电容器131的另一端连接至第一运算放大器124的反向输入端；
第八开关134和第九开关135用于改变控制第六开关132和第七开关133的开关控制信号。
采用正负打码的工作时序，本发明实施例的检测电容的装置具有很强的低频共模噪声和1/f噪声抑制能力。
在一些可能的实现方式中，至少一个待测电容器包括第一待测电容器101和第二待测电容器102；
变换电路120输出的第一待测电容器101和第二待测电容器102对应的电压信号的差分信号表示第一待测电容器101和第二待测电容器102的电容变化。
在一些可能的实现方式中，打码电路110包括第一开关111、第二开关112、第三开关113、第十开关114和第一直流电压源115；
第一待测电容器101的一端通过第三开关113和第一开关111连接至第一直流电压源115，且该第一待测电容器101的一端通过第三开关113和第二开关112接地，第一待测电容器101的另一端接地；
第二待测电容器102的一端通过第十开关114和第一开关111连接至第 一直流电压源115，且该第二待测电容器102的一端通过第十开关114和第二开关112接地，第二待测电容器102的另一端接地。
在一些可能的实现方式中，变换电路120包括第四开关121、第五开关122、第一反馈电容器123、第一运算放大器124、第十一开关125、第十二开关126、第二反馈电容器127和第二运算放大器128；
第四开关121连接于第一待测电容器101的一端和第一运算放大器124的反向输入端之间；
第一反馈电容器123连接于第一运算放大器124的反向输入端和输出端之间；
第五开关122连接于第一运算放大器124的反向输入端和输出端之间；
第十一开关125连接于第二待测电容器102的一端和第二运算放大器128的反向输入端之间；
第二反馈电容器127连接于第二运算放大器128的反向输入端和输出端之间；
第十二开关126连接于第二运算放大器128的反向输入端和输出端之间；
第一运算放大器124和第二运算放大器128的同向输入端均输入共模电压Vcm。
在一些可能的实现方式中，抵消电路130包括第一可调电容器131、第六开关132、第七开关133、第八开关134、第九开关135、第二可调电容器136、第十三开关137、第十四开关138和第二直流电压源139；
第一可调电容器131的一端通过第六开关132连接至第二直流电压源139，且该第一可调电容器131的一端通过第七开关133接地，第一可调电容器131的另一端连接至第一运算放大器124的反向输入端；
第二可调电容器136的一端通过第十三开关137连接至第二直流电压源139，且该第二可调电容器136的一端通过第十四开关138接地，第二可调电容器136的另一端连接至第二运算放大器128的反向输入端；
第八开关134和第九开关135用于改变控制第六开关132、第七开关133、第十三开关137和第十四开关138的开关控制信号。
在一些可能的实现方式中，该装置还包括：
可编程增益放大器140，用于根据第一待测电容器101和第二待测电容器102对应的电压信号输出差分信号。
在一些可能的实现方式中，第一直流电压源115和第二直流电压源139的输出电压相等。
在一些可能的实现方式中，该输出电压为该共模电压Vcm的两倍。
在一些可能的实现方式中，第一待测电容器和第二待测电容器是差分电容传感器中的电容器。
采用差分结构，本发明实施例的检测电容的装置具有很强的温度漂移抑制能力。
第二方面，提供了一种电子设备，包括第一方面或第一方面的任一种可能的实现方式中的检测电容的装置。
第三方面，提供了一种检测压力的装置，包括第一方面或第一方面的任一种可能的实现方式中的检测电容的装置，其中，该检测压力的装置待检测的压力关联该检测电容的装置待检测的待测电容器的电容变化。
附图说明
图1是本发明一个实施例的检测电容的装置的示意图。
图2是本发明另一个实施例的检测电容的装置的示意图。
图3是本发明实施例的检测电容的装置的工作时序图。
图4a-4c是本发明实施例的差分电容压力传感器的示意图。
图5是本发明又一个实施例的检测电容的装置的示意图。
具体实施方式
本发明实施例的技术方案可以应用于各种采用触控的设备中，例如，主动笔、电容笔、移动终端、电脑、家电等。本发明实施例的检测电容的装置可以设置于各种触控设备中，以用于检测触控电容器，即待测电容器的电容变化，进而检测由触控产生的压力变化等。
应理解，待测电容器的电容变化既可以是相对值也可以是绝对值，例如，在待测电容器的初始电容为零的情况下，待测电容器的电容变化即为其电容的绝对值。
还应理解，“电容器”也可以简称为“电容”，相应地，电容器的电容也可以称为电容值。以下为了便于描述，以电容器和电容器的电容为例进行说明。
图1示出了本发明实施例的检测电容的装置的示意图。
如图1所示，该装置可以包括打码电路110、变换电路120和抵消电路130。
打码电路110用于对至少一个待测电容器周期性充放电。
打码电路110也可以称为驱动电路，例如，可以通过开关切换，实现对待测电容器的充放电。
变换电路120用于将该至少一个待测电容器的电容信号转换为电压信号。
变换电路120为电容/电压(C/V)变换电路，例如，可以通过运算放大器以及反馈电路将电容信号转换为电压信号。
抵消电路130用于抵消该至少一个待测电容器的初始电容，以使该电压信号关联该至少一个待测电容器的电容变化。
在本发明实施例中，通过抵消电路130抵消待测电容器的初始电容(包括寄生电容)，例如，通过可调电容器抵消待测电容器的初始电容，使待测电容器的电容未变化时，输出为零，从而使变换电路120的输出信号关联待测电容器的电容变化。
采用抵消电路将初始值设置为零，从而可以提高电容检测的动态范围。
可选地，在本发明一个实施例中，该至少一个待测电容器包括第一待测电容器；
变换电路120输出的不同时刻的电压信号的差模信号表示第一待测电容器的电容变化。
具体而言，在待测电容器的数量为1时，通过变换电路120输出的不同时刻的电压信号的差模信号，反映这1个待测电容器的电容变化。
图2示出了本发明实施例的检测电容的装置的一种具体实现方式的示意图。
应理解，图2只是一种示例，而非限制本发明实施例的范围。
如图2所示，图1中的打码电路110可以包括第一开关111、第二开关112、第三开关113和第一直流电压源115。
第一待测电容器101的一端通过第三开关113和第一开关111连接至第一直流电压源115，且该端通过第三开关113和第二开关112接地，第一待测电容器101的另一端接地。
第一开关111通过第一开关控制信号(表示为PNSW)控制，第二开关112通过PNSW的反相信号
Figure PCTCN2017071490-appb-000001
控制，第三开关113通过第二开关控制信 号(表示为SW)控制。
第一开关111和第三开关113连通，第二开关112关断时，第一待测电容器101由第一直流电压源115充电。第一直流电压源115的输出电压可以表示为Vdc。
第二开关112和第三开关113连通，第一开关111关断时，第一待测电容器101放电。
如图2所示，图1中的变换电路120可以包括第四开关121、第五开关122、第一反馈电容器123和第一运算放大器124。
第四开关121通过SW的反相信号
Figure PCTCN2017071490-appb-000002
控制，第五开关122通过SW控制。
第四开关121连接于第一待测电容器101的一端和第一运算放大器124的反向输入端之间；
第一反馈电容器123连接于第一运算放大器124的反向输入端和输出端之间；
第五开关122连接于第一运算放大器124的反向输入端和输出端之间；
第一运算放大器124的同向输入端输入共模电压Vcm。
可选地，直流电压Vdc可以为共模电压Vcm的两倍，即Vcm＝0.5*Vdc。
如图2所示，图1中的抵消电路130可以包括第一可调电容器131、第六开关132、第七开关133、第八开关134、第九开关135和第二直流电压源139。
第二直流电压源139和第一直流电压源115的输出电压相等，即均为Vdc。
第八开关134通过PNSW控制，第九开关135通过PNSW的反相信号
Figure PCTCN2017071490-appb-000003
控制，第六开关132通过第三开关控制信号CSW控制，第七开关133通过CSW的反相信号
Figure PCTCN2017071490-appb-000004
控制。
第一可调电容器131的一端通过第六开关132连接至第二直流电压源139，且该端通过第七开关133接地，第一可调电容器131的另一端连接至第一运算放大器124的反向输入端；
第八开关134和第九开关135用于改变控制第六开关132和第七开关133的开关控制信号。
具体地，如图2所示，CSW和
Figure PCTCN2017071490-appb-000005
分别是第六开关132和第七开关133 的开关控制信号。第八开关134连通，第九开关135关断时，CSW等于SW；第八开关134关断，第九开关135连通时，CSW等于
Figure PCTCN2017071490-appb-000006
由CSW和
Figure PCTCN2017071490-appb-000007
再分别控制第六开关132和第七开关133。
可选地，图2中第一开关控制信号PNSW和第二开关控制信号SW可以采用如图3所示的信号。
下面结合图3描述图2所示电路的工作原理。
一个完整的电容检测周期由t1、t2、t3、t4组成。该检测时序为正负打码时序。
t1：第一开关111、第三开关113、第八开关134、第六开关132、及第五开关122闭合，第二开关112，第四开关121，第九开关135、及第七开关133断开，此刻直流电压Vdc向第一待测电容器101正向充电。
t2：第二开关112、第三开关113、第九开关135、第六开关132、及第五开关122断开，第一开关111、第四开关121、第八开关134、及第七开关133闭合，此刻，第一待测电容器101上电荷向第一反馈电容器123及第一可调电容器131上转移。此时Vout输出为：
Figure PCTCN2017071490-appb-000008
其中，C1表示第一待测电容器101的电容，Cfb表示第一可调电容器131的电容，Cc表示第一反馈电容器123的电容。
t3：第二开关112、第三开关113、第九开关135、第七开关133、及第五开关122闭合，第一开关111、第四开关121、第八开关134、及第六开关132断开，此刻第一待测电容器101短接到地，第一可调电容器131反向充电。
t4:第一开关111、第三开关113、第八开关134、第七开关133、及第五开关122断开，第二开关112、第四开关121、第九开关135、及第六开关132闭合，此刻，第一反馈电容器123和第一可调电容器131上电荷向第一待测电容器101上转移。此时Vout输出为：
Figure PCTCN2017071490-appb-000009
后级采样电路可通过在t2和t4位置对Vout输出进行采样并相减得出差模信号大小：
Figure PCTCN2017071490-appb-000010
在初始状态，可通过调节第一可调电容器131的电容大小使Cc＝0.5C10。这样，初始电容C10被完全抵消掉，从而输出差模信号大小：
Figure PCTCN2017071490-appb-000011
其中，ΔC表示第一待测电容器101的电容的变化。
由上述分析可知，采用正负打码的工作时序，本发明实施例的检测电容的装置具有很强的低频共模噪声和1/f噪声(也称为闪烁噪声)抑制能力。也就是说，本发明实施例的检测电容的装置能够提高抗干扰性能，这样，当待测电容发生微小变化时，也能够检测到。因此，本发明实施例的检测电容的装置能够检测出微小电容变化，能够提高电容检测的精确度。
另外，本发明实施例的上述抵消电路可以完全抵消初始电容，具有较高的抵消效率。
可选地，在本发明另一个实施例中，该至少一个待测电容器包括第一待测电容器和第二待测电容器；
变换电路120输出的第一待测电容器和第二待测电容器对应的电压信号的差分信号表示第一待测电容器和第二待测电容器的电容变化。
具体而言，在待测电容器的数量为2时，通过变换电路120输出的两个待测电容器对应的电压信号的差分信号，反映两个待测电容器的电容变化。
可选地，对于第一待测电容器和第二待测电容器的电容，可以其中一个待测电容器的电容是变化的，另一个待测电容器的电容是不变化的，不变化的电容可以是标准电容；第一待测电容器和第二待测电容器也可以构成差分电容传感器，即可以是差分电容传感器中的两个电容器。例如，该差分电容传感器可以是差分电容压力传感器。
以差分电容压力传感器为例，图4a-4c分别示出了三种差分电容压力传感器的示意图。如图4a-4c所示，向差分电容压力传感器施加压力，将会引起中间电极片形变或者位移，从而引起电容C1增大，C2减小，形成差分的ΔC。ΔC为C1和C2的变化量之和。
图5示出了本发明实施例的检测电容的装置的另一种具体实现方式的示意图。
应理解，图5只是一种示例，而非限制本发明实施例的范围。
如图5所示，图1中的打码电路110可以包括第一开关111、第二开关 112、第三开关113、第十开关114和第一直流电压源115。
第一开关111通过第一开关控制信号PNSW控制，第二开关112通过PNSW的反相信号
Figure PCTCN2017071490-appb-000012
控制，第三开关113和第十开关114通过第二开关控制信号SW控制。
第一待测电容器101的一端通过第三开关113和第一开关111连接至第一直流电压源115，且该端通过第三开关113和第二开关112接地，第一待测电容器101的另一端接地。
第二待测电容器102的一端通过第十开关114和第一开关111连接至第一直流电压源115，且该端通过第十开关114和第二开关112接地，第二待测电容器102的另一端接地。
第一开关111、第三开关113和第十开关114连通，第二开关112关断时，第一待测电容器101和第二待测电容器102由第一直流电压源115充电；
第二开关112、第三开关113和第十开关114连通，第一开关111关断时，第一待测电容器101和第二待测电容器102放电。
如图5所示，图1中的变换电路120可以包括第四开关121、第五开关122、第一反馈电容器123、第一运算放大器124、第十一开关125、第十二开关126、第二反馈电容器127和第二运算放大器128。
第四开关121和第十一开关125通过SW的反相信号
Figure PCTCN2017071490-appb-000013
控制，第五开关122和第十二开关126通过SW控制。
第四开关121连接于第一待测电容器101的一端和第一运算放大器124的反向输入端之间；
第一反馈电容器123连接于第一运算放大器124的反向输入端和输出端之间；
第五开关122连接于第一运算放大器124的反向输入端和输出端之间；
第十一开关125连接于第二待测电容器102的一端和第二运算放大器128的反向输入端之间；
第二反馈电容器127连接于第二运算放大器128的反向输入端和输出端之间；
第十二开关126连接于第二运算放大器128的反向输入端和输出端之间；
第一运算放大器124和第二运算放大器128的同向输入端均输入共模电压Vcm。
如图5所示，图1中的抵消电路130包括第一可调电容器131、第六开关132、第七开关133、第八开关134、第九开关135、第二可调电容器136、第十三开关137、第十四开关138和第二直流电压源139。
第八开关134通过PNSW控制，第九开关135通过PNSW的反相信号
Figure PCTCN2017071490-appb-000014
控制，第六开关132和第十三开关137通过开关控制信号CSW控制，第七开关133和第十四开关138通过CSW的反相信号
Figure PCTCN2017071490-appb-000015
控制。
第一可调电容器131的一端通过第六开关132连接至第二直流电压源139，且该端通过第七开关133接地，第一可调电容器131的另一端连接至第一运算放大器124的反向输入端；
第二可调电容器136的一端通过第十三开关137连接至第二直流电压源139，且该端通过第十四开关138接地，第二可调电容器136的另一端连接至第二运算放大器128的反向输入端；
第八开关134和第九开关135用于改变控制第六开关132、第七开关133、第十三开关137和第十四开关138的开关控制信号。
可选地，图5中第一开关控制信号PNSW和第二开关控制信号SW可以采用如图3所示的信号。图5中电路的工作时序可以与图2相同。
应理解，图5中分别对应于第一待测电容器101和第二待测电容器102的两路电路中的每一路的工作原理与图2中的电路的工作原理类似。
可选地，图5所示的装置可用于压力传感器。在这种情况下，第一待测电容器101和第二待测电容器102可以是压力传感器中的两个电容器，例如，可以是图4a-4c中的C1和C2。通过图5所示的装置可以检测到第一待测电容器101和第二待测电容器102的电容变化，进而得到压力的变化。
在初始状态，可通过调节第一可调电容器131和第二可调电容器136的电容，使差分输出电压为零。当第一待测电容器101和第二待测电容器102的电容变化时，例如施加压力时，输出差分电压为：
Figure PCTCN2017071490-appb-000016
其中，ΔC表示第一待测电容器101和第二待测电容器102的变化量之和。也就是说，输出差分电压可以表示两个待测电容器的电容变化。
可选地，如图5所示，该装置还可以包括：
可编程增益放大器140，用于根据第一待测电容器101和第二待测电容 器102对应的电压信号输出差分信号。
利用可编程增益放大器140输出差分信号，并可以稳定差分输出的共模电压。
采用差分结构，本发明实施例的检测电容的装置具有很强的温度漂移抑制能力。
可选地，还可以对电路输出进行多次积分平均，以有效提高系统性噪比，提高检测精度，尤其针对待测电容器的电容为fF～pF级的微小电容的情况。
可选地，可以采用模拟积分方案，即增加一级积分电路或改变检测电路时序以增加C/V变换电路的积分次数，然后再进行模数转换器(Analog-to-Digital Converter，ADC)采样。也可以采用数字积分方案，即检测电路输出直接送入ADC进行采样，然后通过数字处理器对采样数据进行积分处理。
综上所述，本发明实施例的检测电容的装置，采用正负打码的工作时序，能有效抑制低频噪声和1/f噪声；采用差分结构，具有温飘抑制能力，零点漂移抑制能力；采用受开关控制信号控制的开关与电容器组成的开关电容电路，具有较低的功耗；从而可以使该装置具有高信噪比，便于集成电路(integrated circuit，IC)集成，并且具有较高的检测灵敏度，其可以检测到fF级的电容。
本发明实施例还提供了一种电子设备，该电子设备可以包括上述本发明实施例的检测电容的装置。
本发明实施例还提供了一种检测压力的装置，该检测压力的装置可以包括上述本发明实施例的检测电容的装置，其中，该检测压力的装置待检测的压力关联该检测电容的装置待检测的待测电容器的电容变化。
例如，该检测压力的装置具体可以为压力传感器，该压力传感器可以设置于触控笔中，但本发明实施例对此并不限定。
应理解，本文中的具体的例子只是为了帮助本领域技术人员更好地理解本发明实施例，而非限制本发明实施例的范围。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执 行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (14)

  1. 一种检测电容的装置，其特征在于，包括：
    打码电路(110)，用于对至少一个待测电容器周期性的充放电；
    变换电路(120)，用于将所述至少一个待测电容器的电容信号转换为电压信号；
    抵消电路(130)，用于抵消所述至少一个待测电容器的初始电容，以使所述电压信号关联所述至少一个待测电容器的电容变化。
  2. 根据权利要求1所述的装置，其特征在于，所述至少一个待测电容器包括第一待测电容器(101)；
    所述变换电路(120)输出的不同时刻的电压信号的差模信号表示所述第一待测电容器(101)的电容变化。
  3. 根据权利要求2所述的装置，其特征在于，所述打码电路(110)包括第一开关(111)、第二开关(112)、第三开关(113)和第一直流电压源(115)；
    所述第一待测电容器(101)的一端通过所述第三开关(113)和所述第一开关(111)连接至所述第一直流电压源(115)，且所述第一待测电容器(101)的一端通过所述第三开关(113)和所述第二开关(112)接地，所述第一待测电容器(101)的另一端接地。
  4. 根据权利要求2或3所述的装置，其特征在于，所述变换电路(120)包括第四开关(121)、第五开关(122)、第一反馈电容器(123)和第一运算放大器(124)；
    第四开关(121)连接于所述第一待测电容器(101)的一端和所述第一运算放大器(124)的反向输入端之间；
    所述第一反馈电容器(123)连接于所述第一运算放大器(124)的反向输入端和输出端之间；
    所述第五开关(122)连接于所述第一运算放大器(124)的反向输入端和输出端之间；
    所述第一运算放大器(124)的同向输入端输入共模电压Vcm。
  5. 根据权利要求4所述的装置，其特征在于，所述抵消电路(130)包括第一可调电容器(131)、第六开关(132)、第七开关(133)、第八开关(134)、第九开关(135)和第二直流电压源(139)；
    所述第一可调电容器(131)的一端通过所述第六开关(132)连接至所述第二直流电压源(139)，且所述第一可调电容器(131)的一端通过所述第七开关(133)接地，所述第一可调电容器(131)的另一端连接至所述第一运算放大器(124)的反向输入端；
    所述第八开关(134)和所述第九开关(135)用于改变控制所述第六开关(132)和所述第七开关(133)的开关控制信号。
  6. 根据权利要求1所述的装置，其特征在于，所述至少一个待测电容器包括第一待测电容器(101)和第二待测电容器(102)；
    所述变换电路(120)输出的所述第一待测电容器(101)和所述第二待测电容器(102)对应的电压信号的差分信号表示所述第一待测电容器(101)和所述第二待测电容器(102)的电容变化。
  7. 根据权利要求6所述的装置，其特征在于，所述打码电路(110)包括第一开关(111)、第二开关(112)、第三开关(113)、第十开关(114)和第一直流电压源(115)；
    所述第一待测电容器(101)的一端通过所述第三开关(113)和所述第一开关(111)连接至所述第一直流电压源(115)，且所述第一待测电容器(101)的一端通过所述第三开关(113)和所述第二开关(112)接地，所述第一待测电容器(101)的另一端接地；
    所述第二待测电容器(102)的一端通过所述第十开关(114)和所述第一开关(111)连接至所述第一直流电压源(115)，且所述第二待测电容器(102)的一端通过所述第十开关(114)和所述第二开关(112)接地，所述第二待测电容器(102)的另一端接地。
  8. 根据权利要求6或7所述的装置，其特征在于，所述变换电路(120)包括第四开关(121)、第五开关(122)、第一反馈电容器(123)、第一运算放大器(124)、第十一开关(125)、第十二开关(126)、第二反馈电容器(127)和第二运算放大器(128)；
    第四开关(121)连接于所述第一待测电容器(101)的一端和所述第一运算放大器(124)的反向输入端之间；
    所述第一反馈电容器(123)连接于所述第一运算放大器(124)的反向输入端和输出端之间；
    所述第五开关(122)连接于所述第一运算放大器(124)的反向输入端 和输出端之间；
    第十一开关(125)连接于所述第二待测电容器(102)的一端和所述第二运算放大器(128)的反向输入端之间；
    所述第二反馈电容器(127)连接于所述第二运算放大器(128)的反向输入端和输出端之间；
    所述第十二开关(126)连接于所述第二运算放大器(128)的反向输入端和输出端之间；
    所述第一运算放大器(124)和所述第二运算放大器(128)的同向输入端均输入共模电压Vcm。
  9. 根据权利要求8所述的装置，其特征在于，所述抵消电路(130)包括第一可调电容器(131)、第六开关(132)、第七开关(133)、第八开关(134)、第九开关(135)、第二可调电容器(136)、第十三开关(137)、第十四开关(138)和第二直流电压源(139)；
    所述第一可调电容器(131)的一端通过所述第六开关(132)连接至所述第二直流电压源(139)，且所述第一可调电容器(131)的一端通过所述第七开关(133)接地，所述第一可调电容器(131)的另一端连接至所述第一运算放大器(124)的反向输入端；
    所述第二可调电容器(136)的一端通过所述第十三开关(137)连接至所述第二直流电压源(139)，且所述第二可调电容器(136)的一端通过所述第十四开关(138)接地，所述第二可调电容器(136)的另一端连接至所述第二运算放大器(128)的反向输入端；
    所述第八开关(134)和所述第九开关(135)用于改变控制所述第六开关(132)、所述第七开关(133)、所述第十三开关(137)和所述第十四开关(138)的开关控制信号。
  10. 根据权利要求6至9中任一项所述的装置，其特征在于，所述装置还包括：
    可编程增益放大器(140)，用于根据所述第一待测电容器(101)和所述第二待测电容器(102)对应的电压信号输出差分信号。
  11. 根据权利要求5或9所述的装置，其特征在于，所述第一直流电压源(115)和所述第二直流电压源(139)的输出电压相等。
  12. 根据权利要求11所述的装置，其特征在于，所述输出电压为所述 共模电压Vcm的两倍。
  13. 一种电子设备，其特征在于，包括根据权利要求1至12中任一项所述检测电容的装置。
  14. 一种检测压力的装置，其特征在于，包括根据权利要求1至12中任一项所述检测电容的装置，其中，所述检测压力的装置待检测的压力关联所述检测电容的装置待检测的待测电容器的电容变化。
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