WO2021013961A1 - Housing element for a housing of a power semiconductor module - Google Patents

Housing element for a housing of a power semiconductor module Download PDF

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Publication number
WO2021013961A1
WO2021013961A1 PCT/EP2020/070869 EP2020070869W WO2021013961A1 WO 2021013961 A1 WO2021013961 A1 WO 2021013961A1 EP 2020070869 W EP2020070869 W EP 2020070869W WO 2021013961 A1 WO2021013961 A1 WO 2021013961A1
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WO
WIPO (PCT)
Prior art keywords
power semiconductor
void
housing
electrically conducting
housing element
Prior art date
Application number
PCT/EP2020/070869
Other languages
French (fr)
Inventor
Andrey Petrov
Chunlei Liu
Slavo Kicin
Jacim JACIMOVIC
Francisco Garcia-Ferre
Original Assignee
Abb Power Grids Switzerland Ag
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Filing date
Publication date
Application filed by Abb Power Grids Switzerland Ag filed Critical Abb Power Grids Switzerland Ag
Publication of WO2021013961A1 publication Critical patent/WO2021013961A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
    • H01L24/65—Structure, shape, material or disposition of the connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Definitions

  • the present invention relates to a housing element for a housing of a power semi conductor module.
  • the present invention particularly relates to a housing element comprising a main body formed from a ceramic material, wherein the main body comprises a two- or three-dimensional void network.
  • the present invention also relates to a power semiconductor module comprising a housing, wherein the hous ing comprises the above housing element. Furthermore, the present invention re lates to a method for producing the above housing element.
  • Power semiconductor modules are generally widely known in the art. Conventional power semiconductor modules are complex assemblies comprising many different components, each dedicated to perform a specific function.
  • a typical power semi conductor module is shown in figure 1. It may comprise a heat sink 1 as cooling structure with vapor chambers 2. The heat sink 1 may be attached to a base plate 3 with thermal paste 4.
  • the baseplate 3 may comprise a metal matrix composite comprising an aluminum matrix with silicon carbide particles, or a copper or alumi num composite, for high thermal conductivity and matching of thermal expansion coefficient.
  • DBC layer 5 On top of the baseplate 3 there may be a direct bonded copper layer 5, also ab breviated as DBC layer 5 that may be attached to the baseplate 3 by an interme diary solder layer 6.
  • the DBC layer 5 may comprise a bottom metal layer 7, a middle ceramic layer 8 as insulation, and a top metal layer 9.
  • the top metal layer 9 may form part of an electric circuit of the power semiconductor module.
  • Power semiconductor devices 10 may either be soldered or sintered to the top metal lay- er 9.
  • the power semiconductor devices 10 may be connected with each other and/or with the top metal layer 9 by a bond wire connection 11.
  • the power semiconductor devices 10 of the power semiconductor module produce heat that needs to be dissipated in order to maintain the functionality of the power semiconductor module.
  • US 2016/322333 describes an electronic module comprising an interposer com prising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encap sulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically iso lating material.
  • EP 3 171 678 A1 describes a printed circuit board including a body and a belly pad seated within with the body.
  • the belly pad is electrically separated into a first pad and a second pad.
  • the first pad and the second pad are arranged to be electrically connected to one another by an interconnect electrically connecting the belly pad to a conductive plane of an electrical component, thereby allowing continuity test ing across an interface between the first pad and the interconnect.
  • JP 2005303209 A describes a concave part being formed approximately in the center of the bottom surface of a circuit substrate where a specified circuit pattern is formed, and a pyrogenic power is mounted in the concave part. Further, in a first concave portion at the opening of the concave part, a metal cap is installed, which is connected externally to a grounding electrode. Sandwiched by the surface op posed to the power mounting surface and the metal cap, a graphite film is provid ed that has good heat conductance and high electrical conductivity as well as, fur thermore, being flexible.
  • a housing element for a housing of a power semiconductor module, wherein the power semiconductor module comprises at least one power semicon ductor device, wherein the housing element comprises a main body, wherein the main body is formed from a ceramic material, wherein the main body comprises a two- or three-dimensional void network, wherein the two- or three-dimensional void network comprises at least one first void, wherein the at least one first void is adapted for providing at least one electrically conducting structure, and wherein at least a part of the electrically conducting structure is adapted for contacting at least one power semiconductor device.
  • Such a housing element provides significant advantages over solutions of the prior art, especially with regard to a higher freedom of design of the electric circuit of the power semiconductor module and it may further provide an efficient cooling behav ior of the power semiconductor device.
  • the present invention thus refers to a housing element.
  • the housing element may be a one piece housing element, a two piece housing element or a multi-piece housing element.
  • the housing element of the present invention may as such form the housing of the power semiconductor module.
  • the housing element of the present invention may be a part of the housing of the power semiconductor module.
  • the housing of the power semiconductor module may comprise one housing element, two housing elements, or several housing ele ments.
  • the housing of the power semiconductor module may also comprise additional pieces.
  • the different housing elements may be formed identically to each other, similarly to each other, or differently to each oth er.
  • the housing element of the present invention comprises the main body formed from a ceramic material, wherein the main body comprises the two- or three- dimensional void network.
  • a network is thus formed from one void or prefer ably from a plurality of voids.
  • the voids may be holes, pores and/or pipes in the main body.
  • the voids are structures in the main body which are free of the ceramic material. The holes, pores and/or pipes thus form the two- or three- dimensional void network.
  • the two- or three-dimensional void network or the voids thereof, respectively, may be interconnected or partially interconnected.
  • the hole and the tube may form one continuous hollow space in the main body.
  • Partially interconnected may indicate that there may be an additional void that may not have an interconnection to an other void. Instead said void may be enclosed by the ceramic material.
  • a void of the two- or three-dimensional network is located on or near the surface of the main body. In this case the void may be represented by a cavity and/or a depression in the surface of the main body.
  • the ex- pression“two- or three-dimensional void network” may mean that the network formed by the voids extends in two dimensions of space or preferably in all three dimensions of space.
  • the two- or three-dimensional void network may be a two-dimensional network or preferably a three-dimensional network.
  • the two- or three-dimensional void network comprises the at least one first void, that is adapted for providing at least one electrically conducting structure. At least a part of the electrically conducting structure is adapted for contacting at least one power semiconductor device of the power semiconductor module. Preferably, the electrically conducting structure is adapted for directly electrically contacting at least one power semiconductor device of the power semiconductor module. In other words, there may be no additional connecting piece or connecting layer in between the electrically conducting structure and the power semiconductor mod ule so that the electrically conducting structure may come in direct contact to the power semiconductor device. Preferably, the electrically conducting structure is adapted to conduct an electrical signal.
  • the electrically conducting structure may be embedded in part of the two- or three-dimensional void network. In other words the two- or three-dimensional void network allows integration of the electrically conducting structure into the main body.
  • the housing element and/or the power semiconductor module comprising said housing element may thus have no layered structure as is known from conven tional power semiconductor modules.
  • the main body comprises the two- or three-dimensional void network, which in part is adapted for providing the elec trically conducting structure. Therefore, it is possible that an additional baseplate and/or an additional substrate is omitted.
  • the present invention may thus be advantageous over conventional power semi conductor modules having layered structures, where the different layers often comprise different types of materials.
  • the DBC layer may comprise a bottom metal layer, a middle ceramic layer, and a top metal layer.
  • An important parameter of the middle ceramic layer may be the coefficient of thermal expansion (CTE), which indicates how much the middle ceramic layer and therefore the DBC layer expands or contracts by a change of temperature.
  • CTE coefficient of thermal expansion
  • a mismatch of the CTE of the ceramic layer with the CTE of the power semiconductor device, the solder, and/or the baseplate, may be a major cause for failures of conventional power semiconductor modules. The origin of these failures may be fatigue induced by the cyclic nature of the load to the power semiconductor module, and consequently cyclic heat generation. This problem, however, may be overcome by the present invention.
  • the layered structure of conven tional power semiconductor modules may lead to a reduced cooling efficiency of the power semiconductor device.
  • the cooling behavior may be increased by a housing element of the present inven tion as it may serve directly as substrate and cooling means like described below, without a layer structure to be required. Consequently the lifetime of a convention al power semiconductor module may be improved according to the present inven tion.
  • the operation temperature of conventional power semiconductor modules may be limited to a temperature of around 150 to 175 °C.
  • the integration of the electrically conducting structure into the main body allows for direct heat take off from the electrically conducting structure into the ceramic material of the main body. This may improve heat dissipation and reduce tempera ture oscillation amplitude under cyclic load of the power semiconductor module.
  • the ceramic material may have a high thermal conductivity and good electrical insulation properties, and may comprise for example silicon nitride, aluminum ni- tride, aluminum oxide or boron nitride.
  • the improved heat dissipation and lower amplitude of temperature oscillations may allow for high power density and may increase the lifetime of the power semiconductor module.
  • the main body formed by the ceramic material may not only perform two functions also known from conventional power semiconductor modules, namely CTE-matching and electrical insulation, but the main body may also act as a heat spreading device.
  • the ceramic material of the main body may be in direct contact with the electrically conducting structure. Therefore, it is able to efficiently spread heat from the power semiconductor device to the whole surface of the main body.
  • the main body may be connected to a heatsink. Therefore, by reduc ing the number of layers, the thermal resistance between the power semiconduc tor device and the heat sink may be reduced, improving the reliability and lifetime of the power semiconductor module.
  • Conventional power semiconductor modules with a layered structure may not only have thermal issues but may also have issues with parasitic currents in neighbor ing electric devices, generated by inductance. High electric current which flows through electric contacts may induce undesired parasitic currents in neighboring electric devices e.g. gate control and power contacts.
  • the layered struc ture of conventional power semiconductor modules only allows for a two- dimensional design of the electric circuit, therefore the capability to reduce the im pact of inductance on neighboring electric devices by the electric circuit design may be limited.
  • the bond wire joints of conventional power semiconductor modules may be especially prone to thermal stress due to weak joint areas and may thus be a potential reason for failure of the power semiconductor module.
  • the electrically conducting structure forming the electric circuit may also be three dimensional. Therefore, a design for the electric circuit may be chosen that reduces the inductance on neighboring electric devices. Wire bond connections may thus be omitted or their number may at least be re Jerusalem.
  • the ceramic material of the main body may also provide the function of an electric circuit housing.
  • the ceramic material may be in direct contact with the electrically conducting structure, therefore reducing the number of bond wire joints in the power semiconductor module. Hence the number of weak joint areas may be reduced, which in turn may improve the reliability and lifetime of the power semiconductor module.
  • the two- or three-dimensional void network in the main body may increase the freedom in electric circuit design, which in turn may reduce inductance and promote efficiency. Furthermore, the number of bond wire joints may be reduced, therefore reducing the danger of wire failures. The possible re duction of the number of layers of the power semiconductor module may reduce thermal resistance. Apart from the above, by allowing the electrically conducting structure to be embedded into the ceramic material, the heat dissipation may be intensified.
  • the two- or three-dimensional void network additionally comprises at least one second void, wherein the at least one second void may be adapted for providing a cooling structure.
  • the main body may not only comprise the at least one first void for providing the at least one electrically conducting structure, but also the at least one second void for providing the cool ing structure.
  • the cooling structure is adapted for dissipating heat from the main body. It may be possible that the cooling structure is directly formed by a part of the two- or three-dimensional void network. In other words, the cooling structure may be integrated in the main body. The integration of the cooling struc ture into the ceramic material allows for direct heat take-off from the ceramic mate rial and therefore from the main body.
  • the integration of the cooling structure in the main body of the housing element may enable to design the cooling structure adapted to the cooling needs of the power semiconductor module and/or adapted to the electrically con ducting structure also being present.
  • double-sided cooling of the power semiconductor device may be possible.
  • the two- or three- dimensional void network may comprise the at least one first void and the at least one second void. More preferably the at least one first void and the at least one second void may form distinct two- or three-dimensional networks. In other words the at least one first void and the at least one second void may not be connected to each other.
  • the main body is formed by the ceramic material.
  • the ce ramic material may have a high thermal conductivity and good electrical insulation properties.
  • the composition of the ceramic material may be chosen in order to match the CTE of the power semiconductor module.
  • the ceramic material may comprise a material selected from the group consisting of silicon nitride, aluminum nitride, aluminum oxide or boron ni tride, for example.
  • the ceramic material may be provided with or without a sinter ing additive like, for instance, an alkali additive.
  • a housing element may be provided wherein at least one void of the two- or three-dimensional void network, and thus particularly at least one of the first voids and the second voids, at least in part has a diameter that is equal to or less than 500 pm.
  • the respective void or voids may have the form of a pipe having a length and a diameter, with the diameter being smaller than the length.
  • the diameter of the pipe may be equal to or smaller than 500 pm, for example 150 pm. This does not exclude that there may be another size of the voids that may be larger than 500 pm.
  • the length of the pipe may be in the range between 1 mm to 100 mm.
  • the lower border of the di ameter may generally be chosen in dependence of the desired need, e.g. if the respective void is used for forming a cooling structure or an electrically conducting structure and thus the respective working requirements and may be chosen by the person skilled in the art without problems.
  • a diameter of a void shall be defined by the maximum diameter of a sphere that can be placed in the void. Therefore, the void diameter is meant to be understood in a three-dimensional manner and shall mean that in no direction, the diameter is smaller than the defined value.
  • the cross-section of a void such as of a pipe, may be circular, oval, rectangular or may have a more complex-shape, like for instance H-beam or cross.
  • Preferably the cross-section is rectangular with the a/b ratio (sides ratio) of greater than 2.
  • Such cross-section normally allows for reduction of the skin-effect and overall in ductance losses, especially at high current frequencies.
  • the voids of the two- or three-dimensional void network that may have at least in part a diameter that is equal to or less than 500 pm comprise the at least one first void.
  • the electrically conducting structure may also have at least in part a diameter that is equal to or smaller than 500 pm. Having such a diameter may increase heat dissipation form the electrically conducting structure into the ceramic material, since the surface-area-to-volume ratio, may be higher.
  • a diameter that is equal to or less than 500 pm may lead to an increased design freedom and enables miniaturization of the power semicon ductor module. Also it allows for having more electrically conducting structures per volume of the main body, allowing more power semiconductor devices to be con tacted independently of each other.
  • the at least one first void is adapted for providing the at least one electrically conducting structure.
  • a housing element may be provided wherein the housing element comprises the at least one electrically conducting structure, and wherein the at least one electrically conducting structure is formed by an electrically conducting material that is contained at least in a part of the at least one first void.
  • the electrically conducting material may be contained in the complete first void or in the complete first voids in particular when the first void is formed as a tube or channel.
  • An electrically conducing material may be a material having an electrical conductivity of at least 10 5 S/m, such as of at least 10 6 S/m at 20 °C, these values being understood in an exemplary manner.
  • the electrically conducting material has an electrical conductivity of at least 10 7 S/m at 20 °.
  • the electrically conducting material comprises a metal.
  • the electrically conducting material may comprise copper or an alloy thereof, aluminum or an alloy thereof, tungsten, silver, gold or molybdenum.
  • the electrical conductivity of a material may be an important property of the mate rial that quantifies the material's ability to conduct an electric current.
  • the electrical conductivity may be measured in siemens per metre (S/m).
  • the electrically conducting material may be contained at least in a part of the pores, holes, and/or pipes of the first void of the main body.
  • the electrically conducting structure is formed by the electrically conducting material that is contained at least in a part of the pores, holes, and/or pipes.
  • the electrically conducting structure may be formed by a pipe of the main body that is filled with the electrically conducting material. Therefore the electrically conduct ing structure, that may be formed by the electrically conducting material contained in the at least one first void, may have the same outer shape as the inner shape of the at least one first void containing the electrically conducting material. This may have the advantage that the electrically conducting structure may have a very complex two- or three-dimensional shape, such as three-dimensional shape.
  • the electrically conducting structure may be efficiently protected by the main body. Therefore, the lifetime of the electrically conducting structure may be increased.
  • the housing element comprises at least one cooling structure, wherein the at least one cooling structure comprises at least one of a vapor chamber, a cooling channel, and a heat pipe, and wherein the cooling struc ture is formed at least in part by the at least one second void.
  • the cooling structure is adapted to dissipate heat from the main body.
  • the cooling structure is formed at least in part by the at least one second void and thus for example by pores, holes, and/or pipes of the main body, the heat may be guided into the ceramic material of the main body therefore also the cooling struc ture may be embedded in the ceramic material.
  • the at least one second void of the main body that may form the cooling structure may be connected to a heat sink. Therefore also the cooling structure may be connected to a heat sink. This may allow for a very efficient cooling of the main body and in turn of the power semiconductor module.
  • the cooling structure may comprise a vapor chamber, a cooling channel and/or a heat pipe.
  • a vapor chamber Preferably, the vapor chamber, the cooling channel and/or the heat pipe are formed by the pores, holes, and/or pipes of the main body. More preferably, the vapor chamber, the cooling channel and/or the heat pipe are embedded in the ce ramic material.
  • the housing element With regard to further advantages and technical features of the housing element, it is referred to the power semiconductor module, the method for producing a hous ing element, the figures and the further description.
  • the present invention further relates to a power semiconductor module comprising a housing wherein the housing comprises at least one housing element as de scribed above.
  • Such a power semiconductor module provides significant advantages over solu tions of the prior art, especially with regard to at least one of lifetime, reliability, freedom of design of the electric circuit and cooling efficiency.
  • the housing of the power semiconductor device forms a press pack housing.
  • the power semiconductor device may either be soldered or sintered to the top metal layer of the DBC layer.
  • the solder may comprise a low-melting alloy, thus the operation temperature of conventional power semiconductor modules may be limited to a temperature of around 150 to 175 °C.
  • the pow- er semiconductor device may be hold in place by a force acting on the power sem iconductor device exerted from the housing.
  • the housing comprises one housing element like described above and an additional element and the power semiconductor device is sand wiched in between the housing element and the additional element.
  • the housing comprises two housing elements as de scribed above, and the two housing elements sandwich the power semiconductor device in between.
  • the force applied on the power semiconductor device may be due to the gravitational force of the upper housing element or of the upper addi tional element, respectively. It may also be possible that the two housing elements or the housing element and the additional element are pressed together by pole- pieces.
  • the force applied on the power semiconductor device may be due to a spring in the power semiconductor module.
  • the spring may be in between the two housings elements or in between the housing element and the additional element.
  • the spring may lead to the advantage that the force applied on the power semiconductor device may be adjusted by the spring con stant.
  • the spring may act as an independent suspension, so that only a certain force is applied to the power semiconductor device.
  • it may be possi ble to use sintering process to physically attach the housing elements, or use pol ymer- or silica glass-based bonding.
  • the power semiconductor module comprises at least one power semiconductor device, and wherein the power semiconductor de vice is encapsulated by the housing.
  • the housing may be formed by one housing element like described above. More over, it is possible that the housing is formed by two housing elements like de scribed above. It is even possible that the housing is formed by several housing elements e.g. three four or more housing elements like described above.
  • the different housing elements may be formed identically to each oth er, similarly to each other, or differently to each other, wherein at least one hous ing element is formed like described above.
  • one of the housing elements may comprise the at least one cooling structure and the at least one electrically conducting structure, while the other housing element may only comprise the at least one electrically conducting structure.
  • the two- or three-dimensional void network of the two housing elements may have an identical, a similar, or a different design.
  • the at least one power semiconductor device is encapsulated by the housing.
  • the at least one power semiconductor device may be in contact to the housing element on at least two sides of the power semiconductor device.
  • the at least one power semiconductor device of the power semiconductor module may be in direct electrical contact to the at least one electrically conduct ing structure of the housing element.
  • the electrically conducting structure may be directly contacted to the power semiconductor device, thus there may be no additional connecting pieces or layers in between the at least one pow er semiconductor device and the electrically conducting structure.
  • This may also mean that the at least one first void that is adapted for providing the at least one electrically conducting structure, may also extend to the power semiconductor de vice.
  • the layered structure of conventional power semiconductor modules where the different layers often comprise different types of materials may have some issues. Therefore, by omitting additional layers, these disadvantages including different CTEs of different materials or upper limits of the operating tem perature due to low melting alloys may be overcome.
  • the power semiconductor device comprises a first side and a second side, wherein the first side is located opposite to the second side, and wherein a cooling structure of the housing element is located adjacent to the first side and wherein a cooling structure of the housing element is located ad jacent to second side of the power semiconductor device.
  • the first side may com prise one or more upper contacts of the power semiconductor device, such as the emitter and/or gate and the second side may comprise one or more lower contacts of the power semiconductor device, such as the collector.
  • the cooling structure is adapted for dissipating heat from the at least one power semiconductor device.
  • the power semiconductor device may have the form of a cuboid. Having a cooling structure adjacent to the first side and adjacent to the second side of the power semiconductor device may mean that the power semiconductor device is located in between cooling structures.
  • the power semiconductor device is sandwiched in between the two cooling structures and thus a cooling structure is provided adjacent to the first side and thus opposing to the second side and a cooling structure is provided adjacent to the second side and thus op posing to the first side of the power semiconductor module.
  • a double sided cooling of the power semiconductor device may increase heat dissipation tremendously.
  • the housing element the method for producing a housing element, the figures, and the further description.
  • the present invention further relates to a method for producing the above de scribed housing element.
  • the method comprises the step of a) forming a main body from a ceramic material preferably by layer manufacturing, wherein the main body comprises a two- or three-dimensional void network, wherein the two- or three-dimensional void network comprises at least one first void, and wherein the at least one first void is adapted for providing the at least one electrically conduct ing structure.
  • the main body of the housing element is produced by a layer manufacturing step.
  • Layer manufacturing may be a process where the de- sired shape of the main body is not produced by removing material but by adding material in successive layers. In such processes, the material may be joined or solidified to create a two- or three-dimensional object, i.e. the main body and thus the housing element.
  • Using layer manufacturing allows producing complex two- or three-dimensional shapes and structures with a high precision. Therefore, the housing element, the main body, the two- or three-dimensional void network in the main body, the electrically conducting structure and/or the cooling structure may be easily and precisely produced.
  • material extrusion may be used.
  • a feedstock material may be pushed through an extruder.
  • a ceramic slurry that may comprise a binder mixture may be used as feedstock material.
  • powder bed fusion as additive manufacturing may be used. Powder bed fusion additive manufacturing may designate a process in which thermal energy, for example from a laser or an electron beam, selectively fuses regions of a powder bed.
  • directed energy deposition as addi tive manufacturing process may be used in which focused thermal energy may fuse materials by melting them as they are being deposited.
  • additive manufacturing may be used as layer manufacturing technique.
  • a ceramic slurry may be used.
  • a two-step process can be used, where first the ceramic green body is produced preferably by an ad ditive manufacturing technique like stereolithography, fused deposition modeling or binder-jetting, and as a second step, the ceramic green body is sintered prefer ably in a furnace to yield the above described ceramic housing.
  • the sintering step may be realized in a furnace under controlled gas atmosphere and at temperature typically above 900°C to yield the said ceramic main body. Locations in the main body where no ceramic slurry is extruded form the two- or three-dimensional net work of voids.
  • physical vapor deposition may be used which may be a variety of vacuum deposition methods to produce the main body and thus the housing element.
  • a material may go from a con densed phase to a vapor phase and then back to a condensed phase.
  • the method comprises a multi-material layer manu facturing step such, that the main body and the electrically conducting structure are formed in a single and thus common manufacturing step, i.e. in the multi material manufacturing step.
  • different types of materials may be deposited in the same process step to produce the main body and the electrically conducting structure simultaneously.
  • a multi-material deposition and/or multi-material printing may be used where dif ferent types of materials are deposited in the same process step, to produce the housing element.
  • Multi-material deposition and/or multi-material printing allows objects to be composed of complex and heterogeneous arrangements of materi als.
  • the ceramic material and the electrically conducting material that may form the electrically conducting structure may be deposited together in one common process step. Therefore by using multi-material deposition and/or multi material printing it may be possible to produce the main body and the electrically conducting structure in a single manufacturing step.
  • a two-step process for forming the main body from the ceramic ma terial in which according to a first step, the ceramic green body is produced such as by an additive manufacturing technique, such as stereolithogra phy, fused deposition modeling or binder-jetting, and in which according to a sec ond step, the ceramic green body is sintered.
  • the sintering step may be re alized in a furnace under controlled gas atmosphere and at temperature typically above 900°C to yield the said ceramic main body.
  • the method further comprises the step of b) filling at least part of the at least one first void with an electrically conducting mate rial.
  • the electrically conducting material preferably comprises a metal. More preferably copper or an alloy thereof, aluminum or an alloy thereof, silver, gold, tungsten or molybdenum may be used.
  • the step of filling at least a part of the at least one first void with the electrically conducting material may be achieved by melt press casting or high-temperature infiltration of the electrically conducting material into the at least one first void. In this process, the electrically conducting material may be melted to a liquid phase.
  • the molten electrically conducting mate rial may infiltrate the voids through capillary action or assisted by positive or nega tive pressure.
  • the housing element is produced in subsequent processing steps.
  • the main body which comprises the two- or three-dimensional void network, may be produced by layer manufacturing, such as additive manufacturing like described above.
  • the electrically conducting structure may be produced in that the at least one first void is filled with an electrically conducting material.
  • the electrically conducting structure may be produced by high- temperature infiltration or melt press casting of the electrically conducting material into at least a part of the at least one first void.
  • the temperature used should be above the meting point of the electrically conducting material which formed the electrical ly conducting structure.
  • the housing element the power semicon ductor module, the figures, and the further description.
  • the present invention solves an important object how to produce a housing element for a power semiconductor module, wherein the hous ing element improves at least one of the reliability, freedom of design, lifetime, and cooling efficiency of the power semiconductor module significantly.
  • Fig. 1 shows a schematic view of a power semiconductor module known from prior art
  • Fig. 2a shows a schematic view of a housing element according to a first embod iment of the invention
  • Fig. 2b shows a schematic view of a housing element according to a second em bodiment of the invention.
  • Fig. 2c shows a schematic view of a power semiconductor module comprising the housing element of figure 2b), according to the present invention.
  • Fig. 1 shows a power semiconductor module known from prior art.
  • the different layers of the power semiconductor module may be dedicated to perform a specific function of the power semiconductor module as described in the section back ground art of this application.
  • Figures 2a) to 2c) all show a schematic view of a housing element 20. Further more, figures 2a) to 2b) also illustrate the steps of a method for producing the housing element 20 according to an embodiment of the invention. Furthermore figure 2c) also shows a power semiconductor module 22.
  • the shown embodiments show subsequent steps when forming the power semi conductor module 22.
  • the housing element 20 may be part of a housing of a power semiconductor module 22.
  • the power semiconductor module 22 com- prises at least one power semiconductor device 24.
  • the power semiconductor module 22 comprises two power semiconductor devices 24.
  • Fur thermore, in this embodiment of the invention, the housing of the power semicon ductor module 22 comprises two housing elements 20.
  • the housing element 20 comprises a main body 26 that is formed from a ceramic material.
  • the ceramic material comprises silicon nitride, alumi num nitride, aluminum oxide or boron nitride.
  • the main body 26 comprises a two- or three-dimensional void network 28.
  • the two- or three-dimensional void network 28 is formed by holes, pores and/or pipes in the main body 26.
  • the main body 26 is free of the ceramic material.
  • some part of the two- or three-dimensional void network 28 may be located on the sur face of the main body 26.
  • the two- or three-dimensional void network 28 may form a cavity and/or depression in the surface of the main body 26.
  • the two- or three-dimensional void network 28 comprises at least one first void 30, wherein the at least one first void 30 is adapted for providing at least one electri cally conducting structure 32.
  • the electrically conducting structure 32 is depicted in figures 2b) and 2c). At least a part of the electrically conducting structure 32 is adapted for contacting at least one power semiconductor device 24 of the power semiconductor module 22, as can be seen in figure 2c).
  • the electrically conducting structure 32 may be formed by an electrically conduct ing material that is contained at least in a part of the at least one first void 30.
  • the two- or three-dimensional void network 28 additionally comprises at least one second void 34.
  • the second void 34 is adapted for providing a cooling structure 36.
  • the cooling structure 36 is directly formed by the at least one second void 34.
  • the at least one first void 30 and the at least one second void 34 are not interconnected to each other.
  • the at least one first void 30 may form a two- or three-dimensional network that may be interconnected or partially interconnected and the at least one second void 34 may form a two- or three-dimensional network that may be interconnected or partially interconnected.
  • the voids 30, 34 of the two- or three-dimensional void network 28 at least in part have a diameter 38 that is equal to or less than 500 pm.
  • some voids 30, 34 have the form of a pipe, wherein the pipe has a length and a diameter 38, with the diameter 38 being smaller than the length. This does not exclude that there may be another size of the voids 30, 34 that may be larger than 500 pm.
  • the length of the pipe may be 20 mm.
  • the cross- section of the pipe may be circular, or, preferably, rectangular, with the a/b ratio of greater than 2.
  • Figure 2c shows not only a schematic view of the housing element 20, but also of the power semiconductor module 22.
  • the electrically conducting structure 32 is in direct electrical contact to the power semiconductor device 24. There is no additional layer or structure between the electrically con ducting structure 32 and the power semiconductor device 24.
  • figure 2c shows that the power semiconductor device 24 is encap sulated by the housing.
  • the power semiconductor device 24 comprises a first side 40 and a second side 42, which is opposite of the first side 40.
  • the housing comprises two housing elements 20.
  • the two housing elements 20 allow to have a cooling structure 36 on both sides 40, 42 of the power semicon ductor device 24.
  • the power semiconductor device 24 is sandwiched between the two housing ele ments 22. There may be a mechanical part that executes a mechanical force 44 on the two housing elements 20. In other words, the housing of the power semi conductor module 22 shown in figure 2c) forms a press pack housing.
  • the housing elements 20 shown in figures 2a) to 2c) are produced by layer manu facturing.
  • a possible processing method may be as follows: In a first step the main body 26 containing the first void 30 and second void 34 is formed by layer manu facturing.
  • a feedstock material comprising either ceramic particles with binder material or ceramic precursor compound is used to produce a ceramic green body by means of additive manufacturing, e.g. binder- jetting, stereolithography, selective laser sintering or fused deposition modelling.
  • the green body is then heat-treated in a furnace under controlled gas atmosphere at a temperature above 900°C to yield the housing element 20 with voids 30, 34.
  • the result of this processing step is shown in figure 2a).
  • a second subsequent processing step b) at least part of the first void 30 is filled with an electrically conducting material, preferably copper or an alloy thereof, alu minum or an alloy thereof.
  • an electrically conducting material preferably copper or an alloy thereof, alu minum or an alloy thereof.
  • the electrically conducting structure 32 is formed in the second processing step. The result of which is shown in figure 2b).
  • the electrically conducting structure 32 is produced by high- temperature infiltration (>600°C) or melt press casting of the electrically conducting material into at least a part of the at least one first void 30.
  • the power semiconducting module 22 may be formed.
  • Two housing elements 20 and at least one power semiconductor device 24 may form the power semiconducting module 22.
  • the two housing elements 20 form the press pack housing, wherein an external mechanical force 44 holds the housing elements 20 and the power semiconductor device 24 in place.
  • the two housing elements 20 forming the housing as can be seen in figure 2c) can be connected to each other by means of sintering, preferably using alkali sintering aids, or appropriate organic or glass-based adhesive gluing, or soldering, or me chanical fixture, such as screws or springs.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to a housing element (20) for a housing of a power semiconductor module (22), wherein the power semiconductor module (22) comprises at least one power semiconductor device (24), wherein the housing element (20) comprises a main body (26), wherein the main body (26) is formed from a ceramic material, characterized in that the main body (26) comprises a two- or three- dimensional void network (28), wherein the two- or three-dimensional void network (28) comprises at least one first void (30), wherein the at least one first void (30) is adapted for providing at least one electrically conducting structure (32), and wherein at least a part of the electrically conducting structure (32) is adapted for contacting at least one power semiconductor device (24).

Description

Description
Housing element for a housing of a power semiconductor module
Technical Field
The present invention relates to a housing element for a housing of a power semi conductor module. The present invention particularly relates to a housing element comprising a main body formed from a ceramic material, wherein the main body comprises a two- or three-dimensional void network. The present invention also relates to a power semiconductor module comprising a housing, wherein the hous ing comprises the above housing element. Furthermore, the present invention re lates to a method for producing the above housing element.
Background Art
Power semiconductor modules are generally widely known in the art. Conventional power semiconductor modules are complex assemblies comprising many different components, each dedicated to perform a specific function. A typical power semi conductor module is shown in figure 1. It may comprise a heat sink 1 as cooling structure with vapor chambers 2. The heat sink 1 may be attached to a base plate 3 with thermal paste 4. The baseplate 3 may comprise a metal matrix composite comprising an aluminum matrix with silicon carbide particles, or a copper or alumi num composite, for high thermal conductivity and matching of thermal expansion coefficient.
On top of the baseplate 3 there may be a direct bonded copper layer 5, also ab breviated as DBC layer 5 that may be attached to the baseplate 3 by an interme diary solder layer 6. The DBC layer 5 may comprise a bottom metal layer 7, a middle ceramic layer 8 as insulation, and a top metal layer 9. The top metal layer 9 may form part of an electric circuit of the power semiconductor module. Power semiconductor devices 10 may either be soldered or sintered to the top metal lay- er 9. The power semiconductor devices 10 may be connected with each other and/or with the top metal layer 9 by a bond wire connection 11.
The power semiconductor devices 10 of the power semiconductor module produce heat that needs to be dissipated in order to maintain the functionality of the power semiconductor module.
US 2016/322333 describes an electronic module comprising an interposer com prising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encap sulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically iso lating material.
EP 3 171 678 A1 describes a printed circuit board including a body and a belly pad seated within with the body. The belly pad is electrically separated into a first pad and a second pad. The first pad and the second pad are arranged to be electrically connected to one another by an interconnect electrically connecting the belly pad to a conductive plane of an electrical component, thereby allowing continuity test ing across an interface between the first pad and the interconnect.
JP 2005303209 A describes a concave part being formed approximately in the center of the bottom surface of a circuit substrate where a specified circuit pattern is formed, and a pyrogenic power is mounted in the concave part. Further, in a first concave portion at the opening of the concave part, a metal cap is installed, which is connected externally to a grounding electrode. Sandwiched by the surface op posed to the power mounting surface and the metal cap, a graphite film is provid ed that has good heat conductance and high electrical conductivity as well as, fur thermore, being flexible.
However, the prior art such as referring to the above cited reference still gives room for improvements especially regarding the complexity of the module, the freedom of design of the electronic circuit, the cooling efficiency of the power sem- iconductor module, and in turn the reliability and lifetime of the power semiconduc tor module.
Summary of invention
It is therefore an object of the invention to provide a solution for overcoming at least one disadvantage of the prior art at least in part. It is especially an object of the present invention to provide a reliable power semiconductor module that pro vides a high freedom of design for the electric circuit and with an efficient cooling.
These objects are solved at least in part by a housing element for a housing of a power semiconductor module having the features of independent claim 1. These objects are further solved at least in part by a power semiconductor module having the features of independent claim 7. Furthermore, these objects are solved at least in part by a method for producing the above housing element having the features of independent claim 11. Advantageous embodiments are given in the dependent claims, in the further description as well as in the figures, wherein the described embodiments can, alone or in any combination of the respective embodiments, provide a feature of the present invention unless not clearly excluded.
Described is a housing element for a housing of a power semiconductor module, wherein the power semiconductor module comprises at least one power semicon ductor device, wherein the housing element comprises a main body, wherein the main body is formed from a ceramic material, wherein the main body comprises a two- or three-dimensional void network, wherein the two- or three-dimensional void network comprises at least one first void, wherein the at least one first void is adapted for providing at least one electrically conducting structure, and wherein at least a part of the electrically conducting structure is adapted for contacting at least one power semiconductor device.
Such a housing element provides significant advantages over solutions of the prior art, especially with regard to a higher freedom of design of the electric circuit of the power semiconductor module and it may further provide an efficient cooling behav ior of the power semiconductor device.
The present invention thus refers to a housing element. The housing element may be a one piece housing element, a two piece housing element or a multi-piece housing element. The housing element of the present invention may as such form the housing of the power semiconductor module. Further, the housing element of the present invention may be a part of the housing of the power semiconductor module. In other words, the housing of the power semiconductor module may comprise one housing element, two housing elements, or several housing ele ments. Furthermore, the housing of the power semiconductor module may also comprise additional pieces. In case the housing of the power semiconductor com prises more than one housing element, the different housing elements may be formed identically to each other, similarly to each other, or differently to each oth er.
The housing element of the present invention comprises the main body formed from a ceramic material, wherein the main body comprises the two- or three- dimensional void network. Such a network is thus formed from one void or prefer ably from a plurality of voids. The voids may be holes, pores and/or pipes in the main body. In other words the voids are structures in the main body which are free of the ceramic material. The holes, pores and/or pipes thus form the two- or three- dimensional void network.
The two- or three-dimensional void network or the voids thereof, respectively, may be interconnected or partially interconnected. For example, there may be a hole in the main body that is directly next to a tube, wherein there is no ceramic material in between the said hole and said tube. Thus, the hole and the tube may form one continuous hollow space in the main body. Partially interconnected may indicate that there may be an additional void that may not have an interconnection to an other void. Instead said void may be enclosed by the ceramic material. It may also be possible that a void of the two- or three-dimensional network is located on or near the surface of the main body. In this case the void may be represented by a cavity and/or a depression in the surface of the main body. Furthermore, the ex- pression“two- or three-dimensional void network” may mean that the network formed by the voids extends in two dimensions of space or preferably in all three dimensions of space. Thus, the two- or three-dimensional void network may be a two-dimensional network or preferably a three-dimensional network.
The two- or three-dimensional void network comprises the at least one first void, that is adapted for providing at least one electrically conducting structure. At least a part of the electrically conducting structure is adapted for contacting at least one power semiconductor device of the power semiconductor module. Preferably, the electrically conducting structure is adapted for directly electrically contacting at least one power semiconductor device of the power semiconductor module. In other words, there may be no additional connecting piece or connecting layer in between the electrically conducting structure and the power semiconductor mod ule so that the electrically conducting structure may come in direct contact to the power semiconductor device. Preferably, the electrically conducting structure is adapted to conduct an electrical signal. The electrically conducting structure may be embedded in part of the two- or three-dimensional void network. In other words the two- or three-dimensional void network allows integration of the electrically conducting structure into the main body.
The housing element and/or the power semiconductor module comprising said housing element may thus have no layered structure as is known from conven tional power semiconductor modules. Instead, the main body comprises the two- or three-dimensional void network, which in part is adapted for providing the elec trically conducting structure. Therefore, it is possible that an additional baseplate and/or an additional substrate is omitted.
The present invention may thus be advantageous over conventional power semi conductor modules having layered structures, where the different layers often comprise different types of materials. For example, the DBC layer may comprise a bottom metal layer, a middle ceramic layer, and a top metal layer. An important parameter of the middle ceramic layer may be the coefficient of thermal expansion (CTE), which indicates how much the middle ceramic layer and therefore the DBC layer expands or contracts by a change of temperature. A mismatch of the CTE of the ceramic layer with the CTE of the power semiconductor device, the solder, and/or the baseplate, may be a major cause for failures of conventional power semiconductor modules. The origin of these failures may be fatigue induced by the cyclic nature of the load to the power semiconductor module, and consequently cyclic heat generation. This problem, however, may be overcome by the present invention.
Besides the issue concerning a CTE mismatch, the layered structure of conven tional power semiconductor modules may lead to a reduced cooling efficiency of the power semiconductor device. There may be around six to seven layers be tween the power semiconductor device and the heat sink. Therefore, this layered structure may increase thermal resistance, temperature fluctuations in cycling op eration and overall power semiconductor module temperature. With this regard, the cooling behavior may be increased by a housing element of the present inven tion as it may serve directly as substrate and cooling means like described below, without a layer structure to be required. Consequently the lifetime of a convention al power semiconductor module may be improved according to the present inven tion.
Furthermore, since many of the different layers of the layered structured of con ventional power semiconductor modules may be attached to each other by a sol der layer, and the solder layer may comprise a low-melting alloy, the operation temperature of conventional power semiconductor modules may be limited to a temperature of around 150 to 175 °C.
However, all these drawbacks may be overcome or at least reduced by reducing the number of layers of the power semiconductor module.
The integration of the electrically conducting structure into the main body allows for direct heat take off from the electrically conducting structure into the ceramic material of the main body. This may improve heat dissipation and reduce tempera ture oscillation amplitude under cyclic load of the power semiconductor module. The ceramic material may have a high thermal conductivity and good electrical insulation properties, and may comprise for example silicon nitride, aluminum ni- tride, aluminum oxide or boron nitride. The improved heat dissipation and lower amplitude of temperature oscillations may allow for high power density and may increase the lifetime of the power semiconductor module.
Thus, the main body formed by the ceramic material may not only perform two functions also known from conventional power semiconductor modules, namely CTE-matching and electrical insulation, but the main body may also act as a heat spreading device. The ceramic material of the main body may be in direct contact with the electrically conducting structure. Therefore, it is able to efficiently spread heat from the power semiconductor device to the whole surface of the main body.
Furthermore, the main body may be connected to a heatsink. Therefore, by reduc ing the number of layers, the thermal resistance between the power semiconduc tor device and the heat sink may be reduced, improving the reliability and lifetime of the power semiconductor module.
Conventional power semiconductor modules with a layered structure may not only have thermal issues but may also have issues with parasitic currents in neighbor ing electric devices, generated by inductance. High electric current which flows through electric contacts may induce undesired parasitic currents in neighboring electric devices e.g. gate control and power contacts. However, the layered struc ture of conventional power semiconductor modules only allows for a two- dimensional design of the electric circuit, therefore the capability to reduce the im pact of inductance on neighboring electric devices by the electric circuit design may be limited.
Furthermore, the bond wire joints of conventional power semiconductor modules may be especially prone to thermal stress due to weak joint areas and may thus be a potential reason for failure of the power semiconductor module.
However, these disadvantages may also be overcome by integrating the electrical ly conducting structure into the main body of the housing element. Due to the two- or three-dimensional void network, the electrically conducting structure forming the electric circuit may also be three dimensional. Therefore, a design for the electric circuit may be chosen that reduces the inductance on neighboring electric devices. Wire bond connections may thus be omitted or their number may at least be re duced.
Furthermore, the ceramic material of the main body may also provide the function of an electric circuit housing. The ceramic material may be in direct contact with the electrically conducting structure, therefore reducing the number of bond wire joints in the power semiconductor module. Hence the number of weak joint areas may be reduced, which in turn may improve the reliability and lifetime of the power semiconductor module.
Summarizing the above, the two- or three-dimensional void network in the main body may increase the freedom in electric circuit design, which in turn may reduce inductance and promote efficiency. Furthermore, the number of bond wire joints may be reduced, therefore reducing the danger of wire failures. The possible re duction of the number of layers of the power semiconductor module may reduce thermal resistance. Apart from the above, by allowing the electrically conducting structure to be embedded into the ceramic material, the heat dissipation may be intensified.
It may be provided that the two- or three-dimensional void network additionally comprises at least one second void, wherein the at least one second void may be adapted for providing a cooling structure. In other words, the main body may not only comprise the at least one first void for providing the at least one electrically conducting structure, but also the at least one second void for providing the cool ing structure. Preferably, the cooling structure is adapted for dissipating heat from the main body. It may be possible that the cooling structure is directly formed by a part of the two- or three-dimensional void network. In other words, the cooling structure may be integrated in the main body. The integration of the cooling struc ture into the ceramic material allows for direct heat take-off from the ceramic mate rial and therefore from the main body. This may improve heat dissipation and re duce temperature oscillation amplitude under cyclic load of the power semiconduc tor module even further. Apart from that, the integration of the cooling structure in the main body of the housing element may enable to design the cooling structure adapted to the cooling needs of the power semiconductor module and/or adapted to the electrically con ducting structure also being present. For example, double-sided cooling of the power semiconductor device may be possible. Preferably, the two- or three- dimensional void network may comprise the at least one first void and the at least one second void. More preferably the at least one first void and the at least one second void may form distinct two- or three-dimensional networks. In other words the at least one first void and the at least one second void may not be connected to each other.
As already mentioned, the main body is formed by the ceramic material. The ce ramic material may have a high thermal conductivity and good electrical insulation properties. Furthermore, the composition of the ceramic material may be chosen in order to match the CTE of the power semiconductor module. In order to meet these functions, the ceramic material may comprise a material selected from the group consisting of silicon nitride, aluminum nitride, aluminum oxide or boron ni tride, for example. The ceramic material may be provided with or without a sinter ing additive like, for instance, an alkali additive.
It may further be preferred that a housing element may be provided wherein at least one void of the two- or three-dimensional void network, and thus particularly at least one of the first voids and the second voids, at least in part has a diameter that is equal to or less than 500 pm. For example, the respective void or voids may have the form of a pipe having a length and a diameter, with the diameter being smaller than the length. The diameter of the pipe may be equal to or smaller than 500 pm, for example 150 pm. This does not exclude that there may be another size of the voids that may be larger than 500 pm. For example the length of the pipe may be in the range between 1 mm to 100 mm. The lower border of the di ameter may generally be chosen in dependence of the desired need, e.g. if the respective void is used for forming a cooling structure or an electrically conducting structure and thus the respective working requirements and may be chosen by the person skilled in the art without problems. A diameter of a void shall be defined by the maximum diameter of a sphere that can be placed in the void. Therefore, the void diameter is meant to be understood in a three-dimensional manner and shall mean that in no direction, the diameter is smaller than the defined value.
The cross-section of a void, such as of a pipe, may be circular, oval, rectangular or may have a more complex-shape, like for instance H-beam or cross. Preferably the cross-section is rectangular with the a/b ratio (sides ratio) of greater than 2. Such cross-section normally allows for reduction of the skin-effect and overall in ductance losses, especially at high current frequencies.
Preferably, the voids of the two- or three-dimensional void network that may have at least in part a diameter that is equal to or less than 500 pm comprise the at least one first void. Since the at least one first void is adapted for providing the electrically conducting structure, the electrically conducting structure may also have at least in part a diameter that is equal to or smaller than 500 pm. Having such a diameter may increase heat dissipation form the electrically conducting structure into the ceramic material, since the surface-area-to-volume ratio, may be higher. Furthermore, a diameter that is equal to or less than 500 pm may lead to an increased design freedom and enables miniaturization of the power semicon ductor module. Also it allows for having more electrically conducting structures per volume of the main body, allowing more power semiconductor devices to be con tacted independently of each other.
As already mentioned the at least one first void is adapted for providing the at least one electrically conducting structure. In this context, a housing element may be provided wherein the housing element comprises the at least one electrically conducting structure, and wherein the at least one electrically conducting structure is formed by an electrically conducting material that is contained at least in a part of the at least one first void. Preferably the electrically conducting material may be contained in the complete first void or in the complete first voids in particular when the first void is formed as a tube or channel. An electrically conducing material may be a material having an electrical conductivity of at least 105 S/m, such as of at least 106 S/m at 20 °C, these values being understood in an exemplary manner. Preferably, the electrically conducting material has an electrical conductivity of at least 107 S/m at 20 °. Preferably, the electrically conducting material comprises a metal. Even more preferably, the electrically conducting material may comprise copper or an alloy thereof, aluminum or an alloy thereof, tungsten, silver, gold or molybdenum.
The electrical conductivity of a material may be an important property of the mate rial that quantifies the material's ability to conduct an electric current. The electrical conductivity may be measured in siemens per metre (S/m).
The electrically conducting material may be contained at least in a part of the pores, holes, and/or pipes of the first void of the main body. In other words the electrically conducting structure is formed by the electrically conducting material that is contained at least in a part of the pores, holes, and/or pipes. For example, the electrically conducting structure may be formed by a pipe of the main body that is filled with the electrically conducting material. Therefore the electrically conduct ing structure, that may be formed by the electrically conducting material contained in the at least one first void, may have the same outer shape as the inner shape of the at least one first void containing the electrically conducting material. This may have the advantage that the electrically conducting structure may have a very complex two- or three-dimensional shape, such as three-dimensional shape. Therefore it is possible to choose a shape of the electrically conducting structure that reduces inductance in neighboring electrically conducting structures or in neighboring electric parts of the power semiconductor module. Furthermore, the electrically conducting structure may be efficiently protected by the main body. Therefore, the lifetime of the electrically conducting structure may be increased.
It may further be provided that the housing element comprises at least one cooling structure, wherein the at least one cooling structure comprises at least one of a vapor chamber, a cooling channel, and a heat pipe, and wherein the cooling struc ture is formed at least in part by the at least one second void. As already men tioned, the cooling structure is adapted to dissipate heat from the main body. By forming the cooling structure at least in part by the at least one second void and thus for example by pores, holes, and/or pipes of the main body, the heat may be guided into the ceramic material of the main body therefore also the cooling struc ture may be embedded in the ceramic material. The at least one second void of the main body that may form the cooling structure may be connected to a heat sink. Therefore also the cooling structure may be connected to a heat sink. This may allow for a very efficient cooling of the main body and in turn of the power semiconductor module.
According to the above, the cooling structure may comprise a vapor chamber, a cooling channel and/or a heat pipe. These are different possibilities to provide effi cient cooling of the main body and in turn of the power semiconductor module. Preferably, the vapor chamber, the cooling channel and/or the heat pipe are formed by the pores, holes, and/or pipes of the main body. More preferably, the vapor chamber, the cooling channel and/or the heat pipe are embedded in the ce ramic material.
With regard to further advantages and technical features of the housing element, it is referred to the power semiconductor module, the method for producing a hous ing element, the figures and the further description.
The present invention further relates to a power semiconductor module comprising a housing wherein the housing comprises at least one housing element as de scribed above.
Such a power semiconductor module provides significant advantages over solu tions of the prior art, especially with regard to at least one of lifetime, reliability, freedom of design of the electric circuit and cooling efficiency.
It may be provided that the housing of the power semiconductor device forms a press pack housing. In conventional power semiconductor modules, the power semiconductor device may either be soldered or sintered to the top metal layer of the DBC layer. The solder may comprise a low-melting alloy, thus the operation temperature of conventional power semiconductor modules may be limited to a temperature of around 150 to 175 °C. However, in a press pack housing, the pow- er semiconductor device may be hold in place by a force acting on the power sem iconductor device exerted from the housing.
It may be possible that the housing comprises one housing element like described above and an additional element and the power semiconductor device is sand wiched in between the housing element and the additional element.
It may also be possible that the housing comprises two housing elements as de scribed above, and the two housing elements sandwich the power semiconductor device in between. The force applied on the power semiconductor device may be due to the gravitational force of the upper housing element or of the upper addi tional element, respectively. It may also be possible that the two housing elements or the housing element and the additional element are pressed together by pole- pieces.
Alternatively, it may be possible that the force applied on the power semiconductor device may be due to a spring in the power semiconductor module. The spring may be in between the two housings elements or in between the housing element and the additional element. The spring may lead to the advantage that the force applied on the power semiconductor device may be adjusted by the spring con stant. The spring may act as an independent suspension, so that only a certain force is applied to the power semiconductor device. Alternatively, it may be possi ble to use sintering process to physically attach the housing elements, or use pol ymer- or silica glass-based bonding.
It may further be provided that the power semiconductor module comprises at least one power semiconductor device, and wherein the power semiconductor de vice is encapsulated by the housing.
The housing may be formed by one housing element like described above. More over, it is possible that the housing is formed by two housing elements like de scribed above. It is even possible that the housing is formed by several housing elements e.g. three four or more housing elements like described above. In case the housing of the power semiconductor module comprises more than one hous- ing element, the different housing elements may be formed identically to each oth er, similarly to each other, or differently to each other, wherein at least one hous ing element is formed like described above. For example it may be possible that one of the housing elements may comprise the at least one cooling structure and the at least one electrically conducting structure, while the other housing element may only comprise the at least one electrically conducting structure. Furthermore, the two- or three-dimensional void network of the two housing elements may have an identical, a similar, or a different design.
The at least one power semiconductor device is encapsulated by the housing. Preferably, the at least one power semiconductor device may be in contact to the housing element on at least two sides of the power semiconductor device. Prefer ably, the at least one power semiconductor device of the power semiconductor module may be in direct electrical contact to the at least one electrically conduct ing structure of the housing element. In other words the electrically conducting structure may be directly contacted to the power semiconductor device, thus there may be no additional connecting pieces or layers in between the at least one pow er semiconductor device and the electrically conducting structure. This may also mean that the at least one first void that is adapted for providing the at least one electrically conducting structure, may also extend to the power semiconductor de vice.
As already mentioned, the layered structure of conventional power semiconductor modules, where the different layers often comprise different types of materials may have some issues. Therefore, by omitting additional layers, these disadvantages including different CTEs of different materials or upper limits of the operating tem perature due to low melting alloys may be overcome.
It may further be provided that the power semiconductor device comprises a first side and a second side, wherein the first side is located opposite to the second side, and wherein a cooling structure of the housing element is located adjacent to the first side and wherein a cooling structure of the housing element is located ad jacent to second side of the power semiconductor device. The first side may com prise one or more upper contacts of the power semiconductor device, such as the emitter and/or gate and the second side may comprise one or more lower contacts of the power semiconductor device, such as the collector.
Preferably the cooling structure is adapted for dissipating heat from the at least one power semiconductor device. In other word there may be an adapted design of the cooling structure to the power semiconductor device. Therefore the heat dissipation may be intensified due to the location of the cooling structure to the heat source. In particular, there may be a cooling structure directly located adja cent to the first side of the power semiconductor device and another cooling struc ture directly located adjacent to the second side of the power semiconductor de vice. The power semiconductor device may have the form of a cuboid. Having a cooling structure adjacent to the first side and adjacent to the second side of the power semiconductor device may mean that the power semiconductor device is located in between cooling structures. Or in other words the power semiconductor device is sandwiched in between the two cooling structures and thus a cooling structure is provided adjacent to the first side and thus opposing to the second side and a cooling structure is provided adjacent to the second side and thus op posing to the first side of the power semiconductor module. A double sided cooling of the power semiconductor device may increase heat dissipation tremendously.
With regard to further advantages and technical features of the power semicon ductor module, it is referred to the housing element, the method for producing a housing element, the figures, and the further description.
The present invention further relates to a method for producing the above de scribed housing element. The method comprises the step of a) forming a main body from a ceramic material preferably by layer manufacturing, wherein the main body comprises a two- or three-dimensional void network, wherein the two- or three-dimensional void network comprises at least one first void, and wherein the at least one first void is adapted for providing the at least one electrically conduct ing structure.
It may be provided that the main body of the housing element is produced by a layer manufacturing step. Layer manufacturing may be a process where the de- sired shape of the main body is not produced by removing material but by adding material in successive layers. In such processes, the material may be joined or solidified to create a two- or three-dimensional object, i.e. the main body and thus the housing element. Using layer manufacturing allows producing complex two- or three-dimensional shapes and structures with a high precision. Therefore, the housing element, the main body, the two- or three-dimensional void network in the main body, the electrically conducting structure and/or the cooling structure may be easily and precisely produced.
With regard to layer manufacturing, for example, material extrusion may be used. In this technique, a feedstock material may be pushed through an extruder. For example, a ceramic slurry that may comprise a binder mixture may be used as feedstock material. Furthermore, powder bed fusion as additive manufacturing may be used. Powder bed fusion additive manufacturing may designate a process in which thermal energy, for example from a laser or an electron beam, selectively fuses regions of a powder bed. Furthermore, directed energy deposition as addi tive manufacturing process may be used in which focused thermal energy may fuse materials by melting them as they are being deposited.
Preferably, thus, additive manufacturing may be used as layer manufacturing technique. Again, a ceramic slurry may be used. Furthermore, a two-step process can be used, where first the ceramic green body is produced preferably by an ad ditive manufacturing technique like stereolithography, fused deposition modeling or binder-jetting, and as a second step, the ceramic green body is sintered prefer ably in a furnace to yield the above described ceramic housing. The sintering step may be realized in a furnace under controlled gas atmosphere and at temperature typically above 900°C to yield the said ceramic main body. Locations in the main body where no ceramic slurry is extruded form the two- or three-dimensional net work of voids.
It may further be provided that physical vapor deposition may be used which may be a variety of vacuum deposition methods to produce the main body and thus the housing element. In physical vapor deposition, a material may go from a con densed phase to a vapor phase and then back to a condensed phase. It may further be provided that the method comprises a multi-material layer manu facturing step such, that the main body and the electrically conducting structure are formed in a single and thus common manufacturing step, i.e. in the multi material manufacturing step. Thus, different types of materials may be deposited in the same process step to produce the main body and the electrically conducting structure simultaneously.
A multi-material deposition and/or multi-material printing may be used where dif ferent types of materials are deposited in the same process step, to produce the housing element. Multi-material deposition and/or multi-material printing allows objects to be composed of complex and heterogeneous arrangements of materi als. For example, the ceramic material and the electrically conducting material that may form the electrically conducting structure may be deposited together in one common process step. Therefore by using multi-material deposition and/or multi material printing it may be possible to produce the main body and the electrically conducting structure in a single manufacturing step.
Furthermore, a two-step process for forming the main body from the ceramic ma terial can be used, in which according to a first step, the ceramic green body is produced such as by an additive manufacturing technique, such as stereolithogra phy, fused deposition modeling or binder-jetting, and in which according to a sec ond step, the ceramic green body is sintered. Again, the sintering step may be re alized in a furnace under controlled gas atmosphere and at temperature typically above 900°C to yield the said ceramic main body.
It may be provided that after step a), the method further comprises the step of b) filling at least part of the at least one first void with an electrically conducting mate rial. Preferably, the electrically conducting material preferably comprises a metal. More preferably copper or an alloy thereof, aluminum or an alloy thereof, silver, gold, tungsten or molybdenum may be used. The step of filling at least a part of the at least one first void with the electrically conducting material may be achieved by melt press casting or high-temperature infiltration of the electrically conducting material into the at least one first void. In this process, the electrically conducting material may be melted to a liquid phase. The molten electrically conducting mate rial may infiltrate the voids through capillary action or assisted by positive or nega tive pressure.
According to the above, it may be possible that the housing element is produced in subsequent processing steps. In a first processing step, the main body, which comprises the two- or three-dimensional void network, may be produced by layer manufacturing, such as additive manufacturing like described above. In a subse quent processing step, the electrically conducting structure may be produced in that the at least one first void is filled with an electrically conducting material. In this context the electrically conducting structure may be produced by high- temperature infiltration or melt press casting of the electrically conducting material into at least a part of the at least one first void.
With regard to high-temperature infiltration, the temperature used should be above the meting point of the electrically conducting material which formed the electrical ly conducting structure.
With regard to further advantages and technical features of the method for produc ing a housing element, it is referred to the housing element, the power semicon ductor module, the figures, and the further description.
To summarize the above, the present invention solves an important object how to produce a housing element for a power semiconductor module, wherein the hous ing element improves at least one of the reliability, freedom of design, lifetime, and cooling efficiency of the power semiconductor module significantly.
Further embodiments and advantages of the method are directly and unambigu ously derived by the person skilled in the art from the system as described before.
Brief description of drawings These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. Individual features disclosed in the embodiments can constitute alone or in combination an aspect of the pre sent invention. Features of the different embodiments can be carried over from one embodiment to another embodiment.
In the drawings:
Fig. 1 shows a schematic view of a power semiconductor module known from prior art;
Fig. 2a) shows a schematic view of a housing element according to a first embod iment of the invention;
Fig. 2b) shows a schematic view of a housing element according to a second em bodiment of the invention; and
Fig. 2c) shows a schematic view of a power semiconductor module comprising the housing element of figure 2b), according to the present invention.
Description of embodiments
Fig. 1 shows a power semiconductor module known from prior art. The different layers of the power semiconductor module may be dedicated to perform a specific function of the power semiconductor module as described in the section back ground art of this application.
Figures 2a) to 2c) all show a schematic view of a housing element 20. Further more, figures 2a) to 2b) also illustrate the steps of a method for producing the housing element 20 according to an embodiment of the invention. Furthermore figure 2c) also shows a power semiconductor module 22.
The shown embodiments show subsequent steps when forming the power semi conductor module 22.
As can be seen in Figure 2c) the housing element 20 may be part of a housing of a power semiconductor module 22. The power semiconductor module 22 com- prises at least one power semiconductor device 24. In this embodiment the power semiconductor module 22 comprises two power semiconductor devices 24. Fur thermore, in this embodiment of the invention, the housing of the power semicon ductor module 22 comprises two housing elements 20.
The housing element 20 comprises a main body 26 that is formed from a ceramic material. In this embodiment the ceramic material comprises silicon nitride, alumi num nitride, aluminum oxide or boron nitride. As can easily be seen in figure 2a), the main body 26 comprises a two- or three-dimensional void network 28. The two- or three-dimensional void network 28 is formed by holes, pores and/or pipes in the main body 26. Within the two- or three-dimensional void network 28 the main body 26 is free of the ceramic material. As can be seen in figure 2a) some part of the two- or three-dimensional void network 28 may be located on the sur face of the main body 26. In this case the two- or three-dimensional void network 28 may form a cavity and/or depression in the surface of the main body 26. The two- or three-dimensional void network 28 comprises at least one first void 30, wherein the at least one first void 30 is adapted for providing at least one electri cally conducting structure 32. The electrically conducting structure 32 is depicted in figures 2b) and 2c). At least a part of the electrically conducting structure 32 is adapted for contacting at least one power semiconductor device 24 of the power semiconductor module 22, as can be seen in figure 2c).
The electrically conducting structure 32 may be formed by an electrically conduct ing material that is contained at least in a part of the at least one first void 30.
In the embodiments shown in figures 2a) to 2c) the two- or three-dimensional void network 28 additionally comprises at least one second void 34. The second void 34 is adapted for providing a cooling structure 36. As can be seen the cooling structure 36 is directly formed by the at least one second void 34. The at least one first void 30 and the at least one second void 34 are not interconnected to each other. However, the at least one first void 30 may form a two- or three-dimensional network that may be interconnected or partially interconnected and the at least one second void 34 may form a two- or three-dimensional network that may be interconnected or partially interconnected. The voids 30, 34 of the two- or three-dimensional void network 28 at least in part have a diameter 38 that is equal to or less than 500 pm. As can be seen on figures 2a) to 2c) some voids 30, 34 have the form of a pipe, wherein the pipe has a length and a diameter 38, with the diameter 38 being smaller than the length. This does not exclude that there may be another size of the voids 30, 34 that may be larger than 500 pm. For example the length of the pipe may be 20 mm. The cross- section of the pipe may be circular, or, preferably, rectangular, with the a/b ratio of greater than 2.
Figure 2c) shows not only a schematic view of the housing element 20, but also of the power semiconductor module 22. As can be seen in figure 2c) the electrically conducting structure 32 is in direct electrical contact to the power semiconductor device 24. There is no additional layer or structure between the electrically con ducting structure 32 and the power semiconductor device 24.
Furthermore, figure 2c) shows that the power semiconductor device 24 is encap sulated by the housing. The power semiconductor device 24 comprises a first side 40 and a second side 42, which is opposite of the first side 40. In this embodiment the housing comprises two housing elements 20. The two housing elements 20 allow to have a cooling structure 36 on both sides 40, 42 of the power semicon ductor device 24.
The power semiconductor device 24 is sandwiched between the two housing ele ments 22. There may be a mechanical part that executes a mechanical force 44 on the two housing elements 20. In other words, the housing of the power semi conductor module 22 shown in figure 2c) forms a press pack housing.
The housing elements 20 shown in figures 2a) to 2c) are produced by layer manu facturing. A possible processing method may be as follows: In a first step the main body 26 containing the first void 30 and second void 34 is formed by layer manu facturing. In this embodiment of the method a feedstock material comprising either ceramic particles with binder material or ceramic precursor compound is used to produce a ceramic green body by means of additive manufacturing, e.g. binder- jetting, stereolithography, selective laser sintering or fused deposition modelling. The green body is then heat-treated in a furnace under controlled gas atmosphere at a temperature above 900°C to yield the housing element 20 with voids 30, 34. The result of this processing step is shown in figure 2a).
In a second subsequent processing step b) at least part of the first void 30 is filled with an electrically conducting material, preferably copper or an alloy thereof, alu minum or an alloy thereof. Thus the electrically conducting structure 32 is formed in the second processing step. The result of which is shown in figure 2b). In this embodiment the electrically conducting structure 32 is produced by high- temperature infiltration (>600°C) or melt press casting of the electrically conducting material into at least a part of the at least one first void 30.
In a further processing step the power semiconducting module 22 may be formed. Two housing elements 20 and at least one power semiconductor device 24 may form the power semiconducting module 22. The two housing elements 20 form the press pack housing, wherein an external mechanical force 44 holds the housing elements 20 and the power semiconductor device 24 in place.
The two housing elements 20 forming the housing as can be seen in figure 2c) can be connected to each other by means of sintering, preferably using alkali sintering aids, or appropriate organic or glass-based adhesive gluing, or soldering, or me chanical fixture, such as screws or springs.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the dis closed embodiments. Other variations to be disclosed embodiments can be un derstood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word“comprising” does not exclude other elements or steps, and the indefinite article“a” or“an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting scope. Reference signs list
1 heat sink (prior art)
2 vapor chamber (prior art)
3 base plate (prior art)
4 thermal paste (prior art)
5 DBC layer (prior art)
6 intermediary solder layer (prior art)
7 bottom metal layer (prior art)
8 middle ceramic layer (prior art)
9 top metal layer (prior art)
10 power sem iconductor device (prior art)
11 bond wire connection (prior art) 20 housing element
22 power semiconductor module
24 power semiconductor device
26 main body
28 two- or three-dimensional void network 30 first void
32 electrically conducting structure
34 second void
36 cooling structure
38 diameter
40 first side of power semiconductor device 42 second side of power semiconductor device 44 mechanical force

Claims

Claims
1. A housing element (20) for a housing of a power semiconductor module (22), wherein the power semiconductor module (22) comprises at least one power semiconductor device (24), wherein the housing element (20) comprises a main body (26), wherein the main body (26) is formed from a ceramic materi al, characterized in that the main body (26) comprises a two- or three- dimensional void network (28), wherein the two- or three-dimensional void network (28) comprises at least one first void (30), wherein the at least one first void (30) is adapted for providing at least one electrically conducting structure (32), and wherein at least a part of the electrically conducting struc ture (32) is adapted for contacting at least one power semiconductor device (24).
2. The housing element (20) according to claim 1 , characterized in that the two- or three-dimensional void network (28) additionally comprises at least one second void (34), wherein the at least one second void (34) is adapted for providing a cooling structure (36).
3. The housing element (20) according to claim 1 or 2, characterized in that at least one of the following features is provided:
the ceramic material comprises a material selected from the group consisting of silicon nitride, aluminum nitride, aluminum oxide or boron ni tride; and
the electrically conducting structure comprises a material selected from the group consisting of copper or an alloy thereof, aluminum or an alloy thereof, tungsten, silver, gold or molybdenum.
4. The housing element (20) according to any of claims 1 to 3, characterized in that at least one void of the two- or three-dimensional void network (28) has a diameter (38) that is equal to or less than 500 pm.
5. The housing element (20) according to any of claims 1 to 4, characterized in that the housing element (20) comprises at least one electrically conducting structure (32), wherein the at least one electrically conducting structure (32) is formed by an electrically conducting material that is contained at least in a part of the at least one first void (30).
6. The housing element (20) according to any of claims 2 to 5, characterized in that the housing element (20) comprises at least one cooling structure (36), wherein the at least one cooling structure (36) comprises at least one of a vapor chamber, a cooling channel, and a heat pipe, and wherein the cooling structure (36) is formed at least in part by the at least one second void (34).
7. A power semiconductor module (22), comprising a housing, wherein the housing comprises at least one housing element (20) according to any of claims 1 to 6.
8. The power semiconductor module (22) according to claim 7, characterized in that the housing forms a press pack housing.
9. The power semiconductor module (22) according to claim 7 or 8, character ized in that the power semiconductor module (22) comprises at least one power semiconductor device (24), wherein the power semiconductor device (24) is encapsulated by the housing.
10. The power semiconductor module (22) according to claim 9 characterized in that the power semiconductor device (24) comprises a first side (40) and a second side (42), wherein the first side (40) is located opposite to the second side (42), wherein a cooling structure (36) of the housing element (20) is lo cated adjacent to the first side (40) of the power semiconductor device (24)and wherein a cooling structure (36) of the housing element (20) is locat ed adjacent to the second side (42) of the power semiconductor device (24).
11. A method for producing a housing element (20) according to any of claims 1 to 6, comprising the step of
a) forming a main body (26) from a ceramic material, wherein the main body (26) comprises a two- or three-dimensional void net work (28), wherein the two- or three-dimensional void network (28) comprises at least one first void (30), and wherein the at least one first void (30) is adapted for providing the at least one electrically conducting structure (32).
12. The method according to claim 11 , characterized in that the main body (26) of the housing element (20) is produced by using a layer manufacturing step.
13. The method according to any of claims 11 or 12, characterized in that step a) comprises forming a green body and sintering the green body.
14. The method according to any of claims 11 to 13, characterized in that
after step a) the method comprises the further step b), wherein step b) com prises filling at least part of the at least one first void (30) with an electrically conducting material; or in that
the method comprises a multi-material layer manufacturing step such, that the main body (26) and the electrically conducting structure (32) are formed in a single manufacturing step.
15. The method according to claim 14, characterized in that the step of filling at least part of the at least one first void (30) with an electrically conducting ma terial is performed by high-temperature infiltration or melt press casting of the electrically conducting material into at least a part of the at least one first void (30).
PCT/EP2020/070869 2019-07-25 2020-07-23 Housing element for a housing of a power semiconductor module WO2021013961A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727455A (en) * 1985-02-14 1988-02-23 Brown, Boveri & Cie Ag Semiconductor power module with an integrated heat pipe
JP2005303209A (en) 2004-04-15 2005-10-27 Murata Mfg Co Ltd Hybrid module
US20160322333A1 (en) 2015-04-28 2016-11-03 Infineon Technologies Ag Electronic module comprising fluid cooling channel and method of manufacturing the same
EP3171678A1 (en) 2015-11-20 2017-05-24 Hamilton Sundstrand Corporation Circuit boards and circuit board assemblies

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727455A (en) * 1985-02-14 1988-02-23 Brown, Boveri & Cie Ag Semiconductor power module with an integrated heat pipe
JP2005303209A (en) 2004-04-15 2005-10-27 Murata Mfg Co Ltd Hybrid module
US20160322333A1 (en) 2015-04-28 2016-11-03 Infineon Technologies Ag Electronic module comprising fluid cooling channel and method of manufacturing the same
EP3171678A1 (en) 2015-11-20 2017-05-24 Hamilton Sundstrand Corporation Circuit boards and circuit board assemblies

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