WO2021006344A1 - Array antenna device - Google Patents

Array antenna device Download PDF

Info

Publication number
WO2021006344A1
WO2021006344A1 PCT/JP2020/027091 JP2020027091W WO2021006344A1 WO 2021006344 A1 WO2021006344 A1 WO 2021006344A1 JP 2020027091 W JP2020027091 W JP 2020027091W WO 2021006344 A1 WO2021006344 A1 WO 2021006344A1
Authority
WO
WIPO (PCT)
Prior art keywords
main surface
carrier
antenna unit
groove
array antenna
Prior art date
Application number
PCT/JP2020/027091
Other languages
French (fr)
Japanese (ja)
Inventor
巧弥 長峯
弘行 植松
西村　俊雄
剛士 塩出
威 中里
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to GB2115467.9A priority Critical patent/GB2598674B/en
Priority to JP2021530740A priority patent/JP7126619B2/en
Publication of WO2021006344A1 publication Critical patent/WO2021006344A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H01Q21/065—Patch antenna array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q13/00—Waveguide horns or mouths; Slot antennas; Leaky-waveguide antennas; Equivalent structures causing radiation along the transmission path of a guided wave
    • H01Q13/08—Radiating ends of two-conductor microwave transmission lines, e.g. of coaxial lines, of microstrip lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335—Material
    • H01L2224/33505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45155—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8313—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H01L2924/14215—Low-noise amplifier [LNA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • This disclosure relates to an array antenna device.
  • Patent Document 1 discloses a phased array antenna including a plurality of modules and a substrate. Each of the plurality of modules includes a plurality of radiating elements. The plurality of modules are fixed to the substrate using an adhesive.
  • the adhesive crawls up the gap between the plurality of modules and causes a plurality of radiating elements. It sometimes adhered to the surface. If the adhesive adheres to the surface of a plurality of radiating elements, the performance of the array antenna deteriorates.
  • the adhesive is a conductive bonding member such as solder
  • a plurality of radiating elements are electrically short-circuited with each other via the conductive bonding member, and cannot operate as an array antenna. It ends up.
  • the adhesive is an insulating adhesive
  • the dielectric loss of the array antenna increases due to the insulating adhesive adhering to the surfaces of the plurality of radiating elements, and the output of the array antenna decreases.
  • the array antenna device of the present disclosure includes a carrier, a joining member, a first antenna unit, and a second antenna unit.
  • the carrier has a first main surface and a second main surface opposite to the first main surface.
  • the joint member includes a first joint portion and a second joint portion.
  • the first antenna unit is joined to the first main surface of the carrier by using the first joining portion.
  • the second antenna unit is joined to the first main surface of the carrier by using a second joining portion.
  • the second antenna unit is arranged with a gap from the first antenna unit.
  • the first antenna unit and the second antenna unit each include a wiring board proximal to the carrier and a dielectric substrate distal to the carrier.
  • the wiring board has a third main surface facing the carrier and a fourth main surface opposite to the third main surface and facing the dielectric substrate.
  • the wiring board includes a feeding patch antenna element provided on the fourth main surface of the wiring board.
  • the dielectric substrate includes a non-feeding patch antenna element that is arranged corresponding to the feeding patch antenna element.
  • the carrier is provided with a groove extending from the first main surface to the second main surface. In the plan view of the first main surface of the carrier, the grooves are arranged corresponding to the gap between the first antenna unit and the second antenna unit. A slit extending from the first top surface of the feeding patch antenna element to the bottom surface of the groove is formed between the first antenna unit and the second antenna unit.
  • the joining member When fixing the wiring board to the carrier using the joining member, the joining member enters the groove.
  • the groove prevents the joining member from crawling up the gap between the first antenna unit and the second antenna unit and adhering to the surface of the non-feeding patch antenna element. Therefore, the array antenna device of the present disclosure has improved antenna performance.
  • FIG. 5 is a schematic cross-sectional view taken along the section line II-II shown in FIG. 1 of the array antenna device according to the first embodiment.
  • FIG. 5 is a schematic partially enlarged cross-sectional view of a region III shown in FIG. 2 of the array antenna device according to the first embodiment.
  • It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier included in the array antenna apparatus which concerns on Embodiment 1.
  • FIG. It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier included in the array antenna apparatus which concerns on Embodiment 1.
  • FIG. 5 is a schematic cross-sectional view taken along the section line II-II shown in FIG. 1 of the array antenna device according to the first embodiment.
  • FIG. 5 is a schematic partially enlarged cross-sectional view of a region III shown in FIG. 2 of the array antenna device according to the first embodiment.
  • It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier
  • FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XI-XI shown in FIG. 10 of the process shown in FIG.
  • FIG. 10 of the method for manufacturing the array antenna device according to the first embodiment. It is a schematic plan view which shows the next process of the process shown in FIG. 10 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 1.
  • FIG. FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XIII-XIII of the process shown in FIG. 12 of the method for manufacturing the array antenna device according to the first embodiment. It is a schematic plan view which shows the next process of the process shown in FIG. 12 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 1.
  • FIG. FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XV-XV of the process shown in FIG. 14 of the method for manufacturing the array antenna device according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XVII-XVII of the process shown in FIG. 16 of the method for manufacturing the array antenna device according to the first embodiment. It is a schematic plan view which shows the next process of the process shown in FIG. 16 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 1.
  • FIG. FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XIX-XIX of the process shown in FIG. 18 of the method for manufacturing the array antenna device according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XXII-XXII shown in FIG. 21 of the array antenna device according to the second embodiment.
  • FIG. 2 is a schematic partially enlarged cross-sectional view of region XXIII shown in FIG. 22 of the array antenna device according to the second embodiment.
  • FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XXV-XXV shown in FIG.
  • FIG. 24 of the array antenna device according to the third embodiment It is a schematic plan view which shows one step of the manufacturing method of the array antenna apparatus which concerns on Embodiment 3.
  • FIG. FIG. 5 is a schematic cross-sectional view of the array antenna device according to the fourth embodiment. It is a schematic plan view on the 2nd main surface of the carrier included in the array antenna device which concerns on Embodiment 4.
  • FIG. FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XXIX-XXIX shown in FIG. 28 of the carrier included in the array antenna device according to the fourth embodiment. It is a schematic plan view on the front surface of the housing included in the array antenna device according to the fourth embodiment.
  • FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XXXI-XXXI shown in FIG. 30 of the housing included in the array antenna device according to the fourth embodiment. It is schematic cross-sectional view which shows one process of the manufacturing method of the array antenna apparatus which concerns on Embodiment 4.
  • FIG. 5 is a schematic cross-sectional view showing the next step of the step shown in FIG. 32 in the method for manufacturing the array antenna device according to the fourth embodiment.
  • It is schematic cross-sectional view which shows the next process of the process shown in FIG. 33 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 4.
  • FIG. It is a schematic plan view which shows an example of the array antenna apparatus which has 3 or more antenna units.
  • the array antenna device 1 of the first embodiment will be described with reference to FIGS. 1 to 4F.
  • the array antenna device 1 mainly includes a carrier 6, a joining member 7, a first antenna unit 2a, and a second antenna unit 2b.
  • the array antenna device 1 may further include a housing 5, an external substrate 35, an electronic component 37, and an electrical connection member 40.
  • the housing 5 has a front surface 5s.
  • the front surface 5s of the housing 5 extends in the first direction (x direction) and the second direction (y direction) intersecting the first direction. Specifically, the second direction is perpendicular to the first direction. It is made of a metal with high thermal conductivity, for example an aluminum alloy.
  • the housing 5 is electrically grounded.
  • the carrier 6 has a first main surface 6s and a second main surface 6u on the opposite side of the first main surface 6s.
  • the first main surface 6s and the second main surface 6u extend in the first direction (x direction) and the second direction (y direction), respectively.
  • the first main surface 6s and the second main surface 6u are separated from each other in the third direction (z direction) perpendicular to the first direction (x direction) and the second direction (y direction).
  • the second main surface 6u of the carrier 6 faces the front surface 5s of the housing 5.
  • the carrier 6 is fixed to the front surface 5s of the housing 5 by using, for example, a fixing member (not shown) such as a screw.
  • the carrier 6 may be firmly fixed by the housing 5 by using a fixing member (not shown) such as a screw and an adhesive (not shown).
  • the carrier 6 is electrically grounded.
  • the carrier 6 relaxes the thermal strain of the wiring board 10 due to the difference in the coefficient of linear expansion between the housing 5 and the wiring board 10.
  • the difference in the coefficient of linear expansion between the carrier 6 and the wiring board 10 is preferably 3 ⁇ 10 -6 (/ K) or less.
  • the carrier 6 transfers the heat generated by the first antenna unit 2a and the second antenna unit 2b to the housing 5. Therefore, the carrier 6 may be formed of a material having high thermal conductivity, such as copper (Cu), copper-tungsten (Cu-W) alloy, or copper-molybdenum (Cu-Mo) alloy. preferable.
  • nickel plating or chrome plating may be applied to the surface of the carrier 6 (first main surface 6s, second main surface 6u, etc.).
  • the carrier 6 is provided with a groove 8 extending from the first main surface 6s to the second main surface 6u.
  • the groove 8 is defined by a bottom surface 8b and side surfaces 8j and 8k.
  • the side surface 8j of the groove 8 is proximal to the first antenna unit 2a and distal to the second antenna unit 2b.
  • the side surface 8k of the groove 8 is proximal to the second antenna unit 2b and distal to the first antenna unit 2a.
  • the width 8w of the groove 8 is defined as the minimum distance between the side surface 8j and the side surface 8k.
  • the groove 8 is provided in a straight line.
  • the bottom surface 8b of the groove 8 is separated from the second main surface 6u of the carrier 6.
  • the bottom surface 8b of the groove 8 is not particularly limited, but is a plane parallel to the first main surface 6s of the carrier 6.
  • the depth 60d of the slit 60 which will be described later, can be easily managed, and the quality of the array antenna device 1 is stabilized. ..
  • the depth 8d of the groove 8 is defined as the distance from the first main surface 6s of the carrier 6 to the bottom surface 8b of the groove 8.
  • the thickness 6t of the thinnest portion of the carrier 6 is defined as the distance from the bottom surface 8b of the groove 8 to the second main surface 6u of the carrier 6.
  • the thickness 6t of the thinnest portion of the carrier 6 is given by the difference between the thickness of the carrier 6 and the depth 8d of the groove 8.
  • the thickness 6t of the thinnest portion of the carrier 6 is appropriately determined according to the mechanical strength required for the carrier 6 and the long-term reliability required for the array antenna device 1.
  • the thickness of the thinnest portion of the carrier 6 is not particularly limited, but may be 1 mm or more.
  • the cross-sectional shape of the groove 8 is rectangular.
  • the cross-sectional shape of the groove 8 is not limited to a rectangle, and may be, for example, the cross-sectional shape shown in any of FIGS. 4A to 4F.
  • the cross-sectional shape of the groove 8 may be trapezoidal.
  • the side surfaces 8j, 8k of the groove 8 may be tilted with respect to the first main surface 6s so as to approach each other as they approach the first main surface 6s of the carrier 6.
  • the side surfaces 8j, 8k of the groove 8 may be tilted with respect to the first main surface 6s so as to separate from each other as they approach the first main surface 6s of the carrier 6.
  • the corner portion between the first main surface 6s of the carrier 6 and the side surfaces 8j and 8k of the groove 8 may be chamfered.
  • the corner portion between the first main surface 6s and the side surfaces 8j and 8k may be linearly chamfered.
  • the corners between the first main surface 6s and the side surfaces 8j, 8k may be round chamfered.
  • the side surfaces 8j, 8k of the groove 8 recede near the bottom surface 8b of the groove 8, and the bottom surface 8b of the groove 8 has a wider width than the opening of the groove 8. May be good.
  • the groove 8 may have a shape symmetrical with respect to the center line in the width direction (first direction (x direction)) of the groove 8. .. As shown in FIG. 4F, the groove 8 may have a shape that is asymmetric with respect to the center line in the width direction of the groove 8.
  • the joining member 7 includes a first joining portion 7a and a second joining portion 7b.
  • the joining member 7 may be separated from the bottom surface 8b of the groove 8 of the carrier 6.
  • the first joint portion 7a may be separated from the second joint portion 7b in the groove 8.
  • the joining member 7 may be a conductive joining member such as a solder, a conductive resin adhesive, or an anisotropic conductive adhesive, or an insulating joining member such as an insulating resin adhesive. May be good.
  • the joining member 7 As the joining member 7, a liquid or solid state can be used. In the manufacturing process described later, the joining member 7 is required to have a viscosity that allows it to be flexibly deformed with respect to a load. On the other hand, in order to prevent the joining member 7 from coming into contact with an unintended place, the joining member 7 is required to have a viscosity that does not easily flow due to vibration during the manufacturing process. In order to achieve both of these, the viscosity of the joining member 7 when it is liquid is preferably in the range of 5 Pa ⁇ s or more and 300 Pa ⁇ s or less, and more preferably 10 Pa ⁇ s or more and 50 Pa ⁇ s or less.
  • the first antenna unit 2a is joined to the first main surface 6s of the carrier 6 by using the first joining portion 7a.
  • the second antenna unit 2b is joined to the first main surface 6s of the carrier 6 by using the second joining portion 7b.
  • the second antenna unit 2b is arranged with a gap of 10 g from the first antenna unit 2a.
  • the groove 8 is arranged corresponding to the gap 10 g between the first antenna unit 2a and the second antenna unit 2b.
  • the width 10w of the gap 10g is narrower than the width 8w of the groove 8.
  • the width 10w of the gap 10g may be wider than the width 8w of the groove 8.
  • the width 10w of the gap 10g may be equal to the width 8w of the groove 8.
  • the second antenna unit 2b has the same configuration as the first antenna unit 2a.
  • the first antenna unit 2a includes a wiring board 10 and a dielectric board 26. In the third direction (z direction), the wiring board 10 and the dielectric board 26 are laminated.
  • the wiring board 10 is arranged on the side proximal to the carrier 6 with respect to the dielectric board 26.
  • the dielectric substrate 26 is arranged on the side distal to the carrier 6 with respect to the wiring substrate 10.
  • the side surface 10j of the wiring board 10 of the first antenna unit 2a protrudes from the side surface 8j of the groove 8 toward the center line in the width direction (first direction (x direction)) of the groove 8.
  • the portion of the wiring board 10 of the first antenna unit 2a that protrudes from the side surface 8j of the groove 8 is the eaves portion 10m.
  • the length of the eaves portion 10 m in the width direction of the groove 8 is, for example, 0.5 mm or less.
  • the side surface 10k of the wiring board 10 of the second antenna unit 2b protrudes from the side surface 8k of the groove 8 toward the center line in the width direction of the groove 8.
  • the portion of the wiring board 10 of the second antenna unit 2b that protrudes from the side surface 8k of the groove 8 is the eaves portion 10n.
  • the length of the eaves portion 10n in the width direction of the groove 8 is, for example, 0.5 mm or less.
  • the eaves portions 10m and 10n effectively prevent the joining member 7 from climbing up to the fourth main surface 10s of the wiring board 10.
  • the side surface 10j of the wiring board 10 of the first antenna unit 2a may be flush with the side surface 8j of the groove 8.
  • the side surface 10k of the wiring board 10 of the second antenna unit 2b may be flush with the side surface 8k of the groove 8.
  • the side surface 10j of the wiring board 10 of the first antenna unit 2a may be retracted from the center of the width direction (first direction (x direction)) of the groove 8 with respect to the side surface 8j of the groove 8.
  • the side surface 10k of the wiring board 10 of the second antenna unit 2b may be retracted from the center of the groove 8 in the width direction with respect to the side surface 8k of the groove 8.
  • the length of one side of the wiring board 10 may be 30 mm or less. Therefore, the thermal strain of the wiring board 10 due to the difference in the coefficient of thermal expansion between the wiring board 10 and the carrier 6 is reduced, and the array antenna device 1 has improved long-term reliability.
  • the wiring board 10 includes a semiconductor board 11, a wiring layer 15 provided on the semiconductor board 11, a feeding patch antenna element 19, and a ground conductor layer 20.
  • the wiring board 10 has a third main surface 10h facing the first main surface 6s of the carrier 6, and a fourth main surface 10s opposite to the third main surface 10h.
  • the third main surface 10h and the fourth main surface 10s extend in the first direction (x direction) and the second direction (y direction), respectively.
  • the semiconductor substrate 11 is arranged between the wiring layer 15 and the carrier 6.
  • the semiconductor substrate 11 is closer to the carrier 6 than the wiring layer 15.
  • the semiconductor substrate 11 is a circuit board manufactured by a general semiconductor wafer manufacturing process.
  • the semiconductor substrate 11 is made of a semiconductor material such as Si, SiGe, GaAs, InP, GaSb, SiC or GaN.
  • the semiconductor substrate 11 includes an active circuit 13 and a control circuit 14.
  • the active circuit 13 and the control circuit 14 are integrated on the semiconductor substrate 11.
  • the active circuit 13 and the control circuit 14 are provided on the side of the semiconductor substrate 11 facing the wiring layer 15.
  • the active circuit 13 includes, for example, a high-frequency electric element that transmits or receives electromagnetic waves such as microwaves and millimeter waves.
  • the high frequency electric element may be, for example, a low noise amplifier, a high power amplifier, or a phase shifter.
  • the active circuit 13 is connected to the feeding patch antenna element 19.
  • the active circuit 13 can transmit or receive electromagnetic waves via the feeding patch antenna element 19.
  • the control circuit 14 controls the operation of the active circuit 13.
  • the wiring layer 15 is electrically connected to the active circuit 13 and the feeding patch antenna element 19.
  • the wiring layer 15 includes an insulating layer 16 and a conductive via 18.
  • the conductive via 18 is provided in the insulating layer 16.
  • the conductive via 18 is connected to the active circuit 13 and the feeding patch antenna element 19.
  • the conductive via 18 is made of a metal material having a low electrical resistance, such as copper. Nickel plating and gold plating may be applied to the surface of the conductive via 18 to prevent rust on the conductive via 18.
  • the insulating layer 16 is preferably made of a material having a small dielectric loss tangent (tan ⁇ ).
  • the insulating layer 16 may be formed of a material having a dielectric loss tangent (tan ⁇ ) of 0.005 or less at an electromagnetic wave frequency of 1 GHz, or may be formed of a material having a dielectric loss tangent of 0.003 or less at an electromagnetic wave frequency of 1 GHz. You may.
  • the insulating layer 16 is preferably made of a material having excellent heat resistance and electrical insulation.
  • the insulating layer 16 is not particularly limited, but may be formed of a thermoplastic polyimide resin or a thermosetting polyimide resin.
  • the insulating layer 16 is not particularly limited, but may have a thickness of 3 ⁇ m or more and 15 ⁇ m or less.
  • the wiring layer 15 further includes a conductor 17.
  • the conductor 17 is provided in the insulating layer 16. One end of the conductor 17 is connected to the connection terminal 30. The other end of the conductor 17 is connected to the active circuit 13 or the control circuit 14.
  • the thickness of the conductor 17 is, for example, 5 ⁇ m or more and 30 ⁇ m or less.
  • the width of the conductor 17 is determined by the amount or frequency of the current flowing through the conductor 17.
  • the width of the conductor 17 is not particularly limited, but is 5 ⁇ m or more and 500 ⁇ m or less.
  • the conductor 17 is made of a metal material having a low electrical resistance, such as copper. Nickel plating and gold plating may be applied to the surface of the conductor 17 to prevent rust on the conductor 17.
  • the wiring layer 15 is formed by, for example, the following process.
  • the insulating layer 16 is formed on the semiconductor substrate 11.
  • a liquid insulating resin is applied onto the semiconductor substrate 11 by using a spin coating method to form an insulating resin film on the semiconductor substrate 11.
  • the insulating resin film is cured by applying heat to the insulating resin film or irradiating it with ultraviolet rays. In this way, the insulating layer 16 is formed.
  • the insulating sheet is placed on the semiconductor substrate 11. The insulating sheet is cured by applying heat to the insulating sheet or irradiating it with ultraviolet rays. In this way, the insulating layer 16 is formed.
  • the wiring layer 15 is obtained.
  • the wiring board 10 may include a connection terminal 30 made of a conductive material such as copper or gold. As shown in FIG. 1, in a plan view of the first main surface 6s of the carrier 6, the connection terminals 30 are arranged along one side of the wiring board 10 facing the external board 35. The connection terminal 30 is provided on the fourth main surface 10s exposed from the dielectric substrate 26. The fourth main surface 10s of the wiring board 10 is the surface of the insulating layer 16 distal to the carrier 6 (or the semiconductor substrate 11).
  • the feeding patch antenna element 19 is arranged on the fourth main surface 10s of the wiring board 10 facing the dielectric substrate 26.
  • the wiring board 10 includes a plurality of feeding patch antenna elements 19, and the plurality of feeding patch antenna elements 19 form a two-dimensional array on the fourth main surface 10s of the wiring board 10. It may be placed on top.
  • the plurality of feeding patch antenna elements 19 may be arranged on the fourth main surface 10s of the wiring board 10 in a one-dimensional array.
  • the plurality of feeding patch antenna elements 19 of the first antenna unit 2a and the plurality of feeding patch antenna elements 19 of the second antenna unit 2b are arranged at equal intervals. There is.
  • the feeding patch antenna element 19 has a first top surface 19t distal to the carrier 6.
  • the feeding patch antenna element 19 is connected to the active circuit 13 via the conductive via 18.
  • the feeding patch antenna element 19 is not particularly limited, but is made of a conductive material such as copper or gold.
  • the ground conductor layer 20 is provided on the fourth main surface 10s of the wiring board 10.
  • the ground conductor layer 20 is separated from the feeding patch antenna element 19 and is electrically insulated from the feeding patch antenna element 19.
  • the ground conductor layer 20 may surround the feeding patch antenna element 19.
  • the ground conductor layer 20 may also be provided on the outermost side of the fourth main surface 10s of the wiring board 10.
  • the ground conductor layer 20 is not particularly limited, but is made of a conductive material such as copper or gold.
  • the ground conductor layer 20 shields the noise of the electromagnetic wave generated in the active circuit 13 and suppresses the noise from being coupled to the feeding patch antenna element 19 or the non-feeding patch antenna element 29.
  • the ground conductor layer 20 has a second top surface 20t distal to the carrier 6.
  • the second top surface 20t of the ground conductor layer 20 is substantially flush with the first top surface 19t of the feeding patch antenna element 19.
  • the fact that the second top surface 20t of the ground conductor layer 20 is substantially flush with the first top surface 19t of the feeding patch antenna element 19 means that the feeding is fed to the second top surface 20t of the ground conductor layer 20.
  • This means that the deviation of the patch antenna element 19 from the first top surface 19t in the third direction (z direction) is 5 ⁇ m or less.
  • the deviation in the third direction (z direction) between the second top surface 20t of the ground conductor layer 20 and the first top surface 19t of the feeding patch antenna element 19 may be 3 ⁇ m or less, and may be 2 ⁇ m or less. It may be 1 ⁇ m or less.
  • the second top surface 20t of the ground conductor layer 20 is preferably flush with the first top surface 19t of the feeding patch antenna element 19. That is, the deviation in the third direction (z direction) between the second top surface 20t of the ground conductor layer 20 and the first top surface 19t of the feeding patch antenna element 19 is preferably 0 ⁇ m.
  • the dielectric substrate 26 is attached to the fourth main surface 10s of the wiring board 10 via the adhesive layer 22.
  • the dielectric substrate 26 includes a dielectric base material 27 and a non-feeding patch antenna element 29 arranged corresponding to the feeding patch antenna element 19.
  • the dielectric base material 27 has a fifth main surface 27r facing the fourth main surface 10s of the wiring board 10 and a sixth main surface 27s opposite to the fifth main surface 27r.
  • the fifth main surface 27r and the sixth main surface 27s extend in the first direction (x direction) and the second direction (y direction), respectively.
  • the dielectric substrate 27 may be, for example, a high frequency printed circuit board, a liquid crystal polymer substrate, or a ceramic substrate such as a low temperature co-fired ceramics (LTCC) substrate.
  • the dielectric base material 27 may be a fluororesin-based high-frequency printed circuit board having a low dielectric constant and a low dielectric loss, such as polytetrafluoroethylene (PTFE).
  • PTFE polytetrafluoroethylene
  • the adhesive layer 22 may be made of, for example, a thermoplastic resin such as a fluorine-based thermoplastic resin or a thermosetting resin.
  • the adhesive layer 22 may be formed of a material having a dielectric loss tangent (tan ⁇ ) of 0.005 or less at an electromagnetic wave frequency of 1 GHz, or may be formed of a material having a dielectric loss tangent of 0.003 or less at an electromagnetic wave frequency of 1 GHz. You may. Since the adhesive layer 22 is made of a material having a dielectric loss tangent of 0.005 or less at an electromagnetic wave frequency of 1 GHz, the loss of electromagnetic waves in the array antenna device 1 can be reduced, and the radiation efficiency of the array antenna device 1 can be improved. ..
  • the non-feeding patch antenna element 29 is arranged on the sixth main surface 27s of the dielectric base material 27.
  • the dielectric substrate 26 includes a plurality of non-feeding patch antenna elements 29, and the plurality of non-feeding patch antenna elements 29 are arranged in a two-dimensional array on the sixth main surface 27s. It may be arranged.
  • the plurality of non-feeding patch antenna elements 29 may be arranged on the sixth main surface 27s in a one-dimensional array.
  • the plurality of non-feeding patch antenna elements 29 of the first antenna unit 2a and the plurality of non-feeding patch antenna elements 29 of the second antenna unit 2b are arranged at equal intervals. There is.
  • the non-feeding patch antenna element 29 is electromagnetically coupled to the corresponding feeding patch antenna element 19.
  • the non-feeding patch antenna element 29 is electromagnetically coupled to the active circuit 13 via the feeding patch antenna element 19 and the conductive via 18.
  • the active circuit 13 can transmit or receive electromagnetic waves via the feeding patch antenna element 19 and the non-feeding patch antenna element 29.
  • the non-feeding patch antenna element 29 is not particularly limited, but is made of a conductive material such as copper or gold.
  • the external board 35 is placed on the front surface 5s of the housing 5.
  • the external board 35 is separated from the wiring board 10.
  • the external substrate 35 is, for example, a printed circuit board.
  • the printed circuit board may be, for example, a high-frequency printed circuit board, a liquid crystal polymer substrate, or a ceramic substrate such as a low-temperature co-fired ceramics (LTCC) substrate.
  • the printed circuit board may be a fluororesin-based high-frequency printed circuit board having a low dielectric constant and a low dielectric loss such as polytetrafluoroethylene (PTFE).
  • PTFE polytetrafluoroethylene
  • the printed circuit board may be made of a material having a dielectric loss tangent (tan ⁇ ) of 0.005 or less at an electromagnetic wave frequency of 1 GHz, or may be formed of a material having a dielectric loss tangent of 0.003 or less at an electromagnetic wave frequency of 1 GHz. May be good.
  • the external substrate 35 having a low dielectric constant and a low dielectric loss can reduce the transmission delay and transmission loss of high frequency signals such as microwaves or millimeter waves.
  • the circuit 36 is formed on the surface of the external substrate 35 on the opposite side of the housing 5.
  • the circuit 36 is designed to transmit a power supply current, a high frequency signal, a digital control signal, and the like.
  • the circuit 36 is made of a conductive material such as copper, gold or aluminum.
  • the circuit 36 can be formed by patterning by a general subtractive method or an additive method.
  • the electronic component 37 is mounted on the surface of the external substrate 35 on the side opposite to the housing 5.
  • the electronic component 37 is, for example, a resistor, a capacitor, an inductor, a connector, a semiconductor package, or the like.
  • the electronic component 37 is electrically connected to the circuit 36 using solder, a conductive adhesive, a metal wire, or the like.
  • the electrical connection member 40 electrically connects the connection terminal 30 and the circuit 36 to each other.
  • the electrical connection member 40 includes a conductor made of a conductive material such as gold, silver, copper or nickel.
  • the electrical connection member 40 may further include an insulating base material that supports the conductor.
  • the electrical connection member 40 is not particularly limited, but may be a flexible printed circuit board, a wire harness, a conductive ribbon, or a conductive wire.
  • the groove 8 is arranged corresponding to the gap 10 g between the first antenna unit 2a and the second antenna unit 2b. Therefore, a slit 60 extending from the first top surface 19t of the feeding patch antenna element 19 to the bottom surface 8b of the groove 8 is formed between the first antenna unit 2a and the second antenna unit 2b. As shown in FIG. 3, the depth 60d of the slit 60 is defined as the distance from the first top surface 19t of the feeding patch antenna element 19 to the bottom surface 8b of the groove 8 in the third direction (z direction).
  • the second top surface 20t of the ground conductor layer 20 is substantially flush with the first top surface 19t of the feeding patch antenna element 19. Therefore, the depth 60d of the slit 60 is also the distance from the second top surface 20t of the ground conductor layer 20 to the bottom surface 8b of the groove 8 in the third direction (z direction).
  • the depth 60d of the slit 60 is given by the sum of the depth 8d of the groove 8, the thickness 10d of the wiring board 10, and the thickness 7d of the joining member 7.
  • the depth 8d of the groove 8 is defined as the distance from the first main surface 6s of the carrier 6 to the bottom surface 8b of the groove 8 in the third direction (z direction).
  • the thickness 10d of the wiring board 10 is defined as the distance from the first top surface 19t of the feeding patch antenna element 19 to the third main surface 10h of the wiring board 10.
  • the thickness 7d of the joining member 7 is defined as an average distance from the third main surface 10h of the wiring board 10 to the first main surface 6s of the carrier 6.
  • the minimum width of the slit 60 is smaller than the depth 60d of the slit 60.
  • the minimum width of the slit 60 is defined as the smaller of the width 10w of the gap 10g and the width 8w of the groove 8.
  • the width 10w of the gap 10g between the first antenna unit 2a and the second antenna unit 2b is between the side surface 10j of the wiring board 10 of the first antenna unit 2a and the side surface 10k of the wiring board 10 of the second antenna unit 2b. Is defined as the average distance of.
  • the width 8w of the groove 8 is defined as the average distance between the side surface 8j and the side surface 8k of the groove 8.
  • the depth 60d of the slit 60 or the like can be measured by a contact-type length measurement method using a caliper or the like, or a length measurement method using an optical microscope and a micrometer.
  • the thickness 7d of the joining member 7 is such that the wiring board 10 is bonded to the carrier 6 via the joining member 7 and then the first top surface 19t of the feeding patch antenna element 19 of the wiring board 10 is formed from the second main surface 6u of the carrier 6. It is obtained by measuring the distance to and subtracting the thickness of the carrier 6 and the thickness of the wiring board 10 10d from this distance.
  • the distance from the second main surface 6u of the carrier 6 to the first top surface 19t of the feeding patch antenna element 19 of the wiring board 10, the thickness of the carrier 6 and the thickness 10d of the wiring board 10 are as high as a laser microscope. It can be measured using the length measuring means of.
  • the depth 60d of the slit 60 is substantially an integral multiple of half the wavelength ⁇ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19.
  • the fact that the depth 60d of the slit 60 is substantially an integral multiple of half the wavelength ⁇ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19 means that the depth 60d of the slit 60 is an electromagnetic wave. It means that it is within the range of an integral multiple of half of the wavelength ⁇ of ⁇ ⁇ 1/16 of the wavelength ⁇ of electromagnetic waves.
  • the depth 60d of the slit 60 is preferably equal to an integral multiple of half the wavelength ⁇ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19. For example, when the frequency of the electromagnetic wave transmitted or received by the array antenna device 1 is 50 GHz, the wavelength ⁇ of the electromagnetic wave is 6 mm, and the depth 60d of the slit 60 is set to an integral multiple of 3 mm.
  • the groove 8 provided in the carrier 6 of the array antenna device 1 will be described.
  • the groove 8 is arranged corresponding to the gap 10 g between the first antenna unit 2a and the second antenna unit 2b.
  • the joining member 7 used for joining the wiring board 10 to the carrier 6 enters the groove 8 due to the pressure applied to the wiring board 10 in the joining process or the weight of the wiring board 10 itself.
  • the groove 8 prevents the joining member 7 from crawling up the gap 10 g between the first antenna unit 2a and the second antenna unit 2b and adhering to the surface of the non-feeding patch antenna element 29.
  • the joining member 7 When the joining member 7 is a conductive joining member, the joining member 7 electrically short-circuits the non-feeding patch antenna element 29 of the first antenna unit 2a and the non-feeding patch antenna element 29 of the second antenna unit 2b. Can be prevented.
  • the joining member 7 is an insulating joining member, it is possible to prevent the dielectric loss of the array antenna device 1 from increasing due to the joining member 7 adhering to the non-feeding patch antenna element 29. In this way, the antenna performance of the array antenna device 1 can be improved.
  • the depth 60d of the slit 60 is the distance from the first top surface 19t of the feeding patch antenna element 19 (or the second top surface 20t of the ground conductor layer 20) to the bottom surface 8b of the groove 8 in the third direction (z direction). Therefore, the depth 60d of the slit 60 is equal to the distance from the virtual surface 10p to the bottom surface 8b of the groove 8.
  • a part of the electromagnetic wave transmitted or received by the array antenna device 1 enters from the virtual surface 10p toward the bottom surface 8b of the groove 8 and is reflected by the bottom surface 8b of the groove 8.
  • the incident electromagnetic wave and the reflected electromagnetic wave interfere with each other, and a standing wave of the electromagnetic wave is generated in the slit 60 between the bottom surface 8b of the groove 8 and the virtual surface 10p.
  • the bottom surface 8b of the groove 8 is a fixed end of the standing wave, and the node of the standing wave is located on the bottom surface 8b of the groove 8.
  • the carrier 6 is electrically grounded, and the potential of the node of the standing wave is the ground potential.
  • the potential of the standing wave on the virtual surface 10p changes as follows according to the depth 60d of the slit 60 and the wavelength ⁇ of the electromagnetic wave.
  • the standing wave of the electromagnetic wave The belly is located on the virtual surface 10p.
  • the antinode of the standing wave of the electromagnetic wave is located instead of the node of the standing wave of the electromagnetic wave which is the ground potential.
  • the potential of the standing wave of the electromagnetic wave on the virtual surface 10p is different from the ground potential.
  • the potential of the standing wave of the electromagnetic wave on the virtual surface 10p between the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b is different from the ground potential of the ground conductor layer 20.
  • the potential of the ground conductor layer 20 of the first antenna unit 2a is the ground potential
  • the potential of the ground conductor layer 20 of the second antenna unit 2b is different from the ground potential of the electromagnetic wave on the virtual surface 10p. Due to the electric potential of the wave, it may not be the ground potential.
  • the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b may have different potentials from each other.
  • the gain of the electromagnetic wave in the array antenna device 1 decreases. Further, the difference between the phase of the electromagnetic wave radiated from the feeding patch antenna element 19 of the first antenna unit 2a and the phase of the electromagnetic wave radiated from the feeding patch antenna element 19 of the second antenna unit 2b deviates from the design value. .. Therefore, the side lobe level of the array antenna device 1 becomes large. The antenna performance of the array antenna device 1 deteriorates.
  • the side lobe means an electromagnetic wave radiated in a direction other than the direction in which it should be radiated.
  • the sidelobe level means the ratio of the intensity of the electromagnetic wave radiated in the direction other than the originally radiated direction to the intensity of the electromagnetic wave radiated in the direction originally radiated.
  • the side lobe level is an index of the directivity of the electromagnetic wave radiated from the array antenna device 1. The smaller the sidelobe level, the higher the directivity of the electromagnetic wave and the higher the antenna performance of the array antenna device 1.
  • the depth 60d of the slit 60 is half the wavelength ⁇ of the emitted electromagnetic wave.
  • the node of the standing wave of the electromagnetic wave is located on the virtual surface 10p.
  • a standing wave node of an electromagnetic wave which is a ground potential, is located on the virtual surface 10p. Therefore, the potential of the standing wave of the electromagnetic wave on the virtual surface 10p is equal to the ground potential which is the potential of the standing wave of the electromagnetic wave on the bottom surface 8b of the groove 8.
  • the potential of the standing wave on the virtual surface 10p between the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b is equal to the ground potential of the ground conductor layer 20.
  • the ground conductor layer 20 of the first antenna unit 2a is electromagnetically coupled to the ground conductor layer 20 of the second antenna unit 2b at the same ground potential.
  • Both the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b have a ground potential.
  • the gain of the electromagnetic wave in the array antenna device 1 is maximized (see FIG. 9). .. Further, the difference between the phase of the electromagnetic wave radiated from the feeding patch antenna element 19 of the first antenna unit 2a and the phase of the electromagnetic wave radiated from the feeding patch antenna element 19 of the second antenna unit 2b is as the design value. Therefore, the side lobe level of the array antenna device 1 becomes small. The antenna performance of the array antenna device 1 is improved.
  • a groove 8 is formed in the carrier 6.
  • the groove 8 is formed by, for example, mechanical processing such as grinding or polishing, or chemical processing such as etching.
  • the joining member 7 is provided on the first main surface 6s of the carrier 6.
  • the joining member 7 includes a first joining portion 7a and a second joining portion 7b.
  • the groove 8 is located between the first joint portion 7a and the second joint portion 7b.
  • the joining member 7 is subjected to a printing method using a metal mask, a ejection method using a dispenser, or a pin transfer method to obtain the first main surface 6s of the carrier 6. Provided on top.
  • the joining member 7 is a solid such as a sheet, the joining member 7 is placed on the first main surface 6s of the carrier 6.
  • the wiring board 10 is fixed to the carrier 6 via the joining member 7. Specifically, the wiring board 10 is placed on the joining member 7 while aligning the wiring board 10 with respect to the carrier 6.
  • the joining member 7 is cured while pressing the wiring board 10 against the carrier 6.
  • the first joint portion 7a and the second joint portion 7b may be individually cured. Therefore, the relative position accuracy between the wiring boards 10 can be improved. It becomes possible to manufacture the array antenna device 1 for high frequencies, which requires high assembly accuracy.
  • the first joint portion 7a and the second joint portion 7b may be cured together. Therefore, the manufacturing time of the array antenna device 1 can be shortened, and the manufacturing cost of the array antenna device 1 can be reduced.
  • the adhesive layer 22 is provided on the fourth main surface 10s of the wiring board 10, the first top surface 19t of the feeding patch antenna element 19, and the second top surface 20t of the ground conductor layer 20.
  • the adhesive layer 22 is the fourth main surface of the wiring board 10 by a printing method using a metal mask, a discharge method using a dispenser, or a pin transfer method. 10s, it is provided on the first top surface 19t of the feeding patch antenna element 19 and the second top surface 20t of the ground conductor layer 20.
  • the adhesive layer 22 is the fourth main surface 10s of the wiring board 10, the first top surface 19t of the feeding patch antenna element 19, and the second top of the ground conductor layer 20. It is placed on the surface 20t.
  • the dielectric substrate 26 is adhered to the wiring substrate 10 via the adhesive layer 22.
  • the non-feeding patch antenna element 29 of the dielectric substrate 26 is arranged corresponding to the feeding patch antenna element 19 of the wiring board 10.
  • the dielectric substrate 26 is attached to the wiring board 10 so that the center of the non-feeding patch antenna element 29 coincides with the center of the feeding patch antenna element 19 in the plan view of the first main surface 6s of the carrier 6. It is placed against.
  • a dielectric material is used by using an alignment mark (not shown) formed on the fourth main surface 10s of the wiring board 10 and an alignment mark (not shown) formed on the fifth main surface 27r of the dielectric substrate 26.
  • the board 26 may be aligned with respect to the wiring board 10.
  • the carrier 6 is fixed to the housing 5 using a fixing member (not shown) such as a screw.
  • the external substrate 35 is fixed to the housing 5 using a fixing member (not shown) such as a screw.
  • An electronic component 37 is mounted on the external substrate 35.
  • the external board 35 is aligned with the wiring board 10 so that the circuit 36 of the external board 35 and the connection terminal 30 of the wiring board 10 face each other in a plan view of the first main surface 6s of the carrier 6.
  • the circuit 36 of the external board 35 and the connection terminal 30 of the wiring board 10 are connected by using the electrical connection member 40.
  • the electrical connection member 40 is a metal wire
  • the electrical connection member 40 is bonded to the circuit 36 and the connection terminal 30 by using a wire bonder or the like.
  • the electrical connection member 40 is a flexible printed circuit board
  • the electrical connection member 40 is joined to the connection terminal 30 and the circuit 36 by using a flip chip bonder or the like.
  • the electrical connection member 40 is joined to the connection terminal 30 and the circuit 36 using solder, an anisotropic conductive adhesive, or a conductive adhesive. In this way, the array antenna device 1 shown in FIGS. 1 to 3 can be obtained.
  • the array antenna device 1 of the present embodiment includes two antenna units (first antenna unit 2a and second antenna unit 2b), but the number of antenna units included in the array antenna device 1 is 3 or more. You may. Four or more antenna units may be arranged in a matrix in the first direction (x direction) and the second direction (y direction).
  • the array antenna device 1 of the present embodiment includes a carrier 6, a joining member 7, a first antenna unit 2a, and a second antenna unit 2b.
  • the carrier 6 has a first main surface 6s and a second main surface 6u on the opposite side of the first main surface 6s.
  • the joining member 7 includes a first joining portion 7a and a second joining portion 7b.
  • the first antenna unit 2a is joined to the first main surface 6s of the carrier 6 by using the first joining portion 7a.
  • the second antenna unit 2b is joined to the first main surface 6s of the carrier 6 by using the second joining portion 7b.
  • the second antenna unit 2b is arranged with a gap of 10 g from the first antenna unit 2a.
  • the first antenna unit 2a and the second antenna unit 2b each include a wiring board 10 proximal to the carrier 6 and a dielectric substrate 26 distal to the carrier 6.
  • the wiring board 10 has a third main surface 10h facing the carrier 6 and a fourth main surface 10s on the opposite side of the third main surface 10h and facing the dielectric substrate 26.
  • the wiring board 10 includes a feeding patch antenna element 19 provided on the fourth main surface 10s of the wiring board 10.
  • the dielectric substrate 26 includes a non-feeding patch antenna element 29 arranged corresponding to the feeding patch antenna element 19.
  • the carrier 6 is provided with a groove 8 extending from the first main surface 6s to the second main surface 6u.
  • the groove 8 is arranged corresponding to the gap 10 g between the first antenna unit 2a and the second antenna unit 2b.
  • a slit 60 extending from the first top surface 19t of the feeding patch antenna element 19 to the bottom surface 8b of the groove 8 is formed between the first antenna unit 2a and the second antenna unit 2b.
  • the groove 8 prevents the joining member 7 from crawling up the gap 10 g between the first antenna unit 2a and the second antenna unit 2b and adhering to the surface of the non-feeding patch antenna element 29.
  • the array antenna device 1 has improved antenna performance.
  • the wiring board 10 includes a ground conductor layer 20 provided on the fourth main surface 10s of the wiring board 10 and separated from the feeding patch antenna element 19. ..
  • the second top surface 20t of the ground conductor layer 20 is substantially flush with the first top surface 19t of the feeding patch antenna element 19.
  • the carrier 6 is electrically grounded.
  • the depth 60d of the slit 60 is substantially an integral multiple of half the wavelength ⁇ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19.
  • the ground conductor layer 20 of the first antenna unit 2a is electromagnetically coupled to the ground conductor layer 20 of the second antenna unit 2b at the same ground potential.
  • the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b have equal ground potentials.
  • the gain of the electromagnetic wave in the array antenna device 1 is maximized.
  • the side lobe level of the array antenna device 1 becomes smaller.
  • the array antenna device 1 has improved antenna performance.
  • the minimum width of the slit 60 is smaller than the depth 60d of the slit 60. Therefore, a standing wave of electromagnetic waves transmitted or received from the array antenna device 1 is stably formed in the depth 60d direction of the slit 60. The gain of the electromagnetic wave in the array antenna device 1 is maximized. The side lobe level of the array antenna device 1 becomes smaller. The array antenna device 1 has improved antenna performance.
  • the width 10w of the gap 10g is narrower than the width 8w of the groove 8.
  • the first antenna unit 2a (particularly the eaves portion 10m) and the second antenna unit 2b (the eaves portion 10n) effectively prevent the joining member 7 from climbing up to the fourth main surface 10s of the wiring board 10.
  • the array antenna device 1 has improved antenna performance.
  • the joining member 7 is separated from the bottom surface 8b of the groove 8. Therefore, the effective length of the depth 60d of the slit 60 for the electromagnetic wave transmitted or received by the array antenna device 1 does not change depending on the joining member 7.
  • the gain of the electromagnetic wave in the array antenna device 1 is maximized.
  • the side lobe level of the array antenna device 1 becomes smaller.
  • the array antenna device 1 has improved antenna performance.
  • the first joint portion 7a is separated from the second joint portion 7b in the groove 8.
  • the first joint portion 7a comes into contact with the second joint portion 7b to form a closed space surrounded by the joint member 7 and the groove 8, during the manufacturing process of the array antenna device 1 and the operation of the array antenna device 1.
  • the gas in the closed space may expand and the joining member 7 may burst.
  • the joint member 7 since the first joint portion 7a is separated from the second joint portion 7b, the joint member 7 is prevented from bursting.
  • the first joint portion 7a and the second joint portion 7b are conductive joint members, it is possible to prevent an electrical short circuit between the first antenna unit 2a and the second antenna unit 2b.
  • the array antenna device 1 has improved antenna performance.
  • the joining member 7 is a conductive joining member.
  • the groove 8 prevents the joining member 7, which is a conductive joining member, from crawling up the gap 10g between the first antenna unit 2a and the second antenna unit 2b and adhering to the surface of the non-feeding patch antenna element 29.
  • the bonding member 7, which is a conductive bonding member can prevent the non-feeding patch antenna element 29 of the first antenna unit 2a and the non-feeding patch antenna element 29 of the second antenna unit 2b from being electrically short-circuited.
  • the array antenna device 1 has improved antenna performance.
  • the joining member 7 is an insulating joining member.
  • the groove 8 prevents the joining member 7, which is an insulating joining member, from crawling up the gap 10g between the first antenna unit 2a and the second antenna unit 2b and adhering to the surface of the non-feeding patch antenna element 29. To prevent. It is possible to prevent the bonding member 7, which is an insulating bonding member, from adhering to the surface of the non-feeding patch antenna element 29 and increasing the dielectric loss of the array antenna device 1.
  • the array antenna device 1 has improved antenna performance.
  • the non-feeding patch antenna element 29 of the first antenna unit 2a is a plurality of non-feeding patch antenna elements 29.
  • the non-feeding patch antenna element 29 of the second antenna unit 2b is a plurality of non-feeding patch antenna elements 29.
  • the plurality of non-feeding patch antenna elements 29 of the first antenna unit 2a and the plurality of non-feeding patch antenna elements 29 of the second antenna unit 2b are arranged at equal intervals. There is.
  • the array antenna device 1 has improved antenna performance.
  • Embodiment 2 The array antenna device 1b according to the second embodiment will be described with reference to FIGS. 21 to 23.
  • the array antenna device 1b of the present embodiment has the same configuration as the array antenna device 1 of the first embodiment, but is mainly different in the following points.
  • the groove 8 extends from the first main surface 6s to the second main surface 6u.
  • the groove 8 penetrates the carrier 6 in the thickness direction of the carrier 6 (third direction (z direction)).
  • the carrier 6 is composed of a plurality of carrier portions (first carrier portion 6a and second carrier portion 6b).
  • the bottom surface 8b of the groove 8 is the front surface 5s of the housing 5 facing the second main surface 6u.
  • the housing 5 is electrically grounded.
  • the array antenna device 1b of the present embodiment exerts the following effects in addition to the effects of the array antenna device 1 of the first embodiment.
  • the array antenna device 1b of the present embodiment further includes a housing 5 that supports the second main surface 6u of the carrier 6.
  • the groove 8 extends from the first main surface 6s to the second main surface 6u.
  • the bottom surface 8b of the groove 8 is the front surface 5s of the housing 5 facing the second main surface 6u.
  • the housing 5 is electrically grounded.
  • the array antenna device 1b can be miniaturized. Further, since the thickness of the carrier 6 is reduced, the thermal resistance from the wiring board 10 to the housing 5 is reduced. The array antenna device 1b can efficiently dissipate the heat generated in the wiring board 10 to the housing 5.
  • Embodiment 3 The array antenna device 1c according to the third embodiment will be described with reference to FIGS. 24 and 25.
  • the array antenna device 1c of the present embodiment has the same configuration as the array antenna device 1 of the first embodiment, but is mainly different in the following points.
  • the recess 9 is provided on the first main surface 6s of the carrier 6.
  • the first antenna unit 2a and the second antenna unit 2b are arranged in the recess 9.
  • the area of the recess 9 is larger than the total area of the wiring boards 10 of the first antenna unit 2a and the second antenna unit 2b.
  • the depth 9d of the recess 9 is preferably smaller than the thickness 10d of the wiring board 10 (see FIG. 3).
  • the side surface of the recess 9 is inclined with respect to the first main surface 6s of the carrier 6 so that the recess 9 tapers from the first main surface 6s of the carrier 6 toward the bottom surface of the recess 9.
  • the side surface of the recess 9 may be perpendicular to the first main surface 6s of the carrier 6.
  • the distance 66d from the side surface 8j of the groove 8 to the side of the bottom surface of the recess 9 opposite to the groove 8 is between the length of one side of the wiring board 10 of the first antenna unit 2a and the length of the eaves portion 10m. May be equal to the difference between. Therefore, the wiring board 10 of the first antenna unit 2a can be accurately aligned in the first direction (x direction) with respect to the carrier 6.
  • the distance 67d from the side surface 8k of the groove 8 to the side of the bottom surface of the recess 9 opposite to the groove 8 is between the length of one side of the wiring board 10 of the second antenna unit 2b and the length of the eaves portion 10n. May be equal to the difference between. Therefore, the wiring board 10 of the second antenna unit 2b can be accurately aligned in the first direction (x direction) with respect to the carrier 6.
  • the manufacturing method of the array antenna device 1c of the present embodiment includes the same steps as the manufacturing method of the array antenna device 1 of the first embodiment, but is mainly different in the following points.
  • a recess 9 is formed in the carrier 6 in addition to the groove 8.
  • the recess 9 is formed by mechanical processing such as grinding or polishing, for example.
  • the first antenna unit 2a and the second antenna unit 2b are aligned by the recess 9.
  • the side of the third main surface 10h of the wiring board 10 located on the opposite side of the groove 8 and the side of the recess 9 provided in the carrier 6 located on the opposite side of the groove 8 are observed. While aligning the wiring board 10 with respect to the recess 9.
  • the side of the third main surface 10h of the wiring board 10 located on the side opposite to the groove 8 is set on the side of the recess 9 provided in the carrier 6 located on the side opposite to the groove 8. The wiring board 10 is aligned with respect to the recess 9 so as to be in contact with each other.
  • the array antenna device 1c of the present embodiment exerts the following effects in addition to the effects of the array antenna device 1 of the first embodiment.
  • the recess 9 is provided on the first main surface 6s of the carrier 6.
  • the first antenna unit 2a and the second antenna unit 2b are joined to the recess 9. Therefore, the height of the array antenna device 1c is reduced.
  • the array antenna device 1c can be miniaturized. Further, since the first antenna unit 2a and the second antenna unit 2b are aligned by the recess 9, the array antenna device 1c can be easily manufactured with high accuracy.
  • Embodiment 4 The array antenna device 1d according to the fourth embodiment will be described with reference to FIGS. 27 to 31.
  • the array antenna device 1d of the present embodiment has the same configuration as the array antenna device 1 of the first embodiment, but is mainly different in the following points.
  • the groove 8 extends from the first main surface 6s of the carrier 6 to the second main surface 6u.
  • the groove 8 penetrates the carrier 6 in the thickness direction of the carrier 6 (third direction (z direction)).
  • the carrier 6 is composed of a plurality of carrier portions (first carrier portion 6a and second carrier portion 6b).
  • the bottom surface 8b of the groove 8 is the front surface 5s of the housing 5 facing the second main surface 6u.
  • the housing 5 is electrically grounded.
  • a plurality of insertion portions 70 are provided on the second main surface 6u of the first carrier portion 6a and the second carrier portion 6b, respectively. Further, a plurality of pin portions 71 corresponding to the plurality of insertion portions 70 are provided on the front surface 5s of the housing 5.
  • the insertion portion 70 will be described. As shown in FIGS. 28 and 29, the insertion portion 70 is a hole extending from the second main surface 6u of the first carrier portion 6a and the second carrier portion 6b constituting the carrier 6 toward the first main surface 6s. is there. The insertion portion 70 may penetrate the first carrier portion 6a and the second carrier portion 6b in the third direction (z direction).
  • the insertion portions 70 are provided for one carrier portion. It is preferable that the insertion portions 70 have a distance between them as large as possible in one carrier portion. For example, when the plane shapes of the first carrier portion 6a and the second carrier portion 6b are rectangular, the insertion portion 70 may be provided at the corner portions located diagonally of the first carrier portion 6a and the second carrier portion 6b. Good.
  • any shape may be adopted as the planar shape of the insertion portion 70.
  • the planar shape of the insertion portion 70 may be circular or oval for ease of processing.
  • the planar shape of the insertion portion 70 may be a polygonal shape such as a square.
  • the pin portion 71 is a substantially cylindrical convex portion formed from the front surface 5s of the housing 5 in the direction opposite to the housing 5. That is, the pin portion 71 is a convex portion formed so as to project from the front surface 5s of the housing 5.
  • the pin portion 71 is formed so that the dimension in the third direction (z direction) from the front surface 5s of the housing 5 to the top surface of the pin portion 71 is less than 8d in depth.
  • the pin portion 71 may adopt any shape as the planar shape of the pin portion 71 in the plan view of the front surface 5s of the housing 5.
  • a polygonal shape such as a circular shape, a rectangular shape, or a substantially rhombus shape can be used.
  • the dimensions of the pin portion 71 are determined so that they can be inserted into the corresponding insertion portion 70.
  • the pin portion 71 has a tapered portion, such as a tapered portion, a spherical portion, and a curved surface portion that is convex outward, at the tip portion distal to the front surface 5s of the housing 5, and the width becomes smaller as the distance from the front surface 5s of the housing 5 decreases.
  • a shape may be provided.
  • the functions of the insertion portion 70 and the pin portion 71 will be described.
  • the first carrier portion 6a and the second carrier portion 6b are mounted on the front surface 5s of the housing 5, a plurality of pin portions 71 corresponding to each other are inserted into the plurality of insertion portions 70.
  • the first carrier portion 6a and the first carrier portion 6a and the pin portion 71 are provided by the positional accuracy according to the dimensional difference between the insertion portion 70 and the pin portion 71 in the first direction (x direction) and the second direction (y direction).
  • the second carrier portion 6b and the housing 5 can be accurately aligned in the first direction (x direction) and the second direction (y direction). That is, the relative positions of the first carrier portion 6a and the second carrier portion 6b can be easily and highly accurately determined via the housing 5.
  • the manufacturing method of the array antenna device 1d of the present embodiment includes the same steps as the manufacturing method of the array antenna device 1 of the first embodiment, but is mainly different in the following points.
  • the insertion portion 70 is formed in the first carrier portion 6a and the second carrier portion 6b.
  • the insertion portion 70 is formed by using a processing method such as drilling, laser processing, or electrolytic polishing when manufacturing the first carrier portion 6a and the second carrier portion 6b.
  • a pin portion 71 is formed on the front surface 5s of the housing 5.
  • the pin portion 71 may be fixed to the housing 5 after being processed as a member different from the housing 5 in a process different from the housing 5 as an example. Any method can be used for fixing the pin portion 71 to the housing 5, but for example, a method such as screw tightening, press fitting, or shrink fitting can be used.
  • the pin portion 71 may be simultaneously formed as a portion integrated with the housing 5 by mechanical grinding, laser processing, electrolytic polishing, or the like.
  • the joining member 7 is supplied to the first main surface 6s of the first carrier portion 6a and the second carrier portion 6b, respectively, and then the first antenna unit 2a and the second antenna unit 2b are joined. It is mounted on the member 7.
  • the first antenna unit 2a and the second antenna unit 2b are the first main of the first carrier portion 6a and the second carrier portion 6b by means of equipment such as a flip chip bonder capable of highly accurate alignment by recognition of upper and lower twin-lens cameras. It is mounted while checking the relative position with the surface 6s. At this time, as shown in FIGS.
  • the relative positions of the first antenna unit 2a and the first carrier portion 6a and the relative positions of the second antenna unit 2b and the second carrier portion 6b are the insertion portions.
  • the feeding patch antenna elements 19 of the first antenna unit 2a and the second antenna unit 2b may be aligned at equal intervals. That is, the first antenna unit 2a and the second antenna unit 2b have an insertion portion 70 provided in the first carrier portion 6a and the second carrier portion 6b, respectively, and a pin portion 71 provided in the front surface 5s of the housing 5.
  • the eaves portions 10m and 10n shown in FIG. 34 are formed so that the total dimensions in the first direction (x direction) are smaller than the distance of 8w (see FIG. 3). Therefore, when the first antenna unit 2a and the second antenna unit 2b are mounted on the housing 5, the first antenna unit 2a and the second antenna unit 2b do not interfere with each other.
  • the array antenna device 1d of the present embodiment has the following effects in addition to the effects of the array antenna device 1 of the first embodiment by having the above configuration.
  • a plurality of insertion portions 70 are provided on the second main surface 6u of the first carrier portion 6a and the second carrier portion 6b, respectively. Further, a plurality of pin portions 71 corresponding to the plurality of insertion portions 70 are provided on the front surface 5s of the housing 5. Therefore, when the first carrier portion 6a and the second carrier portion 6b are mounted on the front surface 5s of the housing 5, the plurality of insertion portions 70 and the corresponding pin portions 71 are used in the first direction (x). The relative positions of the first carrier portion 6a and the second carrier portion 6b in the direction) and the second direction (y direction) can be kept within a certain range. That is, the housing 5, the first carrier portion 6a, and the second carrier portion 6b can be manufactured in a highly accurate and easily positioned state.
  • the advantage of the array antenna device 1d described above is that a relatively high effect can be obtained when the number of antenna units is increased. That is, in the case of the array antenna device 1e as shown in FIG. 35, for example, in the alignment by the recess 9 in the third embodiment, the third antenna unit 2c and the fourth antenna unit 2d can form the recess 9 on only one side. Alignment is not possible in the second direction (y direction).
  • the array antenna device 1d of the present embodiment by providing the insertion portion 70 and the pin portion 71, the relative positions of the antenna units can be aligned regardless of the number of antenna units.
  • the array antenna device 1e shown in FIG. 35 has six antenna units (first antenna unit 2a, second antenna unit 2b) on a carrier 6 including a first carrier portion 6a and a second carrier portion 6b (see FIG. 27). , 3rd antenna unit 2c, 4th antenna unit 2d, 5th antenna unit 2e, and 6th antenna unit 2f) are joined by a joining member.
  • the first antenna unit 2a is joined to the first carrier portion 6a by the first joining portion 7a.
  • the second antenna unit 2b is joined to the second carrier portion 6b by the second joint portion 7b.
  • the third antenna unit 2c is joined to the first carrier portion 6a by the third joint portion 7c.
  • the fourth antenna unit 2d is joined to the second carrier portion 6b by the fourth joint portion 7g.
  • the fifth antenna unit 2e is joined to the first carrier portion 6a by the fifth joint portion 7e.
  • the sixth antenna unit 2f is joined to the second carrier portion 6b by the sixth joint portion 7f.
  • the configuration of the array antenna device 1d of the present embodiment (the configuration including the plurality of insertion portions 70 and the pin portion 71) is the configuration of three or more antenna units such as the array antenna device 1e shown in FIG. 35.
  • the array antenna device can be manufactured with high accuracy and easily.
  • Embodiments 1-4 disclosed this time are exemplary in all respects and are not restrictive. As long as there is no contradiction, at least two of Embodiments 1-4 may be combined.
  • the basic scope of the present disclosure is shown by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope of the claims.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Waveguide Aerials (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Abstract

Provided is an array antenna device having improved antenna performance. The array antenna device (1) is provided with a carrier (6), a bonding member (7), a first antenna unit (2a), and a second antenna unit (2b). The first antenna unit (2a) and the second antenna unit (2b) are bonded to the carrier (6) by means of the bonding member (7). The carrier (6) has a groove (8) extending from a first major surface (6s) toward a second major surface (6u). In a plan view of the carrier (6), the groove (8) is disposed in correspondence to a gap (10g) between the first antenna unit (2a) and the second antenna unit (2b).

Description

アレイアンテナ装置Array antenna device
　本開示は、アレイアンテナ装置に関する。 This disclosure relates to an array antenna device.
　特開２００１－７６２８公報（特許文献１）は、複数のモジュールと、基板とを備えるフェーズドアレイアンテナを開示している。複数のモジュールは、各々、複数の放射素子を含んでいる。複数のモジュールは、接着剤を用いて、基板に固定されている。 Japanese Patent Application Laid-Open No. 2001-7628 (Patent Document 1) discloses a phased array antenna including a plurality of modules and a substrate. Each of the plurality of modules includes a plurality of radiating elements. The plurality of modules are fixed to the substrate using an adhesive.
特開２００１－７６２８公報JP 2001-7628
　しかし、特許文献１に開示されたアレイアンテナでは、接着剤を用いて複数のモジュールを基板に固定する際に、接着剤が、複数のモジュールの間の隙間を這い上がって、複数の放射素子の表面に付着することがあった。接着剤が複数の放射素子の表面に付着すると、アレイアンテナの性能が低下する。例えば、接着剤がはんだのような導電性接合部材である場合には、複数の放射素子が導電性接合部材を介して互いに電気的に短絡してしまい、アレイアンテナとして動作することができなくなってしまう。また、接着剤が絶縁性接着剤の場合には、絶縁性接着剤が複数の放射素子の表面に付着することによってアレイアンテナの誘電損失が増加して、アレイアンテナの出力が減少する。本開示は、上記の課題を鑑みてなされたものであり、その目的は、改善されたアンテナ性能を有するアレイアンテナ装置を提供することである。 However, in the array antenna disclosed in Patent Document 1, when a plurality of modules are fixed to the substrate by using an adhesive, the adhesive crawls up the gap between the plurality of modules and causes a plurality of radiating elements. It sometimes adhered to the surface. If the adhesive adheres to the surface of a plurality of radiating elements, the performance of the array antenna deteriorates. For example, when the adhesive is a conductive bonding member such as solder, a plurality of radiating elements are electrically short-circuited with each other via the conductive bonding member, and cannot operate as an array antenna. It ends up. Further, when the adhesive is an insulating adhesive, the dielectric loss of the array antenna increases due to the insulating adhesive adhering to the surfaces of the plurality of radiating elements, and the output of the array antenna decreases. The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide an array antenna device having improved antenna performance.
　本開示のアレイアンテナ装置は、キャリアと、接合部材と、第１アンテナユニットと、第２アンテナユニットを備えている。キャリアは、第１主面と、第１主面とは反対側の第２主面とを有する。接合部材は、第１接合部と、第２接合部とを含む。第１アンテナユニットは、キャリアの第１主面に、第１接合部を用いて接合されている。第２アンテナユニットは、キャリアの第１主面に、第２接合部を用いて接合されている。第２アンテナユニットは、第１アンテナユニットからギャップを空けて配置されている。第１アンテナユニットと第２アンテナユニットとは、各々、キャリアに近位する配線基板と、キャリアから遠位する誘電体基板とを含む。配線基板は、キャリアに対向する第３主面と、第３主面とは反対側であり、かつ、誘電体基板に対向する第４主面とを有する。配線基板は、配線基板の第４主面上に設けられている給電パッチアンテナ素子を含む。誘電体基板は、給電パッチアンテナ素子に対応して配置されている無給電パッチアンテナ素子を含む。キャリアには、第１主面から第２主面に向けて延在する溝が設けられている。キャリアの第１主面の平面視において、溝は、第１アンテナユニットと第２アンテナユニットとの間のギャップに対応して配置されている。給電パッチアンテナ素子の第１頂面から溝の底面まで延在するスリットが、第１アンテナユニットと第２アンテナユニットとの間に形成されている。 The array antenna device of the present disclosure includes a carrier, a joining member, a first antenna unit, and a second antenna unit. The carrier has a first main surface and a second main surface opposite to the first main surface. The joint member includes a first joint portion and a second joint portion. The first antenna unit is joined to the first main surface of the carrier by using the first joining portion. The second antenna unit is joined to the first main surface of the carrier by using a second joining portion. The second antenna unit is arranged with a gap from the first antenna unit. The first antenna unit and the second antenna unit each include a wiring board proximal to the carrier and a dielectric substrate distal to the carrier. The wiring board has a third main surface facing the carrier and a fourth main surface opposite to the third main surface and facing the dielectric substrate. The wiring board includes a feeding patch antenna element provided on the fourth main surface of the wiring board. The dielectric substrate includes a non-feeding patch antenna element that is arranged corresponding to the feeding patch antenna element. The carrier is provided with a groove extending from the first main surface to the second main surface. In the plan view of the first main surface of the carrier, the grooves are arranged corresponding to the gap between the first antenna unit and the second antenna unit. A slit extending from the first top surface of the feeding patch antenna element to the bottom surface of the groove is formed between the first antenna unit and the second antenna unit.
　接合部材を用いて配線基板をキャリアに固定する際に、接合部材は溝に入り込む。溝は、接合部材が、第１アンテナユニットと第２アンテナユニットとの間のギャップを這い上がって、無給電パッチアンテナ素子の表面に付着することを防止する。そのため、本開示のアレイアンテナ装置は、改善されたアンテナ性能を有する。 When fixing the wiring board to the carrier using the joining member, the joining member enters the groove. The groove prevents the joining member from crawling up the gap between the first antenna unit and the second antenna unit and adhering to the surface of the non-feeding patch antenna element. Therefore, the array antenna device of the present disclosure has improved antenna performance.
実施の形態１に係るアレイアンテナ装置の概略平面図である。It is a schematic plan view of the array antenna device which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置の、図１に示される断面線ＩＩ－ＩＩにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the section line II-II shown in FIG. 1 of the array antenna device according to the first embodiment. 実施の形態１に係るアレイアンテナ装置の、図２に示される領域ＩＩＩの概略部分拡大断面図である。FIG. 5 is a schematic partially enlarged cross-sectional view of a region III shown in FIG. 2 of the array antenna device according to the first embodiment. 実施の形態１に係るアレイアンテナ装置に含まれるキャリアに設けられる溝の変形例を示す、概略部分拡大断面図である。It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier included in the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置に含まれるキャリアに設けられる溝の変形例を示す、概略部分拡大断面図である。It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier included in the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置に含まれるキャリアに設けられる溝の変形例を示す、概略部分拡大断面図である。It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier included in the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置に含まれるキャリアに設けられる溝の変形例を示す、概略部分拡大断面図である。It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier included in the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置に含まれるキャリアに設けられる溝の変形例を示す、概略部分拡大断面図である。It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier included in the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置に含まれるキャリアに設けられる溝の変形例を示す、概略部分拡大断面図である。It is a schematic partial enlarged sectional view which shows the modification of the groove provided in the carrier included in the array antenna apparatus which concerns on Embodiment 1. FIG. 第１比較例のアレイアンテナ装置の概略部分拡大断面図である。It is a schematic partial enlarged sectional view of the array antenna device of the 1st comparative example. 実施の形態１の第１実施例のアレイアンテナ装置の概略部分拡大断面図である。It is a schematic partial enlarged sectional view of the array antenna apparatus of 1st Example of Embodiment 1. FIG. 第２比較例のアレイアンテナ装置の概略部分拡大断面図である。It is a schematic partial enlarged sectional view of the array antenna device of the 2nd comparative example. 実施の形態１の第２実施例のアレイアンテナ装置の概略部分拡大断面図である。It is a schematic partial enlarged sectional view of the array antenna apparatus of 2nd Example of Embodiment 1. FIG. スリットの深さとアレイアンテナ装置の利得との関係を表すグラフを示す図である。It is a figure which shows the graph which shows the relationship between the depth of a slit, and the gain of an array antenna apparatus. 実施の形態１に係るアレイアンテナ装置の製造方法の一工程を示す概略平面図である。It is a schematic plan view which shows one step of the manufacturing method of the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置の製造方法の図１０に示される工程の、図１０に示される断面線ＸＩ－ＸＩにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XI-XI shown in FIG. 10 of the process shown in FIG. 10 of the method for manufacturing the array antenna device according to the first embodiment. 実施の形態１に係るアレイアンテナ装置の製造方法における、図１０に示す工程の次工程を示す概略平面図である。It is a schematic plan view which shows the next process of the process shown in FIG. 10 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置の製造方法の図１２に示される工程の断面線ＸＩＩＩ－ＸＩＩＩにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XIII-XIII of the process shown in FIG. 12 of the method for manufacturing the array antenna device according to the first embodiment. 実施の形態１に係るアレイアンテナ装置の製造方法における、図１２に示す工程の次工程を示す概略平面図である。It is a schematic plan view which shows the next process of the process shown in FIG. 12 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置の製造方法の図１４に示される工程の断面線ＸＶ－ＸＶにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XV-XV of the process shown in FIG. 14 of the method for manufacturing the array antenna device according to the first embodiment. 実施の形態１に係るアレイアンテナ装置の製造方法における、図１４に示す工程の次工程を示す概略平面図である。It is a schematic plan view which shows the next process of the process shown in FIG. 14 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置の製造方法の図１６に示される工程の断面線ＸＶＩＩ－ＸＶＩＩにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XVII-XVII of the process shown in FIG. 16 of the method for manufacturing the array antenna device according to the first embodiment. 実施の形態１に係るアレイアンテナ装置の製造方法における、図１６に示す工程の次工程を示す概略平面図である。It is a schematic plan view which shows the next process of the process shown in FIG. 16 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 1. FIG. 実施の形態１に係るアレイアンテナ装置の製造方法の図１８に示される工程の断面線ＸＩＸ－ＸＩＸにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XIX-XIX of the process shown in FIG. 18 of the method for manufacturing the array antenna device according to the first embodiment. 実施の形態１の変形例に係るアレイアンテナ装置の概略部分拡大断面図である。It is a schematic partial enlarged sectional view of the array antenna device which concerns on the modification of Embodiment 1. FIG. 実施の形態２に係るアレイアンテナ装置の概略平面図である。It is a schematic plan view of the array antenna device which concerns on Embodiment 2. FIG. 実施の形態２に係るアレイアンテナ装置の、図２１に示される断面線ＸＸＩＩ－ＸＸＩＩにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XXII-XXII shown in FIG. 21 of the array antenna device according to the second embodiment. 実施の形態２に係るアレイアンテナ装置の、図２２に示される領域ＸＸＩＩＩの概略部分拡大断面図である。FIG. 2 is a schematic partially enlarged cross-sectional view of region XXIII shown in FIG. 22 of the array antenna device according to the second embodiment. 実施の形態３に係るアレイアンテナ装置の概略平面図である。It is a schematic plan view of the array antenna device which concerns on Embodiment 3. FIG. 実施の形態３に係るアレイアンテナ装置の、図２４に示される断面線ＸＸＶ－ＸＸＶにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XXV-XXV shown in FIG. 24 of the array antenna device according to the third embodiment. 実施の形態３に係るアレイアンテナ装置の製造方法の一工程を示す概略平面図である。It is a schematic plan view which shows one step of the manufacturing method of the array antenna apparatus which concerns on Embodiment 3. FIG. 実施の形態４に係るアレイアンテナ装置の概略断面図である。FIG. 5 is a schematic cross-sectional view of the array antenna device according to the fourth embodiment. 実施の形態４に係るアレイアンテナ装置に含まれるキャリアの第２主面における概略平面視である。It is a schematic plan view on the 2nd main surface of the carrier included in the array antenna device which concerns on Embodiment 4. FIG. 実施の形態４に係るアレイアンテナ装置に含まれるキャリアの、図２８に示される断面線ＸＸＩＸ－ＸＸＩＸにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XXIX-XXIX shown in FIG. 28 of the carrier included in the array antenna device according to the fourth embodiment. 実施の形態４に係るアレイアンテナ装置に含まれる筐体の前面における概略平面視である。It is a schematic plan view on the front surface of the housing included in the array antenna device according to the fourth embodiment. 実施の形態４に係るアレイアンテナ装置に含まれる筐体の、図３０に示される断面線ＸＸＸＩ－ＸＸＸＩにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line XXXI-XXXI shown in FIG. 30 of the housing included in the array antenna device according to the fourth embodiment. 実施の形態４に係るアレイアンテナ装置の製造方法の一工程を示す概略断面図である。It is schematic cross-sectional view which shows one process of the manufacturing method of the array antenna apparatus which concerns on Embodiment 4. FIG. 実施の形態４に係るアレイアンテナ装置の製造方法における、図３２に示す工程の次工程を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing the next step of the step shown in FIG. 32 in the method for manufacturing the array antenna device according to the fourth embodiment. 実施の形態４に係るアレイアンテナ装置の製造方法における、図３３に示す工程の次工程を示す概略断面図である。It is schematic cross-sectional view which shows the next process of the process shown in FIG. 33 in the manufacturing method of the array antenna apparatus which concerns on Embodiment 4. FIG. ３つ以上のアンテナユニットを有するアレイアンテナ装置の一例を示す、概略平面図である。It is a schematic plan view which shows an example of the array antenna apparatus which has 3 or more antenna units.
　以下、本開示の実施の形態を説明する。なお、同一の構成には同一の参照番号を付し、その説明は繰り返さない。 Hereinafter, embodiments of the present disclosure will be described. The same reference number is assigned to the same configuration, and the description is not repeated.
　実施の形態１．
　図１から図４Ｆを参照して、実施の形態１のアレイアンテナ装置１を説明する。アレイアンテナ装置１は、キャリア６と、接合部材７と、第１アンテナユニット２ａと、第２アンテナユニット２ｂとを主に備えている。アレイアンテナ装置１は、筐体５と、外部基板３５と、電子部品３７と、電気接続部材４０とをさらに備えてもよい。 Embodiment 1.
The array antenna device 1 of the first embodiment will be described with reference to FIGS. 1 to 4F. The array antenna device 1 mainly includes a carrier 6, a joining member 7, a first antenna unit 2a, and a second antenna unit 2b. The array antenna device 1 may further include a housing 5, an external substrate 35, an electronic component 37, and an electrical connection member 40.
　筐体５は、前面５ｓを有している。筐体５の前面５ｓは、筐体５は、第１方向（ｘ方向）と、第１方向に交差する第２方向（ｙ方向）とに延在している。特定的には、第２方向は、第１方向に垂直である。例えば、アルミニウム合金のような、高い熱伝導率を有する金属で形成されている。筐体５は、電気的に接地されている。 The housing 5 has a front surface 5s. The front surface 5s of the housing 5 extends in the first direction (x direction) and the second direction (y direction) intersecting the first direction. Specifically, the second direction is perpendicular to the first direction. It is made of a metal with high thermal conductivity, for example an aluminum alloy. The housing 5 is electrically grounded.
　キャリア６は、第１主面６ｓと、第１主面６ｓとは反対側の第２主面６ｕとを有している。第１主面６ｓと第２主面６ｕとは、各々、第１方向（ｘ方向）と第２方向（ｙ方向）とに延在している。第１主面６ｓと第２主面６ｕとは、第１方向（ｘ方向）及び第２方向（ｙ方向）に垂直な第３方向（ｚ方向）に互いに離間している。キャリア６の第２主面６ｕは、筐体５の前面５ｓに面している。キャリア６は、例えば、ねじ等の固定部材（図示せず）を用いて、筐体５の前面５ｓに固定されている。キャリア６は、ねじ等の固定部材（図示せず）と接着剤（図示せず）とを用いて、筐体５により強固に固定されてもよい。キャリア６は、電気的に接地されている。 The carrier 6 has a first main surface 6s and a second main surface 6u on the opposite side of the first main surface 6s. The first main surface 6s and the second main surface 6u extend in the first direction (x direction) and the second direction (y direction), respectively. The first main surface 6s and the second main surface 6u are separated from each other in the third direction (z direction) perpendicular to the first direction (x direction) and the second direction (y direction). The second main surface 6u of the carrier 6 faces the front surface 5s of the housing 5. The carrier 6 is fixed to the front surface 5s of the housing 5 by using, for example, a fixing member (not shown) such as a screw. The carrier 6 may be firmly fixed by the housing 5 by using a fixing member (not shown) such as a screw and an adhesive (not shown). The carrier 6 is electrically grounded.
　キャリア６は、筐体５と配線基板１０との間の線膨張係数の差に起因する配線基板１０の熱ひずみを緩和する。キャリア６と配線基板１０との間の線膨張係数の差は、好ましくは、３×１０-6（／Ｋ）以下である。キャリア６は、第１アンテナユニット２ａ及び第２アンテナユニット２ｂで発生する熱を筐体５に伝達する。そのため、キャリア６は、銅（Ｃｕ）、銅－タングステン（Ｃｕ－Ｗ）合金、または、銅－モリブデン（Ｃｕ－Ｍｏ）合金のような、高い熱伝導率を有する材料で形成されていることが好ましい。キャリア６の防錆のために、ニッケルめっきまたはクロムめっきがキャリア６の表面（第１主面６ｓ及び第２主面６ｕなど）に施されてもよい。 The carrier 6 relaxes the thermal strain of the wiring board 10 due to the difference in the coefficient of linear expansion between the housing 5 and the wiring board 10. The difference in the coefficient of linear expansion between the carrier 6 and the wiring board 10 is preferably 3 × 10 -6 (/ K) or less. The carrier 6 transfers the heat generated by the first antenna unit 2a and the second antenna unit 2b to the housing 5. Therefore, the carrier 6 may be formed of a material having high thermal conductivity, such as copper (Cu), copper-tungsten (Cu-W) alloy, or copper-molybdenum (Cu-Mo) alloy. preferable. To prevent rust on the carrier 6, nickel plating or chrome plating may be applied to the surface of the carrier 6 (first main surface 6s, second main surface 6u, etc.).
　キャリア６には、第１主面６ｓから第２主面６ｕに向けて延在する溝８が設けられている。溝８は、底面８ｂと、側面８ｊ，８ｋとによって規定されている。溝８の側面８ｊは、第１アンテナユニット２ａに近位し、かつ、第２アンテナユニット２ｂから遠位している。溝８の側面８ｋは、第２アンテナユニット２ｂに近位し、かつ、第１アンテナユニット２ａから遠位している。溝８の幅８ｗは、側面８ｊと側面８ｋとの間の最小距離として定義される。図１に示される、キャリア６の第１主面６ｓの平面視において、溝８は、直線状に設けられている。 The carrier 6 is provided with a groove 8 extending from the first main surface 6s to the second main surface 6u. The groove 8 is defined by a bottom surface 8b and side surfaces 8j and 8k. The side surface 8j of the groove 8 is proximal to the first antenna unit 2a and distal to the second antenna unit 2b. The side surface 8k of the groove 8 is proximal to the second antenna unit 2b and distal to the first antenna unit 2a. The width 8w of the groove 8 is defined as the minimum distance between the side surface 8j and the side surface 8k. In the plan view of the first main surface 6s of the carrier 6 shown in FIG. 1, the groove 8 is provided in a straight line.
　溝８の底面８ｂは、キャリア６の第２主面６ｕから離間されている。溝８の底面８ｂは、特に限定されないが、キャリア６の第１主面６ｓに平行な平面である。溝８の底面８ｂがキャリア６の第１主面６ｓに平行な平面である場合には、後述するスリット６０の深さ６０ｄの管理が容易になり、アレイアンテナ装置１の品質が安定化される。 The bottom surface 8b of the groove 8 is separated from the second main surface 6u of the carrier 6. The bottom surface 8b of the groove 8 is not particularly limited, but is a plane parallel to the first main surface 6s of the carrier 6. When the bottom surface 8b of the groove 8 is a plane parallel to the first main surface 6s of the carrier 6, the depth 60d of the slit 60, which will be described later, can be easily managed, and the quality of the array antenna device 1 is stabilized. ..
　溝８の深さ８ｄは、キャリア６の第１主面６ｓから溝８の底面８ｂまでの距離として定義される。キャリア６の最薄部分の厚さ６ｔは、溝８の底面８ｂからキャリア６の第２主面６ｕまでの距離として定義される。キャリア６の最薄部分の厚さ６ｔは、キャリア６の厚さと溝８の深さ８ｄとの間の差よって与えられる。キャリア６の最薄部分の厚さ６ｔは、キャリア６に要求される機械的強度及びアレイアンテナ装置１に要求される長期信頼性などに応じて、適宜定められる。キャリア６の最薄部分の厚さ６ｔは、特に限定されないが、１ｍｍ以上であってもよい。 The depth 8d of the groove 8 is defined as the distance from the first main surface 6s of the carrier 6 to the bottom surface 8b of the groove 8. The thickness 6t of the thinnest portion of the carrier 6 is defined as the distance from the bottom surface 8b of the groove 8 to the second main surface 6u of the carrier 6. The thickness 6t of the thinnest portion of the carrier 6 is given by the difference between the thickness of the carrier 6 and the depth 8d of the groove 8. The thickness 6t of the thinnest portion of the carrier 6 is appropriately determined according to the mechanical strength required for the carrier 6 and the long-term reliability required for the array antenna device 1. The thickness of the thinnest portion of the carrier 6 is not particularly limited, but may be 1 mm or more.
　図２及び図３に示されるように、溝８の断面形状は、矩形である。溝８の断面形状は、矩形に限られず、例えば、図４Ａから図４Ｆのいずれかに示される断面形状であってもよい。図４Ａ及び図４Ｂに示されるように、溝８の断面形状は台形であってもよい。図４Ａに示されるように、溝８の側面８ｊ，８ｋは、キャリア６の第１主面６ｓに近づくにつれて互いに近づくように、第１主面６ｓに対して傾いてもよい。図４Ｂに示されるように、溝８の側面８ｊ，８ｋは、キャリア６の第１主面６ｓに近づくにつれて互いに離れるように、第１主面６ｓに対して傾いてもよい。 As shown in FIGS. 2 and 3, the cross-sectional shape of the groove 8 is rectangular. The cross-sectional shape of the groove 8 is not limited to a rectangle, and may be, for example, the cross-sectional shape shown in any of FIGS. 4A to 4F. As shown in FIGS. 4A and 4B, the cross-sectional shape of the groove 8 may be trapezoidal. As shown in FIG. 4A, the side surfaces 8j, 8k of the groove 8 may be tilted with respect to the first main surface 6s so as to approach each other as they approach the first main surface 6s of the carrier 6. As shown in FIG. 4B, the side surfaces 8j, 8k of the groove 8 may be tilted with respect to the first main surface 6s so as to separate from each other as they approach the first main surface 6s of the carrier 6.
　図４Ｃ及び図４Ｄに示されるように、キャリア６の第１主面６ｓと溝８の側面８ｊ，８ｋとの間の角部は、面取りされてもよい。具体的には、図４Ｃに示されるように、第１主面６ｓと側面８ｊ，８ｋとの間の角部は、直線角面取りされてもよい。図４Ｄに示されるように、第１主面６ｓと側面８ｊ，８ｋとの間の角部は、丸面取りされてもよい。図４Ｅに示されるように、溝８の側面８ｊ，８ｋは、溝８の底面８ｂの近くで後退しており、溝８の底面８ｂは、溝８の開口部よりも広い幅を有してもよい。図２、図３及び図４Ａから図４Ｅに示されるように、溝８は、溝８の幅方向（第１方向（ｘ方向））の中心線に対して対称な形状を有してもよい。図４Ｆに示されるように、溝８は、溝８の幅方向の中心線に対して非対称な形状を有してもよい。 As shown in FIGS. 4C and 4D, the corner portion between the first main surface 6s of the carrier 6 and the side surfaces 8j and 8k of the groove 8 may be chamfered. Specifically, as shown in FIG. 4C, the corner portion between the first main surface 6s and the side surfaces 8j and 8k may be linearly chamfered. As shown in FIG. 4D, the corners between the first main surface 6s and the side surfaces 8j, 8k may be round chamfered. As shown in FIG. 4E, the side surfaces 8j, 8k of the groove 8 recede near the bottom surface 8b of the groove 8, and the bottom surface 8b of the groove 8 has a wider width than the opening of the groove 8. May be good. As shown in FIGS. 2, 3 and 4A to 4E, the groove 8 may have a shape symmetrical with respect to the center line in the width direction (first direction (x direction)) of the groove 8. .. As shown in FIG. 4F, the groove 8 may have a shape that is asymmetric with respect to the center line in the width direction of the groove 8.
　図１から図３に示されるように、接合部材７は、第１接合部７ａと、第２接合部７ｂとを含む。接合部材７は、キャリア６の溝８の底面８ｂから離間されてもよい。第１接合部７ａは、溝８において、第２接合部７ｂから離間されてもよい。接合部材７は、はんだ、導電性樹脂接着剤、または、異方性導電接着剤のような導電性接合部材であってもよいし、絶縁性樹脂接着剤のような絶縁性接合部材であってもよい。 As shown in FIGS. 1 to 3, the joining member 7 includes a first joining portion 7a and a second joining portion 7b. The joining member 7 may be separated from the bottom surface 8b of the groove 8 of the carrier 6. The first joint portion 7a may be separated from the second joint portion 7b in the groove 8. The joining member 7 may be a conductive joining member such as a solder, a conductive resin adhesive, or an anisotropic conductive adhesive, or an insulating joining member such as an insulating resin adhesive. May be good.
　接合部材７は、液体状や固体状のものを用いることができる。後述する製造プロセスにおいて、接合部材７は荷重に対して柔軟に変形する程度の粘度が求められる。一方で、意図しない場所に接合部材７が接触することを避けるためには、接合部材７は製造プロセス中の振動によって容易に流れない程度の粘度が求められる。これらを両立させるために、接合部材７が液状である場合の粘度は５Ｐａ・ｓ以上３００Ｐａ・ｓ以下の範囲であることが望ましく、さらに望ましくは１０Ｐａ・ｓ以上５０Ｐａ・ｓ以下である。 As the joining member 7, a liquid or solid state can be used. In the manufacturing process described later, the joining member 7 is required to have a viscosity that allows it to be flexibly deformed with respect to a load. On the other hand, in order to prevent the joining member 7 from coming into contact with an unintended place, the joining member 7 is required to have a viscosity that does not easily flow due to vibration during the manufacturing process. In order to achieve both of these, the viscosity of the joining member 7 when it is liquid is preferably in the range of 5 Pa · s or more and 300 Pa · s or less, and more preferably 10 Pa · s or more and 50 Pa · s or less.
　第１アンテナユニット２ａは、キャリア６の第１主面６ｓに、第１接合部７ａを用いて接合されている。第２アンテナユニット２ｂは、キャリア６の第１主面６ｓに、第２接合部７ｂを用いて接合されている。第２アンテナユニット２ｂは、第１アンテナユニット２ａからギャップ１０ｇを空けて配置されている。キャリア６の第１主面６ｓの平面視において、溝８は、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇに対応して配置されている。図３に示されるように、ギャップ１０ｇの幅１０ｗは、溝８の幅８ｗより狭い。図２０に示される本実施の形態の変形例のように、ギャップ１０ｇの幅１０ｗは、溝８の幅８ｗより広くてもよい。ギャップ１０ｇの幅１０ｗは、溝８の幅８ｗに等しくてもよい。 The first antenna unit 2a is joined to the first main surface 6s of the carrier 6 by using the first joining portion 7a. The second antenna unit 2b is joined to the first main surface 6s of the carrier 6 by using the second joining portion 7b. The second antenna unit 2b is arranged with a gap of 10 g from the first antenna unit 2a. In the plan view of the first main surface 6s of the carrier 6, the groove 8 is arranged corresponding to the gap 10 g between the first antenna unit 2a and the second antenna unit 2b. As shown in FIG. 3, the width 10w of the gap 10g is narrower than the width 8w of the groove 8. As in the modified example of the present embodiment shown in FIG. 20, the width 10w of the gap 10g may be wider than the width 8w of the groove 8. The width 10w of the gap 10g may be equal to the width 8w of the groove 8.
　第２アンテナユニット２ｂは、第１アンテナユニット２ａと同様の構成を備えている。以下、第１アンテナユニット２ａの構成を説明する。第１アンテナユニット２ａは、配線基板１０と、誘電体基板２６とを含む。第３方向（ｚ方向）において、配線基板１０と誘電体基板２６とは積層されている。配線基板１０は、誘電体基板２６よりも、キャリア６に近位する側に配置されている。誘電体基板２６は、配線基板１０よりも、キャリア６に遠位する側に配置されている。 The second antenna unit 2b has the same configuration as the first antenna unit 2a. Hereinafter, the configuration of the first antenna unit 2a will be described. The first antenna unit 2a includes a wiring board 10 and a dielectric board 26. In the third direction (z direction), the wiring board 10 and the dielectric board 26 are laminated. The wiring board 10 is arranged on the side proximal to the carrier 6 with respect to the dielectric board 26. The dielectric substrate 26 is arranged on the side distal to the carrier 6 with respect to the wiring substrate 10.
　第１アンテナユニット２ａの配線基板１０の側面１０ｊは、溝８の側面８ｊよりも、溝８の幅方向（第１方向（ｘ方向））の中心線に向かって出っ張っている。第１アンテナユニット２ａの配線基板１０のうち溝８の側面８ｊから出っ張っている部分は、ひさし部１０ｍである。溝８の幅方向におけるひさし部１０ｍの長さは、例えば、０．５ｍｍ以下である。第２アンテナユニット２ｂの配線基板１０の側面１０ｋは、溝８の側面８ｋよりも、溝８の幅方向の中心線に向かって出っ張っている。第２アンテナユニット２ｂの配線基板１０のうち溝８の側面８ｋから出っ張っている部分は、ひさし部１０ｎである。溝８の幅方向におけるひさし部１０ｎの長さは、例えば、０．５ｍｍ以下である。ひさし部１０ｍ，１０ｎは、接合部材７が配線基板１０の第４主面１０ｓに這い上がることを効果的に防止する。 The side surface 10j of the wiring board 10 of the first antenna unit 2a protrudes from the side surface 8j of the groove 8 toward the center line in the width direction (first direction (x direction)) of the groove 8. The portion of the wiring board 10 of the first antenna unit 2a that protrudes from the side surface 8j of the groove 8 is the eaves portion 10m. The length of the eaves portion 10 m in the width direction of the groove 8 is, for example, 0.5 mm or less. The side surface 10k of the wiring board 10 of the second antenna unit 2b protrudes from the side surface 8k of the groove 8 toward the center line in the width direction of the groove 8. The portion of the wiring board 10 of the second antenna unit 2b that protrudes from the side surface 8k of the groove 8 is the eaves portion 10n. The length of the eaves portion 10n in the width direction of the groove 8 is, for example, 0.5 mm or less. The eaves portions 10m and 10n effectively prevent the joining member 7 from climbing up to the fourth main surface 10s of the wiring board 10.
　第１アンテナユニット２ａの配線基板１０の側面１０ｊは、溝８の側面８ｊに面一であってもよい。第２アンテナユニット２ｂの配線基板１０の側面１０ｋは、溝８の側面８ｋに面一であってもよい。第１アンテナユニット２ａの配線基板１０の側面１０ｊは、溝８の側面８ｊよりも、溝８の幅方向（第１方向（ｘ方向））の中心から後退してもよい。第２アンテナユニット２ｂの配線基板１０の側面１０ｋは、溝８の側面８ｋよりも、溝８の幅方向の中心から後退してもよい。 The side surface 10j of the wiring board 10 of the first antenna unit 2a may be flush with the side surface 8j of the groove 8. The side surface 10k of the wiring board 10 of the second antenna unit 2b may be flush with the side surface 8k of the groove 8. The side surface 10j of the wiring board 10 of the first antenna unit 2a may be retracted from the center of the width direction (first direction (x direction)) of the groove 8 with respect to the side surface 8j of the groove 8. The side surface 10k of the wiring board 10 of the second antenna unit 2b may be retracted from the center of the groove 8 in the width direction with respect to the side surface 8k of the groove 8.
　キャリア６の第１主面６ｓの平面視において、配線基板１０の一辺の長さは、３０ｍｍ以下であってもよい。そのため、配線基板１０とキャリア６との間の熱膨張係数の差に起因する配線基板１０の熱歪みが小さくなって、アレイアンテナ装置１は向上された長期信頼性を有する。 In a plan view of the first main surface 6s of the carrier 6, the length of one side of the wiring board 10 may be 30 mm or less. Therefore, the thermal strain of the wiring board 10 due to the difference in the coefficient of thermal expansion between the wiring board 10 and the carrier 6 is reduced, and the array antenna device 1 has improved long-term reliability.
　図２及び図３に示されるように、配線基板１０は、半導体基板１１と、半導体基板１１上に設けられた配線層１５と、給電パッチアンテナ素子１９と、接地導体層２０とを含む。配線基板１０は、キャリア６の第１主面６ｓに対向する第３主面１０ｈと、第３主面１０ｈとは反対側の第４主面１０ｓとを有する。第３主面１０ｈと第４主面１０ｓとは、各々、第１方向（ｘ方向）と第２方向（ｙ方向）とに延在している。 As shown in FIGS. 2 and 3, the wiring board 10 includes a semiconductor board 11, a wiring layer 15 provided on the semiconductor board 11, a feeding patch antenna element 19, and a ground conductor layer 20. The wiring board 10 has a third main surface 10h facing the first main surface 6s of the carrier 6, and a fourth main surface 10s opposite to the third main surface 10h. The third main surface 10h and the fourth main surface 10s extend in the first direction (x direction) and the second direction (y direction), respectively.
　半導体基板１１は、配線層１５とキャリア６との間に配置されている。半導体基板１１は、配線層１５よりもキャリア６に近位している。半導体基板１１は、一般的な半導体ウェハ製造プロセスによって製造される回路基板である。半導体基板１１は、例えば、Ｓｉ、ＳｉＧｅ、ＧａＡｓ、ＩｎＰ、ＧａＳｂ、ＳｉＣまたはＧａＮなどの半導体材料で形成されている。 The semiconductor substrate 11 is arranged between the wiring layer 15 and the carrier 6. The semiconductor substrate 11 is closer to the carrier 6 than the wiring layer 15. The semiconductor substrate 11 is a circuit board manufactured by a general semiconductor wafer manufacturing process. The semiconductor substrate 11 is made of a semiconductor material such as Si, SiGe, GaAs, InP, GaSb, SiC or GaN.
　半導体基板１１は、能動回路１３と、制御回路１４とを含む。能動回路１３と制御回路１４とは、半導体基板１１に集積されている。能動回路１３と制御回路１４とは、半導体基板１１のうち配線層１５に面する側に設けられている。能動回路１３は、例えば、マイクロ波やミリ波などの電磁波の送信または受信を行う高周波電気素子を含んでいる。高周波電気素子は、例えば、低雑音増幅器、大電力増幅器、または、移相器であってもよい。能動回路１３は、給電パッチアンテナ素子１９に接続されている。能動回路１３は、給電パッチアンテナ素子１９を介して、電磁波を送信または受信することができる。制御回路１４は、能動回路１３の動作を制御する。 The semiconductor substrate 11 includes an active circuit 13 and a control circuit 14. The active circuit 13 and the control circuit 14 are integrated on the semiconductor substrate 11. The active circuit 13 and the control circuit 14 are provided on the side of the semiconductor substrate 11 facing the wiring layer 15. The active circuit 13 includes, for example, a high-frequency electric element that transmits or receives electromagnetic waves such as microwaves and millimeter waves. The high frequency electric element may be, for example, a low noise amplifier, a high power amplifier, or a phase shifter. The active circuit 13 is connected to the feeding patch antenna element 19. The active circuit 13 can transmit or receive electromagnetic waves via the feeding patch antenna element 19. The control circuit 14 controls the operation of the active circuit 13.
　配線層１５は、能動回路１３と、給電パッチアンテナ素子１９とに互いに電気的に接続している。具体的には、配線層１５は、絶縁層１６と、導電ビア１８とを含む。導電ビア１８は、絶縁層１６中に設けられている。導電ビア１８は、能動回路１３と、給電パッチアンテナ素子１９とに接続されている。導電ビア１８は、例えば、銅のような低い電気抵抗を有する金属材料で形成されている。導電ビア１８の防錆のために、導電ビア１８の表面に、ニッケルめっきと金めっきとが施されてもよい。 The wiring layer 15 is electrically connected to the active circuit 13 and the feeding patch antenna element 19. Specifically, the wiring layer 15 includes an insulating layer 16 and a conductive via 18. The conductive via 18 is provided in the insulating layer 16. The conductive via 18 is connected to the active circuit 13 and the feeding patch antenna element 19. The conductive via 18 is made of a metal material having a low electrical resistance, such as copper. Nickel plating and gold plating may be applied to the surface of the conductive via 18 to prevent rust on the conductive via 18.
　絶縁層１６は、小さな誘電正接（ｔａｎδ）を有する材料で形成されていることが好ましい。絶縁層１６は、１ＧＨｚの電磁波の周波数において０．００５以下の誘電正接（ｔａｎδ）を有する材料で形成されてもよく、１ＧＨｚの電磁波の周波数において０．００３以下の誘電正接を有する材料で形成されてもよい。絶縁層１６は、耐熱性及び電気絶縁性が優れた材料で形成されていることが好ましい。絶縁層１６は、特に限定されないが、熱可塑性ポリイミド樹脂または熱硬化性ポリイミド樹脂で形成されてもよい。絶縁層１６は、特に限定されないが、３μｍ以上１５μｍ以下の厚さを有してもよい。 The insulating layer 16 is preferably made of a material having a small dielectric loss tangent (tan δ). The insulating layer 16 may be formed of a material having a dielectric loss tangent (tan δ) of 0.005 or less at an electromagnetic wave frequency of 1 GHz, or may be formed of a material having a dielectric loss tangent of 0.003 or less at an electromagnetic wave frequency of 1 GHz. You may. The insulating layer 16 is preferably made of a material having excellent heat resistance and electrical insulation. The insulating layer 16 is not particularly limited, but may be formed of a thermoplastic polyimide resin or a thermosetting polyimide resin. The insulating layer 16 is not particularly limited, but may have a thickness of 3 μm or more and 15 μm or less.
　配線層１５は、導体１７をさらに含んでいる。導体１７は、絶縁層１６中に設けられている。導体１７の一方端は、接続端子３０に接続されている。導体１７の他方端は、能動回路１３または制御回路１４に接続されている。導体１７の厚さは、例えば、５μｍ以上３０μ以下である。導体１７の幅は、導体１７を流れる電流の量または周波数などによって決定される。導体１７の幅は、特に限定されないが、５μｍ以上５００μｍ以下である。導体１７は、例えば、銅のような低い電気抵抗を有する金属材料で形成されている。導体１７の防錆のために、導体１７の表面に、ニッケルめっきと金めっきとが施されてもよい。 The wiring layer 15 further includes a conductor 17. The conductor 17 is provided in the insulating layer 16. One end of the conductor 17 is connected to the connection terminal 30. The other end of the conductor 17 is connected to the active circuit 13 or the control circuit 14. The thickness of the conductor 17 is, for example, 5 μm or more and 30 μm or less. The width of the conductor 17 is determined by the amount or frequency of the current flowing through the conductor 17. The width of the conductor 17 is not particularly limited, but is 5 μm or more and 500 μm or less. The conductor 17 is made of a metal material having a low electrical resistance, such as copper. Nickel plating and gold plating may be applied to the surface of the conductor 17 to prevent rust on the conductor 17.
　配線層１５は、例えば、以下の工程によって形成される。半導体基板１１上に絶縁層１６を形成する。一例では、スピンコート法を用いて半導体基板１１上に液状の絶縁樹脂を塗布して、半導体基板１１上に絶縁樹脂膜を形成する。それから、絶縁樹脂膜に熱を印加する、または、紫外線を照射することによって、絶縁樹脂膜を硬化させる。こうして、絶縁層１６が形成される。別の例では、半導体基板１１上に絶縁シートを載置する。絶縁シートに熱を印加する、または、紫外線を照射することによって、絶縁シートを硬化させる。こうして、絶縁層１６が形成される。 The wiring layer 15 is formed by, for example, the following process. The insulating layer 16 is formed on the semiconductor substrate 11. In one example, a liquid insulating resin is applied onto the semiconductor substrate 11 by using a spin coating method to form an insulating resin film on the semiconductor substrate 11. Then, the insulating resin film is cured by applying heat to the insulating resin film or irradiating it with ultraviolet rays. In this way, the insulating layer 16 is formed. In another example, the insulating sheet is placed on the semiconductor substrate 11. The insulating sheet is cured by applying heat to the insulating sheet or irradiating it with ultraviolet rays. In this way, the insulating layer 16 is formed.
　それから、エッチングなどの一般的なパターニング工程によって、絶縁層１６に孔を形成する。孔に銅のような導電材料を充填することによって、導体１７と導電ビア１８とが形成される。こうして、配線層１５が得られる。 Then, holes are formed in the insulating layer 16 by a general patterning process such as etching. By filling the holes with a conductive material such as copper, the conductor 17 and the conductive via 18 are formed. In this way, the wiring layer 15 is obtained.
　配線基板１０は、例えば、銅または金のような導電材料で形成されている接続端子３０を含んでもよい。図１に示されるように、キャリア６の第１主面６ｓの平面視において、接続端子３０は、外部基板３５に対向する配線基板１０の一辺に沿って配列されている。接続端子３０は、誘電体基板２６から露出している第４主面１０ｓ上に設けられている。配線基板１０の第４主面１０ｓは、キャリア６（または半導体基板１１）から遠位する絶縁層１６の表面である。 The wiring board 10 may include a connection terminal 30 made of a conductive material such as copper or gold. As shown in FIG. 1, in a plan view of the first main surface 6s of the carrier 6, the connection terminals 30 are arranged along one side of the wiring board 10 facing the external board 35. The connection terminal 30 is provided on the fourth main surface 10s exposed from the dielectric substrate 26. The fourth main surface 10s of the wiring board 10 is the surface of the insulating layer 16 distal to the carrier 6 (or the semiconductor substrate 11).
　給電パッチアンテナ素子１９は、誘電体基板２６に対向する配線基板１０の第４主面１０ｓ上に配置されている。図２及び図３に示されるように、配線基板１０は、複数の給電パッチアンテナ素子１９を含み、複数の給電パッチアンテナ素子１９は、二次元アレイ状に、配線基板１０の第４主面１０ｓ上に配置されてもよい。複数の給電パッチアンテナ素子１９は、一次元アレイ状に、配線基板１０の第４主面１０ｓ上に配置されてもよい。キャリア６の第１主面６ｓの平面視において、第１アンテナユニット２ａの複数の給電パッチアンテナ素子１９と、第２アンテナユニット２ｂの複数の給電パッチアンテナ素子１９とは、等間隔に配列されている。 The feeding patch antenna element 19 is arranged on the fourth main surface 10s of the wiring board 10 facing the dielectric substrate 26. As shown in FIGS. 2 and 3, the wiring board 10 includes a plurality of feeding patch antenna elements 19, and the plurality of feeding patch antenna elements 19 form a two-dimensional array on the fourth main surface 10s of the wiring board 10. It may be placed on top. The plurality of feeding patch antenna elements 19 may be arranged on the fourth main surface 10s of the wiring board 10 in a one-dimensional array. In the plan view of the first main surface 6s of the carrier 6, the plurality of feeding patch antenna elements 19 of the first antenna unit 2a and the plurality of feeding patch antenna elements 19 of the second antenna unit 2b are arranged at equal intervals. There is.
　給電パッチアンテナ素子１９は、キャリア６から遠位する第１頂面１９ｔを有している。給電パッチアンテナ素子１９は、導電ビア１８を介して、能動回路１３に接続されている。給電パッチアンテナ素子１９は、特に限定されないが、銅または金のような導電材料で形成されている。 The feeding patch antenna element 19 has a first top surface 19t distal to the carrier 6. The feeding patch antenna element 19 is connected to the active circuit 13 via the conductive via 18. The feeding patch antenna element 19 is not particularly limited, but is made of a conductive material such as copper or gold.
　接地導体層２０は、配線基板１０の第４主面１０ｓ上に設けられている。接地導体層２０は、給電パッチアンテナ素子１９から離間されており、給電パッチアンテナ素子１９から電気的に絶縁されている。第４主面１０ｓ（または第１主面６ｓ）の平面視において、接地導体層２０は、給電パッチアンテナ素子１９を取り囲んでもよい。接地導体層２０は、配線基板１０の第４主面１０ｓの最も外側にも設けられてもよい。接地導体層２０は、特に限定されないが、銅または金のような導電材料で形成されている。接地導体層２０は、能動回路１３で発生した電磁波のノイズを遮蔽し、このノイズが給電パッチアンテナ素子１９または無給電パッチアンテナ素子２９に結合することを抑制する。 The ground conductor layer 20 is provided on the fourth main surface 10s of the wiring board 10. The ground conductor layer 20 is separated from the feeding patch antenna element 19 and is electrically insulated from the feeding patch antenna element 19. In a plan view of the fourth main surface 10s (or the first main surface 6s), the ground conductor layer 20 may surround the feeding patch antenna element 19. The ground conductor layer 20 may also be provided on the outermost side of the fourth main surface 10s of the wiring board 10. The ground conductor layer 20 is not particularly limited, but is made of a conductive material such as copper or gold. The ground conductor layer 20 shields the noise of the electromagnetic wave generated in the active circuit 13 and suppresses the noise from being coupled to the feeding patch antenna element 19 or the non-feeding patch antenna element 29.
　接地導体層２０は、キャリア６から遠位する第２頂面２０ｔを有している。接地導体層２０の第２頂面２０ｔは、給電パッチアンテナ素子１９の第１頂面１９ｔと実質的に面一である。本明細書において、接地導体層２０の第２頂面２０ｔが給電パッチアンテナ素子１９の第１頂面１９ｔと実質的に面一であることは、接地導体層２０の第２頂面２０ｔと給電パッチアンテナ素子１９の第１頂面１９ｔとの間の第３方向（ｚ方向）のずれが、５μｍ以下であることを意味する。接地導体層２０の第２頂面２０ｔと給電パッチアンテナ素子１９の第１頂面１９ｔとの間の第３方向（ｚ方向）のずれは、３μｍ以下であってもよく、２μｍ以下であってもよく、１μｍ以下であってもよい。接地導体層２０の第２頂面２０ｔは、好ましくは、給電パッチアンテナ素子１９の第１頂面１９ｔと面一である。すなわち、接地導体層２０の第２頂面２０ｔと給電パッチアンテナ素子１９の第１頂面１９ｔとの間の第３方向（ｚ方向）のずれは、好ましくは、０μｍである。 The ground conductor layer 20 has a second top surface 20t distal to the carrier 6. The second top surface 20t of the ground conductor layer 20 is substantially flush with the first top surface 19t of the feeding patch antenna element 19. In the present specification, the fact that the second top surface 20t of the ground conductor layer 20 is substantially flush with the first top surface 19t of the feeding patch antenna element 19 means that the feeding is fed to the second top surface 20t of the ground conductor layer 20. This means that the deviation of the patch antenna element 19 from the first top surface 19t in the third direction (z direction) is 5 μm or less. The deviation in the third direction (z direction) between the second top surface 20t of the ground conductor layer 20 and the first top surface 19t of the feeding patch antenna element 19 may be 3 μm or less, and may be 2 μm or less. It may be 1 μm or less. The second top surface 20t of the ground conductor layer 20 is preferably flush with the first top surface 19t of the feeding patch antenna element 19. That is, the deviation in the third direction (z direction) between the second top surface 20t of the ground conductor layer 20 and the first top surface 19t of the feeding patch antenna element 19 is preferably 0 μm.
　誘電体基板２６は、接着層２２を介して、配線基板１０の第４主面１０ｓに取り付けられている。誘電体基板２６は、誘電体基材２７と、給電パッチアンテナ素子１９に対応して配置されている無給電パッチアンテナ素子２９とを含む。 The dielectric substrate 26 is attached to the fourth main surface 10s of the wiring board 10 via the adhesive layer 22. The dielectric substrate 26 includes a dielectric base material 27 and a non-feeding patch antenna element 29 arranged corresponding to the feeding patch antenna element 19.
　誘電体基材２７は、配線基板１０の第４主面１０ｓに対向する第５主面２７ｒと、第５主面２７ｒとは反対側の第６主面２７ｓとを有している。第５主面２７ｒと第６主面２７ｓとは、各々、第１方向（ｘ方向）と第２方向（ｙ方向）とに延在している。誘電体基材２７は、例えば、高周波用プリント基板、液晶ポリマー基板、または、低温同時焼成セラミックス（ＬＴＣＣ）基板のようなセラミックス基板であってもよい。誘電体基材２７は、ポリテトラフルオロエチレン（ＰＴＦＥ）などの低誘電率および低誘電損失を有するフッ素樹脂系の高周波用プリント基板であってもよい。低誘電率および低誘電損失を有する誘電体基材２７は、マイクロ波またはミリ波のような高周波信号の伝送遅延および伝送損失を減少させることができる。 The dielectric base material 27 has a fifth main surface 27r facing the fourth main surface 10s of the wiring board 10 and a sixth main surface 27s opposite to the fifth main surface 27r. The fifth main surface 27r and the sixth main surface 27s extend in the first direction (x direction) and the second direction (y direction), respectively. The dielectric substrate 27 may be, for example, a high frequency printed circuit board, a liquid crystal polymer substrate, or a ceramic substrate such as a low temperature co-fired ceramics (LTCC) substrate. The dielectric base material 27 may be a fluororesin-based high-frequency printed circuit board having a low dielectric constant and a low dielectric loss, such as polytetrafluoroethylene (PTFE). The dielectric substrate 27 having a low dielectric constant and a low dielectric loss can reduce the transmission delay and transmission loss of high frequency signals such as microwaves or millimeter waves.
　接着層２２は、例えば、フッ素系熱可塑性樹脂のような熱可塑性樹脂または熱硬化性樹脂から構成されてもよい。接着層２２は、１ＧＨｚの電磁波の周波数において０．００５以下の誘電正接（ｔａｎδ）を有する材料で形成されてもよく、１ＧＨｚの電磁波の周波数において０．００３以下の誘電正接を有する材料で形成されてもよい。接着層２２は１ＧＨｚの電磁波の周波数において０．００５以下の誘電正接を有する材料から構成されているため、アレイアンテナ装置１における電磁波の損失が小さくなり、アレイアンテナ装置１の放射効率は向上され得る。 The adhesive layer 22 may be made of, for example, a thermoplastic resin such as a fluorine-based thermoplastic resin or a thermosetting resin. The adhesive layer 22 may be formed of a material having a dielectric loss tangent (tan δ) of 0.005 or less at an electromagnetic wave frequency of 1 GHz, or may be formed of a material having a dielectric loss tangent of 0.003 or less at an electromagnetic wave frequency of 1 GHz. You may. Since the adhesive layer 22 is made of a material having a dielectric loss tangent of 0.005 or less at an electromagnetic wave frequency of 1 GHz, the loss of electromagnetic waves in the array antenna device 1 can be reduced, and the radiation efficiency of the array antenna device 1 can be improved. ..
　無給電パッチアンテナ素子２９は、誘電体基材２７の第６主面２７ｓ上に配置されている。図１から図３に示されるように、誘電体基板２６は複数の無給電パッチアンテナ素子２９を含み、複数の無給電パッチアンテナ素子２９は、二次元アレイ状に、第６主面２７ｓ上に配置されてもよい。複数の無給電パッチアンテナ素子２９は、一次元アレイ状に、第６主面２７ｓ上に配置されてもよい。キャリア６の第１主面６ｓの平面視において、第１アンテナユニット２ａの複数の無給電パッチアンテナ素子２９と第２アンテナユニット２ｂの複数の無給電パッチアンテナ素子２９とは等間隔に配列されている。 The non-feeding patch antenna element 29 is arranged on the sixth main surface 27s of the dielectric base material 27. As shown in FIGS. 1 to 3, the dielectric substrate 26 includes a plurality of non-feeding patch antenna elements 29, and the plurality of non-feeding patch antenna elements 29 are arranged in a two-dimensional array on the sixth main surface 27s. It may be arranged. The plurality of non-feeding patch antenna elements 29 may be arranged on the sixth main surface 27s in a one-dimensional array. In the plan view of the first main surface 6s of the carrier 6, the plurality of non-feeding patch antenna elements 29 of the first antenna unit 2a and the plurality of non-feeding patch antenna elements 29 of the second antenna unit 2b are arranged at equal intervals. There is.
　無給電パッチアンテナ素子２９は、対応する給電パッチアンテナ素子１９に電磁気的に結合されている。無給電パッチアンテナ素子２９は、給電パッチアンテナ素子１９と導電ビア１８とを介して、能動回路１３に電磁気的に結合されている。能動回路１３は、給電パッチアンテナ素子１９及び無給電パッチアンテナ素子２９を介して、電磁波を送信または受信することができる。無給電パッチアンテナ素子２９は、特に限定されないが、銅または金のような導電材料で形成されている。 The non-feeding patch antenna element 29 is electromagnetically coupled to the corresponding feeding patch antenna element 19. The non-feeding patch antenna element 29 is electromagnetically coupled to the active circuit 13 via the feeding patch antenna element 19 and the conductive via 18. The active circuit 13 can transmit or receive electromagnetic waves via the feeding patch antenna element 19 and the non-feeding patch antenna element 29. The non-feeding patch antenna element 29 is not particularly limited, but is made of a conductive material such as copper or gold.
　外部基板３５は、筐体５の前面５ｓ上に載置されている。外部基板３５は、配線基板１０から離間されている。外部基板３５は、例えば、プリント基板である。プリント基板は、例えば、高周波用プリント基板、液晶ポリマー基板、または、低温同時焼成セラミックス（ＬＴＣＣ）基板のようなセラミックス基板であってもよい。プリント基板は、ポリテトラフルオロエチレン（ＰＴＦＥ）などの低誘電率および低誘電損失を有するフッ素樹脂系の高周波用プリント基板であってもよい。プリント基板は、１ＧＨｚの電磁波の周波数において０．００５以下の誘電正接（ｔａｎδ）を有する材料で形成されてもよく、１ＧＨｚの電磁波の周波数において０．００３以下の誘電正接を有する材料で形成されてもよい。低誘電率および低誘電損失を有する外部基板３５は、マイクロ波またはミリ波のような高周波信号の伝送遅延および伝送損失を減少させることができる。 The external board 35 is placed on the front surface 5s of the housing 5. The external board 35 is separated from the wiring board 10. The external substrate 35 is, for example, a printed circuit board. The printed circuit board may be, for example, a high-frequency printed circuit board, a liquid crystal polymer substrate, or a ceramic substrate such as a low-temperature co-fired ceramics (LTCC) substrate. The printed circuit board may be a fluororesin-based high-frequency printed circuit board having a low dielectric constant and a low dielectric loss such as polytetrafluoroethylene (PTFE). The printed circuit board may be made of a material having a dielectric loss tangent (tan δ) of 0.005 or less at an electromagnetic wave frequency of 1 GHz, or may be formed of a material having a dielectric loss tangent of 0.003 or less at an electromagnetic wave frequency of 1 GHz. May be good. The external substrate 35 having a low dielectric constant and a low dielectric loss can reduce the transmission delay and transmission loss of high frequency signals such as microwaves or millimeter waves.
　回路３６は、筐体５とは反対側の外部基板３５の表面に形成されている。回路３６は、電源電流、高周波信号及びデジタル制御信号などを伝送するように設計されている。回路３６は、銅、金またはアルミニウムなどの導電材料で形成されている。回路３６は、一般的なサブトラクティブ方式またはアディティブ方式によるパターニングによって形成され得る。電子部品３７は、筐体５とは反対側の外部基板３５の表面に搭載されている。電子部品３７は、例えば、抵抗、コンデンサ、インダクタ、コネクタまたは半導体パッケージ等である。電子部品３７は、はんだ、導電性接着剤または金属ワイヤなどを用いて、回路３６に電気的に接続されている。 The circuit 36 is formed on the surface of the external substrate 35 on the opposite side of the housing 5. The circuit 36 is designed to transmit a power supply current, a high frequency signal, a digital control signal, and the like. The circuit 36 is made of a conductive material such as copper, gold or aluminum. The circuit 36 can be formed by patterning by a general subtractive method or an additive method. The electronic component 37 is mounted on the surface of the external substrate 35 on the side opposite to the housing 5. The electronic component 37 is, for example, a resistor, a capacitor, an inductor, a connector, a semiconductor package, or the like. The electronic component 37 is electrically connected to the circuit 36 using solder, a conductive adhesive, a metal wire, or the like.
　電気接続部材４０は、接続端子３０と回路３６とを互いに電気的に接続している。電気接続部材４０は、金、銀、銅またはニッケルなどの導電材料で形成されている導体を含む。電気接続部材４０は、この導体を支持する絶縁基材をさらに含んでもよい。電気接続部材４０は、特に限定されないが、フレキシブルプリント基板、ワイヤハーネス、導電リボンまたは導電ワイヤであってもよい。 The electrical connection member 40 electrically connects the connection terminal 30 and the circuit 36 to each other. The electrical connection member 40 includes a conductor made of a conductive material such as gold, silver, copper or nickel. The electrical connection member 40 may further include an insulating base material that supports the conductor. The electrical connection member 40 is not particularly limited, but may be a flexible printed circuit board, a wire harness, a conductive ribbon, or a conductive wire.
　溝８は、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇに対応して配置されている。そのため、給電パッチアンテナ素子１９の第１頂面１９ｔから溝８の底面８ｂまで延在するスリット６０が、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間に形成されている。図３に示されるように、スリット６０の深さ６０ｄは、第３方向（ｚ方向）における、給電パッチアンテナ素子１９の第１頂面１９ｔから溝８の底面８ｂまでの距離として定義される。接地導体層２０の第２頂面２０ｔは、給電パッチアンテナ素子１９の第１頂面１９ｔと実質的に面一である。そのため、スリット６０の深さ６０ｄは、第３方向（ｚ方向）における、接地導体層２０の第２頂面２０ｔから溝８の底面８ｂまでの距離でもある。 The groove 8 is arranged corresponding to the gap 10 g between the first antenna unit 2a and the second antenna unit 2b. Therefore, a slit 60 extending from the first top surface 19t of the feeding patch antenna element 19 to the bottom surface 8b of the groove 8 is formed between the first antenna unit 2a and the second antenna unit 2b. As shown in FIG. 3, the depth 60d of the slit 60 is defined as the distance from the first top surface 19t of the feeding patch antenna element 19 to the bottom surface 8b of the groove 8 in the third direction (z direction). The second top surface 20t of the ground conductor layer 20 is substantially flush with the first top surface 19t of the feeding patch antenna element 19. Therefore, the depth 60d of the slit 60 is also the distance from the second top surface 20t of the ground conductor layer 20 to the bottom surface 8b of the groove 8 in the third direction (z direction).
　スリット６０の深さ６０ｄは、溝８の深さ８ｄと、配線基板１０の厚さ１０ｄと、接合部材７の厚さ７ｄとの合計によって与えられる。溝８の深さ８ｄは、第３方向（ｚ方向）における、キャリア６の第１主面６ｓから溝８の底面８ｂまでの距離として定義される。配線基板１０の厚さ１０ｄは、給電パッチアンテナ素子１９の第１頂面１９ｔから配線基板１０の第３主面１０ｈまでの距離として定義される。接合部材７の厚さ７ｄは、配線基板１０の第３主面１０ｈからキャリア６の第１主面６ｓまでの平均距離として定義される。 The depth 60d of the slit 60 is given by the sum of the depth 8d of the groove 8, the thickness 10d of the wiring board 10, and the thickness 7d of the joining member 7. The depth 8d of the groove 8 is defined as the distance from the first main surface 6s of the carrier 6 to the bottom surface 8b of the groove 8 in the third direction (z direction). The thickness 10d of the wiring board 10 is defined as the distance from the first top surface 19t of the feeding patch antenna element 19 to the third main surface 10h of the wiring board 10. The thickness 7d of the joining member 7 is defined as an average distance from the third main surface 10h of the wiring board 10 to the first main surface 6s of the carrier 6.
　スリット６０の最小幅は、スリット６０の深さ６０ｄよりも小さい。スリット６０の最小幅は、ギャップ１０ｇの幅１０ｗ及び溝８の幅８ｗのうち小さい方として定義される。第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇの幅１０ｗは、第１アンテナユニット２ａの配線基板１０の側面１０ｊと第２アンテナユニット２ｂの配線基板１０の側面１０ｋとの間の平均距離として定義される。溝８の幅８ｗは、溝８の側面８ｊと側面８ｋとの間の平均距離として定義される。 The minimum width of the slit 60 is smaller than the depth 60d of the slit 60. The minimum width of the slit 60 is defined as the smaller of the width 10w of the gap 10g and the width 8w of the groove 8. The width 10w of the gap 10g between the first antenna unit 2a and the second antenna unit 2b is between the side surface 10j of the wiring board 10 of the first antenna unit 2a and the side surface 10k of the wiring board 10 of the second antenna unit 2b. Is defined as the average distance of. The width 8w of the groove 8 is defined as the average distance between the side surface 8j and the side surface 8k of the groove 8.
　なお、スリット６０の深さ６０ｄなどは、ノギス等を用いた接触式の測長方法、または、光学顕微鏡とマイクロメータとを用いた測長方法によって測定され得る。接合部材７の厚さ７ｄは、接合部材７を介して配線基板１０をキャリア６に接着した後に、キャリア６の第２主面６ｕから配線基板１０の給電パッチアンテナ素子１９の第１頂面１９ｔまでの距離を測定し、この距離から、キャリア６の厚さと配線基板１０の厚さ１０ｄとを差し引くことによって求められる。キャリア６の第２主面６ｕから配線基板１０の給電パッチアンテナ素子１９の第１頂面１９ｔまでの距離、キャリア６の厚さ及び配線基板１０の厚さ１０ｄは、レーザ顕微鏡のような高精度の測長手段を用いて測定され得る。 The depth 60d of the slit 60 or the like can be measured by a contact-type length measurement method using a caliper or the like, or a length measurement method using an optical microscope and a micrometer. The thickness 7d of the joining member 7 is such that the wiring board 10 is bonded to the carrier 6 via the joining member 7 and then the first top surface 19t of the feeding patch antenna element 19 of the wiring board 10 is formed from the second main surface 6u of the carrier 6. It is obtained by measuring the distance to and subtracting the thickness of the carrier 6 and the thickness of the wiring board 10 10d from this distance. The distance from the second main surface 6u of the carrier 6 to the first top surface 19t of the feeding patch antenna element 19 of the wiring board 10, the thickness of the carrier 6 and the thickness 10d of the wiring board 10 are as high as a laser microscope. It can be measured using the length measuring means of.
　図６及び図８に示されるように、スリット６０の深さ６０ｄは、実質的に、給電パッチアンテナ素子１９が送信または受信する電磁波の波長λの半分の整数倍である。本明細書において、スリット６０の深さ６０ｄが、実質的に、給電パッチアンテナ素子１９が送信または受信する電磁波の波長λの半分の整数倍であることは、スリット６０の深さ６０ｄが、電磁波の波長λの半分の整数倍±電磁波の波長λの１６分の１の範囲内にあることを意味する。スリット６０の深さ６０ｄは、好ましくは、給電パッチアンテナ素子１９が送信または受信する電磁波の波長λの半分の整数倍に等しい。例えば、アレイアンテナ装置１が送信また受信する電磁波の周波数が５０ＧＨｚである場合、電磁波の波長λは６ｍｍであり、スリット６０の深さ６０ｄは、３ｍｍの整数倍に設定される。 As shown in FIGS. 6 and 8, the depth 60d of the slit 60 is substantially an integral multiple of half the wavelength λ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19. In the present specification, the fact that the depth 60d of the slit 60 is substantially an integral multiple of half the wavelength λ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19 means that the depth 60d of the slit 60 is an electromagnetic wave. It means that it is within the range of an integral multiple of half of the wavelength λ of λ ± 1/16 of the wavelength λ of electromagnetic waves. The depth 60d of the slit 60 is preferably equal to an integral multiple of half the wavelength λ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19. For example, when the frequency of the electromagnetic wave transmitted or received by the array antenna device 1 is 50 GHz, the wavelength λ of the electromagnetic wave is 6 mm, and the depth 60d of the slit 60 is set to an integral multiple of 3 mm.
　アレイアンテナ装置１のキャリア６に設けられている溝８の作用を説明する。キャリア６の第１主面６ｓの平面視において、溝８は、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇに対応して配置されている。配線基板１０をキャリア６に接合する際に用いられる接合部材７が、接合工程において配線基板１０に印加される圧力または配線基板１０の自重などのために、溝８に入り込む。溝８は、接合部材７が、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇを這い上がって、無給電パッチアンテナ素子２９の表面に付着することを防止する。 The operation of the groove 8 provided in the carrier 6 of the array antenna device 1 will be described. In the plan view of the first main surface 6s of the carrier 6, the groove 8 is arranged corresponding to the gap 10 g between the first antenna unit 2a and the second antenna unit 2b. The joining member 7 used for joining the wiring board 10 to the carrier 6 enters the groove 8 due to the pressure applied to the wiring board 10 in the joining process or the weight of the wiring board 10 itself. The groove 8 prevents the joining member 7 from crawling up the gap 10 g between the first antenna unit 2a and the second antenna unit 2b and adhering to the surface of the non-feeding patch antenna element 29.
　接合部材７が導電性接合部材である場合には、接合部材７によって第１アンテナユニット２ａの無給電パッチアンテナ素子２９と第２アンテナユニット２ｂの無給電パッチアンテナ素子２９とが電気的に短絡することが防止され得る。接合部材７が絶縁性接合部材である場合には、接合部材７が無給電パッチアンテナ素子２９に付着することによってアレイアンテナ装置１の誘電損失が増加することが防止され得る。こうして、アレイアンテナ装置１のアンテナ性能は、改善され得る。 When the joining member 7 is a conductive joining member, the joining member 7 electrically short-circuits the non-feeding patch antenna element 29 of the first antenna unit 2a and the non-feeding patch antenna element 29 of the second antenna unit 2b. Can be prevented. When the joining member 7 is an insulating joining member, it is possible to prevent the dielectric loss of the array antenna device 1 from increasing due to the joining member 7 adhering to the non-feeding patch antenna element 29. In this way, the antenna performance of the array antenna device 1 can be improved.
　図５から図９を参照して、スリット６０の深さ６０ｄを、実質的に、給電パッチアンテナ素子１９が送信または受信する電磁波の波長λの半分の整数倍とすることによって得られる作用を説明する。 With reference to FIGS. 5 to 9, the operation obtained by setting the depth 60d of the slit 60 to substantially an integral multiple of half the wavelength λ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19 will be described. To do.
　接地導体層２０の第２頂面２０ｔと面一であり、かつ、スリット６０（または溝８）に位置する仮想面１０ｐを考える。スリット６０の深さ６０ｄは、第３方向（ｚ方向）における、給電パッチアンテナ素子１９の第１頂面１９ｔ（または接地導体層２０の第２頂面２０ｔ）から溝８の底面８ｂまでの距離として定義されるため、スリット６０の深さ６０ｄは、仮想面１０ｐから溝８の底面８ｂまでの距離に等しい。 Consider a virtual surface 10p that is flush with the second top surface 20t of the ground conductor layer 20 and is located in the slit 60 (or groove 8). The depth 60d of the slit 60 is the distance from the first top surface 19t of the feeding patch antenna element 19 (or the second top surface 20t of the ground conductor layer 20) to the bottom surface 8b of the groove 8 in the third direction (z direction). Therefore, the depth 60d of the slit 60 is equal to the distance from the virtual surface 10p to the bottom surface 8b of the groove 8.
　アレイアンテナ装置１が送信または受信する電磁波の一部は、仮想面１０ｐから溝８の底面８ｂに向かって入射し、溝８の底面８ｂで反射する。入射した電磁波と反射した電磁波とが互いに干渉して、溝８の底面８ｂと仮想面１０ｐとの間のスリット６０内に、電磁波の定在波が発生する。溝８の底面８ｂは定在波の固定端であり、定在波の節が溝８の底面８ｂに位置する。キャリア６は、電気的に接地されており、定在波の節の電位は接地電位である。スリット６０の深さ６０ｄと、電磁波の波長λとに応じて、仮想面１０ｐにおける定在波の電位は、次のように変化する。 A part of the electromagnetic wave transmitted or received by the array antenna device 1 enters from the virtual surface 10p toward the bottom surface 8b of the groove 8 and is reflected by the bottom surface 8b of the groove 8. The incident electromagnetic wave and the reflected electromagnetic wave interfere with each other, and a standing wave of the electromagnetic wave is generated in the slit 60 between the bottom surface 8b of the groove 8 and the virtual surface 10p. The bottom surface 8b of the groove 8 is a fixed end of the standing wave, and the node of the standing wave is located on the bottom surface 8b of the groove 8. The carrier 6 is electrically grounded, and the potential of the node of the standing wave is the ground potential. The potential of the standing wave on the virtual surface 10p changes as follows according to the depth 60d of the slit 60 and the wavelength λ of the electromagnetic wave.
　図５及び図７に示される第１及び第２の比較例のように、スリット６０の深さ６０ｄが、電磁波の波長λの４分の１の奇数倍である場合、電磁波の定在波の腹が仮想面１０ｐに位置する。仮想面１０ｐには、接地電位である電磁波の定在波の節ではなく、電磁波の定在波の腹が位置している。仮想面１０ｐにおける電磁波の定在波の電位は、接地電位と異なる。第１アンテナユニット２ａの接地導体層２０と第２アンテナユニット２ｂの接地導体層２０との間にある仮想面１０ｐにおける電磁波の定在波の電位は、接地導体層２０の接地電位と異なる。そのため、第１アンテナユニット２ａの接地導体層２０の電位が接地電位であったとしても、第２アンテナユニット２ｂの接地導体層２０の電位は、接地電位とは異なる仮想面１０ｐにおける電磁波の定在波の電位のために、接地電位でなくなることがある。第１アンテナユニット２ａの接地導体層２０と第２アンテナユニット２ｂの接地導体層２０とは、互いに異なる電位を有することがある。 As in the first and second comparative examples shown in FIGS. 5 and 7, when the depth 60d of the slit 60 is an odd multiple of a quarter of the wavelength λ of the electromagnetic wave, the standing wave of the electromagnetic wave The belly is located on the virtual surface 10p. On the virtual surface 10p, the antinode of the standing wave of the electromagnetic wave is located instead of the node of the standing wave of the electromagnetic wave which is the ground potential. The potential of the standing wave of the electromagnetic wave on the virtual surface 10p is different from the ground potential. The potential of the standing wave of the electromagnetic wave on the virtual surface 10p between the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b is different from the ground potential of the ground conductor layer 20. Therefore, even if the potential of the ground conductor layer 20 of the first antenna unit 2a is the ground potential, the potential of the ground conductor layer 20 of the second antenna unit 2b is different from the ground potential of the electromagnetic wave on the virtual surface 10p. Due to the electric potential of the wave, it may not be the ground potential. The ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b may have different potentials from each other.
　第１アンテナユニット２ａの接地導体層２０と第２アンテナユニット２ｂの接地導体層２０とが互いに異なる電位を有すると、アレイアンテナ装置１における電磁波の利得が低下する。また、第１アンテナユニット２ａの給電パッチアンテナ素子１９から放射される電磁波の位相と、第２アンテナユニット２ｂの給電パッチアンテナ素子１９から放射される電磁波の位相との間の差が設計値からずれる。そのため、アレイアンテナ装置１のサイドローブレベルが大きくなる。アレイアンテナ装置１のアンテナ性能が低下する。 When the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b have different potentials, the gain of the electromagnetic wave in the array antenna device 1 decreases. Further, the difference between the phase of the electromagnetic wave radiated from the feeding patch antenna element 19 of the first antenna unit 2a and the phase of the electromagnetic wave radiated from the feeding patch antenna element 19 of the second antenna unit 2b deviates from the design value. .. Therefore, the side lobe level of the array antenna device 1 becomes large. The antenna performance of the array antenna device 1 deteriorates.
　本明細書において、サイドローブは、本来放射されるべき方向以外の方向に放射される電磁波を意味する。サイドローブレベルは、本来放射されるべき方向に放射される電磁波の強度に対する、本来放射されるべき方向以外の方向に放射される電磁波の強度の比を意味する。サイドローブレベルは、アレイアンテナ装置１から放射される電磁波の指向性の指標である。サイドローブレベルが小さいほど、アレイアンテナ装置１はより高い電磁波の指向性を有し、より高いアンテナ性能を有する。 In the present specification, the side lobe means an electromagnetic wave radiated in a direction other than the direction in which it should be radiated. The sidelobe level means the ratio of the intensity of the electromagnetic wave radiated in the direction other than the originally radiated direction to the intensity of the electromagnetic wave radiated in the direction originally radiated. The side lobe level is an index of the directivity of the electromagnetic wave radiated from the array antenna device 1. The smaller the sidelobe level, the higher the directivity of the electromagnetic wave and the higher the antenna performance of the array antenna device 1.
　これに対し、図６及び図８に示される本実施の形態の第１及び第２の実施例のように、スリット６０の深さ６０ｄが、放射される電磁波の波長λの２分の１の整数倍である場合、電磁波の定在波の節が仮想面１０ｐに位置する。仮想面１０ｐには、溝８の底面８ｂと同様に、接地電位である電磁波の定在波の節が位置している。そのため、仮想面１０ｐにおける電磁波の定在波の電位は、溝８の底面８ｂにおける電磁波の定在波の電位である接地電位に等しい。第１アンテナユニット２ａの接地導体層２０と第２アンテナユニット２ｂの接地導体層２０との間にある仮想面１０ｐにおける定在波の電位は、接地導体層２０の接地電位に等しい。第１アンテナユニット２ａの接地導体層２０は、同じ接地電位で、第２アンテナユニット２ｂの接地導体層２０に電磁気的に結合する。第１アンテナユニット２ａの接地導体層２０と第２アンテナユニット２ｂの接地導体層２０とは、いずれも接地電位を有する。 On the other hand, as in the first and second embodiments of the present embodiment shown in FIGS. 6 and 8, the depth 60d of the slit 60 is half the wavelength λ of the emitted electromagnetic wave. When it is an integral multiple, the node of the standing wave of the electromagnetic wave is located on the virtual surface 10p. Similar to the bottom surface 8b of the groove 8, a standing wave node of an electromagnetic wave, which is a ground potential, is located on the virtual surface 10p. Therefore, the potential of the standing wave of the electromagnetic wave on the virtual surface 10p is equal to the ground potential which is the potential of the standing wave of the electromagnetic wave on the bottom surface 8b of the groove 8. The potential of the standing wave on the virtual surface 10p between the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b is equal to the ground potential of the ground conductor layer 20. The ground conductor layer 20 of the first antenna unit 2a is electromagnetically coupled to the ground conductor layer 20 of the second antenna unit 2b at the same ground potential. Both the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b have a ground potential.
　第１アンテナユニット２ａの接地導体層２０と第２アンテナユニット２ｂの接地導体層２０とは互いに等しい接地電位を有するため、アレイアンテナ装置１における電磁波の利得が最大化される（図９を参照）。また、第１アンテナユニット２ａの給電パッチアンテナ素子１９から放射される電磁波の位相と、第２アンテナユニット２ｂの給電パッチアンテナ素子１９から放射される電磁波の位相との間の差が設計値のとおりとなるため、アレイアンテナ装置１のサイドローブレベルが小さくなる。アレイアンテナ装置１のアンテナ性能が向上する。 Since the ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b have equal ground potentials, the gain of the electromagnetic wave in the array antenna device 1 is maximized (see FIG. 9). .. Further, the difference between the phase of the electromagnetic wave radiated from the feeding patch antenna element 19 of the first antenna unit 2a and the phase of the electromagnetic wave radiated from the feeding patch antenna element 19 of the second antenna unit 2b is as the design value. Therefore, the side lobe level of the array antenna device 1 becomes small. The antenna performance of the array antenna device 1 is improved.
　図１、図２及び図１０から図１９を参照して、本実施の形態のアレイアンテナ装置１の製造方法の一例を説明する。 An example of the manufacturing method of the array antenna device 1 of the present embodiment will be described with reference to FIGS. 1, 2 and 10 to 19.
　図１０及び図１１に示されるように、キャリア６に溝８を形成する。溝８は、例えば、研削もしくは研磨のような機械的加工、または、エッチングのような化学的加工によって形成される。 As shown in FIGS. 10 and 11, a groove 8 is formed in the carrier 6. The groove 8 is formed by, for example, mechanical processing such as grinding or polishing, or chemical processing such as etching.
　図１０及び図１１に示されるように、キャリア６の第１主面６ｓ上に、接合部材７を設ける。接合部材７は、第１接合部７ａと、第２接合部７ｂとを含む。溝８は、第１接合部７ａと、第２接合部７ｂとの間に位置している。接合部材７に使用する材料が液状である場合には、接合部材７は、メタルマスクを用いた印刷法、ディスペンサを用いた吐出法、または、ピン転写法によって、キャリア６の第１主面６ｓ上に設けられる。接合部材７がシートのような固体である場合には、接合部材７はキャリア６の第１主面６ｓ上に載置される。 As shown in FIGS. 10 and 11, the joining member 7 is provided on the first main surface 6s of the carrier 6. The joining member 7 includes a first joining portion 7a and a second joining portion 7b. The groove 8 is located between the first joint portion 7a and the second joint portion 7b. When the material used for the joining member 7 is liquid, the joining member 7 is subjected to a printing method using a metal mask, a ejection method using a dispenser, or a pin transfer method to obtain the first main surface 6s of the carrier 6. Provided on top. When the joining member 7 is a solid such as a sheet, the joining member 7 is placed on the first main surface 6s of the carrier 6.
　図１２及び図１３に示されるように、接合部材７を介して、配線基板１０をキャリア６に固定する。具体的には、キャリア６に対して配線基板１０を位置合わせしながら、配線基板１０を接合部材７上に載置する。配線基板１０をキャリア６に押しつけながら、接合部材７を硬化させる。一例では、接合部材７を硬化させる際に、第１接合部７ａと第２接合部７ｂとを個別に硬化してもよい。そのため、配線基板１０間の相対的な位置精度を向上させることができる。高い組立て精度を要求される高周波数用のアレイアンテナ装置１の製造が可能になる。別の例では、接合部材７を硬化させる際に、第１接合部７ａと第２接合部７ｂとを一括して硬化してもよい。そのため、アレイアンテナ装置１の製造時間を短縮することができて、アレイアンテナ装置１の製造コストが低減される。 As shown in FIGS. 12 and 13, the wiring board 10 is fixed to the carrier 6 via the joining member 7. Specifically, the wiring board 10 is placed on the joining member 7 while aligning the wiring board 10 with respect to the carrier 6. The joining member 7 is cured while pressing the wiring board 10 against the carrier 6. In one example, when the joint member 7 is cured, the first joint portion 7a and the second joint portion 7b may be individually cured. Therefore, the relative position accuracy between the wiring boards 10 can be improved. It becomes possible to manufacture the array antenna device 1 for high frequencies, which requires high assembly accuracy. In another example, when the joint member 7 is cured, the first joint portion 7a and the second joint portion 7b may be cured together. Therefore, the manufacturing time of the array antenna device 1 can be shortened, and the manufacturing cost of the array antenna device 1 can be reduced.
　図１４及び図１５に示されるように、配線基板１０の第４主面１０ｓ、給電パッチアンテナ素子１９の第１頂面１９ｔ及び接地導体層２０の第２頂面２０ｔ上に、接着層２２を設ける。接着層２２に使用する材料が液状である場合には、接着層２２は、メタルマスクを用いた印刷法、ディスペンサを用いた吐出法、または、ピン転写法によって、配線基板１０の第４主面１０ｓ、給電パッチアンテナ素子１９の第１頂面１９ｔ及び接地導体層２０の第２頂面２０ｔ上に設けられる。接着層２２がシートのような固体である場合には、接着層２２は、配線基板１０の第４主面１０ｓ、給電パッチアンテナ素子１９の第１頂面１９ｔ及び接地導体層２０の第２頂面２０ｔ上に載置される。 As shown in FIGS. 14 and 15, the adhesive layer 22 is provided on the fourth main surface 10s of the wiring board 10, the first top surface 19t of the feeding patch antenna element 19, and the second top surface 20t of the ground conductor layer 20. Provide. When the material used for the adhesive layer 22 is liquid, the adhesive layer 22 is the fourth main surface of the wiring board 10 by a printing method using a metal mask, a discharge method using a dispenser, or a pin transfer method. 10s, it is provided on the first top surface 19t of the feeding patch antenna element 19 and the second top surface 20t of the ground conductor layer 20. When the adhesive layer 22 is a solid such as a sheet, the adhesive layer 22 is the fourth main surface 10s of the wiring board 10, the first top surface 19t of the feeding patch antenna element 19, and the second top of the ground conductor layer 20. It is placed on the surface 20t.
　図１６及び図１７に示されるように、接着層２２を介して、誘電体基板２６を配線基板１０に接着する。誘電体基板２６の無給電パッチアンテナ素子２９は、配線基板１０の給電パッチアンテナ素子１９に対応して配置されている。具体的には、キャリア６の第１主面６ｓの平面視において、無給電パッチアンテナ素子２９の中心が、給電パッチアンテナ素子１９の中心に一致するように、誘電体基板２６は配線基板１０に対して配置される。配線基板１０の第４主面１０ｓに形成されたアライメントマーク（図示せず）と、誘電体基板２６の第５主面２７ｒに形成されたアライメントマーク（図示せず）とを用いて、誘電体基板２６は、配線基板１０に対してアライメントされてもよい。 As shown in FIGS. 16 and 17, the dielectric substrate 26 is adhered to the wiring substrate 10 via the adhesive layer 22. The non-feeding patch antenna element 29 of the dielectric substrate 26 is arranged corresponding to the feeding patch antenna element 19 of the wiring board 10. Specifically, the dielectric substrate 26 is attached to the wiring board 10 so that the center of the non-feeding patch antenna element 29 coincides with the center of the feeding patch antenna element 19 in the plan view of the first main surface 6s of the carrier 6. It is placed against. A dielectric material is used by using an alignment mark (not shown) formed on the fourth main surface 10s of the wiring board 10 and an alignment mark (not shown) formed on the fifth main surface 27r of the dielectric substrate 26. The board 26 may be aligned with respect to the wiring board 10.
　図１８及び図１９に示されるように、キャリア６を、筐体５に、ねじのような固定部材（図示せず）を用いて固定する。外部基板３５を、筐体５に、ねじのような固定部材（図示せず）を用いて固定する。外部基板３５には、電子部品３７が搭載されている。キャリア６の第１主面６ｓの平面視において、外部基板３５の回路３６と配線基板１０の接続端子３０とが互いに対向するように、外部基板３５は配線基板１０に対してアライメントされる。 As shown in FIGS. 18 and 19, the carrier 6 is fixed to the housing 5 using a fixing member (not shown) such as a screw. The external substrate 35 is fixed to the housing 5 using a fixing member (not shown) such as a screw. An electronic component 37 is mounted on the external substrate 35. The external board 35 is aligned with the wiring board 10 so that the circuit 36 of the external board 35 and the connection terminal 30 of the wiring board 10 face each other in a plan view of the first main surface 6s of the carrier 6.
　それから、外部基板３５の回路３６と、配線基板１０の接続端子３０とを、電気接続部材４０を用いて接続する。具体的には、電気接続部材４０が金属ワイヤである場合には、電気接続部材４０は、ワイヤボンダ等を用いて、回路３６と接続端子３０とにボンディングされる。電気接続部材４０がフレキシブルプリント基板である場合には、電気接続部材４０は、フリップチップボンダ等を用いて、接続端子３０と回路３６とに接合される。電気接続部材４０は、はんだ、異方導電性接着材、または、導電性接着材を用いて、接続端子３０と回路３６とに接合される。こうして、図１から図３に示されるアレイアンテナ装置１を得ることができる。 Then, the circuit 36 of the external board 35 and the connection terminal 30 of the wiring board 10 are connected by using the electrical connection member 40. Specifically, when the electrical connection member 40 is a metal wire, the electrical connection member 40 is bonded to the circuit 36 and the connection terminal 30 by using a wire bonder or the like. When the electrical connection member 40 is a flexible printed circuit board, the electrical connection member 40 is joined to the connection terminal 30 and the circuit 36 by using a flip chip bonder or the like. The electrical connection member 40 is joined to the connection terminal 30 and the circuit 36 using solder, an anisotropic conductive adhesive, or a conductive adhesive. In this way, the array antenna device 1 shown in FIGS. 1 to 3 can be obtained.
　本実施の形態のアレイアンテナ装置１は、２つのアンテナユニット（第１アンテナユニット２ａ及び第２アンテナユニット２ｂ）を備えているが、アレイアンテナ装置１が備えるアンテナユニットの数は、３以上であってもよい。４つ以上のアンテナユニットが、第１方向（ｘ方向）と第２方向（ｙ方向）とにマトリクス状に配置されてもよい。 The array antenna device 1 of the present embodiment includes two antenna units (first antenna unit 2a and second antenna unit 2b), but the number of antenna units included in the array antenna device 1 is 3 or more. You may. Four or more antenna units may be arranged in a matrix in the first direction (x direction) and the second direction (y direction).
　本実施の形態のアレイアンテナ装置１の効果を説明する。
　本実施の形態のアレイアンテナ装置１は、キャリア６と、接合部材７と、第１アンテナユニット２ａと、第２アンテナユニット２ｂを備えている。キャリア６は、第１主面６ｓと、第１主面６ｓとは反対側の第２主面６ｕとを有する。接合部材７は、第１接合部７ａと、第２接合部７ｂとを含む。第１アンテナユニット２ａは、キャリア６の第１主面６ｓに、第１接合部７ａを用いて接合されている。第２アンテナユニット２ｂは、キャリア６の第１主面６ｓに、第２接合部７ｂを用いて接合されている。第２アンテナユニット２ｂは、第１アンテナユニット２ａからギャップ１０ｇを空けて配置されている。第１アンテナユニット２ａと第２アンテナユニット２ｂとは、各々、キャリア６に近位する配線基板１０と、キャリア６から遠位する誘電体基板２６とを含む。配線基板１０は、キャリア６に対向する第３主面１０ｈと、第３主面１０ｈとは反対側であり、かつ、誘電体基板２６に対向する第４主面１０ｓとを有する。配線基板１０は、配線基板１０の第４主面１０ｓ上に設けられている給電パッチアンテナ素子１９を含む。誘電体基板２６は、給電パッチアンテナ素子１９に対応して配置されている無給電パッチアンテナ素子２９を含む。キャリア６には、第１主面６ｓから第２主面６ｕに向けて延在する溝８が設けられている。キャリア６の第１主面６ｓの平面視において、溝８は、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇに対応して配置されている。給電パッチアンテナ素子１９の第１頂面１９ｔから溝８の底面８ｂまで延在するスリット６０が、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間に形成されている。 The effect of the array antenna device 1 of the present embodiment will be described.
The array antenna device 1 of the present embodiment includes a carrier 6, a joining member 7, a first antenna unit 2a, and a second antenna unit 2b. The carrier 6 has a first main surface 6s and a second main surface 6u on the opposite side of the first main surface 6s. The joining member 7 includes a first joining portion 7a and a second joining portion 7b. The first antenna unit 2a is joined to the first main surface 6s of the carrier 6 by using the first joining portion 7a. The second antenna unit 2b is joined to the first main surface 6s of the carrier 6 by using the second joining portion 7b. The second antenna unit 2b is arranged with a gap of 10 g from the first antenna unit 2a. The first antenna unit 2a and the second antenna unit 2b each include a wiring board 10 proximal to the carrier 6 and a dielectric substrate 26 distal to the carrier 6. The wiring board 10 has a third main surface 10h facing the carrier 6 and a fourth main surface 10s on the opposite side of the third main surface 10h and facing the dielectric substrate 26. The wiring board 10 includes a feeding patch antenna element 19 provided on the fourth main surface 10s of the wiring board 10. The dielectric substrate 26 includes a non-feeding patch antenna element 29 arranged corresponding to the feeding patch antenna element 19. The carrier 6 is provided with a groove 8 extending from the first main surface 6s to the second main surface 6u. In the plan view of the first main surface 6s of the carrier 6, the groove 8 is arranged corresponding to the gap 10 g between the first antenna unit 2a and the second antenna unit 2b. A slit 60 extending from the first top surface 19t of the feeding patch antenna element 19 to the bottom surface 8b of the groove 8 is formed between the first antenna unit 2a and the second antenna unit 2b.
　接合部材７を用いて配線基板１０をキャリア６に固定する際に、接合部材７は、溝８に入り込む。溝８は、接合部材７が、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇを這い上がって、無給電パッチアンテナ素子２９の表面に付着することを防止する。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 When the wiring board 10 is fixed to the carrier 6 using the joining member 7, the joining member 7 enters the groove 8. The groove 8 prevents the joining member 7 from crawling up the gap 10 g between the first antenna unit 2a and the second antenna unit 2b and adhering to the surface of the non-feeding patch antenna element 29. The array antenna device 1 has improved antenna performance.
　本実施の形態のアレイアンテナ装置１では、配線基板１０は、配線基板１０の第４主面１０ｓ上に設けられており、かつ、給電パッチアンテナ素子１９から離間されている接地導体層２０を含む。接地導体層２０の第２頂面２０ｔは、給電パッチアンテナ素子１９の第１頂面１９ｔと実質的に面一である。キャリア６は、電気的に接地されている。スリット６０の深さ６０ｄは、実質的に、給電パッチアンテナ素子１９が送信または受信する電磁波の波長λの半分の整数倍である。 In the array antenna device 1 of the present embodiment, the wiring board 10 includes a ground conductor layer 20 provided on the fourth main surface 10s of the wiring board 10 and separated from the feeding patch antenna element 19. .. The second top surface 20t of the ground conductor layer 20 is substantially flush with the first top surface 19t of the feeding patch antenna element 19. The carrier 6 is electrically grounded. The depth 60d of the slit 60 is substantially an integral multiple of half the wavelength λ of the electromagnetic wave transmitted or received by the feeding patch antenna element 19.
　そのため、第１アンテナユニット２ａの接地導体層２０は、同じ接地電位で、第２アンテナユニット２ｂの接地導体層２０に電磁気的に結合する。第１アンテナユニット２ａの接地導体層２０と第２アンテナユニット２ｂの接地導体層２０とは互いに等しい接地電位を有する。アレイアンテナ装置１における電磁波の利得が最大化される。アレイアンテナ装置１のサイドローブレベルが小さくなる。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 Therefore, the ground conductor layer 20 of the first antenna unit 2a is electromagnetically coupled to the ground conductor layer 20 of the second antenna unit 2b at the same ground potential. The ground conductor layer 20 of the first antenna unit 2a and the ground conductor layer 20 of the second antenna unit 2b have equal ground potentials. The gain of the electromagnetic wave in the array antenna device 1 is maximized. The side lobe level of the array antenna device 1 becomes smaller. The array antenna device 1 has improved antenna performance.
　本実施の形態のアレイアンテナ装置１では、スリット６０の最小幅は、スリット６０の深さ６０ｄよりも小さい。そのため、スリット６０の深さ６０ｄ方向に、アレイアンテナ装置１から送信または受信される電磁波の定在波が安定的に形成される。アレイアンテナ装置１における電磁波の利得が最大化される。アレイアンテナ装置１のサイドローブレベルが小さくなる。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 In the array antenna device 1 of the present embodiment, the minimum width of the slit 60 is smaller than the depth 60d of the slit 60. Therefore, a standing wave of electromagnetic waves transmitted or received from the array antenna device 1 is stably formed in the depth 60d direction of the slit 60. The gain of the electromagnetic wave in the array antenna device 1 is maximized. The side lobe level of the array antenna device 1 becomes smaller. The array antenna device 1 has improved antenna performance.
　本実施の形態のアレイアンテナ装置１では、ギャップ１０ｇの幅１０ｗは、溝８の幅８ｗより狭い。第１アンテナユニット２ａ（特にひさし部１０ｍ）と第２アンテナユニット２ｂ（ひさし部１０ｎ）とは、接合部材７が配線基板１０の第４主面１０ｓに這い上がることを効果的に防止する。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 In the array antenna device 1 of the present embodiment, the width 10w of the gap 10g is narrower than the width 8w of the groove 8. The first antenna unit 2a (particularly the eaves portion 10m) and the second antenna unit 2b (the eaves portion 10n) effectively prevent the joining member 7 from climbing up to the fourth main surface 10s of the wiring board 10. The array antenna device 1 has improved antenna performance.
　本実施の形態のアレイアンテナ装置１では、接合部材７は、溝８の底面８ｂから離間されている。そのため、アレイアンテナ装置１が送信または受信する電磁波にとってのスリット６０の深さ６０ｄの実効的な長さが接合部材７によって変化することがない。アレイアンテナ装置１における電磁波の利得が最大化される。アレイアンテナ装置１のサイドローブレベルが小さくなる。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 In the array antenna device 1 of the present embodiment, the joining member 7 is separated from the bottom surface 8b of the groove 8. Therefore, the effective length of the depth 60d of the slit 60 for the electromagnetic wave transmitted or received by the array antenna device 1 does not change depending on the joining member 7. The gain of the electromagnetic wave in the array antenna device 1 is maximized. The side lobe level of the array antenna device 1 becomes smaller. The array antenna device 1 has improved antenna performance.
　本実施の形態のアレイアンテナ装置１では、第１接合部７ａは、溝８において、第２接合部７ｂから離間されている。第１接合部７ａが第２接合部７ｂに接触して、接合部材７と溝８とで囲まれた閉塞空間が形成されると、アレイアンテナ装置１の製造工程やアレイアンテナ装置１の動作時に、閉塞空間内の気体が膨張して、接合部材７が破裂する可能性がある。本実施の形態では、第１接合部７ａは第２接合部７ｂから離間されているため、接合部材７の破裂が防止される。また、第１接合部７ａ及び第２接合部７ｂが導電性接合部材である場合には、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間で電気的に短絡することが防止される。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 In the array antenna device 1 of the present embodiment, the first joint portion 7a is separated from the second joint portion 7b in the groove 8. When the first joint portion 7a comes into contact with the second joint portion 7b to form a closed space surrounded by the joint member 7 and the groove 8, during the manufacturing process of the array antenna device 1 and the operation of the array antenna device 1. , The gas in the closed space may expand and the joining member 7 may burst. In the present embodiment, since the first joint portion 7a is separated from the second joint portion 7b, the joint member 7 is prevented from bursting. Further, when the first joint portion 7a and the second joint portion 7b are conductive joint members, it is possible to prevent an electrical short circuit between the first antenna unit 2a and the second antenna unit 2b. The array antenna device 1 has improved antenna performance.
　本実施の形態のアレイアンテナ装置１では、接合部材７は、導電性接合部材である。溝８は、導電性接合部材である接合部材７が、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇを這い上がって、無給電パッチアンテナ素子２９の表面に付着することを防止する。導電性接合部材である接合部材７によって、第１アンテナユニット２ａの無給電パッチアンテナ素子２９と第２アンテナユニット２ｂの無給電パッチアンテナ素子２９とが電気的に短絡することが防止され得る。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 In the array antenna device 1 of the present embodiment, the joining member 7 is a conductive joining member. The groove 8 prevents the joining member 7, which is a conductive joining member, from crawling up the gap 10g between the first antenna unit 2a and the second antenna unit 2b and adhering to the surface of the non-feeding patch antenna element 29. To prevent. The bonding member 7, which is a conductive bonding member, can prevent the non-feeding patch antenna element 29 of the first antenna unit 2a and the non-feeding patch antenna element 29 of the second antenna unit 2b from being electrically short-circuited. The array antenna device 1 has improved antenna performance.
　本実施の形態のアレイアンテナ装置１では、接合部材７は、絶縁性接合部材である。溝８は、絶縁性接合部材である接合部材７が、第１アンテナユニット２ａと第２アンテナユニット２ｂとの間のギャップ１０ｇを這い上がって、無給電パッチアンテナ素子２９の表面に付着することを防止する。絶縁性接合部材である接合部材７が無給電パッチアンテナ素子２９の表面に付着して、アレイアンテナ装置１の誘電損失が増加することが防止され得る。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 In the array antenna device 1 of the present embodiment, the joining member 7 is an insulating joining member. The groove 8 prevents the joining member 7, which is an insulating joining member, from crawling up the gap 10g between the first antenna unit 2a and the second antenna unit 2b and adhering to the surface of the non-feeding patch antenna element 29. To prevent. It is possible to prevent the bonding member 7, which is an insulating bonding member, from adhering to the surface of the non-feeding patch antenna element 29 and increasing the dielectric loss of the array antenna device 1. The array antenna device 1 has improved antenna performance.
　本実施の形態のアレイアンテナ装置１では、第１アンテナユニット２ａの無給電パッチアンテナ素子２９は、複数の無給電パッチアンテナ素子２９である。第２アンテナユニット２ｂの無給電パッチアンテナ素子２９は、複数の無給電パッチアンテナ素子２９である。キャリア６の第１主面６ｓの平面視において、第１アンテナユニット２ａの複数の無給電パッチアンテナ素子２９と第２アンテナユニット２ｂの複数の無給電パッチアンテナ素子２９とは等間隔に配列されている。アレイアンテナ装置１は、改善されたアンテナ性能を有する。 In the array antenna device 1 of the present embodiment, the non-feeding patch antenna element 29 of the first antenna unit 2a is a plurality of non-feeding patch antenna elements 29. The non-feeding patch antenna element 29 of the second antenna unit 2b is a plurality of non-feeding patch antenna elements 29. In the plan view of the first main surface 6s of the carrier 6, the plurality of non-feeding patch antenna elements 29 of the first antenna unit 2a and the plurality of non-feeding patch antenna elements 29 of the second antenna unit 2b are arranged at equal intervals. There is. The array antenna device 1 has improved antenna performance.
　実施の形態２．
　図２１から図２３を参照して、実施の形態２に係るアレイアンテナ装置１ｂを説明する。本実施の形態のアレイアンテナ装置１ｂは、実施の形態１のアレイアンテナ装置１と同様の構成を備えているが、以下の点で主に異なっている。 Embodiment 2.
The array antenna device 1b according to the second embodiment will be described with reference to FIGS. 21 to 23. The array antenna device 1b of the present embodiment has the same configuration as the array antenna device 1 of the first embodiment, but is mainly different in the following points.
　アレイアンテナ装置１ｂでは、溝８は、第１主面６ｓから第２主面６ｕまで延在している。溝８は、キャリア６の厚さ方向（第３方向（ｚ方向））において、キャリア６を貫通している。キャリア６は、複数のキャリア部分（第１キャリア部分６ａ及び第２キャリア部分６ｂ）で構成されている。溝８の底面８ｂは、第２主面６ｕに面する筐体５の前面５ｓである。筐体５は、電気的に接地されている。 In the array antenna device 1b, the groove 8 extends from the first main surface 6s to the second main surface 6u. The groove 8 penetrates the carrier 6 in the thickness direction of the carrier 6 (third direction (z direction)). The carrier 6 is composed of a plurality of carrier portions (first carrier portion 6a and second carrier portion 6b). The bottom surface 8b of the groove 8 is the front surface 5s of the housing 5 facing the second main surface 6u. The housing 5 is electrically grounded.
　本実施の形態のアレイアンテナ装置１ｂは、実施の形態１のアレイアンテナ装置１の効果に加えて、以下の効果を奏する。 The array antenna device 1b of the present embodiment exerts the following effects in addition to the effects of the array antenna device 1 of the first embodiment.
　本実施の形態のアレイアンテナ装置１ｂは、キャリア６の第２主面６ｕを支持する筐体５をさらに備えている。溝８は、第１主面６ｓから第２主面６ｕまで延在している。溝８の底面８ｂは、第２主面６ｕに面する筐体５の前面５ｓである。筐体５は、電気的に接地されている。 The array antenna device 1b of the present embodiment further includes a housing 5 that supports the second main surface 6u of the carrier 6. The groove 8 extends from the first main surface 6s to the second main surface 6u. The bottom surface 8b of the groove 8 is the front surface 5s of the housing 5 facing the second main surface 6u. The housing 5 is electrically grounded.
　そのため、キャリア６の厚さが減少する。アレイアンテナ装置１ｂは小型化され得る。また、キャリア６の厚さが減少するため、配線基板１０から筐体５までの熱抵抗が減少する。アレイアンテナ装置１ｂは、配線基板１０で発生した熱を、筐体５に効率的に放散させることができる。 Therefore, the thickness of the carrier 6 is reduced. The array antenna device 1b can be miniaturized. Further, since the thickness of the carrier 6 is reduced, the thermal resistance from the wiring board 10 to the housing 5 is reduced. The array antenna device 1b can efficiently dissipate the heat generated in the wiring board 10 to the housing 5.
　実施の形態３．
　図２４及び図２５を参照して、実施の形態３に係るアレイアンテナ装置１ｃを説明する。本実施の形態のアレイアンテナ装置１ｃは、実施の形態１のアレイアンテナ装置１と同様の構成を備えているが、以下の点で主に異なっている。 Embodiment 3.
The array antenna device 1c according to the third embodiment will be described with reference to FIGS. 24 and 25. The array antenna device 1c of the present embodiment has the same configuration as the array antenna device 1 of the first embodiment, but is mainly different in the following points.
　アレイアンテナ装置１ｃでは、キャリア６の第１主面６ｓに凹部９が設けられている。第１アンテナユニット２ａと第２アンテナユニット２ｂとは、凹部９に配置されている。キャリア６の第１主面６ｓの平面視において、凹部９の面積は、第１アンテナユニット２ａ及び第２アンテナユニット２ｂの配線基板１０の総面積より大きい。凹部９の深さ９ｄは、配線基板１０の厚さ１０ｄ（図３を参照）より小さいことが好ましい。キャリア６の第１主面６ｓから凹部９の底面に向かうにつれて凹部９が先細となるように、凹部９の側面は、キャリア６の第１主面６ｓに対して傾いている。凹部９の側面は、キャリア６の第１主面６ｓに垂直であってもよい。 In the array antenna device 1c, the recess 9 is provided on the first main surface 6s of the carrier 6. The first antenna unit 2a and the second antenna unit 2b are arranged in the recess 9. In the plan view of the first main surface 6s of the carrier 6, the area of the recess 9 is larger than the total area of the wiring boards 10 of the first antenna unit 2a and the second antenna unit 2b. The depth 9d of the recess 9 is preferably smaller than the thickness 10d of the wiring board 10 (see FIG. 3). The side surface of the recess 9 is inclined with respect to the first main surface 6s of the carrier 6 so that the recess 9 tapers from the first main surface 6s of the carrier 6 toward the bottom surface of the recess 9. The side surface of the recess 9 may be perpendicular to the first main surface 6s of the carrier 6.
　溝８の側面８ｊから凹部９の底面のうち溝８とは反対側に位置する辺までの距離６６ｄは、第１アンテナユニット２ａの配線基板１０の一辺の長さとひさし部１０ｍの長さとの間の差に等しくてもよい。そのため、第１アンテナユニット２ａの配線基板１０は、キャリア６に対して、第１方向（ｘ方向）に正確にアライメントされ得る。溝８の側面８ｋから凹部９の底面のうち溝８とは反対側に位置する辺までの距離６７ｄは、第２アンテナユニット２ｂの配線基板１０の一辺の長さとひさし部１０ｎの長さとの間の差に等しくてもよい。そのため、第２アンテナユニット２ｂの配線基板１０は、キャリア６に対して、第１方向（ｘ方向）に正確にアライメントされ得る。 The distance 66d from the side surface 8j of the groove 8 to the side of the bottom surface of the recess 9 opposite to the groove 8 is between the length of one side of the wiring board 10 of the first antenna unit 2a and the length of the eaves portion 10m. May be equal to the difference between. Therefore, the wiring board 10 of the first antenna unit 2a can be accurately aligned in the first direction (x direction) with respect to the carrier 6. The distance 67d from the side surface 8k of the groove 8 to the side of the bottom surface of the recess 9 opposite to the groove 8 is between the length of one side of the wiring board 10 of the second antenna unit 2b and the length of the eaves portion 10n. May be equal to the difference between. Therefore, the wiring board 10 of the second antenna unit 2b can be accurately aligned in the first direction (x direction) with respect to the carrier 6.
　図２６を参照して、本実施の形態のアレイアンテナ装置１ｃの製造方法の一例を説明する。本実施の形態のアレイアンテナ装置１ｃの製造方法は、実施の形態１のアレイアンテナ装置１の製造方法と同様の工程を備えるが、以下の点で主に異なる。 An example of the manufacturing method of the array antenna device 1c of the present embodiment will be described with reference to FIG. 26. The manufacturing method of the array antenna device 1c of the present embodiment includes the same steps as the manufacturing method of the array antenna device 1 of the first embodiment, but is mainly different in the following points.
　図２６に示されるように、キャリア６に、溝８に加えて凹部９を形成する。凹部９は、例えば、研削もしくは研磨のような機械的加工によって形成される。 As shown in FIG. 26, a recess 9 is formed in the carrier 6 in addition to the groove 8. The recess 9 is formed by mechanical processing such as grinding or polishing, for example.
　また、接合部材７を介して、配線基板１０をキャリア６に固定する際、第１アンテナユニット２ａと第２アンテナユニット２ｂとは、凹部９によってアライメントされる。一例では、配線基板１０の第３主面１０ｈのうち溝８とは反対側に位置する辺と、キャリア６に設けられた凹部９のうち、溝８とは反対側に位置する辺とを観察しながら、配線基板１０を凹部９に対してアライメントする。別の例では、配線基板１０の第３主面１０ｈのうち溝８とは反対側に位置する辺を、キャリア６に設けられた凹部９のうち、溝８とは反対側に位置する辺に接触させるように、配線基板１０を凹部９に対してアライメントする。 Further, when the wiring board 10 is fixed to the carrier 6 via the joining member 7, the first antenna unit 2a and the second antenna unit 2b are aligned by the recess 9. In one example, the side of the third main surface 10h of the wiring board 10 located on the opposite side of the groove 8 and the side of the recess 9 provided in the carrier 6 located on the opposite side of the groove 8 are observed. While aligning the wiring board 10 with respect to the recess 9. In another example, the side of the third main surface 10h of the wiring board 10 located on the side opposite to the groove 8 is set on the side of the recess 9 provided in the carrier 6 located on the side opposite to the groove 8. The wiring board 10 is aligned with respect to the recess 9 so as to be in contact with each other.
　本実施の形態のアレイアンテナ装置１ｃは、実施の形態１のアレイアンテナ装置１の効果に加えて、以下の効果を奏する。 The array antenna device 1c of the present embodiment exerts the following effects in addition to the effects of the array antenna device 1 of the first embodiment.
　本実施の形態のアレイアンテナ装置１ｃでは、キャリア６の第１主面６ｓに凹部９が設けられている。第１アンテナユニット２ａと第２アンテナユニット２ｂとは、凹部９に接合されている。そのため、アレイアンテナ装置１ｃの高さが減少する。アレイアンテナ装置１ｃは小型化され得る。また、第１アンテナユニット２ａと第２アンテナユニット２ｂとは、凹部９によってアライメントされるため、アレイアンテナ装置１ｃは高精度かつ容易に製造され得る。 In the array antenna device 1c of the present embodiment, the recess 9 is provided on the first main surface 6s of the carrier 6. The first antenna unit 2a and the second antenna unit 2b are joined to the recess 9. Therefore, the height of the array antenna device 1c is reduced. The array antenna device 1c can be miniaturized. Further, since the first antenna unit 2a and the second antenna unit 2b are aligned by the recess 9, the array antenna device 1c can be easily manufactured with high accuracy.
　実施の形態４．
　図２７から図３１を参照して、実施の形態４に係るアレイアンテナ装置１ｄを説明する。本実施の形態のアレイアンテナ装置１ｄは、実施の形態１のアレイアンテナ装置１と同様の構成を備えているが、以下の点で主に異なっている。 Embodiment 4.
The array antenna device 1d according to the fourth embodiment will be described with reference to FIGS. 27 to 31. The array antenna device 1d of the present embodiment has the same configuration as the array antenna device 1 of the first embodiment, but is mainly different in the following points.
　アレイアンテナ装置１ｄでは、溝８は、キャリア６の第１主面６ｓから第２主面６ｕまで延在している。溝８は、キャリア６の厚さ方向（第３方向（ｚ方向））において、キャリア６を貫通している。キャリア６は、複数のキャリア部分（第１キャリア部分６ａ及び第２キャリア部分６ｂ）で構成されている。溝８の底面８ｂは、第２主面６ｕに面する筐体５の前面５ｓである。筐体５は、電気的に接地されている。 In the array antenna device 1d, the groove 8 extends from the first main surface 6s of the carrier 6 to the second main surface 6u. The groove 8 penetrates the carrier 6 in the thickness direction of the carrier 6 (third direction (z direction)). The carrier 6 is composed of a plurality of carrier portions (first carrier portion 6a and second carrier portion 6b). The bottom surface 8b of the groove 8 is the front surface 5s of the housing 5 facing the second main surface 6u. The housing 5 is electrically grounded.
　アレイアンテナ装置１ｄでは、第１キャリア部分６ａおよび第２キャリア部分６ｂの第２主面６ｕにそれぞれ、複数の挿入部７０が設けられている。また、筐体５の前面５ｓには、複数の挿入部７０に対応した、複数のピン部７１が設けられている。 In the array antenna device 1d, a plurality of insertion portions 70 are provided on the second main surface 6u of the first carrier portion 6a and the second carrier portion 6b, respectively. Further, a plurality of pin portions 71 corresponding to the plurality of insertion portions 70 are provided on the front surface 5s of the housing 5.
　まず、挿入部７０について説明する。挿入部７０は、図２８および図２９に示されるとおり、キャリア６を構成する第１キャリア部分６ａおよび第２キャリア部分６ｂの第２主面６ｕから第１主面６ｓに向かって延伸する穴である。挿入部７０は、第１キャリア部分６ａおよび第２キャリア部分６ｂを第３方向（ｚ方向）に貫通していても良い。 First, the insertion portion 70 will be described. As shown in FIGS. 28 and 29, the insertion portion 70 is a hole extending from the second main surface 6u of the first carrier portion 6a and the second carrier portion 6b constituting the carrier 6 toward the first main surface 6s. is there. The insertion portion 70 may penetrate the first carrier portion 6a and the second carrier portion 6b in the third direction (z direction).
　挿入部７０は、１つのキャリア部分に対して２つ以上を設けることが好ましい。挿入部７０は、１つのキャリア部分において、互いの距離を可能な限り大きくすることが好ましい。たとえば、第１キャリア部分６ａおよび第２キャリア部分６ｂの平面形状が四角形状である場合、挿入部７０を第１キャリア部分６ａおよび第２キャリア部分６ｂの対角線上に位置する角部に設けてもよい。 It is preferable to provide two or more insertion portions 70 for one carrier portion. It is preferable that the insertion portions 70 have a distance between them as large as possible in one carrier portion. For example, when the plane shapes of the first carrier portion 6a and the second carrier portion 6b are rectangular, the insertion portion 70 may be provided at the corner portions located diagonally of the first carrier portion 6a and the second carrier portion 6b. Good.
　第１キャリア部分６ａおよび第２キャリア部分６ｂの第２主面６ｕの平面視において、挿入部７０の平面形状は任意の形状を採用してもよい。たとえば、加工の容易さから挿入部７０の平面形状を円形状あるいは長円形状としてもよい。あるいは、挿入部７０の平面形状を四角などの多角形状としてもよい。 In the plan view of the second main surface 6u of the first carrier portion 6a and the second carrier portion 6b, any shape may be adopted as the planar shape of the insertion portion 70. For example, the planar shape of the insertion portion 70 may be circular or oval for ease of processing. Alternatively, the planar shape of the insertion portion 70 may be a polygonal shape such as a square.
　次に、ピン部７１について説明する。ピン部７１は、図３０および図３１に示されるように、筐体５の前面５ｓから筐体５とは反対方向に向かって形成される略円柱形状の凸部である。つまり、ピン部７１は筐体５の前面５ｓから突出するように形成された凸部である。 Next, the pin portion 71 will be described. As shown in FIGS. 30 and 31, the pin portion 71 is a substantially cylindrical convex portion formed from the front surface 5s of the housing 5 in the direction opposite to the housing 5. That is, the pin portion 71 is a convex portion formed so as to project from the front surface 5s of the housing 5.
　ピン部７１は、筐体５の前面５ｓからピン部７１の天面までの第３方向（ｚ方向）での寸法が、深さ８ｄ未満になるように形成される。ピン部７１は、筐体５の前面５ｓの平面視において、ピン部７１の平面形状は任意の形状を採用してもよい。たとえば、ピン部７１の平面形状として、円形状、矩形状、略ひし形等の多角形状といった形状を用いることができる。ピン部７１の寸法は、対応する挿入部７０に挿入可能となるように決定される。ピン部７１は、筐体５の前面５ｓから遠位する先端部に、テーパ形状部、球形部、外側に凸の曲面状部など、筐体５の前面５ｓから離れるほど幅が小さくなる先細の形状を設けてもよい。 The pin portion 71 is formed so that the dimension in the third direction (z direction) from the front surface 5s of the housing 5 to the top surface of the pin portion 71 is less than 8d in depth. The pin portion 71 may adopt any shape as the planar shape of the pin portion 71 in the plan view of the front surface 5s of the housing 5. For example, as the planar shape of the pin portion 71, a polygonal shape such as a circular shape, a rectangular shape, or a substantially rhombus shape can be used. The dimensions of the pin portion 71 are determined so that they can be inserted into the corresponding insertion portion 70. The pin portion 71 has a tapered portion, such as a tapered portion, a spherical portion, and a curved surface portion that is convex outward, at the tip portion distal to the front surface 5s of the housing 5, and the width becomes smaller as the distance from the front surface 5s of the housing 5 decreases. A shape may be provided.
　次に、挿入部７０とピン部７１との機能を説明する。筐体５の前面５ｓに第１キャリア部分６ａおよび第２キャリア部分６ｂを搭載する際、複数の挿入部７０に、互いに対応する複数のピン部７１を挿入する。このとき、図２７に示されるように、挿入部７０とピン部７１の第１方向（ｘ方向）および第２方向（ｙ方向）における寸法差に応じた位置精度によって、第１キャリア部分６ａおよび第２キャリア部分６ｂと筐体５とは、第１方向（ｘ方向）および第２方向（ｙ方向）において正確にアライメントされ得る。すなわち、筐体５を介して、第１キャリア部分６ａと第２キャリア部分６ｂとは、簡易にかつ高精度に相対位置を決定できる。 Next, the functions of the insertion portion 70 and the pin portion 71 will be described. When the first carrier portion 6a and the second carrier portion 6b are mounted on the front surface 5s of the housing 5, a plurality of pin portions 71 corresponding to each other are inserted into the plurality of insertion portions 70. At this time, as shown in FIG. 27, the first carrier portion 6a and the first carrier portion 6a and the pin portion 71 are provided by the positional accuracy according to the dimensional difference between the insertion portion 70 and the pin portion 71 in the first direction (x direction) and the second direction (y direction). The second carrier portion 6b and the housing 5 can be accurately aligned in the first direction (x direction) and the second direction (y direction). That is, the relative positions of the first carrier portion 6a and the second carrier portion 6b can be easily and highly accurately determined via the housing 5.
　図３２から図３５を参照して、本実施の形態のアレイアンテナ装置１ｄの製造方法の一例を説明する。本実施の形態のアレイアンテナ装置１ｄの製造方法は、実施の形態１のアレイアンテナ装置１の製造方法と同様の工程を備えるが、以下の点で主に異なる。 An example of the manufacturing method of the array antenna device 1d of the present embodiment will be described with reference to FIGS. 32 to 35. The manufacturing method of the array antenna device 1d of the present embodiment includes the same steps as the manufacturing method of the array antenna device 1 of the first embodiment, but is mainly different in the following points.
　図３２に示されるように、第１キャリア部分６ａおよび第２キャリア部分６ｂに挿入部７０が形成される。当該挿入部７０は、第１キャリア部分６ａおよび第２キャリア部分６ｂを製造する際に、ドリル加工、レーザ加工、電解研磨加工等の加工方法を用いて形成される。 As shown in FIG. 32, the insertion portion 70 is formed in the first carrier portion 6a and the second carrier portion 6b. The insertion portion 70 is formed by using a processing method such as drilling, laser processing, or electrolytic polishing when manufacturing the first carrier portion 6a and the second carrier portion 6b.
　筐体５の前面５ｓにピン部７１が形成される。たとえば、ピン部７１は、一例として筐体５とは別の工程で、筐体５とは別部材として加工された後、筐体５に対して固定されてもよい。ピン部７１を筐体５に固定する方法は、任意の方法を用いることができるが、たとえばねじ締め、圧入、焼き嵌め等の方法を用いることができる。別の例では、筐体５を製造する際に、機械研削、レーザ加工、電解研磨加工等によって筐体５と一体の部分としてピン部７１を同時に形成してもよい。 A pin portion 71 is formed on the front surface 5s of the housing 5. For example, the pin portion 71 may be fixed to the housing 5 after being processed as a member different from the housing 5 in a process different from the housing 5 as an example. Any method can be used for fixing the pin portion 71 to the housing 5, but for example, a method such as screw tightening, press fitting, or shrink fitting can be used. In another example, when the housing 5 is manufactured, the pin portion 71 may be simultaneously formed as a portion integrated with the housing 5 by mechanical grinding, laser processing, electrolytic polishing, or the like.
　また、図３２に示されるように、第１キャリア部分６ａおよび第２キャリア部分６ｂの第１主面６ｓにそれぞれ接合部材７を供給し、次いで第１アンテナユニット２ａおよび第２アンテナユニット２ｂを接合部材７上に搭載する。第１アンテナユニット２ａおよび第２アンテナユニット２ｂは、フリップチップボンダ等の上下２眼カメラ認識による高精度な位置合わせが可能な設備によって、第１キャリア部分６ａおよび第２キャリア部分６ｂの第１主面６ｓとの相対位置を確認しながら搭載される。このとき、図３３および図３４に示すように、第１アンテナユニット２ａと第１キャリア部分６ａとの相対位置、および、第２アンテナユニット２ｂと第２キャリア部分６ｂとの相対位置は、挿入部７０にピン部７１を挿入した状態において、第１アンテナユニット２ａと第２アンテナユニット２ｂの給電パッチアンテナ素子１９が等間隔になるように位置合わせされてもよい。すなわち、第１アンテナユニット２ａおよび第２アンテナユニット２ｂは、それぞれの第１キャリア部分６ａおよび第２キャリア部分６ｂに設けられた挿入部７０と、筐体５の前面５ｓに設けられたピン部７１とを嵌合させることにより、互いに高精度に位置合わせされた状態で筐体５に固定され得る。 Further, as shown in FIG. 32, the joining member 7 is supplied to the first main surface 6s of the first carrier portion 6a and the second carrier portion 6b, respectively, and then the first antenna unit 2a and the second antenna unit 2b are joined. It is mounted on the member 7. The first antenna unit 2a and the second antenna unit 2b are the first main of the first carrier portion 6a and the second carrier portion 6b by means of equipment such as a flip chip bonder capable of highly accurate alignment by recognition of upper and lower twin-lens cameras. It is mounted while checking the relative position with the surface 6s. At this time, as shown in FIGS. 33 and 34, the relative positions of the first antenna unit 2a and the first carrier portion 6a and the relative positions of the second antenna unit 2b and the second carrier portion 6b are the insertion portions. With the pin portion 71 inserted in the 70, the feeding patch antenna elements 19 of the first antenna unit 2a and the second antenna unit 2b may be aligned at equal intervals. That is, the first antenna unit 2a and the second antenna unit 2b have an insertion portion 70 provided in the first carrier portion 6a and the second carrier portion 6b, respectively, and a pin portion 71 provided in the front surface 5s of the housing 5. By fitting the and, they can be fixed to the housing 5 in a state of being aligned with each other with high accuracy.
　また、図３４に示すひさし部１０ｍ、１０ｎは、第１方向（ｘ方向）の寸法の合計が、距離８ｗ（図３参照）より小さくなるように形成されている。そのため、第１アンテナユニット２ａと第２アンテナユニット２ｂとをそれぞれ筐体５に搭載する際、第１アンテナユニット２ａと第２アンテナユニット２ｂとは互いに干渉しない。 Further, the eaves portions 10m and 10n shown in FIG. 34 are formed so that the total dimensions in the first direction (x direction) are smaller than the distance of 8w (see FIG. 3). Therefore, when the first antenna unit 2a and the second antenna unit 2b are mounted on the housing 5, the first antenna unit 2a and the second antenna unit 2b do not interfere with each other.
　本実施の形態のアレイアンテナ装置１ｄでは、以上の構成を有することにより、実施の形態１のアレイアンテナ装置１の効果に加えて、以下の効果を奏する。 The array antenna device 1d of the present embodiment has the following effects in addition to the effects of the array antenna device 1 of the first embodiment by having the above configuration.
　本実施の形態のアレイアンテナ装置１ｄでは、第１キャリア部分６ａおよび第２キャリア部分６ｂの第２主面６ｕにそれぞれ、複数の挿入部７０が設けられている。また、筐体５の前面５ｓには、複数の挿入部７０に対応した、複数のピン部７１が設けられている。そのため、筐体５の前面５ｓに第１キャリア部分６ａおよび第２キャリア部分６ｂを搭載する際、それぞれの複数の挿入部７０と、対応する複数のピン部７１を用いて、第１方向（ｘ方向）および第２方向（ｙ方向）における第１キャリア部分６ａと第２キャリア部分６ｂとの相対位置を一定範囲に収めることができる。すなわち、筐体５と第１キャリア部分６ａおよび第２キャリア部分６ｂとは、高精度かつ容易に位置決めされた状態で製造され得る。 In the array antenna device 1d of the present embodiment, a plurality of insertion portions 70 are provided on the second main surface 6u of the first carrier portion 6a and the second carrier portion 6b, respectively. Further, a plurality of pin portions 71 corresponding to the plurality of insertion portions 70 are provided on the front surface 5s of the housing 5. Therefore, when the first carrier portion 6a and the second carrier portion 6b are mounted on the front surface 5s of the housing 5, the plurality of insertion portions 70 and the corresponding pin portions 71 are used in the first direction (x). The relative positions of the first carrier portion 6a and the second carrier portion 6b in the direction) and the second direction (y direction) can be kept within a certain range. That is, the housing 5, the first carrier portion 6a, and the second carrier portion 6b can be manufactured in a highly accurate and easily positioned state.
　上述したアレイアンテナ装置１ｄの利点は、アンテナユニット数を多く増やした場合に、相対的に高い効果を得ることができる。すなわち、図３５に示すようなアレイアンテナ装置１ｅの場合、たとえば実施の形態３における凹部９によるアライメントでは、第３アンテナユニット２ｃおよび第４アンテナユニット２ｄは凹部９を１辺にしか形成できないため、第２方向（ｙ方向）についてアライメントができない。 The advantage of the array antenna device 1d described above is that a relatively high effect can be obtained when the number of antenna units is increased. That is, in the case of the array antenna device 1e as shown in FIG. 35, for example, in the alignment by the recess 9 in the third embodiment, the third antenna unit 2c and the fourth antenna unit 2d can form the recess 9 on only one side. Alignment is not possible in the second direction (y direction).
　本実施の形態のアレイアンテナ装置１ｄは、挿入部７０とピン部７１を設けることにより、アンテナユニット数に関わらず、アンテナユニット同士の相対位置をアライメント可能である。図３５に示したアレイアンテナ装置１ｅは、第１キャリア部分６ａおよび第２キャリア部分６ｂ（図２７参照）からなるキャリア６上に、６つのアンテナユニット（第１アンテナユニット２ａ、第２アンテナユニット２ｂ、第３アンテナユニット２ｃ、第４アンテナユニット２ｄ、第５アンテナユニット２ｅ、および第６アンテナユニット２ｆ）が接合部材により接合されている。第１アンテナユニット２ａは第１接合部７ａにより第１キャリア部分６ａに接合されている。第２アンテナユニット２ｂは第２接合部７ｂにより第２キャリア部分６ｂに接合されている。第３アンテナユニット２ｃは第３接合部７ｃにより第１キャリア部分６ａに接合されている。第４アンテナユニット２ｄは第４接合部７ｇにより第２キャリア部分６ｂに接合されている。第５アンテナユニット２ｅは第５接合部７ｅにより第１キャリア部分６ａに接合されている。第６アンテナユニット２ｆは第６接合部７ｆにより第２キャリア部分６ｂに接合されている。 In the array antenna device 1d of the present embodiment, by providing the insertion portion 70 and the pin portion 71, the relative positions of the antenna units can be aligned regardless of the number of antenna units. The array antenna device 1e shown in FIG. 35 has six antenna units (first antenna unit 2a, second antenna unit 2b) on a carrier 6 including a first carrier portion 6a and a second carrier portion 6b (see FIG. 27). , 3rd antenna unit 2c, 4th antenna unit 2d, 5th antenna unit 2e, and 6th antenna unit 2f) are joined by a joining member. The first antenna unit 2a is joined to the first carrier portion 6a by the first joining portion 7a. The second antenna unit 2b is joined to the second carrier portion 6b by the second joint portion 7b. The third antenna unit 2c is joined to the first carrier portion 6a by the third joint portion 7c. The fourth antenna unit 2d is joined to the second carrier portion 6b by the fourth joint portion 7g. The fifth antenna unit 2e is joined to the first carrier portion 6a by the fifth joint portion 7e. The sixth antenna unit 2f is joined to the second carrier portion 6b by the sixth joint portion 7f.
　このように、本実施の形態のアレイアンテナ装置１ｄの構成（複数の挿入部７０とピン部７１とを備える構成）を、図３５に示すアレイアンテナ装置１ｅのような、３つ以上のアンテナユニットを有するアレイアンテナ装置に適用することで、当該アレイアンテナ装置を高精度かつ容易に製造できる。 As described above, the configuration of the array antenna device 1d of the present embodiment (the configuration including the plurality of insertion portions 70 and the pin portion 71) is the configuration of three or more antenna units such as the array antenna device 1e shown in FIG. 35. By applying to an array antenna device having the above, the array antenna device can be manufactured with high accuracy and easily.
　今回開示された実施の形態１－４はすべての点で例示であって制限的なものではないと考えられるべきである。矛盾のない限り、実施の形態１－４の少なくとも２つを組み合わせてもよい。本開示の基本的な範囲は、上記した説明ではなく請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることを意図される。 It should be considered that Embodiments 1-4 disclosed this time are exemplary in all respects and are not restrictive. As long as there is no contradiction, at least two of Embodiments 1-4 may be combined. The basic scope of the present disclosure is shown by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope of the claims.
　１，１ｂ，１ｃ，１ｄ，１ｅ　アレイアンテナ装置、２ａ　第１アンテナユニット、２ｂ　第２アンテナユニット、２ｃ　第３アンテナユニット、２ｄ　第４アンテナユニット、２ｅ　第５アンテナユニット、２ｆ　第６アンテナユニット、５　筐体、５ｓ　前面、６　キャリア、６ａ　第１キャリア部分、６ｂ　第２キャリア部分、６ｓ　第１主面、６ｔ　厚さ、６ｕ　第２主面、７　接合部材、７ａ　第１接合部、７ｂ　第２接合部、７ｃ　第３接合部、７ｇ　第４接合部、７ｅ　第５接合部、７ｆ　第６接合部、７ｄ　厚さ、８　溝、８ｂ　底面、８ｄ　深さ、８ｊ，８ｋ　側面、８ｗ，１０ｗ　幅、９　凹部、９ｄ　深さ、１０　配線基板、１０ｄ　厚さ、１０ｇ　ギャップ、１０ｈ　第３主面、１０ｊ，１０ｋ　側面、１０ｍ，１０ｎ　ひさし部、１０ｐ　仮想面、１０ｓ　第４主面、１１　半導体基板、１３　能動回路、１４　制御回路、１５　配線層、１６　絶縁層、１７　導体、１８　導電ビア、１９　給電パッチアンテナ素子、１９ｔ　第１頂面、２０　接地導体層、２０ｔ　第２頂面、２２　接着層、２６　誘電体基板、２７　誘電体基材、２７ｒ　第５主面、２７ｓ　第６主面、２９　無給電パッチアンテナ素子、３０　接続端子、３５　外部基板、３６　回路、３７　電子部品、４０　電気接続部材、６０　スリット、６０ｄ　深さ、６６ｄ，６７ｄ　距離、７０　挿入部、７１　ピン部。 1,1b, 1c, 1d, 1e Array antenna device, 2a 1st antenna unit, 2b 2nd antenna unit, 2c 3rd antenna unit, 2d 4th antenna unit, 2e 5th antenna unit, 2f 6th antenna unit, 5 Housing, 5s front, 6 carriers, 6a 1st carrier part, 6b 2nd carrier part, 6s 1st main surface, 6t thickness, 6u 2nd main surface, 7 joining members, 7a 1st joining part, 7b 2nd Joint part, 7c 3rd joint part, 7g 4th joint part, 7e 5th joint part, 7f 6th joint part, 7d thickness, 8 grooves, 8b bottom surface, 8d depth, 8j, 8k side surface, 8w, 10w width , 9 concave, 9d depth, 10 wiring board, 10d thickness, 10g gap, 10h 3rd main surface, 10j, 10k side surface, 10m, 10n eaves, 10p virtual surface, 10s 4th main surface, 11 semiconductor substrate, 13 active circuit, 14 control circuit, 15 wiring layer, 16 insulation layer, 17 conductor, 18 conductive via, 19 power supply patch antenna element, 19t 1st top surface, 20 ground conductor layer, 20t 2nd top surface, 22 adhesive layer, 26 Dielectric substrate, 27 Dielectric base material, 27r 5th main surface, 27s 6th main surface, 29 No power supply patch antenna element, 30 Connection terminals, 35 External board, 36 circuits, 37 Electronic components, 40 Electrical connection members, 60 slits, 60d depth, 66d, 67d distance, 70 insertion part, 71 pin part.

Claims (14)

  1. 　第１主面と、前記第１主面とは反対側の第２主面とを有するキャリアと、
    　第１接合部と、第２接合部とを含む接合部材と、
    　前記キャリアの前記第１主面に前記第１接合部を用いて接合されている第１アンテナユニットと、
    　前記キャリアの前記第１主面に前記第２接合部を用いて接合されており、かつ、前記第１アンテナユニットからギャップを空けて配置されている第２アンテナユニットとを備え、
    　前記第１アンテナユニットと前記第２アンテナユニットとは、各々、前記キャリアに近位する配線基板と、前記キャリアから遠位する誘電体基板とを含み、
    　前記配線基板は、前記キャリアに対向する第３主面と、前記第３主面とは反対側であり、かつ、前記誘電体基板に対向する第４主面とを有し、
    　前記配線基板は、前記第４主面上に設けられている給電パッチアンテナ素子を含み、
    　前記誘電体基板は、前記給電パッチアンテナ素子に対応して配置されている無給電パッチアンテナ素子を含み、
    　前記キャリアには、前記第１主面から前記第２主面に向けて延在する溝が設けられており、
    　前記第１主面の平面視において、前記溝は、前記第１アンテナユニットと前記第２アンテナユニットとの間の前記ギャップに対応して配置されており、
    　前記給電パッチアンテナ素子の第１頂面から前記溝の底面まで延在するスリットが、前記第１アンテナユニットと前記第２アンテナユニットとの間に形成されている、アレイアンテナ装置。     A carrier having a first main surface and a second main surface opposite to the first main surface,
    A joint member including a first joint portion and a second joint portion,
    A first antenna unit bonded to the first main surface of the carrier using the first joint portion, and
    A second antenna unit that is joined to the first main surface of the carrier by using the second joint portion and is arranged with a gap from the first antenna unit is provided.
    The first antenna unit and the second antenna unit each include a wiring board proximal to the carrier and a dielectric substrate distal to the carrier.
    The wiring board has a third main surface facing the carrier and a fourth main surface opposite to the third main surface and facing the dielectric substrate.
    The wiring board includes a feeding patch antenna element provided on the fourth main surface.
    The dielectric substrate includes a non-feeding patch antenna element arranged corresponding to the feeding patch antenna element.
    The carrier is provided with a groove extending from the first main surface to the second main surface.
    In the plan view of the first main surface, the groove is arranged corresponding to the gap between the first antenna unit and the second antenna unit.
    An array antenna device in which a slit extending from the first top surface of the feeding patch antenna element to the bottom surface of the groove is formed between the first antenna unit and the second antenna unit.
  2. 　前記配線基板は、前記第４主面上に設けられており、かつ、前記給電パッチアンテナ素子から離間されている接地導体層を含み、
    　前記接地導体層の第２頂面は、前記給電パッチアンテナ素子の前記第１頂面と実質的に面一であり、
    　前記キャリアは、電気的に接地されており、
    　前記スリットの深さは、実質的に、前記給電パッチアンテナ素子が送信または受信する電磁波の波長の半分の整数倍である、請求項１に記載のアレイアンテナ装置。     The wiring board includes a ground conductor layer provided on the fourth main surface and separated from the feeding patch antenna element.
    The second top surface of the ground conductor layer is substantially flush with the first top surface of the feed patch antenna element.
    The carrier is electrically grounded and
    The array antenna device according to claim 1, wherein the depth of the slit is substantially an integral multiple of half the wavelength of the electromagnetic wave transmitted or received by the feeding patch antenna element.
  3. 　前記スリットの最小幅は、前記スリットの前記深さよりも小さい、請求項２に記載のアレイアンテナ装置。 The array antenna device according to claim 2, wherein the minimum width of the slit is smaller than the depth of the slit.
  4. 　前記ギャップの幅は、前記溝の幅より狭い、請求項１から請求項３のいずれか一項に記載のアレイアンテナ装置。 The array antenna device according to any one of claims 1 to 3, wherein the width of the gap is narrower than the width of the groove.
  5. 　前記接合部材は、前記溝の前記底面から離間されている、請求項１から請求項４のいずれか一項に記載のアレイアンテナ装置。 The array antenna device according to any one of claims 1 to 4, wherein the joining member is separated from the bottom surface of the groove.
  6. 　前記第１接合部は、前記溝において、前記第２接合部から離間されている、請求項１から請求項５のいずれか一項に記載のアレイアンテナ装置。 The array antenna device according to any one of claims 1 to 5, wherein the first joint is separated from the second joint in the groove.
  7. 　前記溝の前記底面は、前記第２主面から離間されている、請求項１から請求項６のいずれか一項に記載のアレイアンテナ装置。 The array antenna device according to any one of claims 1 to 6, wherein the bottom surface of the groove is separated from the second main surface.
  8. 　前記キャリアの前記第２主面を支持する筐体をさらに備え、
    　前記溝は、前記第１主面から前記第２主面まで延在しており、
    　前記溝の前記底面は、前記第２主面に面する前記筐体の前面であり、
    　前記筐体は、電気的に接地されている、請求項１から請求項６のいずれか一項に記載のアレイアンテナ装置。     A housing that supports the second main surface of the carrier is further provided.
    The groove extends from the first main surface to the second main surface.
    The bottom surface of the groove is the front surface of the housing facing the second main surface.
    The array antenna device according to any one of claims 1 to 6, wherein the housing is electrically grounded.
  9. 　前記キャリアの前記第２主面を支持する筐体をさらに備え、
    　前記筐体は、前記第２主面に面する前面を含み、
    　前記筐体の前記前面には、複数のピン部が設けられており、
    　前記キャリアの前記第２主面には、前記複数のピン部に対応した複数の挿入部が設けられており、
    　前記複数のピン部と前記複数の挿入部との嵌め合いによって、前記前面の平面視における前記キャリアと前記筐体との相対的な位置が固定される、請求項１から請求項６のいずれか一項に記載のアレイアンテナ装置。     A housing that supports the second main surface of the carrier is further provided.
    The housing includes a front surface facing the second main surface.
    A plurality of pin portions are provided on the front surface of the housing.
    A plurality of insertion portions corresponding to the plurality of pin portions are provided on the second main surface of the carrier.
    Any one of claims 1 to 6, wherein the relative positions of the carrier and the housing in the plan view of the front surface are fixed by the fitting of the plurality of pin portions and the plurality of insertion portions. The array antenna device according to claim 1.
  10. 　前記溝は、前記第１主面から前記第２主面まで延在しており、
    　前記溝の前記底面は、前記筐体の前記前面であり、
    　前記筐体は、電気的に接地されている、請求項９に記載のアレイアンテナ装置。     The groove extends from the first main surface to the second main surface.
    The bottom surface of the groove is the front surface of the housing.
    The array antenna device according to claim 9, wherein the housing is electrically grounded.
  11. 　前記キャリアの前記第１主面に凹部が設けられており、
    　前記第１アンテナユニットと前記第２アンテナユニットとは、前記凹部に接合されている、請求項１から請求項１０のいずれか一項に記載のアレイアンテナ装置。     A recess is provided on the first main surface of the carrier.
    The array antenna device according to any one of claims 1 to 10, wherein the first antenna unit and the second antenna unit are joined to the recess.
  12. 　前記接合部材は、導電性接合部材である、請求項１から請求項１１のいずれか一項に記載のアレイアンテナ装置。 The array antenna device according to any one of claims 1 to 11, wherein the joining member is a conductive joining member.
  13. 　前記接合部材は、絶縁性接合部材である、請求項１から請求項１１のいずれか一項に記載のアレイアンテナ装置。 The array antenna device according to any one of claims 1 to 11, wherein the joining member is an insulating joining member.
  14. 　前記第１アンテナユニットの前記無給電パッチアンテナ素子は、複数の無給電パッチアンテナ素子であり、
    　前記第２アンテナユニットの前記無給電パッチアンテナ素子は、複数の無給電パッチアンテナ素子であり、
    　前記第１主面の前記平面視において、前記第１アンテナユニットの前記複数の無給電パッチアンテナ素子と前記第２アンテナユニットの前記複数の無給電パッチアンテナ素子とは等間隔に配列されている、請求項１から請求項１３のいずれか一項に記載のアレイアンテナ装置。     The non-feeding patch antenna element of the first antenna unit is a plurality of non-feeding patch antenna elements.
    The non-feeding patch antenna element of the second antenna unit is a plurality of non-feeding patch antenna elements.
    In the plan view of the first main surface, the plurality of non-feeding patch antenna elements of the first antenna unit and the plurality of non-feeding patch antenna elements of the second antenna unit are arranged at equal intervals. The array antenna device according to any one of claims 1 to 13.
PCT/JP2020/027091 2019-07-11 2020-07-10 Array antenna device WO2021006344A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB2115467.9A GB2598674B (en) 2019-07-11 2020-07-10 Array antenna Apparatus
JP2021530740A JP7126619B2 (en) 2019-07-11 2020-07-10 array antenna device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-128935 2019-07-11
JP2019128935 2019-07-11

Publications (1)

Publication Number Publication Date
WO2021006344A1 true WO2021006344A1 (en) 2021-01-14

Family

ID=74113780

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/027091 WO2021006344A1 (en) 2019-07-11 2020-07-10 Array antenna device

Country Status (3)

Country Link
JP (1) JP7126619B2 (en)
GB (1) GB2598674B (en)
WO (1) WO2021006344A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154892A (en) * 1997-07-31 1999-02-26 Yupiteru Ind Co Ltd Method and structure for attaching electronic component to glass fluororesin substrate
JPH1188039A (en) * 1997-09-09 1999-03-30 Harness Sogo Gijutsu Kenkyusho:Kk Circuit connection structure inside vehicle
JP2009025930A (en) * 2007-07-18 2009-02-05 Murata Mfg Co Ltd Radio ic device and method for manufacturing the same
JP2011134956A (en) * 2009-12-25 2011-07-07 Shinko Electric Ind Co Ltd Semiconductor device
WO2016067906A1 (en) * 2014-10-30 2016-05-06 三菱電機株式会社 Array antenna device and method for manufacturing same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548302A (en) * 1991-08-14 1993-02-26 Mitsubishi Electric Corp Microwave integrated circuit device
JP2001007628A (en) * 1999-06-25 2001-01-12 Nec Corp Phased array antenna
JP4361658B2 (en) * 2000-02-14 2009-11-11 富士通マイクロエレクトロニクス株式会社 Mounting board and mounting method
US7348666B2 (en) * 2004-06-30 2008-03-25 Endwave Corporation Chip-to-chip trench circuit structure
US9112262B2 (en) * 2011-06-02 2015-08-18 Brigham Young University Planar array feed for satellite communications

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154892A (en) * 1997-07-31 1999-02-26 Yupiteru Ind Co Ltd Method and structure for attaching electronic component to glass fluororesin substrate
JPH1188039A (en) * 1997-09-09 1999-03-30 Harness Sogo Gijutsu Kenkyusho:Kk Circuit connection structure inside vehicle
JP2009025930A (en) * 2007-07-18 2009-02-05 Murata Mfg Co Ltd Radio ic device and method for manufacturing the same
JP2011134956A (en) * 2009-12-25 2011-07-07 Shinko Electric Ind Co Ltd Semiconductor device
WO2016067906A1 (en) * 2014-10-30 2016-05-06 三菱電機株式会社 Array antenna device and method for manufacturing same

Also Published As

Publication number Publication date
JP7126619B2 (en) 2022-08-26
GB2598674A (en) 2022-03-09
GB202115467D0 (en) 2021-12-08
GB2598674B (en) 2023-07-05
JPWO2021006344A1 (en) 2021-01-14

Similar Documents

Publication Publication Date Title
US11437295B2 (en) Semiconductor package and electronic device having the same
US10714838B2 (en) Array antenna apparatus and method of manufacturing the same
US10103450B2 (en) Integration of area efficient antennas for phased array or wafer scale array antenna applications
US8247702B2 (en) Integrated circuit mounted board, printed wiring board, and method of manufacturing integrated circuit mounted board
US7400222B2 (en) Grooved coaxial-type transmission line, manufacturing method and packaging method thereof
US7236070B2 (en) Electronic component module and manufacturing method thereof
EP0933816B1 (en) Hybrid module
US6903700B2 (en) High frequency circuit substrate and method for forming the same
US20150131231A1 (en) Electronic component module and manufacturing method thereof
US9978698B1 (en) Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members
US20090245724A1 (en) Module substrate including optical tranmission mechanism and method of producing the same
CN109326584B (en) Packaged antenna and method of manufacturing the same
KR20080018248A (en) Reduced inductance interconnect for enhanced microwave and millimeter-wave systems
JP2019102660A (en) Electronic equipment and manufacturing method for electronic equipment
US20110174526A1 (en) Circuit module
CN114639943A (en) Integrated circuit package with integrated waveguide emitter
WO2021006344A1 (en) Array antenna device
US11245177B1 (en) Wireless communication module
US10388628B2 (en) Electronic component package
US10679920B2 (en) Semiconductor device having semiconductor package in a wiring board opening
CN114902401B (en) Thermal management package and method
WO2024181322A1 (en) Wiring substrate, and optical module using wiring substrate
JP3510813B2 (en) Hybrid module
CN118117330A (en) Antenna module
JP2000353770A (en) Integrated circuit package, millimeter wave integrated circuit package, and method of assembling and mounting integrated circuit package on board

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20837628

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021530740

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 202115467

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20200710

122 Ep: pct application non-entry in european phase

Ref document number: 20837628

Country of ref document: EP

Kind code of ref document: A1