WO2020262097A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2020262097A1
WO2020262097A1 PCT/JP2020/023520 JP2020023520W WO2020262097A1 WO 2020262097 A1 WO2020262097 A1 WO 2020262097A1 JP 2020023520 W JP2020023520 W JP 2020023520W WO 2020262097 A1 WO2020262097 A1 WO 2020262097A1
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Prior art keywords
semiconductor device
insulating layer
conductor
layer
semiconductor
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PCT/JP2020/023520
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French (fr)
Japanese (ja)
Inventor
高志 平尾
円丈 露野
悠佳 清水
晃 松下
Original Assignee
日立オートモティブシステムズ株式会社
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Application filed by 日立オートモティブシステムズ株式会社 filed Critical 日立オートモティブシステムズ株式会社
Priority to DE112020002625.6T priority Critical patent/DE112020002625T5/en
Priority to CN202080045792.8A priority patent/CN114008775A/en
Publication of WO2020262097A1 publication Critical patent/WO2020262097A1/en

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10254—Diamond [C]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
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    • H01L2924/1067—Oxide
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same.
  • a power semiconductor device having a power conversion unit for driving a motor or the like there is a power semiconductor device having a structure in which a power semiconductor element is sandwiched between a pair of metal plates and a resin is filled between the metal plates to seal the semiconductor element. More specifically, a metal block is bonded to one electrode of the semiconductor element, the metal block is connected to one metal plate, and the other electrode of the semiconductor element is connected to the other metal plate. The area of each metal plate is formed larger than the area of the front and back surfaces of the semiconductor element, and a resin is filled between the pair of metal plates by a molding method such as a transfer molding method to seal the semiconductor element ( For example, see Patent Document 1).
  • the sealing resin formed by the molding method tends to have defects such as voids.
  • a high voltage is applied to a power semiconductor element, so if a defect such as a void is present in the sealing resin, an electric field may be concentrated on the defect and a partial discharge may occur. If the state in which the partial discharge occurs continues, the sealing resin may deteriorate, and eventually dielectric breakdown may occur and the power semiconductor device may fail.
  • the semiconductor device is bonded to the surface electrode with a first insulating layer having an opening and a semiconductor element having a surface electrode exposed from the opening of the first insulating layer.
  • a conductor connected to a relay conductor and a sealing resin filled between the conductor and the second insulating layer are provided.
  • the semiconductor device includes a plurality of semiconductor elements having a first insulating layer having an opening and a surface electrode exposed from the opening of the first insulating layer, and each of the semiconductor elements. It covers at least a part of the relay conductor bonded to the surface electrode, the bonding layer joining each surface electrode and the relay conductor, and each of the first insulating layers, and is in contact with at least the periphery of the bonding layer.
  • a second insulating layer provided and a conductor connecting the respective relay conductors are provided.
  • the method for manufacturing a semiconductor device is to prepare a first insulating layer having an opening and a semiconductor element having a surface electrode exposed from the opening of the first insulating layer.
  • the surface electrode and the relay conductor are joined by a bonding layer, at least a part of the first insulating layer is covered, and at least a second insulating layer in contact with the periphery of the bonding layer is provided, and the relay conductor is provided with a conductor. Includes connecting the conductor and filling the sealing resin between the conductor and the second insulating layer.
  • the occurrence of partial discharge is suppressed even in the presence of voids.
  • FIG. 3 is a sectional view of a first embodiment of the semiconductor device of the present invention.
  • (A) and (B) are sectional views of the semiconductor device in each step for explaining the manufacturing method of the semiconductor device 100 illustrated in FIG.
  • (A) and (B) are cross-sectional views of the semiconductor device in each step following FIG.
  • FIG. 5 is a cross-sectional view of a second embodiment of the semiconductor device of the present invention. It is sectional drawing for demonstrating the action which a high electric field is applied to the void existing in a sealing resin, and partial discharge is generated,
  • (A) is sectional drawing of the semiconductor device 100R of a comparative example,
  • (B) is Sectional drawing of the semiconductor device of this embodiment.
  • FIG. 6 An enlarged exploded perspective view of the semiconductor device shown in FIG. 6 is a cross-sectional view of the semiconductor device shown in FIG. 6, where FIG. 6A is a cross-sectional view before resin sealing, and FIG. 6B is a cross-sectional view after resin sealing.
  • FIG. 1 is a cross-sectional view of a first embodiment of the semiconductor device of the present invention.
  • the semiconductor device 100 includes a semiconductor element 10.
  • the semiconductor element 10 is, for example, a SiC (silicon carbide) MOS FET (Metal-Oxide-Semiconductor Field effect transistor).
  • the semiconductor element 10 has a semiconductor substrate 11, a source electrode 12, a drain electrode 13, an internal wiring 14, and a first insulating layer 15. Although not shown in FIG. 1, the semiconductor element 10 has a gate electrode 17 (see FIG. 7).
  • the semiconductor device 100 includes a semiconductor element 10, a relay conductor 21, a front surface side conductor 22, a back surface side conductor 23, a second insulating layer 31, and a sealing resin 32.
  • the first insulating layer 15 is an insulating film provided inside the semiconductor substrate 11 to protect the impurity region for forming the semiconductor element and the internal wiring 14, and is formed of an inorganic material such as silicon oxide or silicon nitride. Has been done.
  • the first insulating layer 15 is provided with an opening 15a (see also FIG. 2B).
  • the source electrode 12 is formed slightly larger than the opening 15a of the first insulating layer 15, and the inside of the peripheral edge of the source electrode 12 is exposed from the opening 15a of the first insulating layer 15.
  • the first insulating layer 15 is formed of, for example, a resin such as polyimide or polybenzoxador.
  • the first insulating layer 15 is formed by a semiconductor device manufacturer, and its thickness is generally about several ⁇ m.
  • the relay conductor 21 has an area slightly smaller than the opening 15a of the first insulating layer 15, and is joined to the entire surface of the source electrode 12 exposed from the opening 15a of the first insulating layer 15 by the bonding layer 41. ing.
  • the bonding layer 41 has substantially the same area as the relay conductor 21. Therefore, a gap G (see FIG. 2B) is formed between the peripheral edge of the bonding layer 41 and the peripheral edge of the opening 15a of the first insulating layer 15.
  • the relay conductor 21 can be formed of a copper-based metal. Further, the relay conductor 21 can be formed by using a clad material such as CIC (Copper Invar Copper). Invar (registered trademark) is an alloy of iron and nickel and is a material with a low coefficient of thermal expansion. Therefore, by forming the relay conductor 21 from a material containing Invar, even if the semiconductor element 10 becomes hot during driving, It is possible to suppress peeling from the sealing resin 32.
  • CIC Copper Invar Copper
  • the second insulating layer 31 is formed on the first insulating layer 15.
  • the second insulating layer 31 is not formed on the entire surface of the first insulating layer 15, and the peripheral edge side of the first insulating layer 15 is exposed from the second insulating layer 31.
  • the second insulating layer 31 is also filled in the gap G between the peripheral edge of the bonding layer 41 and the peripheral edge of the opening 15a of the first insulating layer 15, and the peripheral edge of the bonding layer 41 and the relay conductor 21 are also filled. It is in contact with the peripheral edge of the region near the joint layer 41 side of the above.
  • the second insulating layer 31 is formed by coating using a potting method, a printing method, or the like.
  • the second insulating layer 31 is formed of, for example, a resin such as polyamideimide, polyimide, polyetheramideimide, or polyetheramide.
  • the first insulating layer 15 and the second insulating layer 31 may be formed of the same resin.
  • the second insulating layer 31 is about several tens of ⁇ m, and is preferably thicker than the thickness of the first insulating layer 15.
  • the surface-side conductor 22 has a surface area of the semiconductor element 10, that is, an area larger than the area of the first insulating layer 15 in a plan view.
  • the surface side conductor 22 is joined to the relay conductor 21 by the joining layer 42.
  • the bonding layer 42 has substantially the same area as the relay conductor 21.
  • the surface side conductor 22 can be formed of a copper-based metal or an aluminum-based metal.
  • the back surface side conductor 23 is bonded to the drain electrode 13 provided on the back surface side facing the source electrode 12 of the semiconductor substrate 11 by the bonding layer 43.
  • the back surface side conductor 23 has the same area as the front surface side conductor 22.
  • the sealing resin 32 is filled between the front surface side conductor 22 and the back surface side conductor 23. That is, the peripheral side surface of the semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 are sealed with the sealing resin 32.
  • the back surface side conductor 23 can be formed of a copper-based metal or an aluminum-based metal.
  • Solder or sintered metal material can be used as the bonding layers 41 to 43.
  • the sealing resin 32 an epoxy resin or the like can be used.
  • a molding method such as transfer molding is suitable, but a printing method such as a potting method, silk printing, sealing printing, inkjet printing, thermal transfer printing or the like may be used.
  • FIG. 5 is a cross-sectional view for explaining the action of applying a high electric field to the voids existing in the sealing resin to generate a partial discharge.
  • FIG. 5A is a cross-sectional view showing a void generated in the sealing resin of the semiconductor device 100R of the comparative example
  • FIG. 5B is a void generated in the sealing resin of the semiconductor device 100 of the present embodiment. It is sectional drawing which shows.
  • the semiconductor device 100R of the comparative example shown in FIG. 5A does not have the relay conductor 21 of the semiconductor device 100 of the present embodiment.
  • the surface-side conductor 22R has a protruding portion 25 facing the portion of the source electrode 12 exposed from the opening 15a of the first insulating layer 15.
  • the protruding portion 25 is integrally molded with the surface side conductor 22R. That is, after the protruding portion 25 and the source electrode 12 are joined by the joining layer 41, the peripheral region of the gap G between the inner peripheral edge portion of the opening 15a of the first insulating layer 15 and the joining layer 41 is sealed. It is covered with the surface side conductor 22R via the resin 32.
  • the second insulating layer 31R when the second insulating layer 31R is applied on the first insulating layer 15 before the sealing resin 32 is filled between the front surface side conductor 22R and the back surface side conductor 23, the front surface side conductor 22R becomes an obstacle. Therefore, it is difficult to form the second insulating layer 31R so as to be in contact with the peripheral edge of the bonding layer 41 or the peripheral edge of the protruding portion 25. That is, the gap G between the inner peripheral edge of the opening 15a of the first insulating layer 15 and the bonding layer 41 is not covered by the first insulating layer 15 or the second insulating layer 31R. In FIG.
  • the second insulating layer 31R when the second insulating layer 31R is filled before the surface side conductor 22R is joined to the source electrode 12, the region where the surface side conductor 22R of the source electrode 12 is joined (surface side conductor joining region).
  • a step is required to prevent the second insulating layer 31R) from invading the surface. Further, in this step, it is necessary to provide a slight gap G between the surface side conductor bonding region of the source electrode 12 and the inner peripheral edge portion of the opening 15a of the first insulating layer 15, and the insulating material is provided in this slight gap G. can not be sufficiently filled, the sealing resin degradation due to a high electric field of voids a V can not be avoided.
  • a high electric field is generated around the source electrode 12.
  • a SiC MOS FET produces a high electric field with a dielectric breakdown electric field strength about 10 times that of a Si MOSFET.
  • voids A V is present in the sealing resin 32 near the source electrode 12
  • a high electric field is concentrated on the void A V, partial discharge may occur. If the state in which the partial discharge occurs continues, the sealing resin 32 deteriorates, and finally dielectric breakdown occurs and the semiconductor element 10 fails.
  • a sealing resin by molding method is difficult to fill, there is a high probability that voids A V occurs.
  • the semiconductor device 100 of the present embodiment has a relay conductor 21 provided between the source electrode 12 and the surface side conductor 22. Therefore, in a state where the relay conductor 21 is bonded to the source electrode 12 by the bonding layer 41, the second insulating layer 31 is attached to the peripheral portion of the first insulating layer 15 before the surface side conductor 22 is bonded to the relay conductor 21. It can be filled in the gap G between the bonding layer 41 and the bonding layer 41.
  • voids A V is present in the second insulating layer 31 by a sealing resin 32 in a state where the gap G is covered between the peripheral edge portion of the first insulating layer 15 and the bonding layer 41, generated in the source electrode 12 periphery a high electric field is divided voltage and half to be applied to the voltage and the second insulating layer 31 applied to the void a V.
  • Voltage applied to the voids A V is the air layer is related to the ratio of the dielectric constant of the second insulating layer 31 for dielectric constant, and the void A V thickness and the second insulating layer 31 thickness of the air layer.
  • the thickness increases in the second insulating layer 31, the thickness of the void A V decreases, the voltage to focus the void A V decreases. Therefore, by setting the thickness of the second insulating layer 31 to a predetermined thickness or more, the voltage applied to the void A V can be smaller than the partial discharge inception voltage.
  • the second insulating layer 31 has a predetermined thickness or more, then the front side conductor 22 is joined to the relay conductor 21 by the joining layer 42, and the sealing resin is formed between the front side conductor 22 and the back side conductor 23. If 32 filled with, be void a V is generated in the sealing resin 32, it is possible to suppress the partial discharge occurs. Next, a method of manufacturing the semiconductor device 100 will be described.
  • FIGS. 3 (A) and 3 (B) are cross-sectional views of the semiconductor device in each step for explaining the manufacturing method of the semiconductor device 100 illustrated in FIG. 1, and FIGS. 3 (A) and 3 (B).
  • B) is a cross-sectional view of the semiconductor device in each step following FIG.
  • the semiconductor element 10 is prepared. As described above, the semiconductor element 10 has a semiconductor substrate 11, a source electrode 12, a drain electrode 13, an internal wiring 14, and a first insulating layer 15. Then, as shown in FIG. 2A, the drain electrode 13 of the semiconductor element 10 and the back surface side conductor 23 are joined by the joining layer 43.
  • solder or a sintered metal material can be used as the bonding layer 43.
  • the sintered metal material has a powder or paste form, and becomes a sintered metal by heating.
  • As the sintered metal material it is preferable to use a sintered metal bonding paste containing copper or silver.
  • a bonding layer 43 is interposed between the drain electrode 13 of the semiconductor element 10 and the back surface side conductor 23, and the bonding is performed by thermocompression bonding.
  • the source electrode 12 of the semiconductor element 10 and the relay conductor 21 are joined by the joining layer 41.
  • the bonding layer 41 the same layer as the bonding layer 43 is used.
  • a bonding layer 41 is interposed between the source electrode 12 of the semiconductor element 10 and the relay conductor 21 and bonded by thermocompression bonding.
  • the bonding layer 41 that joins the source electrode 12 of the semiconductor element 10 and the relay conductor 21 is provided in the opening 15a of the first insulating layer 15 of the semiconductor element 10. That is, the bonding layer 41 is smaller than the opening 15a of the first insulating layer 15 of the semiconductor element 10. Therefore, a gap G is formed between the peripheral edge of the first insulating layer 15 and the bonding layer 41.
  • FIG. 2 (A) and the process of FIG. 2 (B) may be reversed. Moreover, you may carry out in the same process.
  • the drain electrode 13 of the semiconductor element 10 and the back surface side conductor 23 are interposed with the bonding layer 43, and the bonding layer 41 is interposed between the source electrode 12 of the semiconductor element 10 and the relay conductor 21. , In this state, the whole is thermocompression bonded.
  • the second insulating layer 31 is applied on the first insulating layer 15.
  • the second insulating layer 31 is formed in the peripheral edge of the bonding layer 41 in the gap G (see FIG. 2B) between the peripheral edge of the bonding layer 41 and the peripheral edge of the opening 15a of the first insulating layer 15. Filled to touch.
  • the second insulating layer 31 may be provided so as to be in contact with the lower end portion side of the relay conductor 21, in other words, the peripheral edge portion on the bonding layer 41 side.
  • a potting method using a dispenser or a printing method can be used for forming the second insulating layer 31.
  • As a printing method silk printing, sealing printing, inkjet printing, thermal transfer printing and the like can be applied.
  • the surface side conductor 22 is joined to the relay conductor 21 by the joining layer 42.
  • the bonding layer 42 the same layer as the bonding layers 41 and 43 is used.
  • a bonding layer 42 is interposed between the relay conductor 21 and the surface side conductor 22 and bonded by thermocompression bonding.
  • the sealing resin 32 is filled between the front surface side conductor 22 and the back surface side conductor 23.
  • the semiconductor device 100 shown in FIG. 1 is formed in which the peripheral side surface of the semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 are sealed with the sealing resin 32.
  • the transfer molding method is suitable for forming the sealing resin 32, but a potting method or a printing method may also be used.
  • the semiconductor device 100 is joined to a semiconductor element 10 having a first insulating layer 15 having an opening 15a and a source electrode (surface electrode) 12 exposed from the opening 15a of the first insulating layer 15 and the source electrode 12.
  • the second insulation is provided so as to cover at least a part of the first insulating layer 15 and the joint layer 41 that joins the relay conductor 21 and the source electrode 12 and the relay conductor 21 so as to be in contact with at least the periphery of the joint layer 41.
  • the layer 31 includes a surface-side conductor (conductor) 22 connected to the relay conductor 21, and a sealing resin 32 filled between the surface-side conductor 22 and the second insulating layer 31.
  • the source electrode 12 exposed from the opening 15a of the first insulating layer 15 is covered with the second insulating layer 31 provided in contact with the periphery of the bonding layer 41. Therefore, even if there is a void A V in the sealing resin 32, the occurrence of partial discharge can be suppressed, it is possible to suppress the deterioration of the sealing resin 32.
  • FIG. 4 is a cross-sectional view of a second embodiment of the semiconductor device of the present invention.
  • the semiconductor device 100 of the second embodiment has a structure in which the second insulating layer 31a extends on the outer peripheral side surface of the semiconductor element 10 and is in contact with the back surface side conductor 23.
  • the second insulating layer 31 is formed only on the front surface side of the semiconductor element 10, and is not extended so as to be in contact with the back surface side conductor 23.
  • the joining layer 41 may be melted by heating during thermocompression bonding, and the relay conductor 21 may be misaligned.
  • the second insulating layer 31a extends to a position where it contacts the back surface side conductor 23. Since the second insulating layer 31a is in contact with the relay conductor 21, even if the bonding layer 41 is melted by heating during thermocompression bonding, the movement of the relay conductor 21 is restricted by the second insulating layer 31a in contact with the back surface side conductor 23. Will be done.
  • the other configurations of the second embodiment are the same as those of the first embodiment, and the corresponding configurations are designated by the same reference numerals and the description thereof will be omitted.
  • the second embodiment also has the same effect as that of the first embodiment. Further, according to the second embodiment, it is possible to suppress the misalignment of the relay conductor 21 when the surface side conductor 22 is joined to the relay conductor 21.
  • FIG. 6 is an exploded perspective view of a third embodiment of the semiconductor device of the present invention.
  • the semiconductor device 200 includes four semiconductor devices 300, an outer front surface side conductor 222, and an outer back surface side conductor 223.
  • the four semiconductor devices 300 are arranged in a matrix with two rows in the horizontal direction and two columns in the vertical direction, separated from each other.
  • the outer front surface side conductor 222 and the outer back surface side conductor 223 each have a size that covers the entire region of the four semiconductor devices 300 arranged in a matrix. All four semiconductor devices 300 have the same structure.
  • the two semiconductor devices 300 each have an upper arm circuit, and the remaining two semiconductor devices 300 each have a lower arm circuit.
  • the semiconductor device 300 having the upper arm circuit and the semiconductor device 300 having the lower arm circuit are connected in series to form an upper and lower arm series circuit.
  • a power conversion device capable of obtaining AC outputs having different phases can be configured from the connection portion between the upper arm circuit and the lower arm circuit.
  • FIG. 7 is an enlarged exploded perspective view of the semiconductor device shown in FIG. 6,
  • FIG. 8 is a cross-sectional view of the semiconductor device shown in FIG. 6, and
  • FIG. 8 (A) is a cross section before resin sealing.
  • FIG. 8 (B) is a cross-sectional view after resin sealing.
  • the semiconductor device 300 includes four semiconductor elements 10, a front surface side conductor 122, and a back surface side conductor 123.
  • the four semiconductor elements 10 are arranged in a matrix with two rows in the horizontal direction and two columns in the vertical direction, separated from each other. That is, the semiconductor device 300 is configured as a 4in1 package.
  • the front surface side conductor 122 and the back surface side conductor 123 each have a size that covers the entire region of the four semiconductor elements 10 arranged in a matrix.
  • Each of the four semiconductor elements 10 has the same structure as the semiconductor element of the first embodiment. That is, as shown in FIG. 8, the semiconductor element 10 has a semiconductor substrate 11, a source electrode 12, a drain electrode 13, an internal wiring 14, and a first insulating layer 15. As shown in FIG. 8, a relay conductor 21 is bonded to the source electrode 12 of each semiconductor element 10 via a bonding layer 41. Further, on the first insulating layer 15 of each semiconductor element 10, a second insulating layer 31 is formed which is in contact with the peripheral edge of the bonding layer 41 and the peripheral region of the relay conductor 21 near the bonding layer 41 side.
  • the surface-side conductor 122 is attached to a rectangular body covering the four semiconductor elements 10 and to the tips of legs extending from each of the four corners of the rectangular body. It has a sense connection portion 131 projecting toward the back surface side conductor 123 side.
  • the sense connection portion 131 has a quadrangular prism shape and has a large cross-sectional area as compared with the bonding wire. The reason why the sense connection portion 131 has a large cross-sectional area is to secure the strength to withstand the load acting on the front surface side conductor 122 and the back surface side conductor 123 and to reduce the inductance.
  • the back surface side conductor 123 is a member corresponding to the back surface side conductor 23 of the first embodiment, but in the third embodiment, the four semiconductor elements 10 have a size of being bonded via the bonding layer 43.
  • the back surface side conductor 123 is provided with an insulating layer 151 on the entire surface excluding the region where the four semiconductor elements 10 are joined. Resin or ceramic can be used for the insulating layer 151.
  • a gate wiring 152 and a sense wiring 153 are provided on the insulating layer 151 formed on the back surface side conductor 123.
  • the gate wiring 152 and the sense wiring 153 are connected to a control unit (not shown).
  • the control unit applies a voltage to the source electrode 12 of the semiconductor element 10 via the gate wiring 152 with the connection of the semiconductor element 10 to the source electrode 12 via the sense wiring 153 as ground, that is, as a reference potential. ..
  • the reason for increasing the cross-sectional area of the sense connection portion 131 is to reduce the inductance, but to be precise, it is to reduce the inductance in the connection of the semiconductor element 10 with the source electrode 12 via the sense wiring 153. ..
  • the gate wiring 152 is placed on the insulating layer 151 provided on the back surface side conductor 123 between the two pairs of semiconductor elements 10 separated to the left and right, in other words, the back surface side conductor 123. It is formed so as to extend in the vertical direction of the back surface side conductor 123 at the center of the left side and the right side of the above.
  • the gate electrode 17 of each semiconductor element 10 is connected to the gate wiring 152 by a bonding wire 161.
  • the sense wiring 153 is formed so as to surround the outside of the gate wiring 152 with a slight gap from the gate wiring 152.
  • the sense wiring 153 extends in the vertical direction of the back surface side conductor 123 and extends along the upper side side surface and the lower side side surface of the back surface side conductor 123 to the vicinity of the corner portion of the back surface side conductor 123. Has a part.
  • the sense wiring 153 has a sense contact region 153a to which the lower end surface of the sense connection portion 131 of the surface side conductor 122 is joined in the vicinity of each corner portion.
  • the sense contact area 153a is a part of the sense wiring 153, and actually there is no partition line indicating the area. However, in FIG. 7, the sense contact area 153a is illustrated by a rectangular solid line for easy understanding. There is.
  • the surface-side conductor 122 is bonded to the source electrode 12 of each semiconductor element 10 by the bonding layer 42 (see FIGS. 8A and 8B). Therefore, the sense wiring 153 is connected to the source electrode 12 of each semiconductor element 10 via the surface side conductor 122.
  • the four semiconductor elements 10 are arranged close to each other, the heat emitted from each semiconductor element 10 is concentrated in a narrow region, and the back surface side conductor 123 becomes hot. Therefore, as shown in FIG. 7, the four semiconductor elements 10 are arranged so as to be separated from each other by a predetermined width or more so that heat is not concentrated. However, if the semiconductor elements 10 are arranged apart from each other by a predetermined width or more, the area of the back surface side conductor 123, in other words, the semiconductor device 300 becomes large. Therefore, by routing the gate wiring 152 and the sense wiring 153 in the central space where the semiconductor element 10 is separated, the space is effectively utilized and the area of the back surface side conductor 123 is reduced.
  • the sense contact region 153a to which the lower end surface of the sense connection portion 131 of the surface side conductor 122 is joined is outside the rectangular outer peripheral region in which the four semiconductor elements 10 are arranged. Is located in. Therefore, the inductance in the connection of the semiconductor element 10 with the source electrode 12 via the sense wiring 153 can be reduced.
  • the four semiconductor devices 300 constituting the semiconductor device 200 shown in FIG. 6 are arranged between the outer front surface side conductor 222 and the outer back surface side conductor 223.
  • the surface-side conductor 122 of each semiconductor device 300 is joined to the outer surface-side conductor 222 by a bonding layer 44.
  • the back surface side conductor 123 of each semiconductor device 300 is joined to the outer back surface side conductor 223 by the bonding layer 45.
  • the bonding layers 44 and 45 can be formed by using the same material as the bonding layers 41 to 43.
  • the state shown in FIG. 8A is a state in which the sealing resin 32 is not filled in the four semiconductor devices 300 constituting the semiconductor device 200. That is, each semiconductor element 10, the second insulating layer 31, and the like are not sealed by the sealing resin 32. However, on the first insulating layer 15 of each semiconductor element 10, a second insulating layer 31 is formed in contact with the peripheral edge of the bonding layer 41 and the peripheral region of the relay conductor 21 near the bonding layer 41 side. Therefore, in this state, a high electric field application test in which a high electric field is applied to the source electrode 12 can be performed. By applying a high electric field to the source electrode 12, it is inspected whether partial discharge is generated, the semiconductor element 10 is damaged, or the characteristics are deteriorated, and defective products are removed or repaired. can do. As a result, the productivity can be improved as compared with the inspection after the resin is sealed.
  • a sealing resin 32 is filled between the outer front surface side conductor 222 and the outer back surface side conductor 223, and the peripheral side surface of each semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 are filled. Is sealed with the sealing resin 32.
  • the high electric field application test may be performed in the state of FIG. 8 (b), may be performed in the state of FIG. 8 (a), and may be performed again in the state of FIG. 8 (b).
  • the sense wiring 153 and the source electrode 12 are exemplified as a structure in which the sense wiring 153 and the source electrode 12 are connected by a sense connection portion 131 integrally provided on the surface side conductor 122.
  • the sense wiring 153 and the source electrode 12 may be connected by a bonding wire.
  • the semiconductor device 300 is exemplified as a 4in1 package in which four arm circuits are integrated.
  • the semiconductor device 300 may be a package in which a plurality of arm circuits are integrated, and can be widely applied to an N (N ⁇ 2) in 1 package.
  • the switching element is exemplified as a MOS FET.
  • MOS FET Metal Organic Switches
  • IGBT Insulated Gate Bipolar Transistor
  • a SiC (silicon carbide) MOS FET is preferred as the switching element.
  • the present invention can be applied not only to silicon carbide but also to semiconductor devices using gallium nitride, gallium oxide, and diamond as a base material.
  • the present invention can also be applied to ordinary Si MOS FETs.

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Abstract

A semiconductor device 100 comprises: a semiconductor element 10 that includes a first insulating layer 15 having an opening 15a, and a source electrode 12 exposed from the opening 15a of the first insulating layer 15; a relay conductor 21 that is bonded to the source electrode 12; a bonding layer 41 that bonds the source electrode 12 to the relay conductor 21; a second insulating layer 31 that covers at least a portion of the first insulating layer 15 and is formed at least in contact with the periphery of the bonding layer 41; a front surface side conductor 22 that is connected to the relay conductor 21; and a sealing resin 32 that fills the space between the front surface side conductor 22 and the second insulating layer 31. Thus, the semiconductor device is provided in which occurrence of partial discharge is suppressed even if there are voids.

Description

半導体装置およびその製造方法Semiconductor devices and their manufacturing methods
　本発明は、半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the same.
　モータ等を駆動する電力変換部を有するパワー半導体装置として、パワー半導体素子を一対の金属板により挟んで、金属板間に樹脂を充填して半導体素子を封止する構造を有するものがある。より詳細には、半導体素子の一方の電極に金属ブロックを接合し、この金属ブロックを一方の金属板に接続し、半導体素子の他方の電極を他方の金属板に接続する。各金属板の面積は、半導体素子の表裏面の面積より大きく形成されており、この一対の金属板間に、トランスファーモールド法等のモールド法により、樹脂を充填して半導体素子を封止する（例えば、特許文献１参照）。 As a power semiconductor device having a power conversion unit for driving a motor or the like, there is a power semiconductor device having a structure in which a power semiconductor element is sandwiched between a pair of metal plates and a resin is filled between the metal plates to seal the semiconductor element. More specifically, a metal block is bonded to one electrode of the semiconductor element, the metal block is connected to one metal plate, and the other electrode of the semiconductor element is connected to the other metal plate. The area of each metal plate is formed larger than the area of the front and back surfaces of the semiconductor element, and a resin is filled between the pair of metal plates by a molding method such as a transfer molding method to seal the semiconductor element ( For example, see Patent Document 1).
特開２０１１－１１４１７６号公報Japanese Unexamined Patent Publication No. 2011-114176
　モールド法により形成する封止樹脂には、ボイド（空隙）等の欠陥部が生じ易い。パワー半導体装置では、パワー半導体素子に高電圧が印加されるため、封止樹脂にボイド等の欠陥部が存在すると、その欠陥部に電界が集中し、部分放電が発生する可能性がある。部分放電が発生した状態が続くと、封止樹脂が劣化し、最終的に絶縁破壊してパワー半導体装置が故障する虞がある。 The sealing resin formed by the molding method tends to have defects such as voids. In a power semiconductor device, a high voltage is applied to a power semiconductor element, so if a defect such as a void is present in the sealing resin, an electric field may be concentrated on the defect and a partial discharge may occur. If the state in which the partial discharge occurs continues, the sealing resin may deteriorate, and eventually dielectric breakdown may occur and the power semiconductor device may fail.
　本発明の第一の態様によると、半導体装置は、開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する半導体素子と、前記表面電極に接合された中継導体と、前記表面電極と前記中継導体とを接合する接合層と、前記第一絶縁層の少なくとも一部を覆い、少なくとも前記接合層の周囲に接して設けられた第二絶縁層と、前記中継導体に接続された導体と、前記導体と前記第二絶縁層との間に充填された封止樹脂と、を備える。
　本発明の第二の態様によると、半導体装置は、開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する複数の半導体素子と、前記各半導体素子の前記表面電極に接合された中継導体と、前記各表面電極と前記各中継導体を接合する接合層と、前記各第一絶縁層の少なくとも一部を覆い、少なくとも前記各接合層の周囲に接して設けられた第二絶縁層と、前記各中継導体を接続する導体と、を備える。
　本発明の第三の態様によると、半導体装置の製造方法は、開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する半導体素子を準備することと、前記表面電極と中継導体とを接合層により接合することと、前記第一絶縁層の少なくとも一部を覆い、少なくとも前記接合層の周囲に接する第二絶縁層を設けることと、前記中継導体に導体を接続することと、前記導体と前記第二絶縁層との間に封止樹脂を充填することと、を含む。 According to the first aspect of the present invention, the semiconductor device is bonded to the surface electrode with a first insulating layer having an opening and a semiconductor element having a surface electrode exposed from the opening of the first insulating layer. A relay conductor, a bonding layer for joining the surface electrode and the relay conductor, a second insulating layer that covers at least a part of the first insulating layer and is provided in contact with at least the periphery of the bonding layer, and the above. A conductor connected to a relay conductor and a sealing resin filled between the conductor and the second insulating layer are provided.
According to the second aspect of the present invention, the semiconductor device includes a plurality of semiconductor elements having a first insulating layer having an opening and a surface electrode exposed from the opening of the first insulating layer, and each of the semiconductor elements. It covers at least a part of the relay conductor bonded to the surface electrode, the bonding layer joining each surface electrode and the relay conductor, and each of the first insulating layers, and is in contact with at least the periphery of the bonding layer. A second insulating layer provided and a conductor connecting the respective relay conductors are provided.
According to the third aspect of the present invention, the method for manufacturing a semiconductor device is to prepare a first insulating layer having an opening and a semiconductor element having a surface electrode exposed from the opening of the first insulating layer. The surface electrode and the relay conductor are joined by a bonding layer, at least a part of the first insulating layer is covered, and at least a second insulating layer in contact with the periphery of the bonding layer is provided, and the relay conductor is provided with a conductor. Includes connecting the conductor and filling the sealing resin between the conductor and the second insulating layer.
　本発明によれば、ボイドが存在しても、部分放電の発生が抑制される。 According to the present invention, the occurrence of partial discharge is suppressed even in the presence of voids.
本発明の半導体装置の第１の実施形態の断面図。FIG. 3 is a sectional view of a first embodiment of the semiconductor device of the present invention. （Ａ）、（Ｂ）は、図１に図示された半導体装置１００の製造方法を説明するための各工程における半導体装置の断面図。(A) and (B) are sectional views of the semiconductor device in each step for explaining the manufacturing method of the semiconductor device 100 illustrated in FIG. （Ａ）、（Ｂ）は、図２に続く各工程における半導体装置の断面図。(A) and (B) are cross-sectional views of the semiconductor device in each step following FIG. 本発明の半導体装置の第２の実施形態の断面図。FIG. 5 is a cross-sectional view of a second embodiment of the semiconductor device of the present invention. 封止樹脂に存在するボイドに高電界が印加され、部分放電が発生する作用を説明するための断面図であり、（Ａ）は、比較例の半導体装置１００Ｒの断面図、（Ｂ）は、本実施形態の半導体装置の断面図。It is sectional drawing for demonstrating the action which a high electric field is applied to the void existing in a sealing resin, and partial discharge is generated, (A) is sectional drawing of the semiconductor device 100R of a comparative example, (B) is Sectional drawing of the semiconductor device of this embodiment. 本発明の半導体装置の第３の実施形態の分解斜視図。An exploded perspective view of a third embodiment of the semiconductor device of the present invention. 図６に図示された半導体装置の拡大分解斜視図。An enlarged exploded perspective view of the semiconductor device shown in FIG. 図６に図示された半導体装置の断面図であり、（Ａ）は樹脂封止前の断面図、（Ｂ）は、樹脂封止後の断面図。6 is a cross-sectional view of the semiconductor device shown in FIG. 6, where FIG. 6A is a cross-sectional view before resin sealing, and FIG. 6B is a cross-sectional view after resin sealing.
　以下、図面を参照して本発明の実施形態を説明する。以下の記載および図面は、本発明を説明するための例示であって、説明の明確化のため、適宜、省略および簡略化がなされている。本発明は、他の種々の形態でも実施する事が可能である。特に限定しない限り、各構成要素は単数でも複数でも構わない。
　図面において示す各構成要素の位置、大きさ、形状、範囲などは、発明の理解を容易にするため、実際の位置、大きさ、形状、範囲などを表していない場合がある。このため、本発明は、必ずしも、図面に開示された位置、大きさ、形状、範囲などに限定されない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and are appropriately omitted and simplified for clarification of the description. The present invention can also be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.
The position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc., in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the position, size, shape, range and the like disclosed in the drawings.
－第１の実施形態－
　以下、図１～図３を参照して、本発明の第１の実施形態を説明する。
　図１は、本発明の半導体装置の第１の実施形態の断面図である。
　半導体装置１００は、半導体素子１０を備えている。半導体素子１０は、例えば、ＳｉＣ（シリコンカーバイト）ＭＯＳ　ＦＥＴ（Metal-Oxide-Semiconductor　Field effecttransistor）である。半導体素子１０は、半導体基板１１と、ソース電極１２と、ドレイン電極１３と、内部配線１４と、第一絶縁層１５を有する。なお、図１には、図示しないが、半導体素子１０は、ゲート電極１７（図７参照）を有する。半導体装置１００は、半導体素子１０と、中継導体２１と、表面側導体２２と、裏面側導体２３と、第二絶縁層３１と、封止樹脂３２を有する。 -First Embodiment-
Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 3.
FIG. 1 is a cross-sectional view of a first embodiment of the semiconductor device of the present invention.
The semiconductor device 100 includes a semiconductor element 10. The semiconductor element 10 is, for example, a SiC (silicon carbide) MOS FET (Metal-Oxide-Semiconductor Field effect transistor). The semiconductor element 10 has a semiconductor substrate 11, a source electrode 12, a drain electrode 13, an internal wiring 14, and a first insulating layer 15. Although not shown in FIG. 1, the semiconductor element 10 has a gate electrode 17 (see FIG. 7). The semiconductor device 100 includes a semiconductor element 10, a relay conductor 21, a front surface side conductor 22, a back surface side conductor 23, a second insulating layer 31, and a sealing resin 32.
　第一絶縁層１５は、半導体基板１１内部に形成された半導体素子形成用の不純物領域および内部配線１４を保護するために設けられた絶縁膜であり、酸化シリコンまたは窒化シリコン等の無機材料により形成されている。第一絶縁層１５には、開口部１５ａ（図２（Ｂ）も参照）が設けられている。ソース電極１２は、第一絶縁層１５の開口部１５ａより少し大きく形成されており、ソース電極１２の周縁部の内側が第一絶縁層１５の開口部１５ａから露出している。第一絶縁層１５は、例えば、ポリイミドまたはポリベンゾオキサドール等の樹脂により形成される。第一絶縁層１５は、半導体素子メーカーにより形成されており、その厚さは、一般的に、数μｍ程度とされている。 The first insulating layer 15 is an insulating film provided inside the semiconductor substrate 11 to protect the impurity region for forming the semiconductor element and the internal wiring 14, and is formed of an inorganic material such as silicon oxide or silicon nitride. Has been done. The first insulating layer 15 is provided with an opening 15a (see also FIG. 2B). The source electrode 12 is formed slightly larger than the opening 15a of the first insulating layer 15, and the inside of the peripheral edge of the source electrode 12 is exposed from the opening 15a of the first insulating layer 15. The first insulating layer 15 is formed of, for example, a resin such as polyimide or polybenzoxador. The first insulating layer 15 is formed by a semiconductor device manufacturer, and its thickness is generally about several μm.
　中継導体２１は、第一絶縁層１５の開口部１５ａより少し小さい面積を有し、接合層４１により、ソース電極１２の、第一絶縁層１５の開口部１５ａから露出した部分の全面に接合されている。接合層４１は、中継導体２１とほぼ同じ面積を有する。従って、接合層４１の周縁部と第一絶縁層１５の開口部１５ａの周縁部との間には隙間Ｇ（図２（Ｂ）参照）が形成されている。中継導体２１は、銅系金属により形成することができる。また、中継導体２１は、ＣＩＣ（Copper Invar Copper）等のクラッド材を用いて形成することができる。インバー（登録商標）は、鉄とニッケルの合金であり、低熱膨張率の材料であるので、インバーを含む材料により中継導体２１を形成することにより、駆動時に半導体素子１０が高温となっても、封止樹脂３２との剥離を抑制することができる。 The relay conductor 21 has an area slightly smaller than the opening 15a of the first insulating layer 15, and is joined to the entire surface of the source electrode 12 exposed from the opening 15a of the first insulating layer 15 by the bonding layer 41. ing. The bonding layer 41 has substantially the same area as the relay conductor 21. Therefore, a gap G (see FIG. 2B) is formed between the peripheral edge of the bonding layer 41 and the peripheral edge of the opening 15a of the first insulating layer 15. The relay conductor 21 can be formed of a copper-based metal. Further, the relay conductor 21 can be formed by using a clad material such as CIC (Copper Invar Copper). Invar (registered trademark) is an alloy of iron and nickel and is a material with a low coefficient of thermal expansion. Therefore, by forming the relay conductor 21 from a material containing Invar, even if the semiconductor element 10 becomes hot during driving, It is possible to suppress peeling from the sealing resin 32.
　第二絶縁層３１は、第一絶縁層１５上に形成されている。第二絶縁層３１は、第一絶縁層１５の全面には形成されておらず、第一絶縁層１５の周縁部側は、第二絶縁層３１から露出している。第二絶縁層３１は、接合層４１の周縁部と第一絶縁層１５の開口部１５ａの周縁部との間の隙間Ｇ内にも充填されており、接合層４１の周縁部および中継導体２１の接合層４１側近傍領域の周縁部に接している。第二絶縁層３１は、後述するように、ポッティング法または印刷法等を用いた塗布により形成される。第二絶縁層３１は、例えば、ポリアミドイミド、ポリイミド、ポリエーテルアミドイミド、ポリエーテルアミド等の樹脂で形成される。第一絶縁層１５と第二絶縁層３１を、同じ樹脂により形成してもよい。第二絶縁層３１は、数十μｍ程度であり、第一絶縁層１５の厚さより厚くすることが好ましい。 The second insulating layer 31 is formed on the first insulating layer 15. The second insulating layer 31 is not formed on the entire surface of the first insulating layer 15, and the peripheral edge side of the first insulating layer 15 is exposed from the second insulating layer 31. The second insulating layer 31 is also filled in the gap G between the peripheral edge of the bonding layer 41 and the peripheral edge of the opening 15a of the first insulating layer 15, and the peripheral edge of the bonding layer 41 and the relay conductor 21 are also filled. It is in contact with the peripheral edge of the region near the joint layer 41 side of the above. As will be described later, the second insulating layer 31 is formed by coating using a potting method, a printing method, or the like. The second insulating layer 31 is formed of, for example, a resin such as polyamideimide, polyimide, polyetheramideimide, or polyetheramide. The first insulating layer 15 and the second insulating layer 31 may be formed of the same resin. The second insulating layer 31 is about several tens of μm, and is preferably thicker than the thickness of the first insulating layer 15.
　表面側導体２２は、半導体素子１０の表面面積、すなわち、第一絶縁層１５の平面視での面積よりも大きい面積を有する。表面側導体２２は、接合層４２により中継導体２１に接合されている。接合層４２は、中継導体２１とほぼ同じ面積を有する。表面側導体２２は、銅系金属またはアルミニウム系金属により形成することができる。 The surface-side conductor 22 has a surface area of the semiconductor element 10, that is, an area larger than the area of the first insulating layer 15 in a plan view. The surface side conductor 22 is joined to the relay conductor 21 by the joining layer 42. The bonding layer 42 has substantially the same area as the relay conductor 21. The surface side conductor 22 can be formed of a copper-based metal or an aluminum-based metal.
　裏面側導体２３は、接合層４３により、半導体基板１１のソース電極１２と対向する裏面側に設けられたドレイン電極１３に接合されている。裏面側導体２３は、表面側導体２２と同じ面積を有する。封止樹脂３２は、表面側導体２２と裏面側導体２３との間に充填されている。つまり、半導体素子１０の周側面、第二絶縁層３１、中継導体２１の周側面は、封止樹脂３２により封止されている。裏面側導体２３は、銅系金属またはアルミニウム系金属により形成することができる。 The back surface side conductor 23 is bonded to the drain electrode 13 provided on the back surface side facing the source electrode 12 of the semiconductor substrate 11 by the bonding layer 43. The back surface side conductor 23 has the same area as the front surface side conductor 22. The sealing resin 32 is filled between the front surface side conductor 22 and the back surface side conductor 23. That is, the peripheral side surface of the semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 are sealed with the sealing resin 32. The back surface side conductor 23 can be formed of a copper-based metal or an aluminum-based metal.
　接合層４１～４３として、はんだや焼結金属材料を用いることができる。
　封止樹脂３２としては、エポキシ樹脂等を用いることができる。封止樹脂３２による封止は、トランスファーモールド等のモールド法等が適しているが、ポッティング法や、シルク印刷、シーリング印刷、インクジェット印刷、熱転写印刷等の印刷法を用いてもよい。
　次に、上記実施形態の半導体装置１００における、ボイドの存在に伴う封止樹脂の劣化抑制作用について説明する。 Solder or sintered metal material can be used as the bonding layers 41 to 43.
As the sealing resin 32, an epoxy resin or the like can be used. For sealing with the sealing resin 32, a molding method such as transfer molding is suitable, but a printing method such as a potting method, silk printing, sealing printing, inkjet printing, thermal transfer printing or the like may be used.
Next, the effect of suppressing deterioration of the sealing resin due to the presence of voids in the semiconductor device 100 of the above embodiment will be described.
　図５は、封止樹脂に存在するボイドに高電界が印加され、部分放電が発生する作用を説明するための断面図である。図５（Ａ）は、比較例の半導体装置１００Ｒの封止樹脂に発生するボイドを示す断面図であり、図５（Ｂ）は、本実施形態の半導体装置１００の封止樹脂に発生するボイドを示す断面図である。
　図５（Ａ）に図示される比較例の半導体装置１００Ｒは、本実施形態の半導体装置１００の中継導体２１を有していない。
　半導体装置１００Ｒでは、表面側導体２２Ｒは、ソース電極１２の、第一絶縁層１５の開口部１５ａから露出した部分に対向する突出部２５を有している。突出部２５は、表面側導体２２Ｒと一体成形されている。すなわち、突出部２５とソース電極１２とを接合層４１により接合した後では、第一絶縁層１５の開口部１５ａの内周縁部と接合層４１との間の隙間Ｇの周辺領域は、封止樹脂３２を介して表面側導体２２Ｒにより覆われている。 FIG. 5 is a cross-sectional view for explaining the action of applying a high electric field to the voids existing in the sealing resin to generate a partial discharge. FIG. 5A is a cross-sectional view showing a void generated in the sealing resin of the semiconductor device 100R of the comparative example, and FIG. 5B is a void generated in the sealing resin of the semiconductor device 100 of the present embodiment. It is sectional drawing which shows.
The semiconductor device 100R of the comparative example shown in FIG. 5A does not have the relay conductor 21 of the semiconductor device 100 of the present embodiment.
In the semiconductor device 100R, the surface-side conductor 22R has a protruding portion 25 facing the portion of the source electrode 12 exposed from the opening 15a of the first insulating layer 15. The protruding portion 25 is integrally molded with the surface side conductor 22R. That is, after the protruding portion 25 and the source electrode 12 are joined by the joining layer 41, the peripheral region of the gap G between the inner peripheral edge portion of the opening 15a of the first insulating layer 15 and the joining layer 41 is sealed. It is covered with the surface side conductor 22R via the resin 32.
　このため、表面側導体２２Ｒと裏面側導体２３との間に封止樹脂３２を充填する前に、第一絶縁層１５上に第二絶縁層３１Ｒを塗布する場合、表面側導体２２Ｒが邪魔になり、第二絶縁層３１Ｒを接合層４１の周縁部や突出部２５の周縁部に接するように形成することは困難である。つまり、第一絶縁層１５の開口部１５ａの内周縁部と接合層４１との間の隙間Ｇは、第一絶縁層１５によっても、第二絶縁層３１Ｒによっても覆われない状態となる。
　なお、図５（Ａ）において、表面側導体２２Ｒをソース電極１２に接合する前に第２絶縁層３１Ｒを充填する場合、ソース電極１２の表面側導体２２Ｒを接合する領域（表面側導体接合領域に第２絶縁層３１Ｒ）が侵入しないようにする工程が必要である。また、この工程では、ソース電極１２の表面側導体接合領域と第１絶縁層１５の開口１５ａの内周縁部との間に僅かな隙間Ｇを設ける必要があり、この僅かな隙間Ｇに絶縁材が十分に充填できず、ボイドＡＶの高電界による封止樹脂劣化は避けられない。 Therefore, when the second insulating layer 31R is applied on the first insulating layer 15 before the sealing resin 32 is filled between the front surface side conductor 22R and the back surface side conductor 23, the front surface side conductor 22R becomes an obstacle. Therefore, it is difficult to form the second insulating layer 31R so as to be in contact with the peripheral edge of the bonding layer 41 or the peripheral edge of the protruding portion 25. That is, the gap G between the inner peripheral edge of the opening 15a of the first insulating layer 15 and the bonding layer 41 is not covered by the first insulating layer 15 or the second insulating layer 31R.
In FIG. 5A, when the second insulating layer 31R is filled before the surface side conductor 22R is joined to the source electrode 12, the region where the surface side conductor 22R of the source electrode 12 is joined (surface side conductor joining region). A step is required to prevent the second insulating layer 31R) from invading the surface. Further, in this step, it is necessary to provide a slight gap G between the surface side conductor bonding region of the source electrode 12 and the inner peripheral edge portion of the opening 15a of the first insulating layer 15, and the insulating material is provided in this slight gap G. can not be sufficiently filled, the sealing resin degradation due to a high electric field of voids a V can not be avoided.
　ＭＯＳ　ＦＥＴ等では、ソース電極１２周辺部には高電界が発生する。特に、ＳｉＣ　ＭＯＳ　ＦＥＴでは、Ｓｉ　ＭＯＳＦＥＴの１０倍程度の絶縁破壊電界強度の高電界が生じる。ソース電極１２周辺の封止樹脂３２にボイドＡＶが存在すると、ボイドＡＶに高電界が集中し、部分放電が発生する可能性がある。部分放電が発生した状態が続くと、封止樹脂３２が劣化し、最終的に絶縁破壊して半導体素子１０が故障する。
　特に、突出部２５がソース電極１２に接合されているような狭い空間には、モールド法による封止樹脂は充填され難く、ボイドＡＶが発生する確率が高い。 In MOS FETs and the like, a high electric field is generated around the source electrode 12. In particular, a SiC MOS FET produces a high electric field with a dielectric breakdown electric field strength about 10 times that of a Si MOSFET. When voids A V is present in the sealing resin 32 near the source electrode 12, a high electric field is concentrated on the void A V, partial discharge may occur. If the state in which the partial discharge occurs continues, the sealing resin 32 deteriorates, and finally dielectric breakdown occurs and the semiconductor element 10 fails.
In particular, in a narrow space such as the protruding portion 25 is bonded to the source electrode 12, a sealing resin by molding method is difficult to fill, there is a high probability that voids A V occurs.
　本実施形態の半導体装置１００は、図５（Ｂ）に図示するように、ソース電極１２と表面側導体２２との間に設けられた中継導体２１を有している。このため、接合層４１により、ソース電極１２に中継導体２１を接合した状態で、表面側導体２２を中継導体２１に接合する前に、第二絶縁層３１を、第一絶縁層１５の周縁部と接合層４１との間の隙間Ｇ内に充填することができる。第二絶縁層３１により第一絶縁層１５の周縁部と接合層４１との間の隙間Ｇが覆われた状態で封止樹脂３２にボイドＡＶが存在すると、ソース電極１２周辺部に発生する高電界は、ボイドＡＶに印加される電圧と第二絶縁層３１に印加される電圧とに分圧される。 As shown in FIG. 5B, the semiconductor device 100 of the present embodiment has a relay conductor 21 provided between the source electrode 12 and the surface side conductor 22. Therefore, in a state where the relay conductor 21 is bonded to the source electrode 12 by the bonding layer 41, the second insulating layer 31 is attached to the peripheral portion of the first insulating layer 15 before the surface side conductor 22 is bonded to the relay conductor 21. It can be filled in the gap G between the bonding layer 41 and the bonding layer 41. When voids A V is present in the second insulating layer 31 by a sealing resin 32 in a state where the gap G is covered between the peripheral edge portion of the first insulating layer 15 and the bonding layer 41, generated in the source electrode 12 periphery a high electric field is divided voltage and half to be applied to the voltage and the second insulating layer 31 applied to the void a V.
　空気層であるボイドＡＶに加わる電圧は、空気層の誘電率に対する第二絶縁層３１の比誘電率、およびボイドＡＶの厚さと第二絶縁層３１の厚さとの比に関連する。第二絶縁層３１の厚さが大きくなり、ボイドＡＶの厚さが小さくなると、ボイドＡＶに集中する電圧が小さくなる。このため、第二絶縁層３１の厚さを所定の厚さ以上とすることにより、ボイドＡＶに加わる電圧を部分放電開始電圧より小さくすることができる。従って、第二絶縁層３１を所定の厚さ以上とすれば、この後、接合層４２により中継導体２１に表面側導体２２を接合し、表面側導体２２と裏面側導体２３間に封止樹脂３２を充填した場合、封止樹脂３２にボイドＡＶが発生しても、部分放電が発生するのを抑制することができる。
　次に、半導体装置１００の製造方法を説明する。 Voltage applied to the voids A V is the air layer is related to the ratio of the dielectric constant of the second insulating layer 31 for dielectric constant, and the void A V thickness and the second insulating layer 31 thickness of the air layer. The thickness increases in the second insulating layer 31, the thickness of the void A V decreases, the voltage to focus the void A V decreases. Therefore, by setting the thickness of the second insulating layer 31 to a predetermined thickness or more, the voltage applied to the void A V can be smaller than the partial discharge inception voltage. Therefore, if the second insulating layer 31 has a predetermined thickness or more, then the front side conductor 22 is joined to the relay conductor 21 by the joining layer 42, and the sealing resin is formed between the front side conductor 22 and the back side conductor 23. If 32 filled with, be void a V is generated in the sealing resin 32, it is possible to suppress the partial discharge occurs.
Next, a method of manufacturing the semiconductor device 100 will be described.
　図２（Ａ）、図２（Ｂ）は、図１に図示された半導体装置１００の製造方法を説明するための各工程における半導体装置の断面図であり、図３（Ａ）、図３（Ｂ）は、図２に続く各工程における半導体装置の断面図である。
　先ず、半導体素子１０を準備する。　上述したように、半導体素子１０は、半導体基板１１と、ソース電極１２と、ドレイン電極１３と、内部配線１４と、第一絶縁層１５とを有する。
　そして、図２（Ａ）に図示するように、半導体素子１０のドレイン電極１３と裏面側導体２３とを接合層４３により接合する。接合層４３として、上述したように、はんだ、または焼結金属材料を用いることができる。焼結金属材料は、粉末やペースト状を有しており、加熱により焼結金属となる。焼結金属材料としては、銅や銀を含む焼結金属接合ペーストを用いることが好ましい。半導体素子１０のドレイン電極１３と裏面側導体２３との間に接合層４３を介在させ、熱圧着することにより接合する。 2 (A) and 2 (B) are cross-sectional views of the semiconductor device in each step for explaining the manufacturing method of the semiconductor device 100 illustrated in FIG. 1, and FIGS. 3 (A) and 3 (B). B) is a cross-sectional view of the semiconductor device in each step following FIG.
First, the semiconductor element 10 is prepared. As described above, the semiconductor element 10 has a semiconductor substrate 11, a source electrode 12, a drain electrode 13, an internal wiring 14, and a first insulating layer 15.
Then, as shown in FIG. 2A, the drain electrode 13 of the semiconductor element 10 and the back surface side conductor 23 are joined by the joining layer 43. As the bonding layer 43, as described above, solder or a sintered metal material can be used. The sintered metal material has a powder or paste form, and becomes a sintered metal by heating. As the sintered metal material, it is preferable to use a sintered metal bonding paste containing copper or silver. A bonding layer 43 is interposed between the drain electrode 13 of the semiconductor element 10 and the back surface side conductor 23, and the bonding is performed by thermocompression bonding.
　次に、図２（Ｂ）に図示するように、半導体素子１０のソース電極１２と中継導体２１とを接合層４１により接合する。接合層４１として、接合層４３と同様なものを用いる。
半導体素子１０のソース電極１２と中継導体２１との間に接合層４１を介在させ、熱圧着することにより接合する。半導体素子１０のソース電極１２と中継導体２１とを接合する接合層４１は、半導体素子１０の第一絶縁層１５の開口部１５ａ内に設けられる。つまり、接合層４１は、半導体素子１０の第一絶縁層１５の開口部１５ａより小さい。このため、第一絶縁層１５の周縁部と接合層４１との間には、隙間Ｇが形成される。 Next, as shown in FIG. 2B, the source electrode 12 of the semiconductor element 10 and the relay conductor 21 are joined by the joining layer 41. As the bonding layer 41, the same layer as the bonding layer 43 is used.
A bonding layer 41 is interposed between the source electrode 12 of the semiconductor element 10 and the relay conductor 21 and bonded by thermocompression bonding. The bonding layer 41 that joins the source electrode 12 of the semiconductor element 10 and the relay conductor 21 is provided in the opening 15a of the first insulating layer 15 of the semiconductor element 10. That is, the bonding layer 41 is smaller than the opening 15a of the first insulating layer 15 of the semiconductor element 10. Therefore, a gap G is formed between the peripheral edge of the first insulating layer 15 and the bonding layer 41.
　図２（Ａ）の工程と、図２（Ｂ）の工程とは、逆の手順としてもよい。また、同一行程で行ってもよい。同一工程で行う場合は、半導体素子１０のドレイン電極１３と裏面側導体２３とを接合層４３を介在させるとともに、半導体素子１０のソース電極１２と中継導体２１との間に接合層４１を介在させ、この状態で、全体を熱圧着する。 The process of FIG. 2 (A) and the process of FIG. 2 (B) may be reversed. Moreover, you may carry out in the same process. When the same process is performed, the drain electrode 13 of the semiconductor element 10 and the back surface side conductor 23 are interposed with the bonding layer 43, and the bonding layer 41 is interposed between the source electrode 12 of the semiconductor element 10 and the relay conductor 21. , In this state, the whole is thermocompression bonded.
　次に、図３（Ａ）に図示するように、第一絶縁層１５上に、第二絶縁層３１を塗布する。第二絶縁層３１は、接合層４１の周縁部と第一絶縁層１５の開口部１５ａの周縁部との間の隙間Ｇ（図２（Ｂ）参照）内に、接合層４１の周縁部に接するように充填される。第二絶縁層３１は、中継導体２１の下端部側、換言すれば、接合層４１側の周縁部に接するように設けてもよい。第二絶縁層３１の形成には、ディスペンサーを用いるポィッテング法、または印刷法を用いることができる。印刷法として、シルク印刷、シーリング印刷、インクジェット印刷、熱転写印刷等を適用することができる。 Next, as shown in FIG. 3A, the second insulating layer 31 is applied on the first insulating layer 15. The second insulating layer 31 is formed in the peripheral edge of the bonding layer 41 in the gap G (see FIG. 2B) between the peripheral edge of the bonding layer 41 and the peripheral edge of the opening 15a of the first insulating layer 15. Filled to touch. The second insulating layer 31 may be provided so as to be in contact with the lower end portion side of the relay conductor 21, in other words, the peripheral edge portion on the bonding layer 41 side. A potting method using a dispenser or a printing method can be used for forming the second insulating layer 31. As a printing method, silk printing, sealing printing, inkjet printing, thermal transfer printing and the like can be applied.
　次に、図３（Ｂ）に図示するように、接合層４２により、中継導体２１に表面側導体２２を接合する。接合層４２として、接合層４１、４３と同様なものを用いる。中継導体２１と表面側導体２２との間に接合層４２を介在させ、熱圧着することにより接合する。 Next, as shown in FIG. 3B, the surface side conductor 22 is joined to the relay conductor 21 by the joining layer 42. As the bonding layer 42, the same layer as the bonding layers 41 and 43 is used. A bonding layer 42 is interposed between the relay conductor 21 and the surface side conductor 22 and bonded by thermocompression bonding.
　この後、表面側導体２２と裏面側導体２３との間に封止樹脂３２を充填する。これにより、半導体素子１０の周側面、第二絶縁層３１、中継導体２１の周側面が、封止樹脂３２により封止された図１に図示される半導体装置１００が形成される。封止樹脂３２の形成は、上述したように、トランスファーモールド法が適しているが、ポッティング法や印刷法を用いてもよい。 After that, the sealing resin 32 is filled between the front surface side conductor 22 and the back surface side conductor 23. As a result, the semiconductor device 100 shown in FIG. 1 is formed in which the peripheral side surface of the semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 are sealed with the sealing resin 32. As described above, the transfer molding method is suitable for forming the sealing resin 32, but a potting method or a printing method may also be used.
　上記第１の実施形態によれば下記の効果を奏する。
（１）半導体装置１００は、開口部１５ａを有する第一絶縁層１５および第一絶縁層１５の開口部１５ａから露出するソース電極（表面電極）１２を有する半導体素子１０と、ソース電極１２に接合された中継導体２１と、ソース電極１２と中継導体２１とを接合する接合層４１と、第一絶縁層１５の少なくとも一部を覆い、少なくとも接合層４１の周囲に接して設けられた第二絶縁層３１と、中継導体２１に接続された表面側導体（導体）２２と、表面側導体２２と第二絶縁層３１との間に充填された封止樹脂３２と、を備える。このように、第一絶縁層１５の開口部１５ａから露出するソース電極１２は、接合層４１の周囲に接して設けられた第二絶縁層３１により覆われている。このため、封止樹脂３２にボイドＡＶが存在しても、部分放電の発生が抑制され、封止樹脂３２の劣化を抑制することができる。 According to the first embodiment, the following effects are obtained.
(1) The semiconductor device 100 is joined to a semiconductor element 10 having a first insulating layer 15 having an opening 15a and a source electrode (surface electrode) 12 exposed from the opening 15a of the first insulating layer 15 and the source electrode 12. The second insulation is provided so as to cover at least a part of the first insulating layer 15 and the joint layer 41 that joins the relay conductor 21 and the source electrode 12 and the relay conductor 21 so as to be in contact with at least the periphery of the joint layer 41. The layer 31 includes a surface-side conductor (conductor) 22 connected to the relay conductor 21, and a sealing resin 32 filled between the surface-side conductor 22 and the second insulating layer 31. As described above, the source electrode 12 exposed from the opening 15a of the first insulating layer 15 is covered with the second insulating layer 31 provided in contact with the periphery of the bonding layer 41. Therefore, even if there is a void A V in the sealing resin 32, the occurrence of partial discharge can be suppressed, it is possible to suppress the deterioration of the sealing resin 32.
－第２の実施形態－
　図４は、本発明の半導体装置の第２の実施形態の断面図である。
　第２の実施形態の半導体装置１００は、第二絶縁層３１ａが、半導体素子１０の外周側面に延在され、裏面側導体２３に接する構造を有する。
　第１の実施形態では、第二絶縁層３１は、半導体素子１０の表面側にのみに形成されており、裏面側導体２３に接するように延在されているものではなかった。このような構造では、接合層４２により、中継導体２１に表面側導体２２を接合する際、熱圧着時の加熱により接合層４１が溶融し、中継導体２１が位置ずれを起こす可能性がある。第二の実施形態では、第二絶縁層３１ａが裏面側導体２３に接する位置まで延在されている。第二絶縁層３１ａは中継導体２１に接しているので、熱圧着時の加熱により接合層４１が溶融しても、中継導体２１の移動は、裏面側導体２３に接する第二絶縁層３１ａにより規制される。 -Second embodiment-
FIG. 4 is a cross-sectional view of a second embodiment of the semiconductor device of the present invention.
The semiconductor device 100 of the second embodiment has a structure in which the second insulating layer 31a extends on the outer peripheral side surface of the semiconductor element 10 and is in contact with the back surface side conductor 23.
In the first embodiment, the second insulating layer 31 is formed only on the front surface side of the semiconductor element 10, and is not extended so as to be in contact with the back surface side conductor 23. In such a structure, when the surface side conductor 22 is joined to the relay conductor 21 by the joining layer 42, the joining layer 41 may be melted by heating during thermocompression bonding, and the relay conductor 21 may be misaligned. In the second embodiment, the second insulating layer 31a extends to a position where it contacts the back surface side conductor 23. Since the second insulating layer 31a is in contact with the relay conductor 21, even if the bonding layer 41 is melted by heating during thermocompression bonding, the movement of the relay conductor 21 is restricted by the second insulating layer 31a in contact with the back surface side conductor 23. Will be done.
　第２の実施形態の他の構成は、第１の実施形態と同様であり、対応する構成に同一の符号を付して説明を省略する。
　第２の実施形態においても、第１の実施形態と同様な効果を奏する。
　また、第２の実施形態によれば、中継導体２１に表面側導体２２を接合する際の中継導体２１の位置ずれを抑制することができる。 The other configurations of the second embodiment are the same as those of the first embodiment, and the corresponding configurations are designated by the same reference numerals and the description thereof will be omitted.
The second embodiment also has the same effect as that of the first embodiment.
Further, according to the second embodiment, it is possible to suppress the misalignment of the relay conductor 21 when the surface side conductor 22 is joined to the relay conductor 21.
－第３の実施形態－
　図６～図８を参照して、本発明の第３の実施形態を説明する。
　図６は、本発明の半導体装置の第３の実施形態の分解斜視図である。
　半導体装置２００は、４つの半導体装置３００と、外側表面側導体２２２と、外側裏面側導体２２３とを備える。４つの半導体装置３００は、相互に離間して、左右方向に２行、上下方向に２列、マトリクス状に配列されている。外側表面側導体２２２と外側裏面側導体２２３は、それぞれ、マトリクス状に配列された４つの半導体装置３００の全領域を覆う大きさを有する。４つの半導体装置３００は、いずれも同一の構造を有する。
　２つの半導体装置３００は、それぞれ、上アーム回路を有し、残りの２つの半導体装置３００は、それぞれ、下アーム回路を有する。また、上アーム回路を有する半導体装置３００と下アーム回路を有する半導体装置３００は、直列に接続され、上下アーム直列回路を構成する。上アーム回路と下アーム回路の接続部から、位相の異なる交流出力が得られる電力変換装置を構成することができる。 -Third embodiment-
A third embodiment of the present invention will be described with reference to FIGS. 6 to 8.
FIG. 6 is an exploded perspective view of a third embodiment of the semiconductor device of the present invention.
The semiconductor device 200 includes four semiconductor devices 300, an outer front surface side conductor 222, and an outer back surface side conductor 223. The four semiconductor devices 300 are arranged in a matrix with two rows in the horizontal direction and two columns in the vertical direction, separated from each other. The outer front surface side conductor 222 and the outer back surface side conductor 223 each have a size that covers the entire region of the four semiconductor devices 300 arranged in a matrix. All four semiconductor devices 300 have the same structure.
The two semiconductor devices 300 each have an upper arm circuit, and the remaining two semiconductor devices 300 each have a lower arm circuit. Further, the semiconductor device 300 having the upper arm circuit and the semiconductor device 300 having the lower arm circuit are connected in series to form an upper and lower arm series circuit. A power conversion device capable of obtaining AC outputs having different phases can be configured from the connection portion between the upper arm circuit and the lower arm circuit.
　図７は、図６に図示された半導体装置の拡大分解斜視図であり、図８は、図６に図示された半導体装置の断面図であり、図８（Ａ）は樹脂封止前の断面図、図８（Ｂ）は、樹脂封止後の断面図である。
　半導体装置３００は、４つの半導体素子１０と、表面側導体１２２と、裏面側導体１２３とを備えている。４つの半導体素子１０は、相互に離間して、左右方向に２行、上下方向に２列、マトリクス状に配列されている。すなわち、半導体装置３００は、４in１パッケージとして構成されている。表面側導体１２２と裏面側導体１２３は、それぞれ、マトリクス状に配列された４つの半導体素子１０の全領域を覆う大きさを有する。 7 is an enlarged exploded perspective view of the semiconductor device shown in FIG. 6, FIG. 8 is a cross-sectional view of the semiconductor device shown in FIG. 6, and FIG. 8 (A) is a cross section before resin sealing. FIG. 8 (B) is a cross-sectional view after resin sealing.
The semiconductor device 300 includes four semiconductor elements 10, a front surface side conductor 122, and a back surface side conductor 123. The four semiconductor elements 10 are arranged in a matrix with two rows in the horizontal direction and two columns in the vertical direction, separated from each other. That is, the semiconductor device 300 is configured as a 4in1 package. The front surface side conductor 122 and the back surface side conductor 123 each have a size that covers the entire region of the four semiconductor elements 10 arranged in a matrix.
　４つの半導体素子１０は、いずれも第１の実施形態の半導体素子と同一の構造を有する。すなわち、図８に図示されるように、半導体素子１０は、半導体基板１１と、ソース電極１２と、ドレイン電極１３と、内部配線１４と、第一絶縁層１５を有する。図８に図示されるように、各半導体素子１０のソース電極１２には接合層４１を介して中継導体２１が接合されている。また、各半導体素子１０の第一絶縁層１５上には、接合層４１の周縁部および中継導体２１の接合層４１側近傍領域周縁部に接する第二絶縁層３１が形成されている。 Each of the four semiconductor elements 10 has the same structure as the semiconductor element of the first embodiment. That is, as shown in FIG. 8, the semiconductor element 10 has a semiconductor substrate 11, a source electrode 12, a drain electrode 13, an internal wiring 14, and a first insulating layer 15. As shown in FIG. 8, a relay conductor 21 is bonded to the source electrode 12 of each semiconductor element 10 via a bonding layer 41. Further, on the first insulating layer 15 of each semiconductor element 10, a second insulating layer 31 is formed which is in contact with the peripheral edge of the bonding layer 41 and the peripheral region of the relay conductor 21 near the bonding layer 41 side.
　図７に図示されるように、表面側導体１２２は、４つの半導体素子１０を覆う矩形形状の本体と、この矩形形状の本体の４つのコーナー部のそれぞれから延在された脚部の先端に、裏面側導体１２３側に向けて突出するセンス接続部１３１とを有する。センス接続部１３１は、四角柱形状を有し、ボンディングワイヤに比し、大きな断面積を有する。センス接続部１３１が大きな断面積を有する理由は、表面側導体１２２と裏面側導体１２３に作用する負荷に耐えられる強度を確保するためと、インダクタンスを小さくするためである。 As illustrated in FIG. 7, the surface-side conductor 122 is attached to a rectangular body covering the four semiconductor elements 10 and to the tips of legs extending from each of the four corners of the rectangular body. It has a sense connection portion 131 projecting toward the back surface side conductor 123 side. The sense connection portion 131 has a quadrangular prism shape and has a large cross-sectional area as compared with the bonding wire. The reason why the sense connection portion 131 has a large cross-sectional area is to secure the strength to withstand the load acting on the front surface side conductor 122 and the back surface side conductor 123 and to reduce the inductance.
　裏面側導体１２３は、第１の実施形態の裏面側導体２３に対応する部材であるが、第３の実施形態では、４つの半導体素子１０が接合層４３を介して接合されるサイズを有する。裏面側導体１２３には、４つの半導体素子１０が接合される領域を除く全面に絶縁層１５１が設けられている。絶縁層１５１には、樹脂やセラミックを用いることができる。 The back surface side conductor 123 is a member corresponding to the back surface side conductor 23 of the first embodiment, but in the third embodiment, the four semiconductor elements 10 have a size of being bonded via the bonding layer 43. The back surface side conductor 123 is provided with an insulating layer 151 on the entire surface excluding the region where the four semiconductor elements 10 are joined. Resin or ceramic can be used for the insulating layer 151.
　裏面側導体１２３上に形成された絶縁層１５１上には、ゲート配線１５２およびセンス配線１５３が設けられている。ゲート配線１５２およびセンス配線１５３は、不図示の制御部に接続される。
　不図示の制御部は、センス配線１５３を介した半導体素子１０のソース電極１２との接続をグランド、すなわち、基準電位として、ゲート配線１５２を介して半導体素子１０のソース電極１２に電圧を印加する。センス接続部１３１の断面積を大きくする理由としてインダクタンスを小さくすることを挙げたが、正確には、センス配線１５３を介した半導体素子１０のソース電極１２との接続におけるインダクタンスを小さくするためである。 A gate wiring 152 and a sense wiring 153 are provided on the insulating layer 151 formed on the back surface side conductor 123. The gate wiring 152 and the sense wiring 153 are connected to a control unit (not shown).
The control unit (not shown) applies a voltage to the source electrode 12 of the semiconductor element 10 via the gate wiring 152 with the connection of the semiconductor element 10 to the source electrode 12 via the sense wiring 153 as ground, that is, as a reference potential. .. The reason for increasing the cross-sectional area of the sense connection portion 131 is to reduce the inductance, but to be precise, it is to reduce the inductance in the connection of the semiconductor element 10 with the source electrode 12 via the sense wiring 153. ..
　図７を参照して、ゲート配線１５２は、裏面側導体１２３上に設けられた絶縁層１５１上を、左右に分離された二対の半導体素子１０の間において、換言すれば、裏面側導体１２３の左辺と右辺の中央において、裏面側導体１２３の上下方向に延在して形成されている。各半導体素子１０のゲート電極１７は、ボンディングワイヤ１６１によりゲート配線１５２に接続されている。センス配線１５３は、ゲート配線１５２と僅かな隙間を開けてゲート配線１５２の外側を囲んで形成されている。センス配線１５３は、裏面側導体１２３の上下方向に延在された部分と、裏面側導体１２３の上辺側の側面および下辺側の側面に沿って裏面側導体１２３のコーナー部近傍まで延在された部分とを有する。 With reference to FIG. 7, the gate wiring 152 is placed on the insulating layer 151 provided on the back surface side conductor 123 between the two pairs of semiconductor elements 10 separated to the left and right, in other words, the back surface side conductor 123. It is formed so as to extend in the vertical direction of the back surface side conductor 123 at the center of the left side and the right side of the above. The gate electrode 17 of each semiconductor element 10 is connected to the gate wiring 152 by a bonding wire 161. The sense wiring 153 is formed so as to surround the outside of the gate wiring 152 with a slight gap from the gate wiring 152. The sense wiring 153 extends in the vertical direction of the back surface side conductor 123 and extends along the upper side side surface and the lower side side surface of the back surface side conductor 123 to the vicinity of the corner portion of the back surface side conductor 123. Has a part.
　センス配線１５３は、各コーナー部の近傍に、表面側導体１２２のセンス接続部１３１の下端面が接合されるセンス接触領域１５３ａを有する。センス接触領域１５３ａは、センス配線１５３の一部であり、実際には、領域を示す仕切り線はないが、図７では、判り易くするためにセンス接触領域１５３ａを矩形形状の実線により図示している。表面側導体１２２は、接合層４２（図８（ａ）、（ｂ）参照）により、各半導体素子１０のソース電極１２に接合される。従って、センス配線１５３は、表面側導体１２２を介して、各半導体素子１０のソース電極１２に接続される。 The sense wiring 153 has a sense contact region 153a to which the lower end surface of the sense connection portion 131 of the surface side conductor 122 is joined in the vicinity of each corner portion. The sense contact area 153a is a part of the sense wiring 153, and actually there is no partition line indicating the area. However, in FIG. 7, the sense contact area 153a is illustrated by a rectangular solid line for easy understanding. There is. The surface-side conductor 122 is bonded to the source electrode 12 of each semiconductor element 10 by the bonding layer 42 (see FIGS. 8A and 8B). Therefore, the sense wiring 153 is connected to the source electrode 12 of each semiconductor element 10 via the surface side conductor 122.
　４つの半導体素子１０を近接して配置すると、各半導体素子１０から放出される熱が狭い領域に集中し、裏面側導体１２３が高温となってしまう。このため、図７に示すように、４つの半導体素子１０を所定幅以上に離間して配置して、熱が集中しないようにしている。しかし、半導体素子１０を所定幅以上に離間して配置すると裏面側導体１２３、換言すれば、半導体装置３００の面積が大きくなる。そこで、半導体素子１０が離間された中央のスペースにゲート配線１５２とセンス配線１５３とを引き回すことにより、スペースの有効活用を図り、裏面側導体１２３の面積の縮小化を図っている。 When the four semiconductor elements 10 are arranged close to each other, the heat emitted from each semiconductor element 10 is concentrated in a narrow region, and the back surface side conductor 123 becomes hot. Therefore, as shown in FIG. 7, the four semiconductor elements 10 are arranged so as to be separated from each other by a predetermined width or more so that heat is not concentrated. However, if the semiconductor elements 10 are arranged apart from each other by a predetermined width or more, the area of the back surface side conductor 123, in other words, the semiconductor device 300 becomes large. Therefore, by routing the gate wiring 152 and the sense wiring 153 in the central space where the semiconductor element 10 is separated, the space is effectively utilized and the area of the back surface side conductor 123 is reduced.
　図７および図８に図示されるように、表面側導体１２２のセンス接続部１３１の下端面が接合されるセンス接触領域１５３ａは、４つの半導体素子１０が配列された、矩形の外周領域の外側に配置されている。このため、センス配線１５３を介した半導体素子１０のソース電極１２との接続におけるインダクタンスを小さくすることができる。 As shown in FIGS. 7 and 8, the sense contact region 153a to which the lower end surface of the sense connection portion 131 of the surface side conductor 122 is joined is outside the rectangular outer peripheral region in which the four semiconductor elements 10 are arranged. Is located in. Therefore, the inductance in the connection of the semiconductor element 10 with the source electrode 12 via the sense wiring 153 can be reduced.
　図６に図示される半導体装置２００を構成する４つの半導体装置３００は、図８（ａ）に図示されるように、外側表面側導体２２２と外側裏面側導体２２３の間に配置される。
　各半導体装置３００の表面側導体１２２は、接合層４４により、外側表面側導体２２２に接合されている。各半導体装置３００の裏面側導体１２３は、接合層４５により、外側裏面側導体２２３に接合されている。接合層４４、４５は、接合層４１～４３と同一の材料を用いて形成することができる。 As shown in FIG. 8A, the four semiconductor devices 300 constituting the semiconductor device 200 shown in FIG. 6 are arranged between the outer front surface side conductor 222 and the outer back surface side conductor 223.
The surface-side conductor 122 of each semiconductor device 300 is joined to the outer surface-side conductor 222 by a bonding layer 44. The back surface side conductor 123 of each semiconductor device 300 is joined to the outer back surface side conductor 223 by the bonding layer 45. The bonding layers 44 and 45 can be formed by using the same material as the bonding layers 41 to 43.
　図８（ａ）に図示された状態は、半導体装置２００を構成する４つの半導体装置３００に、封止樹脂３２が充填されていない状態である。つまり、各半導体素子１０および第二絶縁層３１等は、封止樹脂３２により封止されていない。しかし、各半導体素子１０の第一絶縁層１５上には、接合層４１の周縁部および中継導体２１の接合層４１側近傍領域周縁部に接する第二絶縁層３１が形成されている。このため、この状態で、ソース電極１２に高電界を印加する高電界印加試験を行うことができる。ソース電極１２に高電界を印加することで、部分放電が発生したり、半導体素子１０が損傷したり、特性が劣化したりするか否かを検査し、不良品を除去したり、修理したりすることができる。これにより、樹脂封止後に検査を行うよりも、生産性を向上することができる。 The state shown in FIG. 8A is a state in which the sealing resin 32 is not filled in the four semiconductor devices 300 constituting the semiconductor device 200. That is, each semiconductor element 10, the second insulating layer 31, and the like are not sealed by the sealing resin 32. However, on the first insulating layer 15 of each semiconductor element 10, a second insulating layer 31 is formed in contact with the peripheral edge of the bonding layer 41 and the peripheral region of the relay conductor 21 near the bonding layer 41 side. Therefore, in this state, a high electric field application test in which a high electric field is applied to the source electrode 12 can be performed. By applying a high electric field to the source electrode 12, it is inspected whether partial discharge is generated, the semiconductor element 10 is damaged, or the characteristics are deteriorated, and defective products are removed or repaired. can do. As a result, the productivity can be improved as compared with the inspection after the resin is sealed.
　高電界印加試験後、外側表面側導体２２２と外側裏面側導体２２３との間に、封止樹脂３２を充填し、各半導体素子１０の周側面、第二絶縁層３１、中継導体２１の周側面を、封止樹脂３２により封止する。これにより、図８（ｂ）に図示される半導体装置２００を形成することができる。
　高電界印加試験は、図８（ｂ）の状態で行ってもよいし、図８（ａ）の状態で行って、再度、図８(ｂ)の状態で行ってもよい。 After the high electric field application test, a sealing resin 32 is filled between the outer front surface side conductor 222 and the outer back surface side conductor 223, and the peripheral side surface of each semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 are filled. Is sealed with the sealing resin 32. As a result, the semiconductor device 200 shown in FIG. 8B can be formed.
The high electric field application test may be performed in the state of FIG. 8 (b), may be performed in the state of FIG. 8 (a), and may be performed again in the state of FIG. 8 (b).
　第３の実施形態では、センス配線１５３とソース電極１２とは、表面側導体１２２に一体的に設けたセンス接続部１３１により接続する構造として例示した。しかし、センス配線１５３とソース電極１２とは、ボンディングワイヤにより接続するようにしてもよい。 In the third embodiment, the sense wiring 153 and the source electrode 12 are exemplified as a structure in which the sense wiring 153 and the source electrode 12 are connected by a sense connection portion 131 integrally provided on the surface side conductor 122. However, the sense wiring 153 and the source electrode 12 may be connected by a bonding wire.
　第３の実施形態では、半導体装置３００は、４つのアーム回路が一体化された４in１パッケージとして例示した。しかし、半導体装置３００は、複数のアーム回路が一体化されたパッケージであればよく、Ｎ（Ｎ≧２）in１パッケージに幅広く適用することが可能である。 In the third embodiment, the semiconductor device 300 is exemplified as a 4in1 package in which four arm circuits are integrated. However, the semiconductor device 300 may be a package in which a plurality of arm circuits are integrated, and can be widely applied to an N (N ≧ 2) in 1 package.
　なお、上記各実施形態では、スイッチング用素子を、ＭＯＳ　ＦＥＴとして例示した。
しかし、ＭＯＳ　ＦＥＴに替えて、ＩＧＢＴ（Insulated Gate Bipolar Transistor）等の他の半導体素子を用いてもよい。 In each of the above embodiments, the switching element is exemplified as a MOS FET.
However, other semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor) may be used instead of the MOS FET.
　上記各実施形態では、スイッチング用素子としてＳｉＣ（炭化ケイ素）ＭＯＳ　ＦＥＴが好ましいとした。しかし、本発明は、炭化ケイ素の他にも、窒化ガリウム、酸化ガリウム、ダイヤモンドを母材とする半導体素子に対しても適用することができる。また、本発明は、通常のＳｉ　ＭＯＳ　ＦＥＴにも適用することができる。 In each of the above embodiments, a SiC (silicon carbide) MOS FET is preferred as the switching element. However, the present invention can be applied not only to silicon carbide but also to semiconductor devices using gallium nitride, gallium oxide, and diamond as a base material. The present invention can also be applied to ordinary Si MOS FETs.
　上記では、種々の実施の形態および変形例を説明したが、本発明はこれらの内容に限定されるものではない。本発明の技術的思想の範囲内で考えられるその他の態様も本発明の範囲内に含まれる。 Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other aspects considered within the scope of the technical idea of the present invention are also included within the scope of the present invention.
　１０　　　半導体素子
　１２　　　ソース電極（表面電極）
　１３　　　ドレイン電極（裏面電極）
　１５　　　第一絶縁層
　１５ａ　　開口部
　２１　　　中継導体
　２２　　　表面側導体（導体）
　２３　　　裏面側導体（対向導体）
　３１、３１ａ　　　第二絶縁層
　３２　　　封止樹脂
　４１～４５　　　接合層
１００　　　半導体装置
１２２　　　表面側導体（導体）
１２３　　　裏面側導体
２００　　　半導体装置
２２２　　　外側表面側導体（外側導体）
２２３　　　外側裏面側導体
３００　　　半導体装置
　　ＡＶ　　ボイド
　　Ｇ　　　隙間 10 Semiconductor element 12 Source electrode (surface electrode)
13 Drain electrode (back electrode)
15 First insulating layer 15a Opening 21 Relay conductor 22 Surface side conductor (conductor)
23 Back side conductor (opposite conductor)
31, 31a Second insulating layer 32 Encapsulating resin 41 to 45 Bonding layer 100 Semiconductor device 122 Surface side conductor
123 Back side conductor 200 Semiconductor device 222 Outer front side conductor (outer conductor)
223 outer back side conductor 300 semiconductor devices A V void G gap

Claims (14)

  1. 　開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する半導体素子と、
    　前記表面電極に接合された中継導体と、
    　前記表面電極と前記中継導体とを接合する接合層と、
    　前記第一絶縁層の少なくとも一部を覆い、少なくとも前記接合層の周囲に接して設けられた第二絶縁層と、
    　前記中継導体に接続された導体と、
    　前記導体と前記第二絶縁層との間に充填された封止樹脂と、を備える半導体装置。     A semiconductor device having a first insulating layer having an opening and a surface electrode exposed from the opening of the first insulating layer,
    The relay conductor bonded to the surface electrode and
    A bonding layer that joins the surface electrode and the relay conductor,
    A second insulating layer that covers at least a part of the first insulating layer and is provided in contact with the periphery of the bonding layer.
    With the conductor connected to the relay conductor,
    A semiconductor device including a sealing resin filled between the conductor and the second insulating layer.
  2. 　請求項１に記載の半導体装置において、
    　前記開口部の周縁部と前記接合層の周囲との間に隙間が設けられ、
    　前記第二絶縁層は、前記隙間内に充填されている半導体装置。     In the semiconductor device according to claim 1,
    A gap is provided between the peripheral edge of the opening and the periphery of the bonding layer.
    The second insulating layer is a semiconductor device filled in the gap.
  3. 　請求項１に記載の半導体装置において、
    　前記第二絶縁層は、前記中継導体の少なくとも前記接合層側の周囲に接している半導体装置。     In the semiconductor device according to claim 1,
    The second insulating layer is a semiconductor device in contact with at least the periphery of the relay conductor on the junction layer side.
  4. 　請求項１に記載の半導体装置において、
    　前記導体と前記中継導体とを接合する接合層をさらに備える半導体装置。     In the semiconductor device according to claim 1,
    A semiconductor device further comprising a bonding layer for joining the conductor and the relay conductor.
  5. 　請求項１に記載の半導体装置において、
    　前記導体は、前記半導体素子の前記第一絶縁層全体を覆う面積を有し、
    　前記封止樹脂は、前記半導体素子の周囲を封止する半導体装置。     In the semiconductor device according to claim 1,
    The conductor has an area covering the entire first insulating layer of the semiconductor element.
    The sealing resin is a semiconductor device that seals the periphery of the semiconductor element.
  6. 　請求項１に記載の半導体装置において、
    　前記第二絶縁層は、前記第一絶縁層よりも厚く設けられている半導体装置。     In the semiconductor device according to claim 1,
    The second insulating layer is a semiconductor device provided thicker than the first insulating layer.
  7. 　請求項１に記載の半導体装置において、
    　前記中継導体は、インバーを含む半導体装置。     In the semiconductor device according to claim 1,
    The relay conductor is a semiconductor device including Invar.
  8. 　請求項１に記載の半導体装置において、
    　前記接合層は、金属接合ペーストが焼結された焼結金属である半導体装置。     In the semiconductor device according to claim 1,
    The bonding layer is a semiconductor device in which a metal bonding paste is sintered and is a sintered metal.
  9. 　請求項１に記載の半導体装置において、
    　前記半導体素子は、前記表面電極の対向面側に裏面電極を有し、
    　さらに、前記裏面電極に接続された対向導体を有し、
    　前記第二絶縁層は、前記対向導体に接している半導体装置。     In the semiconductor device according to claim 1,
    The semiconductor element has a back surface electrode on the opposite surface side of the front surface electrode.
    Further, it has an opposing conductor connected to the back electrode and
    The second insulating layer is a semiconductor device in contact with the opposing conductor.
  10. 　請求項１から請求項９までのいずれか一項に記載の半導体装置において、
    　前記半導体素子は、炭化ケイ素、窒化ガリウム、酸化ガリウム、ダイヤモンドのいずれかを母材とする半導体装置。     In the semiconductor device according to any one of claims 1 to 9.
    The semiconductor device is a semiconductor device using any one of silicon carbide, gallium nitride, gallium oxide, and diamond as a base material.
  11. 　開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する複数の半導体素子と、
    　前記各半導体素子の前記表面電極に接合された中継導体と、
    　前記各表面電極と前記各中継導体とを接合する接合層と、
    　前記各第一絶縁層の少なくとも一部を覆い、少なくとも前記各接合層の周囲に接して設けられた第二絶縁層と、
    　前記各中継導体を接続する導体と、を備える半導体装置。     A plurality of semiconductor devices having a first insulating layer having an opening and a surface electrode exposed from the opening of the first insulating layer,
    A relay conductor bonded to the surface electrode of each semiconductor element,
    A bonding layer that joins each surface electrode and each relay conductor,
    A second insulating layer that covers at least a part of each of the first insulating layers and is provided in contact with the periphery of each of the bonding layers.
    A semiconductor device including a conductor connecting the respective relay conductors.
  12. 　請求項１１に記載の半導体装置において、
    　前記導体と前記第二絶縁層との間に充填された封止樹脂と、を備える半導体装置。     In the semiconductor device according to claim 11,
    A semiconductor device including a sealing resin filled between the conductor and the second insulating layer.
  13. 　請求項１１に記載の半導体装置を複数有し、
    　前記各半導体装置の前記導体を接続する外側導体を、さらに有する半導体装置。     Having a plurality of semiconductor devices according to claim 11,
    A semiconductor device further comprising an outer conductor connecting the conductors of each of the semiconductor devices.
  14. 　開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する半導体素子を準備することと、
    　前記表面電極と中継導体とを接合層により接合することと、
    　前記第一絶縁層の少なくとも一部を覆い、少なくとも前記接合層の周囲に接する第二絶縁層を設けることと、
    　前記中継導体に導体を接続することと、
    　前記導体と前記第二絶縁層との間に封止樹脂を充填することと、を含む半導体装置の製造方法。     To prepare a semiconductor device having a first insulating layer having an opening and a surface electrode exposed from the opening of the first insulating layer.
    To join the surface electrode and the relay conductor with a joining layer,
    A second insulating layer that covers at least a part of the first insulating layer and is in contact with at least the periphery of the bonding layer is provided.
    Connecting a conductor to the relay conductor
    A method for manufacturing a semiconductor device, comprising filling a sealing resin between the conductor and the second insulating layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022249803A1 (en) * 2021-05-27 2022-12-01 株式会社デンソー Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024044822A (en) * 2022-09-21 2024-04-02 株式会社デンソー Semiconductor Device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016048760A (en) * 2014-08-28 2016-04-07 三菱電機株式会社 Semiconductor device
JP2018032835A (en) * 2016-08-26 2018-03-01 トヨタ自動車株式会社 Semiconductor device manufacturing method
WO2018173511A1 (en) * 2017-03-22 2018-09-27 株式会社デンソー Semiconductor device
JP2019091915A (en) * 2017-03-08 2019-06-13 三菱電機株式会社 Semiconductor device, manufacturing method therefor, and semiconductor module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011114176A (en) 2009-11-27 2011-06-09 Mitsubishi Electric Corp Power semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016048760A (en) * 2014-08-28 2016-04-07 三菱電機株式会社 Semiconductor device
JP2018032835A (en) * 2016-08-26 2018-03-01 トヨタ自動車株式会社 Semiconductor device manufacturing method
JP2019091915A (en) * 2017-03-08 2019-06-13 三菱電機株式会社 Semiconductor device, manufacturing method therefor, and semiconductor module
WO2018173511A1 (en) * 2017-03-22 2018-09-27 株式会社デンソー Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022249803A1 (en) * 2021-05-27 2022-12-01 株式会社デンソー Semiconductor device
JP7472852B2 (en) 2021-05-27 2024-04-23 株式会社デンソー Semiconductor Device

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