WO2020257960A1 - Architectures d'émetteur-récepteur pour communication optique à haut débit - Google Patents

Architectures d'émetteur-récepteur pour communication optique à haut débit Download PDF

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WO2020257960A1
WO2020257960A1 PCT/CN2019/092504 CN2019092504W WO2020257960A1 WO 2020257960 A1 WO2020257960 A1 WO 2020257960A1 CN 2019092504 W CN2019092504 W CN 2019092504W WO 2020257960 A1 WO2020257960 A1 WO 2020257960A1
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symbols
code
binary
symbol mapping
encoded symbols
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PCT/CN2019/092504
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English (en)
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Hung-Chang Chien
Yi Cai
Weiming Wang
Liangjun ZHANG
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Zte Corporation
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/251—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with block coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H04B10/54—Intensity modulation
    • H04B10/541—Digital intensity or amplitude modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1171—Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2732—Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver

Definitions

  • This document relates to digital communications, and in one aspect, high-rate optical communication systems.
  • transceiver architectures that support non-binary forward error correction (FEC) codes and high-dimensional symbol mappers are disclosed.
  • FEC forward error correction
  • an optical communication method includes using a first encoding process to generate a first plurality of encoded symbols based on a plurality of information symbols; using a second encoding process to generate a second plurality of encoded symbols based on the first plurality of encoded symbols; and generating, based on the second plurality of encoded symbols, a waveform for optical transmission, wherein the second encoding process comprises: (i) a binary forward error correction (FEC) code and a two-dimensional (2D) symbol mapping, or (ii) a non-binary FEC code and the 2D symbol mapping, or (iii) the non-binary FEC code and a four-dimensional (4D) symbol mapping.
  • FEC binary forward error correction
  • an optical communication method includes receiving k-1 data symbols, each symbol comprising m bits; generating a block of k symbols by appending an m-bit zero symbol to the k-1 data symbols; generating an n- symbol codeword by performing a (n, k) Reed-Solomon (RS) encoding process on the block of k symbols; generating a shortened (n-1) -symbol codeword by removing the m-bit zero symbol, corresponding to a (n-1, k-1) Reed-Solomon code; generating an (n+1) -symbol codeword by appending two parity symbols to the shortened (n-1) -symbol codeword, corresponding to a (n+1, k -1) Reed-Solomon code; reshaping the (n+1) -symbol codeword to a symbol matrix; and transmitting a frame comprising the symbol matrix.
  • RS Reed-Solomon
  • the above-described methods are embodied in the form of processor-executable code and stored in a computer-readable program medium.
  • a device that is configured or operable to perform the above-described methods is disclosed.
  • FIG. 1 shows an example of the functional architecture of an optical transceiver.
  • FIG. 2 shows another example of the function architecture of an optical transceiver, in accordance with embodiments of the disclosed technology.
  • FIG. 3 shows 2D projection views of constellations for the optimized 256-point 4-dimensional (4D) (256-D 4 ) modulation.
  • FIG. 4 shows an example of constellations for a dual-polarization (DP) -16QAM (quadrature amplitude modulation) .
  • DP dual-polarization
  • QAM quadrature amplitude modulation
  • FIG. 5A and 5B show examples of framing formats for a Hamming code and Reed-Solomon (RS) code, respectively.
  • FIG. 6 shows a flowchart for an example method of optical communication.
  • FIG. 7 shows a flowchart for another example method of optical communication.
  • FIG. 8 is a block diagram representation of a portion of an optical transmitter or receiver apparatus.
  • FEC Forward error correction
  • OIF has adopted a concatenated FEC comprising an outer code with hard-decision decoding and an inner code with soft-decision decoding, with a combined overhead of 14.8%, thereby trading off between the needed coding gain and the tight power margin of the DSP chip.
  • FIG. 1 An example of a 400ZR optical transceiver with concatenated FEC encoder and decoder, and regular dual polarized (DP) -16QAM mapping and de-mapping, respectively, is shown in FIG 1.
  • the scrambler and convolutional interleaver are also required blocks between the outer and inner FECs to reduce the burst error, but do not require any overhead.
  • the inner Hamming FEC for 400ZR is operated on a binary basis.
  • the output symbol rate is k (1+d 1 ) (1+d 2 ) /m symbols/sbefore modulation using the optical transmitter.
  • the received symbols after initial processing by the optical receiver, go through corresponding de-coding and de-modulation processes, to generate the final decoded (recovered) bits.
  • the transceiver architecture shown in FIG. 1 further includes insertion and removal blocks for (a) padding bits that are needed for the synchronization of FEC frames, and (b) pilot and/or training symbols for channel estimation and synchronization.
  • insertion and removal blocks for (a) padding bits that are needed for the synchronization of FEC frames, and (b) pilot and/or training symbols for channel estimation and synchronization.
  • the 400ZR transceiver architecture shown in FIG. 1 is unable to support all 80-km links since existing implementations include aging optical cables may have significantly higher fiber loss or connection loss than those being referenced (or intended) in the development and specification of the standard.
  • Embodiments of the disclosed technology exhibit, amongst other features, the following characteristics:
  • Backward compatibility should be backward compatible with the standardized 400ZR (e.g., as shown in FIG. 1) .
  • the disclosed technology includes a 400ZR+ optical transceiver architecture that has three switchable coding and modulation modes.
  • the 400ZR+ transceiver architecture shares the same outer hard-decision FEC code with 400ZR, but has two inner soft-decision FEC options: non-binary and binary, and also two symbol mapping options: 4D (256-D 4 ) and 2D (DP-16QAM) , respectively, which gives three reconfigurable coding and modulation modes as follows:
  • Table 1 Modes supported in an example transceiver architecture
  • the third mode in Table 1 is an existing standardized 400ZR mode (e.g., as shown in FIG. 1) where the inner FEC employs a soft-decision Hamming code operating on a bit-by-bit basis. This is followed by independent 16-QAM modulation on two orthogonal polarizations (x and y) of a single optical carrier.
  • Each 16-QAM symbols consist of in-phase (I) and quadrature-phase (Q) components, which may be viewed as two-dimensional (2D) QAM symbol mapping.
  • the second mode in Table 1 employs a non-binary FEC code such as a non-binary low-density parity-check (NB-LDPC) code or a Reed–Solomon (RS) code as the inner FEC option, which is followed by the 16QAM mapping.
  • a non-binary FEC code such as a non-binary low-density parity-check (NB-LDPC) code or a Reed–Solomon (RS) code
  • NB-LDPC non-binary low-density parity-check
  • RS Reed–Solomon
  • Non-binary FEC codes operate on a symbol-by-symbol basis, and thus correlated bit errors that fall into a symbol get corrected together.
  • Existing implementations have demonstrated that a non-binary FEC outperforms a binary FEC in regular QAM systems.
  • the first mode in Table 1 uses a non-binary code as the inner FEC code, and also employs an optimized 256-point four-dimensional (4D) symbol mapping (hereafter referred to as 256-D 4 ) .
  • 4D four-dimensional
  • the 256-D 4 modulation format (whose 2D projection views of constellations are shown in FIG. 3) has the same spectral efficiency of 4 bits/symbol/polarization as the typical dual-polarization (DP) -16QAM (whose constellation is shown in FIG. 4) and is a power efficient 4D format with 256 points.
  • the 2D projection of 256-D 4 onto the in-phase and quadrature plane of x-or y-polarization exhibits a 32-QAM-like constellation, and its probability density has a Gaussian distribution, where the low energy constellation points have higher probability density than high energy ones.
  • the projected constellation point (1, 1) on the x-polarization are interrelated to 16 projected constellation points on the y-polarization, whereas the projected constellation point (-5, -3) on the x-polarization has only 2 interrelated constellation points on the y-polarization.
  • the 256-D 4 modulation format exhibits, amongst other features, the following characteristics:
  • ⁇ 256-D 4 is the most power efficient modulation format with 256 points in four dimensions, and has the same modulation efficiency with DP-16QAM.
  • the 256-D 4 symbol mapping scheme is implemented such that the modulation on two polarizations are dependent.
  • a 256-D 4 symbol has to be defined on a 4D space (xI, xQ, yI, yQ) with xI, xQ, yI, and yQ correlated to each other. This increases the Euclidean distance between constellation points for a given average signal power, thereby improving the receiver sensitivity.
  • the performance of the modes in Table 1 are ranked as:
  • the outer staircase FEC encoded frame includes 10976 ⁇ 119 bits
  • Both the binary or the non-binary inner FEC encoded frame has a payload area of 10976 (column) ⁇ 119 (row) bits, and a parity area of 10976 (column) ⁇ 9 (row) bits, as shown in FIGS. 5A and 5B.
  • FIGS. 5A and 5B show frame formats for a binary (128, 119) Hamming FEC and a non-binary (256, 238) Reed-Solomon FEC, respectively.
  • the FEC frame format for a RS (256, 238) code may be constructed as follows:
  • FIG. 6 shows a flowchart for an example optical communication method 600.
  • the method 600 includes, at step 610, using a first encoding process to generate a first plurality of encoded symbols based on a plurality of information symbols.
  • the method 600 includes, at step 620, using a second encoding process to generate a second plurality of encoded symbols based on the first plurality of encoded symbols.
  • the second encoding process includes (i) a binary forward error correction (FEC) code and a two-dimensional (2D) symbol mapping, or (ii) a non-binary FEC code and the 2D symbol mapping, or (iii) the non-binary FEC code and a four-dimensional (4D) symbol mapping.
  • FEC binary forward error correction
  • the method 600 includes, at step 630, generating, based on the second plurality of encoded symbols, a waveform for optical transmission.
  • the 2D symbol mapping is a 16-QAM (quadrature amplitude modulation) symbol mapping
  • the 4D symbol mapping is a polarization-multiplexed 16-QAM symbol mapping
  • the method 600 further includes the steps of generating, based on scrambling the first plurality of encoded symbols, a plurality of scrambled symbols; generating, based on convolutionally interleaving the plurality of scrambled symbols, a plurality of interleaved symbols; and encoding, using the second encoding process, the plurality of interleaved symbols to generate the second plurality of encoded symbols.
  • the method 600 further includes the step of transmitting, using an optical transmitter, the waveform.
  • the first encoding process comprises a staircase code.
  • the binary FEC code and the non-binary FEC code have an identical number of payload bits and an identical number of parity bits.
  • the non-binary FEC code is a non-binary low-density parity-check code (NB-LDPC) or a Reed-Solomon (RS) code.
  • NB-LDPC non-binary low-density parity-check code
  • RS Reed-Solomon
  • FIG. 7 shows a flowchart for another example optical communication method 700, as described in FIG. 5B.
  • the method 700 includes, at step 710, receiving k-1 data symbols, each symbol comprising m bits.
  • the method 700 includes, at step 720, generating a block of k symbols by appending an m-bit zero symbol to the k-1 data symbols.
  • the method 700 includes, at step 730, generating an n-symbol codeword by performing a (n, k) Reed-Solomon encoding process on the block of k symbols.
  • the method 700 includes, at step 740, generating a shortened (n-1) -symbol codeword by removing the m-bit zero symbol, corresponding to a (n-1, k-1) Reed-Solomon code.
  • the method 700 includes, at step 750, generating an (n+1) -symbol codeword by appending two parity symbols to the shortened (n-1) -symbol codeword, corresponding to a (n+1, k -1) Reed-Solomon code.
  • the method 700 includes, at step 760, reshaping the (n+1) -symbol codeword to a symbol matrix, and at step 870, transmitting a frame comprising the symbol matrix.
  • the Hamming (128, 119) code is replaced with this modified RS (544, 514) code.
  • Embodiments of the disclosed technology include an apparatus for high-rate optical communication.
  • the apparatus in the context of FIG. 2, includes a first encoder configured to generate a first plurality of encoded symbols based on a plurality of information symbols; a second encoder comprising a forward error correction (FEC) code encoder and a symbol mapper, wherein a combination of the FEC code encoder and the symbol mapper are selected from (i) a binary FEC code encoder and a two-dimensional (2D) symbol mapper, (ii) a non-binary FEC encoder and the 2D symbol mapper, or (iii) the non-binary FEC encoder and a four-dimensional (4D) symbol mapper, wherein the second encoder is configured to generate a second plurality of encoded symbols based on the first plurality of encoded symbols; and a waveform generator configured to generate a waveform for optical transmission based on the second plurality of encoded symbols.
  • FEC forward error correction
  • the apparatus further includes a scrambler configured to scramble the first plurality of encoded symbols to generate a plurality of scrambled symbols; and an interleaver configured to convolutionally interleaving the plurality of scrambled symbols to generate a plurality of interleaved symbols, wherein the second encoder generates the second plurality of encoded symbols by encoding the plurality of interleaved symbols.
  • the apparatus further includes an optical transmitter configured to transmit the waveform at a 400 gigabits per second nominal rate.
  • the nominal rate is the transmission rate achieved by the optical transceiver subject to hardware variations, including oscillator accuracy, fiber variations, and the like.
  • an actual system designed for the nominal rate may actually operate by plus or minus 1000 parts per million accuracy away from the nominal rate.
  • the 2D symbol mapping is a typical DP-16QAM symbol mapping
  • the 4D symbol mapping is an optimized 256-point 4D (256-D 4 ) symbol mapping.
  • the first encoding process comprises a staircase code.
  • the non-binary FEC code is a non-binary low-density parity-check code (NB-LDPC) or a Reed-Solomon (RS) code.
  • NB-LDPC non-binary low-density parity-check code
  • RS Reed-Solomon
  • FIG. 8 shows an example of an optical transmitter or receiver apparatus 800 where the techniques described herein may be performed.
  • the apparatus 800 may be include an input interface 802 at which user data may be received for transmission over an optical communication link.
  • the apparatus may include a processor 806 that is configured to perform the various techniques described in the present document.
  • the apparatus 800 may also include an optical transceiver 808 that includes a transmitter circuit and a receiver circuit that performs various operations, including methods 600 and 700, described herein.
  • a computer-readable medium may include removable and non-removable storage devices including, but not limited to, Read Only Memory (ROM) , Random Access Memory (RAM) , compact discs (CDs) , digital versatile discs (DVD) , etc. Therefore, the computer-readable media can include a non-transitory storage media.
  • program modules may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • Computer-or processor-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps or processes.
  • a hardware circuit implementation can include discrete analog and/or digital components that are, for example, integrated as part of a printed circuit board.
  • the disclosed components or modules can be implemented as an Application Specific Integrated Circuit (ASIC) and/or as a Field Programmable Gate Array (FPGA) device.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • DSP digital signal processor
  • the various components or sub-components within each module may be implemented in software, hardware or firmware.
  • the connectivity between the modules and/or components within the modules may be provided using any one of the connectivity methods and media that is known in the art, including, but not limited to, communications over the Internet, wired, or wireless networks using the appropriate protocols.

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  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
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  • Electromagnetism (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

La présente invention concerne des procédés, des systèmes et des dispositifs pour des systèmes de communication optique à haut débit. Un procédé pour une communication optique consiste à utiliser un premier processus de codage pour générer une première pluralité de symboles codés sur la base d'une pluralité de symboles d'informations ; à utiliser un second processus de codage pour générer une seconde pluralité de symboles codés sur la base de la première pluralité de symboles codés ; et à générer, sur la base de la seconde pluralité de symboles codés, une forme d'onde pour une transmission optique, le second processus de codage consistant : (I) à mapper un code de correction d'erreur sans voie de retour (FEC) binaire et d'un symbole en deux dimensions (2D), ou (ii) à mapper un code FEC non binaire et d'un symbole 2D ou (iii) à mapper un code FEC non binaire et d'un symbole en quatre dimensions (4D).
PCT/CN2019/092504 2019-06-24 2019-06-24 Architectures d'émetteur-récepteur pour communication optique à haut débit WO2020257960A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013000746A1 (fr) * 2011-06-30 2013-01-03 Nokia Siemens Networks Oy Procédé de traitement de données pour des réseaux optiques et émetteur pour des réseaux optiques
CN103199876A (zh) * 2013-04-11 2013-07-10 华为技术有限公司 实现软判决fec译码的方法及装置
CN109314530A (zh) * 2016-06-21 2019-02-05 日本电信电话株式会社 光接收机、光传输装置和光接收机用的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013000746A1 (fr) * 2011-06-30 2013-01-03 Nokia Siemens Networks Oy Procédé de traitement de données pour des réseaux optiques et émetteur pour des réseaux optiques
CN103199876A (zh) * 2013-04-11 2013-07-10 华为技术有限公司 实现软判决fec译码的方法及装置
CN109314530A (zh) * 2016-06-21 2019-02-05 日本电信电话株式会社 光接收机、光传输装置和光接收机用的方法

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