WO2020253149A1 - 一种电路单元封装结构 - Google Patents

一种电路单元封装结构 Download PDF

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Publication number
WO2020253149A1
WO2020253149A1 PCT/CN2019/123559 CN2019123559W WO2020253149A1 WO 2020253149 A1 WO2020253149 A1 WO 2020253149A1 CN 2019123559 W CN2019123559 W CN 2019123559W WO 2020253149 A1 WO2020253149 A1 WO 2020253149A1
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Prior art keywords
circuit unit
circuit
electromagnetic shielding
silicon dioxide
packaging structure
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PCT/CN2019/123559
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English (en)
French (fr)
Inventor
王海升
田德文
宋青林
Original Assignee
潍坊歌尔微电子有限公司
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Priority to US17/620,839 priority Critical patent/US20220408549A1/en
Publication of WO2020253149A1 publication Critical patent/WO2020253149A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10121—Optical component, e.g. opto-electronic component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10151—Sensor

Definitions

  • the present invention relates to the field of electronic technology, in particular to a circuit unit packaging structure.
  • the main purpose of the present invention is to provide a circuit unit packaging structure, which aims to solve the problem of too high cost of the circuit unit packaging structure and complicated manufacturing steps.
  • an embodiment of the present invention provides a circuit unit packaging structure.
  • the circuit unit packaging structure includes a circuit substrate on which a circuit unit is provided.
  • the circuit unit includes a silicon dioxide layer and An electronic device on the silicon dioxide layer; an insulator, the insulator is arranged around the circuit unit; an electromagnetic shielding layer, the electromagnetic shielding layer is arranged on the circuit unit and the insulator.
  • the insulator is protruded between the circuit units to form a groove with the silicon dioxide layer, and the electromagnetic shielding layer fills the groove to contact the silicon dioxide layer.
  • the silicon dioxide layer is provided on the circuit substrate in the form of surface mounting.
  • the electromagnetic shielding layer is made of semi-conductive silver glue, which is obtained by adding metal particles to epoxy resin.
  • the material of the electromagnetic shielding layer is aluminum nitride ceramic.
  • the material of the electromagnetic shielding layer is organic glass.
  • the electromagnetic shielding layer is provided with a through hole
  • the circuit unit is a patch antenna
  • the patch antenna includes: a radio frequency circuit formed on the silicon dioxide layer; a radiator; The radiator is formed on the surface of the electromagnetic shielding layer away from the silicon dioxide layer; a feeder line, the feeder passes through the through hole to connect the radio frequency circuit and the radiator.
  • the circuit unit is a photosensitive element
  • the photosensitive element is formed on the silicon dioxide layer
  • the electromagnetic shielding layer is made of a transparent or semi-transparent material.
  • the electromagnetic shielding layer is provided with at least two through holes
  • the circuit unit is a pressure sensing circuit
  • the pressure sensing circuit includes: a controller formed on the silicon dioxide layer Pressure sensor, the pressure sensor is arranged on the surface of the electromagnetic shielding layer away from the silicon dioxide layer; a connection line, the connection line passes through the through hole to connect the controller and the pressure sensor.
  • an embodiment of the present invention provides an electronic device including the circuit unit packaging structure described in any of the foregoing.
  • the circuit substrate, the silicon dioxide layer, and the electromagnetic shielding layer are sequentially stacked, and the silicon layer substrate on the silicon dioxide layer in the prior art is removed, not only can achieve good electromagnetic Shielding effect.
  • the electromagnetic shielding layer is a high-dielectric constant material, it has high-efficiency electrical and thermal conductivity, which can transmit and dissipate the heat in the working process of the circuit unit in time, eliminating the low thermal conductivity of the silicon layer substrate , High brittleness and low reliability, and at the same time, it eliminates the need to form a metal package shell on the circuit substrate again by metal, which is more conducive to mass production, and because the silicon layer substrate is removed, the The overall thickness of the circuit unit packaging structure becomes thinner.
  • FIG. 1 is a schematic flow chart of the first embodiment of the circuit unit packaging process of the present invention
  • Fig. 3 is a schematic structural diagram of the circuit unit packaging structure of the present invention.
  • FIG. 4 is a schematic diagram of a specific flow of the circuit unit packaging process step S20 of the present invention.
  • FIG. 5 is a schematic diagram of a specific flow of the circuit unit packaging process step S221 of the present invention.
  • FIG. 6 is a schematic flowchart of a second embodiment of the circuit unit packaging process of the present invention.
  • FIG. 2a is a schematic diagram of a plurality of circuit units 20 being placed upside down on a circuit substrate during a circuit unit packaging process
  • FIG. 2b is a schematic diagram of a plastic encapsulation epoxy resin
  • FIG. 2c The schematic diagram of the epoxy resin being ground
  • Fig. 2d the schematic diagram of the silicon layer substrate being corroded
  • Fig. 2e the schematic diagram of forming the electromagnetic shielding layer
  • Fig. 2f the schematic diagram of cutting the circuit unit to form the circuit module.
  • a circuit unit packaging process provided by an embodiment of the present invention is used to manufacture the circuit unit packaging structure of the present invention.
  • the circuit unit includes a silicon layer substrate and a silicon dioxide layer stacked on the silicon layer substrate, as the present invention
  • the circuit unit packaging process includes the following steps:
  • Step S10 mounting a plurality of circuit units upside down on a circuit substrate at intervals, wherein the silicon dioxide layer is attached to the circuit substrate, and the silicon layer substrate is away from the circuit substrate;
  • a plurality of the circuit units are mounted on the circuit substrate such as a printed circuit board through surface mount technology (SMT, (Surface Mount Technology) or DB technology (Die Bond) or other mounting processes ,
  • the circuit unit is usually mounted on the circuit substrate in the forward direction, that is, the silicon layer substrate of the circuit unit is mounted on the circuit substrate, and the silicon dioxide layer is Is arranged on the silicon layer substrate, and in this embodiment, the circuit unit is mounted on the circuit substrate upside down, that is, the silicon dioxide layer is attached to the circuit substrate, and the silicon The layer substrate is set on the silicon dioxide layer away from the circuit substrate, the purpose of which is to set the silicon layer substrate on the upper surface so that the silicon layer substrate can be subsequently removed, leaving only the silicon dioxide layer Floor.
  • SMT Surface Mount Technology
  • DB technology Die Bond
  • Step S20 forming an insulator between the circuit units
  • the circuit units are arranged at intervals to fill an insulator between the circuit units.
  • the insulator may be a non-conductive epoxy resin and other materials, which are applied in the circuit through a coating process or a dispensing process.
  • An insulating medium is formed on the substrate, and the insulating medium on the silicon layer substrate is removed by a grinding process to expose the silicon layer substrate, and the insulating medium between circuit units is retained to form the insulator, which insulates different circuit units , While protecting the circuit unit.
  • Step S30 removing the silicon layer substrate to expose the silicon dioxide layer
  • the silicon layer substrate exposed on the upper surface may be removed by an etching process or an acid etching process to expose the silicon dioxide layer on the outer surface.
  • Step S40 forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.
  • an electromagnetic shielding layer may be formed on the silicon dioxide layer and the insulator through a coating process, a dispensing process, or a sputtering process.
  • the electromagnetic shielding layer forms a metal shielding cover to shield the electromagnetic
  • the circuit chip in the layer is isolated from the external electromagnetic interference signal, so as to realize the high anti-harmonic interference of the circuit chip.
  • the circuit units are mounted on the circuit substrate upside down at intervals, and the gaps between the circuit units are filled with insulators, and then the silicon layer substrate of the circuit units is removed, Then, an electromagnetic shielding layer is formed on and on the insulator and silicon dioxide layer to achieve a good electromagnetic shielding effect.
  • the electromagnetic shielding layer is a high-dielectric constant material and has high-efficiency electrical and thermal conductivity characteristics, the The heat in the working process of the circuit unit is transmitted and dissipated in time, which eliminates the disadvantages of low thermal conductivity, high brittleness and low reliability of the silicon layer substrate, and also eliminates the need to form a metal encapsulation shell on the circuit substrate again through metal Steps are more conducive to mass production.
  • the step S20 includes:
  • Step S21 molding epoxy resin on the circuit substrate, wherein the epoxy resin covers the circuit substrate and the circuit unit and the epoxy resin fills the gap between the circuit units;
  • Step S22 Grinding the epoxy resin to remove the epoxy resin covering the circuit units and retain the epoxy resin between the circuit units to form the insulator.
  • the epoxy resin is molded on the circuit substrate so that the epoxy resin fills the gap between the circuit units while the epoxy resin molds the entire circuit substrate. Afterwards, the epoxy resin is ground by a grinding process, so that the thickness of the epoxy resin is gradually reduced until the silicon layer substrate of the circuit unit is exposed on the surface. At this time, the remaining filling is The epoxy resin between the circuit units forms the insulator, and at this time, the insulator is flush with the silicon substrate of the circuit unit.
  • a third embodiment of the circuit unit packaging process of the present invention is proposed based on the foregoing first 1-2 embodiments, and the step S22 includes:
  • Step S221 controlling the grinding jig and the epoxy resin to rotate in the same direction, wherein the grinding jig and the epoxy resin have different rotation speeds.
  • the grinding jig and the epoxy resin are controlled to rotate in the same direction.
  • the grinding jig and the epoxy resin are both rotated counterclockwise or both clockwise.
  • the difference in the rotational speed of the oxygen resin keeps the grinding jig and the epoxy resin in relative motion.
  • the grinding jig and the epoxy resin rotate in the same direction to avoid the difference between the grinding jig and the epoxy A huge pulling force is generated in the meantime, and the circuit unit in the epoxy resin is damaged by the force, which improves the yield of the circuit unit.
  • the step S221 includes:
  • Step S2211 controlling the grinding jig to rotate at a first preset speed to perform a rough grinding operation on the epoxy resin
  • Step S2212 controlling the grinding jig to rotate at a second preset speed to perform a fine grinding operation on the epoxy resin
  • Step S2213 controlling the grinding jig to polish the epoxy resin
  • the first preset speed is greater than the second preset speed.
  • the epoxy resin in the initial stage of grinding the epoxy resin, since the epoxy resin is thick, the epoxy resin may be rough-grinded first to speed up the grinding speed.
  • the epoxy resin is polished by diamond with a large roughness on the surface of the grinding jig.
  • the feed speed of the grinding wheel of the grinding jig during rough grinding can be set to 30mm/s and the rotation speed is 1200-4500 rpm. /Min, the thickness of the diamond on the grinding wheel is 300#, and the rotation speed of the epoxy resin at this time is 2500-4500 rpm.
  • the grinding wheel feed speed of the grinding jig can be appropriately reduced to 3mm /s and/or reduce the roughness of the diamond to 5000#-8000#, the rotation speed of the grinding wheel of the grinding jig can be appropriately reduced or remain unchanged, but the speed of the epoxy resin is slightly increased to reduce The speed difference between the grinding jig and the epoxy resin achieves the effect of fine grinding.
  • the surface of the epoxy resin is grinded by gauze. Since the hardness of the gauze is not high, the rotation speed and feed speed can not be restricted.
  • the gauze makes the epoxy resin appear smoother and smoother while removing the The epoxy resin remaining on the silicon layer substrate completely exposes the silicon layer substrate, facilitating the complete removal of the subsequent silicon layer substrate.
  • a fifth embodiment of the circuit unit packaging process of the present invention is proposed based on the foregoing first to fourth embodiments, and the step S30 includes:
  • Step S31 removing the silicon layer substrate by etching with a hydrofluoric acid solution.
  • the silicon layer substrate is etched away by a hydrofluoric acid solution.
  • the hydrofluoric acid solution includes hydrofluoric acid and barium sulfate, and the concentration ratio of the hydrofluoric acid to barium sulfate is 10:1.
  • the function of the barium sulfate is to determine whether the silicon of the silicon layer substrate is completely dissolved and etched, the concentration of the hydrofluoric acid is 1.2 ml/L, and the concentration of the barium sulfate is 0.12. ml/L, the concentration ratio of the hydrofluoric acid to barium sulfate is 10:1, so as to ensure that the hydrofluoric acid has a faster corrosion rate.
  • the step S40 includes:
  • step S41 the electromagnetic shielding layer is formed on the silicon dioxide layer through a dispensing process, a coating process or a sputtering process.
  • the electromagnetic shielding layer has an electromagnetic shielding function, and its material is semi-conductive silver glue or aluminum nitride ceramic or organic glass, wherein the semi-conductive silver glue is obtained by adding metal particles to epoxy resin .
  • the semi-conductive silver glue, aluminum nitride ceramic, and organic glass are made of transparent or semi-transparent materials, so that light energy enters the conductive shield from the electromagnetic shielding layer and is affected by the photosensitive Component reception.
  • a seventh embodiment of the circuit unit packaging process of the present invention is proposed based on the foregoing first 1-6 embodiments.
  • the method further includes:
  • Step S50 cutting the plurality of circuit units into a plurality of individual circuit modules along the position of the insulator.
  • a plurality of the circuit units are cut into a plurality of individual circuit modules along the position of the insulator, and the circuit modules can be installed in electronic equipment for use.
  • the different circuit units are electromagnetically shielded on the circuit substrate, and then the different circuit units are cut into circuit modules that can be used individually, which improves the production efficiency, and at the same time makes each of the circuit modules have high-efficiency electrical and thermal conductivity, and has better electromagnetic properties.
  • the shielding performance can transmit and dissipate the heat in the working process of the circuit module in time, eliminating the disadvantageous factors of low thermal conductivity, high brittleness and low reliability of the silicon layer substrate.
  • an embodiment of the present invention provides a circuit unit 20 packaging structure 100.
  • the circuit unit 20 packaging structure 100 is manufactured by the above-mentioned circuit unit 20 packaging process.
  • the package structure 100 includes: a circuit substrate 10 on which a circuit unit 20 is provided.
  • the circuit unit 20 includes a silicon dioxide layer 21 and electronic devices arranged on the silicon dioxide layer 21 (not shown in the figure). Show); an insulator 30, the insulator 30 is arranged around the circuit unit 20; an electromagnetic shielding layer 40, the electromagnetic shielding layer 40 is arranged on the circuit unit 20 and the insulator 30.
  • the circuit substrate 10, the silicon dioxide layer 21, and the electromagnetic shielding layer 40 are sequentially stacked, and the silicon layer substrate 23 on the silicon dioxide layer 21 in the prior art is removed (see FIG. 2a).
  • the electromagnetic shielding layer 40 is made of a high dielectric constant material with high electrical and thermal conductivity, it can transfer the heat in the working process of the circuit unit 20 in time It eliminates the disadvantages of low thermal conductivity, high brittleness, and low reliability of the silicon layer substrate 23, and also eliminates the need to form a metal package shell on the circuit substrate 10 through metal again, which is more conducive to mass production
  • the overall thickness of the circuit unit 20 packaging structure 100 can be made thinner.
  • the circuit unit 20 is an RF radio frequency unit
  • the circuit unit 20 can be packaged
  • the structure 100 can achieve a thickness of 400mm.
  • the insulator 30 is protruded between the circuit units 20 to surround the silicon dioxide layer 21 to form a groove 22, and the electromagnetic shielding layer 40 fills the groove 22 to interact with the silicon dioxide layer 21.
  • the silicon layer 21 is in contact.
  • the groove 22 is formed by the hydrofluoric acid etching the silicon layer substrate 23 of the original circuit unit 20, and the silicon layer substrate 23 is not etched through the above-mentioned grinding process and the The insulator 30 is kept flush; the groove 22 can be filled with the electromagnetic shielding layer 40, so that the electromagnetic shielding layer 40 is in direct contact with the silicon dioxide layer 21, and the heat generated by the circuit unit 20 It is transmitted in time, and the electromagnetic shielding layer 40 is confined in the groove 22, and at the same time, it is connected to the silicon dioxide layer 21 and the insulator 30, which can enhance the connection stability of the electromagnetic shielding layer 40.
  • the silicon dioxide layer 21 is provided on the circuit substrate 10 in the form of surface mounting.
  • a plurality of the circuit units 20 are mounted on the circuit substrate 10 such as a printed circuit by surface mount technology (SMT, (Surface Mount Technology) or DB technology (Die Bond) or other mounting processes Board, and the circuit unit 20 is mounted upside down on the circuit substrate 10, that is, the silicon dioxide layer 21 is mounted on the circuit substrate 10, and the silicon substrate 23 is away from the circuit
  • the substrate 10 is disposed on the silicon dioxide layer 21, and its purpose is to dispose the silicon layer substrate 23 on the upper surface, so that the silicon layer substrate 23 can be subsequently removed, and the silicon dioxide layer 21 and the silicon dioxide layer 21 are retained.
  • the magnetic shielding layer is connected.
  • the material of the electromagnetic shielding layer 40 is semi-conductive silver glue, which is obtained by adding metal particles to epoxy resin, or the material of the electromagnetic shielding layer 40 is aluminum nitride ceramic, or
  • the material of the electromagnetic shielding layer 40 is organic glass; when the circuit unit 20 is a photosensitive element, the semi-conductive silver glue, aluminum nitride ceramics, and organic glass are made of transparent or semi-transparent materials, so that light energy can escape from the electromagnetic shielding layer 40 enters the conductive shield and is received by the photosensitive element.
  • the electromagnetic shielding layer 40 is provided with a through hole (not shown), the circuit unit 20 is a patch antenna (not shown), and the patch antenna includes: a radio frequency circuit (not shown) (Shown), the radio frequency circuit is formed on the silicon dioxide layer 21; a radiator (not shown), the radiator is formed on the surface of the electromagnetic shielding layer 40 away from the silicon dioxide layer 21; feeder ( (Not shown), the feeder passes through the through hole to connect the radio frequency circuit and the radiator.
  • the feeder line passes through the through hole to connect the radio frequency circuit and the radiator, thereby transmitting the radio frequency signal of the radio frequency circuit through the feeder line To the radiator, the radiator radiates the radio frequency signal. Due to the existence of the electromagnetic shielding layer 40, the radio frequency signal of the radio frequency circuit can be shielded in the electromagnetic shielding layer 40, and the radio frequency circuit will not affect the surrounding circuits.
  • Electromagnetic interference is generated, and the electromagnetic shielding layer 40 is in direct contact with the radio frequency circuit, which can transfer the heat generated during the operation of the radio frequency circuit, and since the patch antenna does not have a silicon layer substrate 23, the thickness can be made It is as thin as 400mm, which is conducive to the thinning and flattening of electronic products.
  • the electromagnetic shielding layer 40 is provided with at least two through holes (not shown), the circuit unit 20 is a pressure sensing circuit, and the pressure sensing circuit includes a controller (not shown), The controller is formed on the silicon dioxide layer 21; a pressure sensor (not shown), the pressure sensor is arranged on the surface of the electromagnetic shielding layer 40 away from the silicon dioxide layer 21; connecting wires (not shown), so The connecting wire passes through the through hole to connect the controller and the pressure sensor.
  • the electromagnetic shielding layer 40 is provided with a through hole, and the connecting wire passes through the through hole to connect the controller and the pressure sensor, so that the pressure sensed by the pressure sensor is The signal is transmitted to the controller through the connecting wire, and the controller performs subsequent processing on the pressure signal. Due to the existence of the electromagnetic shielding layer 40, the external electromagnetic interference Xin Ahong can be shielded outside the electromagnetic shielding layer 40 , The controller will not receive electromagnetic interference from the peripheral circuit, and the electromagnetic shielding layer 40 is in direct contact with the controller, which can transfer the heat generated during the operation of the controller.
  • the above-mentioned patch antenna and pressure sensing circuit are only examples of the circuit unit 20, and the circuit unit 20 can be a circuit component of any function and a functional circuit composed of multiple same or different circuit components .
  • an embodiment of the present invention provides an electronic device that includes the circuit unit 20 packaging structure 100 as described above. Since the electronic device includes the circuit unit 20 packaging structure 100, it has at least The beneficial effects of the above-mentioned circuit unit 20 packaging structure 100 will not be repeated here.

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Abstract

一种电路单元封装结构（100），所述电路单元封装结构（100）包括：电路基板（10），所述电路基板（10）上设置有电路单元（20），所述电路单元（20）包括二氧化硅层（21）及设置于所述二氧化硅层（21）上的电子器件；绝缘体（30），所述绝缘体（30）围设于所述电路单元（20）周围；电磁屏蔽层（40），所述电磁屏蔽层（40）罩设于所述电路单元（20）及所述绝缘体（30）上。电路单元封装结构（100）具有良好的电磁屏蔽效果且高效散热。

Description

一种电路单元封装结构 技术领域
本发明涉及电子技术领域，特别涉及一种电路单元封装结构。
背景技术
现有技术中，在封装印刷电路板的电路单元时，通常是直接在电路单元上塑封一层胶体，使得电路单元被封装于胶体与印刷电路板之间，如此导致电路单元散热性不好，同时，电路单元容易受到外部射频信号的影响而导致电磁屏蔽性能较差。
发明内容
本发明的主要目的是提供一种电路单元封装结构，旨在解决电路单元封装结构成本太高且制造步骤繁琐的问题。
为实现上述目的，本发明实施例提供了一种电路单元封装结构，所述电路单元封装结构包括：电路基板，所述电路基板上设置有电路单元，所述电路单元包括二氧化硅层及设置于所述二氧化硅层上的电子器件；绝缘体，所述绝缘体围设于所述电路单元周围；电磁屏蔽层，所述电磁屏蔽层罩设于所述电路单元及所述绝缘体上。
优选地，所述绝缘体凸设于所述电路单元之间以与所述二氧化硅层合围形成凹槽，所述电磁屏蔽层填充所述凹槽以与所述二氧化硅层接触。
优选地，所述二氧化硅层以表面贴装的形式设置于所述电路基板上。
优选地，所述电磁屏蔽层材质为半导电银胶，所述半导电银胶通过在环氧树脂中添加金属颗粒得到。
优选地，所述电磁屏蔽层材质为氮化铝陶瓷。
优选地，所述电磁屏蔽层材质为有机玻璃。
优选地，所述电磁屏蔽层上开设有通孔，所述电路单元为贴片天线，所述贴片天线包括：射频电路，所述射频电路形成于所述二氧化硅层；辐射体， 所述辐射体形成于所述电磁屏蔽层背离所述二氧化硅层的表面；馈线，所述馈线穿过所述通孔连接所述射频电路及辐射体。
优选地，所述电路单元为光敏元件，所述光敏元件形成于所述二氧化硅层，所述电磁屏蔽层为透明或者半透明材质。
优选地，所述电磁屏蔽层上开设有至少两个通孔，所述电路单元为压力传感电路，所述压力传感电路包括：控制器，所述控制器形成于所述二氧化硅层；压力传感器，所述压力传感器设置于电磁屏蔽层背离二氧化硅层的表面；连接线，所述连接线穿过所述通孔连接所述控制器及压力传感器。
为实现上述目的，本发明实施例提供一种电子设备，包括如上述任一项所述的电路单元封装结构。
本发明的电路单元封装结构，所述电路基板、二氧化硅层、电磁屏蔽层依次叠设，而去除了现有技术中的二氧化硅层上的硅层衬底，不仅能够达到良好的电磁屏蔽效果，同时，由于所述电磁屏蔽层为高介电常数材料，具有高效的导电导热特性，可以将所述电路单元工作过程中的热量及时传递散发出去，消除了硅层衬底的低导热、高脆性及低可靠性地不利因素，同时也免去需要在电路基板上再次通过金属形成金属封装壳子的步骤，更加利于批量化生产，且由于去除了硅层衬底，可以使得所述电路单元封装结构的整体厚度变得更薄。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本发明电路单元封装工艺第一实施例的流程示意图；
图2a-2f为本发明电路单元封装工艺一实施例的结构流程示意图；
图3为本发明电路单元封装结构的结构示意图；
图4为本发明电路单元封装工艺步骤S20的具体流程示意图；
图5为本发明电路单元封装工艺步骤S221的具体流程示意图；
图6为本发明电路单元封装工艺第二实施例的流程示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明，本发明实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果所述特定姿态发生改变时，则所述方向性指示也相应地随之改变。
另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本发明要求的保护范围之内。
请一并参照图1-3，其中，所述图2a是电路单元封装工艺中将多个电路单元20间隔倒置贴装于电路基板上的示意图；图2b是塑封环氧树脂的示意图；图2c环氧树脂被研磨后的示意图；图2d硅层衬底被腐蚀后的示意图；图2e形成电磁屏蔽层的示意图；图2f将电路单元切割形成电路模块的示意图。本发明实施例提供的一种电路单元封装工艺用于制造本发明的电路单元封装结构，所述电路单元包括硅层衬底及叠设于硅层衬底上的二氧化硅层，作为本发明的电路单元封装工艺的第1实施例，所述电路单元封装工艺包括以下步骤：
步骤S10，将多个电路单元间隔倒置贴装于电路基板上，其中所述二氧化硅层与所述电路基板贴设，所述硅层衬底背离所述电路基板；
在本实施例中，将多个所述电路单元通过表面贴装技术(SMT，(Surface  Mount Technology)或者DB技术(Die Bond)或者其他贴装工艺贴装于所述电路基板如印刷电路板上，且现有技术中，通常是将所述电路单元正向贴装于所述电路基板上，也即电路单元的硅层衬底与所述电路基板贴装，而所述二氧化硅层则设置于所述硅层衬底上，而本实施例中，所述电路单元为倒置贴装于所述电路基板上，也即所述二氧化硅层与所述电路基板贴设，所述硅层衬底背离所述电路基板设置于所述二氧化硅层上，其目的在于将所述硅层衬底设置于上表面，以便后续去除所述硅层衬底，只保留所述二氧化硅层。
步骤S20，在所述在电路单元之间形成绝缘体；
在本实施例中，所述电路单元之间间隔设置，以在所述电路单元之间填充绝缘体，所述绝缘体可为不导电的环氧树脂等材料，通过涂覆工艺或者点胶工艺在电路基板上形成绝缘介质，并通过研磨工艺去除硅层衬底上的绝缘介质暴露所述硅层衬底，并保留电路单元之间绝缘介质以形成所述绝缘体，所述绝缘体将不同的电路单元绝缘，同时对所述电路单元起到保护作用。
步骤S30，去除所述硅层衬底以暴露所述二氧化硅层；
在本实施例中，可以通过刻蚀工艺或者酸液腐蚀工艺去除所述暴露在上表面的硅层衬底，以将所述二氧化硅层暴露在外表面。
步骤S40，在所述二氧化硅层及绝缘体上形成电磁屏蔽层。
在本实施例中，可以通过涂覆工艺或者点胶工艺或者溅射工艺在所述二氧化硅层及绝缘体上形成电磁屏蔽层，所述电磁屏蔽层形成一个金属屏蔽罩子，将所述电磁屏蔽层内的电路芯片与外部的电磁干扰信号隔离，从而实现电路芯片的高抗谐波干扰。
综上所述，本发明通过将所述电路单元间隔倒置贴装于所述电路基板上，并在所述电路单元之间的空隙上填充绝缘体，之后去除所述电路单元的硅层衬底，再在所述绝缘体和二氧化硅层及上形成电磁屏蔽层，达到良好的电磁屏蔽效果，同时，由于所述电磁屏蔽层为高介电常数材料，具有高效的导电导热特性，可以将所述电路单元工作过程中的热量及时传递散发出去，消除了硅层衬底的低导热、高脆性及低可靠性地不利因素，同时也免去需要在电路基板上再次通过金属形成金属封装壳子的步骤，更加利于批量化生产。
请参阅图2、4，基于上述第1实施例提出本发明的电路单元封装工艺的 第2实施例，所述步骤S20包括：
步骤S21，在所述电路基板上塑封环氧树脂，其中，所述环氧树脂覆盖所述电路基板及所述电路单元且所述环氧树脂填充所述电路单元之间的间隙；
步骤S22，对所述环氧树脂进行研磨处理，以去除覆盖在所述电路单元上的环氧树脂并保留所述电路单元之间的环氧树脂以形成所述绝缘体。
在本实施例中，在所述电路基板上塑封环氧树脂，使得所述环氧树脂塑封整个电路基板的同时，所述环氧树脂填充所述环氧树脂填充所述电路单元之间的间隙，之后通过研磨工艺多所述环氧树脂进行研磨，使得所述环氧树脂的厚度逐渐减薄，直至使得所述电路单元的硅层衬底暴露在表面，此时，剩下填充于所述电路单元之间的环氧树脂形成所述绝缘体，此时，所述绝缘体与所述电路单元的硅层衬底平齐。
基于上述第1-2实施例提出本发明的电路单元封装工艺的第3实施例，所述步骤S22包括：
步骤S221，控制研磨治具与所述环氧树脂同向转动，其中，所述研磨治具与所述环氧树脂的转动速度不同。
在本实施例中，控制研磨治具与所述环氧树脂同向转动，例如研磨治具与所述环氧树脂都逆时针转动或者都顺时针转动，通过所述研磨治具与所述环氧树脂的转速差使得所述研磨治具与所述环氧树脂保持相对运动，所述研磨治具与所述环氧树脂同向转动可以避免时所述研磨治具与所述环氧树脂之间产生巨大的拉力而时所述环氧树脂内的电路单元受力造成损害，提高所述电路单元的良率。
请参阅图5，基于上述第1-3实施例提出本发明的电路单元封装工艺的第4实施例，所述步骤S221包括：
步骤S2211，控制所述研磨治具以第一预设转速转动对所述环氧树脂进行粗磨操作；
步骤S2212，控制所述研磨治具以第二预设转速转动对所述环氧树脂进行细磨操作；
步骤S2213，控制所述研磨治具对所述环氧树脂进行抛光处理；
其中，所述第一预设转速大于第二预设转速。
在本实施例中，对所述环氧树脂进行研磨处理的初始阶段，由于所述环氧树脂较厚，故可先对所述环氧树脂进行粗磨处理，以加快研磨速度，此时，通过研磨治具表面的粗度较大的金刚石对所述环氧树脂进行研磨，例如，可以设定粗磨时所述研磨治具的磨轮进给速度为30mm/s，转速为1200-4500转/分，磨轮上金刚石的粗度为300#，而此时所述环氧树脂的转速为2500-4500转/分。
在细磨阶段，由于所述环氧树脂已经变得较薄，为避免对所述环氧树脂内的电路单元造成损坏，此时，可适当降低所述研磨治具的磨轮进给速度为3mm/s及/或降低所述金刚石的粗度为5000#-8000#，所述研磨治具的磨轮，转速可适当降低或者保持不变但是将所述环氧树脂的速度稍微增大以减小所述研磨治具与环氧树脂之间的速度差，达到细致研磨的效果。
在抛光阶段，通过纱布对所述环氧树脂表面进行研磨，由于纱布硬度不高，对转速和进给速度可以不做限制，通过纱布使得所述环氧树脂表明更加光滑平整，同时去除所述硅层衬底上残留的环氧树脂，使所述硅层衬底完全暴露，便于后续硅层衬底完全去除。
基于上述第1-4实施例提出本发明的电路单元封装工艺的第5实施例，所述步骤S30包括：
步骤S31，通过氢氟酸溶液腐蚀去除所述硅层衬底。
在本实施例中，通过氢氟酸溶液刻蚀掉所述硅层衬底，硅层衬底的主要成分为硅(Si)，其与氢氟酸反应的化学方程式为：Si+4HF＝SiF4↑+2H2↑，如果氢氟酸浓度较大，生成的四氟化硅会形成氟硅酸(H2SiF6)，离子方程式为Si+6HF＝2H++SiF6(2-)+2H2↑，SiF4会不断挥发，这样就打破了化学平衡，上述过程不断因为SiF4的挥发而持续进行，从而可以通过氢氟酸低沉本地去除所述硅层衬底。
优选地，在所述步骤S31中；所述氢氟酸溶液中包括氢氟酸及硫酸钡，所述氢氟酸与硫酸钡的浓度配比为10：1。
在本实施例中，所述硫酸钡的作用在于判断所述硅层衬底的硅是否被完全溶解刻蚀，所述氢氟酸的浓度为1.2ml/L，所述硫酸钡的浓度为0.12ml/L， 所述氢氟酸与硫酸钡的浓度配比为10：1，从而保证所述氢氟酸具有较快的腐蚀速度。
基于上述第1-5实施例提出本发明的电路单元封装工艺的第6实施例，，所述步骤S40包括：
步骤S41，通过点胶工艺或者涂覆工艺或者溅射工艺在所述二氧化硅层上形成所述电磁屏蔽层。
在本实施例中，所述电磁屏蔽层具有电磁屏蔽功能，其材质为半导电银胶或者氮化铝陶瓷或者有机玻璃，其中，所述半导电银胶通过在环氧树脂中添加金属颗粒得到。在所述电路单元光敏元件时，所述半导电银胶、氮化铝陶瓷及有机玻璃为透明或者半透明材质，以使光能从所述电磁屏蔽层进入所述导电屏蔽内被所述光敏元件接收。
请参阅图6，基于上述第1-6实施例提出本发明的电路单元封装工艺的第7实施例，所述步骤S40之后还包括：
步骤S50，将多个所述电路单元沿着所述绝缘体位置切割成多个单独的电路模块。
在本实施例中，将多个所述电路单元沿着所述绝缘体位置切割成多个单独的电路模块，即可将电路模块安装至电子设备中进行使用，本发明通过先在同一块所述电路基板上对不同电路单元进行电磁屏蔽，再将不同电路单元切割成可单独使用的电路模块，提高了生产效率，同时使得每个所述电路模块都高效的导电导热特性，具有较好的电磁屏蔽性能，同时可以将所述电路模块工作过程中的热量及时传递散发出去，消除了硅层衬底的低导热、高脆性及低可靠性地不利因素。
请一并参阅图2-3，为实现上述目的，本发明实施例提供一种电路单元20封装结构100，所述电路单元20封装结构100通过上述电路单元20封装工艺制造形成，所述电路单元20封装结构100包括：电路基板10，所述电路基板10上设置有电路单元20，所述电路单元20包括二氧化硅层21及设置于所述二氧化硅层21上的电子器件(图未示)；绝缘体30，所述绝缘体30围设于 所述电路单元20周围；电磁屏蔽层40，所述电磁屏蔽层40罩设于所述电路单元20及所述绝缘体30上。
在本实施例中，所述电路基板10、二氧化硅层21、电磁屏蔽层40依次叠设，而去除了现有技术中的二氧化硅层21上的硅层衬底23(见图2a-2c)，不仅能够达到良好的电磁屏蔽效果，同时，由于所述电磁屏蔽层40为高介电常数材料，具有高效的导电导热特性，可以将所述电路单元20工作过程中的热量及时传递散发出去，消除了硅层衬底23的低导热、高脆性及低可靠性地不利因素，同时也免去需要在电路基板10上再次通过金属形成金属封装壳子的步骤，更加利于批量化生产，且由于去除了硅层衬底23，可以使得所述电路单元20封装结构100的整体厚度变得更薄，例如当所述电路单元20为RF射频单元时，可将所述电路单元20封装结构100做到400mm的厚度。
优选地，所述绝缘体30凸设于所述电路单元20之间以与所述二氧化硅层21合围形成凹槽22，所述电磁屏蔽层40填充所述凹槽22以与所述二氧化硅层21接触。
在本实施例中，所述凹槽22是所述氢氟酸腐蚀原本电路单元20的硅层衬底23形成的，而所述硅层衬底23未被腐蚀前通过上述研磨工艺与所述绝缘体30保持平齐；所述凹槽22可以供所述电磁屏蔽层40填充其中，从而使所述电磁屏蔽层40与所述二氧化硅层21直接接触，将所述电路单元20产生的热量及时传递出去，且所述电磁屏蔽层40限位于所述凹槽22中，同时与所述二氧化硅层21于绝缘体30连接，可以增强所述电磁屏蔽层40的连接文稳固性。
优选地，所述二氧化硅层21以表面贴装的形式设置于所述电路基板10上。在本实施例中，将多个所述电路单元20通过表面贴装技术(SMT，(Surface Mount Technology)或者DB技术(Die Bond)或者其他贴装工艺贴装于所述电路基板10如印刷电路板上，且所述电路单元20为倒置贴装于所述电路基板10上，也即所述二氧化硅层21与所述电路基板10贴设，所述硅层衬底23背离所述电路基板10设置于所述二氧化硅层21上，其目的在于将所述硅层衬底23设置于上表面，以便后续去除所述硅层衬底23，保留所述二氧化硅层 21与所述磁屏蔽层连接。
优选地，所述电磁屏蔽层40材质为半导电银胶，所述半导电银胶通过在环氧树脂中添加金属颗粒得到，或者所述电磁屏蔽层40材质为氮化铝陶瓷，或者所述电磁屏蔽层40材质为有机玻璃；在所述电路单元20光敏元件时，所述半导电银胶、氮化铝陶瓷及有机玻璃为透明或者半透明材质，以使光能从所述电磁屏蔽层40进入所述导电屏蔽内被所述光敏元件接收。
在一实施例中，所述电磁屏蔽层40上开设有通孔(图未示)，所述电路单元20为贴片天线(图未示)，所述贴片天线包括：射频电路(图未示)，所述射频电路形成于所述二氧化硅层21；辐射体(图未示)，所述辐射体形成于所述电磁屏蔽层40背离所述二氧化硅层21的表面；馈线(图未示)，所述馈线穿过所述通孔连接所述射频电路及辐射体。
在本实施例中，通过在所述电磁屏蔽层40上开设有通孔，所述馈线穿过所述通孔连接所述射频电路及辐射体，从而将所述射频电路的射频信号经馈线传递给所述辐射体，辐射体将射频信号辐射出去，由于所述电磁屏蔽层40的存在，可将所述射频电路的射频信号屏蔽在所述电磁屏蔽层40内，射频电路不会对周边电路产生电磁干扰，且所述电磁屏蔽层40与射频电路直接接触，可以将所述射频电路工作过程中产生的热量传递出去，且由于所述贴片天线没有硅层衬底23，厚度可以做的很薄如400mm，有利于电子产品的轻薄化、扁平化。
优选地，所述电磁屏蔽层40上开设有至少两个通孔(图未示)，所述电路单元20为压力传感电路，所述压力传感电路包括：控制器(图未示)，所述控制器形成于所述二氧化硅层21；压力传感器(图未示)，所述压力传感器设置于电磁屏蔽层40背离二氧化硅层21的表面；连接线(图未示)，所述连接线穿过所述通孔连接所述控制器及压力传感器。
在本实施例中，通过在所述电磁屏蔽层40上开设有通孔，所述连接线穿过所述通孔连接所述控制器及压力传感器，从而将所述压力传感器感测到的压力信号经连接线传递给所述控制器，控制器对所述压力信号进行后续处理，由于所述电磁屏蔽层40的存在，可将外部的电磁干扰新阿红屏蔽在所述电磁 屏蔽层40外部，控制器不会收到周边电路的电磁干扰，且所述电磁屏蔽层40与控制器直接接触，可以将所控制器工作过程中产生的热量传递出去。
可以理解，上述贴片天线及压力传感电路只是所述电路单元20的例举，所述电路单元20可以为任意功能的电路元器件及由多种相同或者不同的电路元器件组成的功能电路。
为实现上述目的，本发明实施例提供一种电子设备，所述电子设备包括如上所述的电路单元20封装结构100，由于所述电子设备包括所述电路单元20封装结构100，因此，至少具有上述电路单元20封装结构100的有益效果，在此不再赘述。
以上所述仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是在本发明的构思下，利用本发明说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本发明的专利保护范围内。

Claims (10)

  1. 一种电路单元封装结构，其特征在于，所述电路单元封装结构包括：
    电路基板，所述电路基板上设置有电路单元，所述电路单元包括二氧化硅层及设置于所述二氧化硅层上的电子器件；
    绝缘体，所述绝缘体围设于所述电路单元周围；
    电磁屏蔽层，所述电磁屏蔽层罩设于所述电路单元及所述绝缘体上。
  2. 根据权利要求1所述的电路单元封装结构，其特征在于，所述绝缘体凸设于所述电路单元之间以与所述二氧化硅层合围形成凹槽，所述电磁屏蔽层填充所述凹槽以与所述二氧化硅层接触。
  3. 根据权利要求1所述的电路单元封装结构，其特征在于，所述二氧化硅层以表面贴装的形式设置于所述电路基板上。
  4. 根据权利要求1所述的电路单元封装结构，其特征在于，所述电磁屏蔽层材质为半导电银胶，所述半导电银胶通过在环氧树脂中添加金属颗粒得到。
  5. 根据权利要求1所述的电路单元封装结构，其特征在于，所述电磁屏蔽层材质为氮化铝陶瓷。
  6. 根据权利要求1所述的电路单元封装结构，其特征在于，所述电磁屏蔽层材质为有机玻璃。
  7. 根据权利要求1所述的电路单元封装结构，其特征在于，所述电磁屏蔽层上开设有通孔，所述电路单元为贴片天线，所述贴片天线包括：
    射频电路，所述射频电路形成于所述二氧化硅层；
    辐射体，所述辐射体形成于所述电磁屏蔽层背离所述二氧化硅层的表面；
    馈线，所述馈线穿过所述通孔连接所述射频电路及辐射体。
  8. 根据权利要求1所述的电路单元封装结构，其特征在于，所述电路单元为光敏元件，所述光敏元件形成于所述二氧化硅层，所述电磁屏蔽层为透明或者半透明材质。
  9. 根据权利要求1所述的电路单元封装结构，其特征在于，所述电磁屏蔽层上开设有至少两个通孔，所述电路单元为压力传感电路，所述压力传感电路包括：
    控制器，所述控制器形成于所述二氧化硅层；
    压力传感器，所述压力传感器设置于电磁屏蔽层背离二氧化硅层的表面；
    连接线，所述连接线穿过所述通孔连接所述控制器及压力传感器。
  10. 一种电子设备，其特征在于，包括如权利要求1-9任一项所述的电路单元封装结构。
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