WO2020248762A1 - 供电控制电路、供电控制方法和显示装置 - Google Patents

供电控制电路、供电控制方法和显示装置 Download PDF

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Publication number
WO2020248762A1
WO2020248762A1 PCT/CN2020/090278 CN2020090278W WO2020248762A1 WO 2020248762 A1 WO2020248762 A1 WO 2020248762A1 CN 2020090278 W CN2020090278 W CN 2020090278W WO 2020248762 A1 WO2020248762 A1 WO 2020248762A1
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Prior art keywords
level signal
transistor
output terminal
power supply
resistor
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PCT/CN2020/090278
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English (en)
French (fr)
Inventor
黄建邦
何林昌
刘长波
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/973,752 priority Critical patent/US20210304651A1/en
Publication of WO2020248762A1 publication Critical patent/WO2020248762A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3218—Monitoring of peripheral devices of display devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3265—Power saving in display device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a power supply control circuit, a power supply control method, and a display device.
  • AOD Always On Display
  • embodiments of the present disclosure provide a power supply control circuit for supplying power to a display panel.
  • a first power input terminal of the power supply control circuit is electrically connected to a power output terminal of a power management integrated circuit PMIC.
  • the second power input terminal of the circuit is electrically connected with the power output terminal of the driving integrated circuit DDIC, and the power output terminal of the power supply control circuit is electrically connected with the power receiving terminal of the display panel;
  • the power supply control circuit is configured to receive the first display voltage when the power output terminal of the PMIC outputs the first display voltage, and transmit the first display voltage to the display panel, so that the display panel Bright screen display;
  • the power supply control circuit is used to receive the second display voltage output by the power output terminal of the DDIC when the power output terminal of the PMIC does not output the first display voltage, and transmit the second display voltage to the The display panel enables the display panel to be displayed on the screen.
  • the power output terminal of the PMIC includes a first high-level signal output terminal and a first low-level signal output terminal;
  • the power output terminal of the DDIC includes a second high-level signal output terminal and a second low-level signal output terminal;
  • the power receiving end of the display panel includes a high-level signal receiving end and a low-level signal receiving end;
  • the first display voltage includes a first high-level signal and a first low-level signal
  • the second display voltage includes a second high-level signal and a second low-level signal
  • the power supply control circuit includes a first control sub-circuit and a second control sub-circuit
  • the first control sub-circuit receives the first high-level signal from the first high-level signal output terminal, and sets the first high-level signal The level signal is transmitted to the high-level signal receiving terminal, the second control sub-circuit receives the first low-level signal from the first low-level signal output terminal, and transfers the first low-level signal The flat signal is transmitted to the low-level signal receiving end, so that the display panel is displayed on the bright screen;
  • the first control sub-circuit receives the second high voltage from the second high level signal output terminal Signal and transmit the second high-level signal to the high-level signal receiving end
  • the second control sub-circuit receives the second low-level signal from the second low-level signal output end Signal and transmit the second low-level signal to the low-level signal receiving end, so that the display panel displays on the screen.
  • the first control sub-circuit includes a first transistor and a second transistor
  • the first electrode of the first transistor is electrically connected to the high-level signal output end of the PMIC, the second electrode of the first transistor is electrically connected to the high-level signal receiving end of the display panel, and the The control electrode of a transistor is electrically connected to the high-level signal output terminal of the DDIC;
  • the first electrode of the second transistor is electrically connected to the high-level signal output terminal of the DDIC, the second electrode of the second transistor is electrically connected to the ground terminal, and the control electrode of the second transistor is electrically connected to the PMIC.
  • the high-level signal output terminal is electrically connected.
  • the first control sub-circuit further includes a first resistor, one end of the first resistor is connected to the control electrode of the first transistor, and the other end of the first resistor is connected to the second end of the first transistor. Two-pole connection.
  • the second control sub-circuit includes a third transistor and a fourth transistor
  • the first electrode of the third transistor is electrically connected to the low-level signal output end of the PMIC
  • the second electrode of the third transistor is electrically connected to the low-level signal receiving end of the display panel
  • the The control electrode of the three-transistor is electrically connected to the low-level signal output terminal of the DDIC
  • the first pole of the fourth transistor is electrically connected to the low-level signal output end of the DDIC
  • the second pole of the fourth transistor is electrically connected to the high-level signal output end of the DDIC
  • the fourth The control electrode of the transistor is electrically connected to the ground terminal.
  • the second control sub-circuit further includes a second resistor, one end of the second resistor is connected to the control electrode of the third transistor, and the other end of the second resistor is connected to the third transistor of the third transistor. Two-pole connection.
  • embodiments of the present disclosure also provide a power supply control method, which is applied to the power supply control circuit described above, and the method includes:
  • the power supply control circuit When the power output terminal of the PMIC outputs the first display voltage, the power supply control circuit receives the first display voltage and transmits the first display voltage to the display panel, so that the display panel displays on a bright screen ;
  • the power supply control circuit receives the second display voltage output by the power output terminal of the DDIC and transmits the second power to the display panel, so that The display panel displays on the screen.
  • embodiments of the present disclosure also provide a display device, including a power management integrated circuit PMIC, a driving integrated circuit DDIC, and a display panel, and the display device further includes the power supply control circuit described above.
  • control terminal of the DDIC is connected to the power output terminal of the PMIC
  • the DDIC is used to output a second display voltage through the power output terminal of the DDIC when the power output terminal of the PMIC does not output the first display voltage.
  • Fig. 1 is a circuit diagram of a power supply control circuit transmitting a high-level signal in the related art
  • Fig. 2 is a circuit diagram of a power supply control circuit transmitting low-level signals in the related art
  • FIG. 3 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • FIG. 4 is a circuit diagram of a first control circuit in a power supply control circuit provided by an embodiment of the disclosure
  • FIG. 5 is a circuit diagram of a second control circuit in the power supply control circuit provided by an embodiment of the disclosure.
  • FIG. 6 is a flowchart of a power supply control method provided by an embodiment of the disclosure.
  • PMIC Power Management Integrated Circuit
  • ELVDD_GPIO in Figure 1 is the high-level control signal output terminal of the CPU
  • ELVSS_GPIO in Figure 2 is the low-level control signal output terminal of the CPU
  • the external circuits in Figures 1 and 2 need to be based on the high-voltage CPU
  • the signal output from the output terminal of the level control signal and the output terminal of the low level control signal switch to provide the voltage required for bright screen display or full screen display to the display panel.
  • the embodiments of the present disclosure provide a power supply control circuit, a power supply control method, and a display device to solve the problem that when the PMIC inside the display device does not support the AOD function in the related art, the external circuit used to support the AOD function needs to occupy the display device The problem of system resources.
  • An embodiment of the present disclosure provides a power supply control circuit for supplying power to a display panel.
  • the first power input terminal of the power supply control circuit is electrically connected to the power output terminal of the power management integrated circuit PMIC.
  • the second power input terminal of the power supply control circuit is electrically connected with the power output terminal of the drive integrated circuit DDIC, and the power output terminal of the power supply control circuit is electrically connected with the power receiving terminal of the display panel;
  • the power supply control circuit is configured to receive the first display voltage when the power output terminal of the PMIC outputs the first display voltage, and transmit the first display voltage to the display panel, so that the display panel Bright screen display;
  • the power supply control circuit is used to receive the second display voltage output by the power output terminal of the DDIC when the power output terminal of the PMIC does not output the first display voltage, and transmit the second display voltage to the The display panel enables the display panel to be displayed on the screen.
  • the power supply control circuit uses whether the PMIC outputs the first display voltage as a basis for the display panel to switch between the bright screen display mode and the non-screen display mode. It does not need to be connected to the controller of the display device, that is, it will not occupy the display device.
  • System resources can save the system resources of the display device under the premise of ensuring the normal operation of the AOD function. Therefore, the technical solution provided by the present disclosure can save the system resources of the display device while ensuring the normal operation of the AOD function.
  • the above-mentioned display panel may be a liquid crystal display panel, an Organic Light-Emitting Diode (OLED) display panel, or a quantum dot display panel, etc.
  • OLED Organic Light-Emitting Diode
  • the embodiments of the present disclosure do not limit the specific display of the display panel. panel.
  • the PMIC is the power management integrated circuit of the display device, which can undertake the power conversion, distribution, detection and other power management responsibilities during the overall working process of the display device.
  • the PMIC can provide the voltage required for the bright screen display of the display panel, and the bright screen display of the display panel means that the whole display panel emits light.
  • the first power input terminal of the power supply control circuit is connected to the power output terminal of the PMIC.
  • the power supply control circuit transmits the first display voltage to the display panel.
  • DDIC is the driving circuit in the imaging system of the display device, which can be responsible for driving the display panel and controlling the driving current.
  • DDIC can drive the luminous display of monochromatic, dual-color and full-color display panels.
  • the DDIC can provide the voltage required to make the display panel display on the screen.
  • the screen display is a part of the display panel that emits light and the rest is black.
  • the second power input terminal of the power supply control circuit is connected to the power output terminal of the DDIC.
  • the power supply control circuit transmits the second display voltage provided by the DDIC to the display panel.
  • DDIC can continuously provide the second display voltage, and the power supply control circuit chooses to transmit the second display voltage to the display panel when the power output terminal of the PMIC does not output the first display voltage; or, DDIC can also be connected to the PMIC and detect the PMIC Whether to output the first display voltage, as shown in Figure 3, the second display voltage is output when the PMIC does not output the first display voltage, so that the power supply control circuit displays the second display voltage when the PMIC’s power output terminal does not output the first display voltage. The voltage is transmitted to the display panel.
  • the solution shown in FIG. 3 can reduce the power consumption of the display device, and the specific structure of the solution shown in FIG. 3 will be described later.
  • the power output terminal of the PMIC includes a first high-level signal output terminal and a first low-level signal output terminal;
  • the power output terminal of the DDIC includes a second high-level signal output terminal and a second low-level signal output terminal;
  • the power receiving end of the display panel includes a high-level signal receiving end and a low-level signal receiving end;
  • the first display voltage includes a first high-level signal and a first low-level signal
  • the second display voltage includes a second high-level signal and a second low-level signal
  • the power supply control circuit includes a first control sub-circuit and a second control sub-circuit
  • the first control sub-circuit receives the first high-level signal from the first high-level signal output terminal, and sets the first high-level signal The level signal is transmitted to the high-level signal receiving terminal, the second control sub-circuit receives the first low-level signal from the first low-level signal output terminal, and transfers the first low-level signal The flat signal is transmitted to the low-level signal receiving end, so that the display panel is displayed on the bright screen;
  • the first control sub-circuit receives the second high voltage from the second high level signal output terminal Signal and transmit the second high-level signal to the high-level signal receiving end
  • the second control sub-circuit receives the second low-level signal from the second low-level signal output end Signal and transmit the second low-level signal to the low-level signal receiving end, so that the display panel displays on the screen.
  • the second control sub-circuit When the first control sub-circuit is used to transmit the first high-level signal, the second control sub-circuit is used to transmit the first low-level signal; when the first control sub-circuit is used to transmit the second high-level signal, the The second control sub-circuit is used to transmit the second low-level signal.
  • the first control sub-circuit and the second control sub-circuit cooperate to jointly complete the transmission of the first display voltage or the second display voltage to ensure that the display panel can display normally.
  • the first input terminal of the first control sub-circuit is electrically connected to the first high-level signal output terminal of the PMIC, and the second input terminal of the first control sub-circuit is connected to the second high-level signal output terminal of the DDIC.
  • the level signal output terminal is electrically connected, and the output terminal of the first control sub-circuit is electrically connected to the high level signal receiving terminal of the display panel;
  • the first input terminal of the second control sub-circuit is electrically connected to the first low-level signal output terminal of the PMIC, and the second input terminal of the second control sub-circuit is connected to the second low level of the DDIC
  • the signal output terminal is electrically connected, and the output terminal of the second control sub-circuit is connected to the low-level signal receiving terminal of the display panel.
  • the first control sub-circuit includes a first transistor Q1 and a second transistor Q2;
  • the first pole of the first transistor Q1 is electrically connected to the high-level signal output end of the PMIC, and the second pole of the first transistor Q1 is electrically connected to the high-level signal receiving end of the display panel, so The control electrode of the first transistor Q1 is electrically connected to the high-level signal output terminal of the DDIC;
  • the first electrode of the second transistor Q2 is electrically connected to the high-level signal output terminal of the DDIC, the second electrode of the second transistor Q2 is electrically connected to the ground terminal, and the control electrode of the second transistor Q2 is electrically connected to The high-level signal output terminal of the PMIC is electrically connected.
  • ELVDD_A in Figures 4 and 5 is the high-level signal output terminal of PMIC
  • ELVSS_A is the low-level signal output terminal of PMIC
  • ELVDD_B is the high-level signal receiving terminal of the display panel
  • ELVSS_B is the low-level signal output terminal of the display panel.
  • Level signal receiving terminal ELVDD_C is the high-level signal output terminal of DDIC
  • ELVSS_C is the low-level signal output terminal of DDIC.
  • the high-level output terminal of the PMIC When the display panel needs to be brightly displayed, the high-level output terminal of the PMIC outputs a high-level signal and the high-level output terminal of the DDIC does not output a high-level signal.
  • node A in Figure 4 (the first transistor of the first transistor)
  • the potential of the node D (the control electrode of the second transistor) is high
  • the potential of the node C (the control electrode of the first transistor) is 0V, causing the first transistor Q1 and the second transistor Q2 to be turned on, so that the node B
  • the potential of (the second pole of the first transistor) is also high, and the high-level signal output by the PMIC is transmitted to the display panel.
  • the high-level output terminal of the PMIC does not output a high-level signal and the high-level output terminal of the DDIC outputs a high-level signal.
  • the nodes A and D in Figure 4 are 0V.
  • the first transistor Q1 and the second transistor Q2 are turned off, the node B and the node C are high, and the high-level signal output by the DDIC is transmitted to the display panel.
  • the voltage value of the above-mentioned high-level signal can be between 3.5V and 5.5V, such as 4.6V, but is not limited to this.
  • the first control sub-circuit may further include a first resistor R1, one end of the first resistor R1 is connected to the control electrode of the first transistor Q1, and the other end of the first resistor R1 is connected to the The second electrode of the first transistor Q1 is connected.
  • the first resistor R1 is used to limit the current between the node B and the node C, and protect the display panel from damage by the large current.
  • the resistance value of the first resistor R1 may be 100K ⁇ .
  • the first control sub-circuit may further include a third resistor R3 and a fourth resistor R4.
  • One end of the third resistor R3 is connected to the second pole of the second transistor Q2, and the other end of the third resistor R3 is connected to the ground terminal.
  • One end of the fourth resistor R4 is connected to the control electrode of the second transistor Q2, and the other end of the fourth resistor R4 is connected to the ground.
  • the resistance value of the third resistor R3 and the fourth resistor R4 may be 100K ⁇ .
  • the second control sub-circuit includes a third transistor Q3 and a fourth transistor Q4;
  • the first pole of the third transistor Q3 is electrically connected to the low-level signal output end of the PMIC, and the second pole of the third transistor Q3 is electrically connected to the low-level signal receiving end of the display panel, so The control electrode of the third transistor Q3 is electrically connected to the low-level signal output terminal of the DDIC;
  • the first pole of the fourth transistor Q4 is electrically connected to the low-level signal output terminal of the DDIC, and the second pole of the fourth transistor Q4 is electrically connected to the high-level signal output terminal of the DDIC.
  • the control electrode of the fourth transistor Q4 is electrically connected to the ground terminal.
  • the high-level output terminal of the PMIC outputs a high-level signal
  • the low-level output terminal of the PMIC outputs a low-level signal
  • the low-level output terminal of DDIC does not output a low-level signal.
  • the node E (the first pole of the third transistor) is at a low potential
  • the node H (the second pole of the fourth transistor) is at a high potential
  • the fourth transistor Q4 to turn on, so that the node G (the third transistor's The potential of the control pole) is 4.6V, which in turn causes the third transistor Q3 to be turned on, so that the potential of the node F (the second pole of the third transistor) is also low, and the low-level signal output by the PMIC is transmitted to the display panel.
  • the high-level output terminal of the PMIC does not output high-level signals
  • the low-level output terminal of the PMIC does not output low-level signals
  • the low-level output terminal of DDIC outputs low-level signals.
  • the potentials of node E and node H in FIG. 5 are 0V
  • the third transistor Q3 and the fourth transistor Q4 are turned off, and the potentials of node F and node G are low, so that the low-level signal output by DDIC is transmitted to the display panel .
  • the voltage value of the aforementioned low-level signal can be between -1.8V and -3.8V, such as -2.4V, but is not limited to this.
  • the second control sub-circuit further includes a second resistor R2, one end of the second resistor R2 is connected to the control electrode of the third transistor Q3, and the other end of the second resistor R2 is connected to the third transistor Q3.
  • the second pole of the three transistor Q3 is connected.
  • the second resistor R2 is used to limit the current between the node F and the node G, and protect the display panel from being damaged by a large current.
  • the resistance value of the second resistor R2 may be 100K ⁇ .
  • the second control sub-circuit may further include a fifth resistor R5 and a sixth resistor R6.
  • One end of the fifth resistor R5 is connected to the second pole of the fourth transistor Q4, and the other end of the fifth resistor R5 is connected to the ground terminal.
  • One end of the sixth resistor R6 is connected to the control electrode of the fourth transistor Q4, and the other end of the sixth resistor R6 is connected to the ground.
  • the resistance value of the fifth resistor R5 and the sixth resistor R6 may be 100K ⁇ .
  • the above-mentioned transistors can all be transistors, thin film transistors or field effect transistors or other devices with the same characteristics. Among them, in order to distinguish the two poles of the transistor except the control electrode, one of the poles is called The first pole and the other pole are called the second pole.
  • the control electrode when the transistor is a triode, can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base.
  • the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the first transistor Q1 in FIG. 4 can be a P-type field effect transistor (the first electrode of the first transistor Q1 has a source, and the second electrode of the first transistor Q1 has a drain), and the second transistor Q2 can be an NPN-type transistor. (The first electrode of the second transistor Q2 is the collector, and the second electrode of the second transistor Q2 is the emitter); another example: the third transistor Q3 in FIG. 5 can be an N-type field effect transistor (the first transistor Q1 The electrode is the drain, the second electrode of the first transistor Q1 is the source), and the fourth transistor Q4 can be a PNP transistor (the first electrode of the second transistor Q2 is the emitter, and the second electrode of the second transistor Q2 is the collector).
  • the embodiment of the present disclosure also provides a power supply control method, which is applied to the above-mentioned power supply control circuit. As shown in FIG. 6, the method includes:
  • Step 601 When the power output terminal of the PMIC outputs the first display voltage, the power supply control circuit receives the first display voltage and transmits the first display voltage to the display panel, so that the display panel Bright screen display;
  • Step 602 When the power output terminal of the PMIC does not output the first display voltage, the power supply control circuit receives the second display voltage output by the power output terminal of the DDIC and transmits the second power to the display Panel, the display panel is displayed on the screen.
  • the power supply control circuit uses whether the PMIC outputs the first display voltage as a basis for the display panel to switch between the bright screen display mode and the non-screen display mode. It does not need to be connected to the controller of the display device, that is, it will not occupy the System resources can save the system resources of the display device under the premise of ensuring the normal operation of the AOD function. Therefore, the technical solution provided by the present disclosure can save the system resources of the display device while ensuring the normal operation of the AOD function.
  • the above-mentioned display panel may be a liquid crystal display panel, an Organic Light-Emitting Diode (OLED) display panel, or a quantum dot display panel, etc.
  • OLED Organic Light-Emitting Diode
  • the embodiments of the present disclosure do not limit the specific display of the display panel. panel.
  • the PMIC is the power management integrated circuit of the display device, which can undertake the power conversion, distribution, detection and other power management responsibilities during the overall working process of the display device.
  • the PMIC can provide the voltage required for the bright screen display of the display panel, that is, the entire display panel to emit light.
  • the first power input terminal of the power supply control circuit is connected to the power output terminal of the PMIC.
  • the power supply control circuit transmits the first display voltage to the display panel.
  • DDIC is the driving circuit in the imaging system of the display device, which can be responsible for driving the display panel and controlling the driving current.
  • DDIC can drive the single-color, dual-color and full-color display panel to emit light.
  • DDIC can provide the display panel to display on the screen, that is, part of the display panel is illuminated and displayed, and the rest is black.
  • the second power input terminal of the power supply control circuit is connected to the power output terminal of the DDIC.
  • the power supply control circuit transmits the second display voltage provided by the DDIC to the display panel.
  • DDIC can continuously provide the second display voltage, and the power supply control circuit chooses to transmit the second display voltage to the display panel when the power output terminal of the PMIC does not output the first display voltage; or, DDIC can also be connected to the PMIC and detect the PMIC Whether to output the first display voltage, as shown in Figure 3, the second display voltage is output when the PMIC does not output the first display voltage, so that the power supply control circuit displays the second display voltage when the PMIC’s power output terminal does not output the first display voltage. The voltage is transmitted to the display panel.
  • the solution shown in FIG. 3 can reduce the power consumption of the display device, and the specific structure of the solution shown in FIG. 3 will be described later.
  • the embodiments of the present disclosure also provide a display device, including a power management integrated circuit PMIC, a driving integrated circuit DDIC, and a display panel.
  • the display device further includes the power supply control circuit as described above.
  • the display device can be a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
  • control terminal of the DDIC is connected to the power output terminal of the PMIC
  • the DDIC is used to output a second display voltage through the power output terminal of the DDIC when the power output terminal of the PMIC does not output the first display voltage.
  • DDIC can detect whether the PMIC outputs the first display voltage, DDIC does not output the second display voltage when the PMIC outputs the first display voltage; DDIC outputs the second display voltage when the PMIC does not output the first display voltage.

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Abstract

本公开提供一种供电控制电路、供电控制方法和显示装置，其中，供电控制电路，用于为显示面板供电，所述供电控制电路的第一电能输入端与电源管理集成电路PMIC的电能输出端电连接，所述供电控制电路的第二电能输入端与驱动集成电路DDIC的电能输出端电连接，所述供电控制电路的电能输出端与所述显示面板的电能接收端电连接。

Description

供电控制电路、供电控制方法和显示装置
相关申请的交叉引用
本申请主张在2019年6月14日在中国提交的中国专利申请号No.201910515531.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种供电控制电路、供电控制方法和显示装置。
背景技术
目前很多显示装置在点亮屏幕时只是为了查看时间和通知消息，此时如果屏幕整体亮起显示，耗电量高，因此显示装置逐渐出现了息屏显示(Always On Display，简称AOD)功能，即在不点亮整块屏幕的前提下在屏幕的部分区域显示时间、通知消息等内容，这样显示装置的功耗会大幅降低。然而，一些显示装置为了实现AOD功能，占用了显示装置的系统资源。
发明内容
第一方面，本公开实施例提供一种供电控制电路，用于为显示面板供电，所述供电控制电路的第一电能输入端与电源管理集成电路PMIC的电能输出端电连接，所述供电控制电路的第二电能输入端与驱动集成电路DDIC的电能输出端电连接，所述供电控制电路的电能输出端与所述显示面板的电能接收端电连接；
所述供电控制电路用于在所述PMIC的电能输出端输出第一显示电压时，接收所述第一显示电压，并将所述第一显示电压传输至所述显示面板，使所述显示面板亮屏显示；
所述供电控制电路用于在所述PMIC的电能输出端未输出第一显示电压时，接收所述DDIC的电能输出端输出的第二显示电压，并将所述第二显示电压传输至所述显示面板，使所述显示面板息屏显示。
所述PMIC的电能输出端包括第一高电平信号输出端和第一低电平信号输出端；
所述DDIC的电能输出端包括第二高电平信号输出端和第二低电平信号输出端；
所述显示面板的电能接收端包括高电平信号接收端和低电平信号接收端；
所述第一显示电压包括第一高电平信号和第一低电平信号，所述第二显示电压包括第二高电平信号和第二低电平信号；
所述供电控制电路包括第一控制子电路和第二控制子电路；
在所述PMIC的电能输出端输出第一显示电压时，所述第一控制子电路从所述第一高电平信号输出端接收所述第一高电平信号，并将所述第一高电平信号传输至所述高电平信号接收端，所述第二控制子电路从所述第一低电平信号输出端接收所述第一低电平信号，并将所述第一低电平信号传输至所述低电平信号接收端，使所述显示面板亮屏显示；
在所述PMIC的电能输出端未输出第一显示电压且所述DDIC输出第二显示电压时，所述第一控制子电路从所述第二高电平信号输出端接收所述第二高电平信号，并将所述第二高电平信号传输至所述高电平信号接收端，所述第二控制子电路从所述第二低电平信号输出端接收所述第二低电平信号，并将所述第二低电平信号传输至所述低电平信号接收端，使所述显示面板息屏显示。
进一步地，所述第一控制子电路包括第一晶体管和第二晶体管；
所述第一晶体管的第一极与所述PMIC的高电平信号输出端电连接，所述第一晶体管的第二极与所述显示面板的高电平信号接收端电连接，所述第一晶体管的控制极与所述DDIC的高电平信号输出端电连接；
所述第二晶体管的第一极与所述DDIC的高电平信号输出端电连接，所述第二晶体管的第二极与接地端电连接，所述第二晶体管的控制极与所述PMIC的高电平信号输出端电连接。
进一步地，所述第一控制子电路还包括第一电阻，所述第一电阻的一端与所述第一晶体管的控制极连接，所述第一电阻的另一端与所述第一晶体管的第二极连接。
进一步地，所述第二控制子电路包括第三晶体管和第四晶体管；
所述第三晶体管的第一极与所述PMIC的低电平信号输出端电连接，所述第三晶体管的第二极与所述显示面板的低电平信号接收端电连接，所述第三晶体管的控制极与所述DDIC的低电平信号输出端电连接；
所述第四晶体管的第一极与所述DDIC的低电平信号输出端电连接，所述第四晶体管的第二极与所述DDIC的高电平信号输出端电连接，所述第四晶体管的控制极与接地端电连接。
进一步地，所述第二控制子电路还包括第二电阻，所述第二电阻的一端与所述第三晶体管的控制极连接，所述第二电阻的另一端与所述第三晶体管的第二极连接。
第二方面，本公开实施例还提供一种供电控制方法，应用于如上所述的供电控制电路，所述方法包括：
在所述PMIC的电能输出端输出第一显示电压时，所述供电控制电路接收所述第一显示电压并将所述第一显示电压传输至所述显示面板，使所述显示面板亮屏显示；
在所述PMIC的电能输出端未输出第一显示电压时，所述供电控制电路接收所述DDIC的电能输出端输出的第二显示电压并将所述第二电能传输至所述显示面板，使所述显示面板息屏显示。
第三方面，本公开实施例还提供一种显示装置，包括电源管理集成电路PMIC、驱动集成电路DDIC和显示面板，所述显示装置还包括如上所述的供电控制电路。
进一步地，所述DDIC的控制端与所述PMIC的电能输出端连接；
所述DDIC用于在所述PMIC的电能输出端未输出第一显示电压时，通过所述DDIC的电能输出端输出第二显示电压。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳 动性的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中供电控制电路传输高电平信号的电路图；
图2为相关技术中供电控制电路传输低电平信号的电路图；
图3为本公开一实施例提供的显示装置的结构示意图；
图4为本公开一实施例提供的供电控制电路中第一控制电路的电路图；
图5为本公开一实施例提供的供电控制电路中第二控制电路的电路图；
图6为本公开一实施例提供的供电控制方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
相关技术中，仅有部分型号的电源管理集成电路(Power Management Integrated Circuit，简称PMIC)支持AOD功能，在显示装置内部的PMIC不支持AOD功能时，显示装置只能增加外部电路来支持AOD功能，如图1和图2所示，此时需要借助显示装置的控制器(CPU)来作为外部电路的开关，占用了显示装置的系统资源。具体的，图1中的ELVDD_GPIO为CPU的高电平控制信号输出端，图2中的ELVSS_GPIO为CPU的低电平控制信号输出端，图1和图2中的外部电路需要基于CPU的高电平控制信号输出端和低电平控制信号输出端输出的信号，切换向显示面板提供亮屏显示或息屏显示所需的电压。
本公开实施例针对上述问题，提供一种供电控制电路、供电控制方法和显示装置，以解决相关技术中显示装置内部的PMIC不支持AOD功能时，用于支持AOD功能的外部电路需要占用显示装置的系统资源的问题。
本公开实施例提供一种供电控制电路，用于为显示面板供电，如图3所示，所述供电控制电路的第一电能输入端与电源管理集成电路PMIC的电能输出端电连接，所述供电控制电路的第二电能输入端与驱动集成电路DDIC的电能输出端电连接，所述供电控制电路的电能输出端与所述显示面板的电 能接收端电连接；
所述供电控制电路用于在所述PMIC的电能输出端输出第一显示电压时，接收所述第一显示电压，并将所述第一显示电压传输至所述显示面板，使所述显示面板亮屏显示；
所述供电控制电路用于在所述PMIC的电能输出端未输出第一显示电压时，接收所述DDIC的电能输出端输出的第二显示电压，并将所述第二显示电压传输至所述显示面板，使所述显示面板息屏显示。
本公开实施例中，供电控制电路根据PMIC是否输出第一显示电压作为显示面板在亮屏显示模式和息屏显示模式切换的依据，无需与显示装置的控制器连接，即不会占用显示装置的系统资源，在确保AOD功能正常工作的前提下，能够节约显示装置的系统资源。因此，本公开提供的技术方案能够在确保AOD功能正常工作的前提下，节约显示装置的系统资源。
上述显示面板可以是液晶显示面板，也可以是有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板，还可以是量子点显示面板等，本公开实施例并不限定显示面板具体为何种显示面板。
PMIC为显示装置的电源管理集成电路，在显示装置整体工作过程中可以承担对电能的变换、分配、检测及其他电能管理的职责的芯片。本公开实施例中，PMIC能够提供使显示面板亮屏显示所需的电压，显示面板亮屏显示即显示面板整体发光显示。
供电控制电路的第一电能输入端与PMIC的电能输出端连接，在PMIC的电能输出端输出第一显示电压时，供电控制电路将第一显示电压传输至显示面板。
DDIC为显示装置成像系统中的驱动电路，可以负责驱动显示面板和控制驱动电流，DDIC能够驱动单色、双色和全彩的显示面板发光显示。本公开实施例中，DDIC能够提供使显示面板息屏显示所需的电压，息屏显示即显示面板部分区域发光显示，其余部分黑屏。
供电控制电路的第二电能输入端与DDIC的电能输出端连接，在PMIC的电能输出端未输出第一显示电压时，供电控制电路将DDIC提供的第二显示电压传输至显示面板。
其中，DDIC可以是持续提供第二显示电压，供电控制电路在PMIC的电能输出端未输出第一显示电压时选择将第二显示电压传输至显示面板；或者，DDIC也可以与PMIC连接并检测PMIC是否输出第一显示电压，如图3所示，在PMIC未输出第一显示电压时才输出第二显示电压，从而供电控制电路在PMIC的电能输出端未输出第一显示电压时将第二显示电压传输至显示面板。图3所示方案能够降低显示装置的功耗，后续均以图3所示方案对具体结构进行说明。
进一步地，所述PMIC的电能输出端包括第一高电平信号输出端和第一低电平信号输出端；
所述DDIC的电能输出端包括第二高电平信号输出端和第二低电平信号输出端；
所述显示面板的电能接收端包括高电平信号接收端和低电平信号接收端；
所述第一显示电压包括第一高电平信号和第一低电平信号，所述第二显示电压包括第二高电平信号和第二低电平信号；
所述供电控制电路包括第一控制子电路和第二控制子电路；
在所述PMIC的电能输出端输出第一显示电压时，所述第一控制子电路从所述第一高电平信号输出端接收所述第一高电平信号，并将所述第一高电平信号传输至所述高电平信号接收端，所述第二控制子电路从所述第一低电平信号输出端接收所述第一低电平信号，并将所述第一低电平信号传输至所述低电平信号接收端，使所述显示面板亮屏显示；
在所述PMIC的电能输出端未输出第一显示电压且所述DDIC输出第二显示电压时，所述第一控制子电路从所述第二高电平信号输出端接收所述第二高电平信号，并将所述第二高电平信号传输至所述高电平信号接收端，所述第二控制子电路从所述第二低电平信号输出端接收所述第二低电平信号，并将所述第二低电平信号传输至所述低电平信号接收端，使所述显示面板息屏显示。
在第一控制子电路用于传输第一高电平信号时，第二控制子电路用于传输第一低电平信号；在第一控制子电路用于传输第二高电平信号时，第二控制子电路用于传输第二低电平信号。
本实施例中，通过第一控制子电路和第二控制子电路配合，共同完成第一显示电压或第二显示电压的传输，确保显示面板能够正常显示。
其中，所述第一控制子电路的第一输入端与所述PMIC的第一高电平信号输出端电连接，所述第一控制子电路的第二输入端与所述DDIC的第二高电平信号输出端电连接，所述第一控制子电路的输出端与所述显示面板的高电平信号接收端电连接；
所述第二控制子电路的第一输入端与所述PMIC的第一低电平信号输出端电连接，所述第二控制子电路的第二输入端与所述DDIC的第二低电平信号输出端电连接，所述第二控制子电路的输出端与所述显示面板的低电平信号接收端连接。
进一步地，如图4所示，所述第一控制子电路包括第一晶体管Q1和第二晶体管Q2；
所述第一晶体管Q1的第一极与所述PMIC的高电平信号输出端电连接，所述第一晶体管Q1的第二极与所述显示面板的高电平信号接收端电连接，所述第一晶体管Q1的控制极与所述DDIC的高电平信号输出端电连接；
所述第二晶体管Q2的第一极与所述DDIC的高电平信号输出端电连接，所述第二晶体管Q2的第二极与接地端电连接，所述第二晶体管Q2的控制极与所述PMIC的高电平信号输出端电连接。
其中，图4和图5中的ELVDD_A为PMIC的高电平信号输出端，ELVSS_A为PMIC的低电平信号输出端；ELVDD_B为显示面板的高电平信号接收端，ELVSS_B为显示面板的低电平信号接收端；ELVDD_C为DDIC的高电平信号输出端，ELVSS_C为DDIC的低电平信号输出端。
在需要显示面板亮屏显示时，PMIC的高电平输出端输出高电平信号且DDIC的高电平输出端不输出高电平信号，此时图4中节点A(第一晶体管的第一极)和节点D(第二晶体管的控制极)的电位为高电位，节点C(第一晶体管的控制极)的电位为0V，导致第一晶体管Q1和第二晶体管Q2导通，从而节点B(第一晶体管的第二极)的电位也为高电位，PMIC输出的高电平信号传输至显示面板。
在需要显示面板息屏显示时，PMIC的高电平输出端不输出高电平信号且 DDIC的高电平输出端输出高电平信号，此时图4中的节点A和节点D为0V，导致第一晶体管Q1和第二晶体管Q2关断，节点B和节点C为高电位，DDIC输出的高电平信号传输至显示面板。
其中，上述高电平信号的电压值可以在3.5V至5.5V之间，例如4.6V，但不以此为限。
进一步地，所述第一控制子电路还可以包括第一电阻R1，所述第一电阻R1的一端与所述第一晶体管Q1的控制极连接，所述第一电阻R1的另一端与所述第一晶体管Q1的第二极连接。
第一电阻R1用于限制节点B和节点C之间的电流，保护显示面板免于大电流的破坏。所述第一电阻R1的电阻值可以为100KΩ。
另外，所述第一控制子电路还可以包括第三电阻R3和第四电阻R4，第三电阻R3的一端与第二晶体管Q2的第二极连接，第三电阻R3的另一端与接地端连接；第四电阻R4的一端与第二晶体管Q2的控制极连接，第四电阻R4的另一端与接地端连接。
第三电阻R3和第四电阻R4的电阻值可以为100KΩ。
进一步地，如图5所示，所述第二控制子电路包括第三晶体管Q3和第四晶体管Q4；
所述第三晶体管Q3的第一极与所述PMIC的低电平信号输出端电连接，所述第三晶体管Q3的第二极与所述显示面板的低电平信号接收端电连接，所述第三晶体管Q3的控制极与所述DDIC的低电平信号输出端电连接；
所述第四晶体管Q4的第一极与所述DDIC的低电平信号输出端电连接，所述第四晶体管Q4的第二极与所述DDIC的高电平信号输出端电连接，所述第四晶体管Q4的控制极与接地端电连接。
在需要显示面板亮屏显示时，PMIC的高电平输出端输出高电平信号、PMIC的低电平输出端输出低电平信号且DDIC的低电平输出端不输出低电平信号，此时图5中节点E(第三晶体管的第一极)为低电位，节点H(第四晶体管的第二极)为高电位，导致第四晶体管Q4导通，使得节点G(第三晶体管的控制极)的电位为4.6V，进而导致第三晶体管Q3导通，从而节点F(第三晶体管的第二极)的电位也为低电位，PMIC输出的低电平信号传 输至显示面板。
在需要显示面板息屏显示时，PMIC的高电平输出端不输出高电平信号、PMIC的低电平输出端不输出低电平信号且DDIC的低电平输出端输出低电平信号，此时图5中节点E和节点H的电位为0V，第三晶体管Q3和第四晶体管Q4关断，节点F和节点G的电位为低电位，使得DDIC输出的低电平信号传输至显示面板。
其中，上述低电平信号的电压值可以在-1.8V至-3.8V之间，例如-2.4V，但不以此为限。
进一步地，所述第二控制子电路还包括第二电阻R2，所述第二电阻R2的一端与所述第三晶体管Q3的控制极连接，所述第二电阻R2的另一端与所述第三晶体管Q3的第二极连接。
第二电阻R2用于限制节点F和节点G之间的电流，保护显示面板免于大电流的破坏。所述第二电阻R2的电阻值可以为100KΩ。
另外，所述第二控制子电路还可以包括第五电阻R5和第六电阻R6，第五电阻R5的一端与第四晶体管Q4的第二极连接，第五电阻R5的另一端与接地端连接；第六电阻R6的一端与第四晶体管Q4的控制极连接，第六电阻R6的另一端与接地端连接。
第五电阻R5和第六电阻R6的电阻值可以为100KΩ。
需要说明的是，上述的晶体管(Q1至Q4)均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件，其中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
例如：图4中的第一晶体管Q1可以为P型场效应管(第一晶体管Q1的第一极为源极，第一晶体管Q1的第二极为漏极)，第二晶体管Q2可以为NPN 型三极管(第二晶体管Q2的第一极为集电极，第二晶体管Q2的第二极为发射极)；又例如：图5中的第三晶体管Q3可以为N型场效应管(第一晶体管Q1的第一极为漏极，第一晶体管Q1的第二极为源极)，第四晶体管Q4可以为PNP型三极管(第二晶体管Q2的第一极为发射极，第二晶体管Q2的第二极为集电极)。
本公开实施例还提供一种供电控制方法，应用于如上所述的供电控制电路，如图6所示，所述方法包括：
步骤601：在所述PMIC的电能输出端输出第一显示电压时，所述供电控制电路接收所述第一显示电压并将所述第一显示电压传输至所述显示面板，使所述显示面板亮屏显示；
步骤602：在所述PMIC的电能输出端未输出第一显示电压时，所述供电控制电路接收所述DDIC的电能输出端输出的第二显示电压并将所述第二电能传输至所述显示面板，使所述显示面板息屏显示。
本公开实施例中，供电控制电路根据PMIC是否输出第一显示电压作为显示面板在亮屏显示模式和息屏显示模式切换的依据，无需与显示装置的控制器连接，即不会占用显示装置的系统资源，在确保AOD功能正常工作的前提下，能够节约显示装置的系统资源。因此，本公开提供的技术方案能够在确保AOD功能正常工作的前提下，节约显示装置的系统资源。
上述显示面板可以是液晶显示面板，也可以是有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板，还可以是量子点显示面板等，本公开实施例并不限定显示面板具体为何种显示面板。
PMIC为显示装置的电源管理集成电路，在显示装置整体工作过程中可以承担对电能的变换、分配、检测及其他电能管理的职责的芯片。本公开实施例中，PMIC能够提供使显示面板亮屏显示即显示面板整体发光显示所需的电压。
供电控制电路的第一电能输入端与PMIC的电能输出端连接，在PMIC的电能输出端输出第一显示电压时，供电控制电路将第一显示电压传输至显示面板。
DDIC为显示装置成像系统中的驱动电路，可以负责驱动显示面板和控制 驱动电流，DDIC能够驱动单色、双色和全彩的显示面板发光显示。本公开实施例中，DDIC能够提供使显示面板息屏显示，即显示面板部分区域发光显示，其余部分黑屏。
供电控制电路的第二电能输入端与DDIC的电能输出端连接，在PMIC的电能输出端未输出第一显示电压时，供电控制电路将DDIC提供的第二显示电压传输至显示面板。
其中，DDIC可以是持续提供第二显示电压，供电控制电路在PMIC的电能输出端未输出第一显示电压时选择将第二显示电压传输至显示面板；或者，DDIC也可以与PMIC连接并检测PMIC是否输出第一显示电压，如图3所示，在PMIC未输出第一显示电压时才输出第二显示电压，从而供电控制电路在PMIC的电能输出端未输出第一显示电压时将第二显示电压传输至显示面板。图3所示方案能够降低显示装置的功耗，后续均以图3所示方案对具体结构进行说明。
本公开实施例还提供一种显示装置，包括电源管理集成电路PMIC、驱动集成电路DDIC和显示面板，所述显示装置还包括如上所述的供电控制电路。
显示装置可以是显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
由于显示装置本体的结构是现有技术，其中，供电控制电路的结构在上述实施例中已进行详细说明，因此，本实施例中对于具体的供电控制电路的结构不再赘述。
进一步地，所述DDIC的控制端与所述PMIC的电能输出端连接；
所述DDIC用于在所述PMIC的电能输出端未输出第一显示电压时，通过所述DDIC的电能输出端输出第二显示电压。
本实施例中，DDIC能够检测PMIC是否输出第一显示电压，DDIC在PMIC输出第一显示电压时不输出第二显示电压；DDIC在PMIC未输出第一显示电压时输出第二显示电压。
通过在PMIC输出第一显示电压时不输出第二显示电压，能够节约没有必要的能量损耗，降低显示装置的功耗，也延长了使用电池的显示装置的待机时长。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (14)

  1. 一种供电控制电路，用于为显示面板供电，其中，所述供电控制电路的第一电能输入端与电源管理集成电路PMIC的电能输出端电连接，所述供电控制电路的第二电能输入端与驱动集成电路DDIC的电能输出端电连接，所述供电控制电路的电能输出端与所述显示面板的电能接收端电连接；
    所述供电控制电路用于在所述PMIC的电能输出端输出第一显示电压时，接收所述第一显示电压，并将所述第一显示电压传输至所述显示面板，使所述显示面板亮屏显示；
    所述供电控制电路用于在所述PMIC的电能输出端未输出第一显示电压时，接收所述DDIC的电能输出端输出的第二显示电压，并将所述第二显示电压传输至所述显示面板，使所述显示面板息屏显示。
  2. 根据权利要求1所述的供电控制电路，其中，所述PMIC的电能输出端包括第一高电平信号输出端和第一低电平信号输出端；
    所述DDIC的电能输出端包括第二高电平信号输出端和第二低电平信号输出端；
    所述显示面板的电能接收端包括高电平信号接收端和低电平信号接收端；
    所述第一显示电压包括第一高电平信号和第一低电平信号，所述第二显示电压包括第二高电平信号和第二低电平信号；
    所述供电控制电路包括第一控制子电路和第二控制子电路；
    在所述PMIC的电能输出端输出第一显示电压时，所述第一控制子电路从所述第一高电平信号输出端接收所述第一高电平信号，并将所述第一高电平信号传输至所述高电平信号接收端，所述第二控制子电路从所述第一低电平信号输出端接收所述第一低电平信号，并将所述第一低电平信号传输至所述低电平信号接收端，使所述显示面板亮屏显示；
    在所述PMIC的电能输出端未输出第一显示电压且所述DDIC输出第二显示电压时，所述第一控制子电路从所述第二高电平信号输出端接收所述第二高电平信号，并将所述第二高电平信号传输至所述高电平信号接收端，所述第二控制子电路从所述第二低电平信号输出端接收所述第二低电平信号， 并将所述第二低电平信号传输至所述低电平信号接收端，使所述显示面板息屏显示。
  3. 根据权利要求2所述的供电控制电路，其中，所述第一控制子电路包括第一晶体管和第二晶体管；
    所述第一晶体管的第一极与所述PMIC的高电平信号输出端电连接，所述第一晶体管的第二极与所述显示面板的高电平信号接收端电连接，所述第一晶体管的控制极与所述DDIC的高电平信号输出端电连接；
    所述第二晶体管的第一极与所述DDIC的高电平信号输出端电连接，所述第二晶体管的第二极与接地端电连接，所述第二晶体管的控制极与所述PMIC的高电平信号输出端电连接。
  4. 根据权利要求3所述的供电控制电路，其中，所述第一控制子电路还包括第一电阻，所述第一电阻的一端与所述第一晶体管的控制极连接，所述第一电阻的另一端与所述第一晶体管的第二极连接。
  5. 根据权利要求2所述的供电控制电路，其中，所述第二控制子电路包括第三晶体管和第四晶体管；
    所述第三晶体管的第一极与所述PMIC的低电平信号输出端电连接，所述第三晶体管的第二极与所述显示面板的低电平信号接收端电连接，所述第三晶体管的控制极与所述DDIC的低电平信号输出端电连接；
    所述第四晶体管的第一极与所述DDIC的低电平信号输出端电连接，所述第四晶体管的第二极与所述DDIC的高电平信号输出端电连接，所述第四晶体管的控制极与接地端电连接。
  6. 根据权利要求5所述的供电控制电路，其中，所述第二控制子电路还包括第二电阻，所述第二电阻的一端与所述第三晶体管的控制极连接，所述第二电阻的另一端与所述第三晶体管的第二极连接。
  7. 根据权利要求1所述的供电控制电路，其中，所述PMIC为本身不支持息屏显示的PMIC。
  8. 根据权利要求3所述的供电控制电路，其中，所述第二控制子电路包括第三晶体管和第四晶体管；
    所述第三晶体管的第一极与所述PMIC的低电平信号输出端电连接，所 述第三晶体管的第二极与所述显示面板的低电平信号接收端电连接，所述第三晶体管的控制极与所述DDIC的低电平信号输出端电连接；
    所述第四晶体管的第一极与所述DDIC的低电平信号输出端电连接，所述第四晶体管的第二极与所述DDIC的高电平信号输出端电连接，所述第四晶体管的控制极与接地端电连接。
  9. 根据权利要求8所述的供电控制电路，其中，所述第一控制子电路还包括第一电阻，所述第一电阻的一端与所述第一晶体管的控制极连接，所述第一电阻的另一端与所述第一晶体管的第二极连接；
    所述第二控制子电路还包括第二电阻，所述第二电阻的一端与所述第三晶体管的控制极连接，所述第二电阻的另一端与所述第三晶体管的第二极连接。
  10. 根据权利要求9所述的供电控制电路，其中，所述第一控制子电路还包括第三电阻和第四电阻；所述第三电阻的一端与所述第二晶体管的第二极连接，所述第三电阻的另一端与接地端连接；所述第四电阻的一端与所述第二晶体管的控制极连接，所述第四电阻的另一端与接地端连接。
  11. 根据权利要求10所述的供电控制电路，其中，所述第二控制子电路还包括第五电阻和第六电阻；所述第五电阻的一端与所述第四晶体管的第二极连接，所述第五电阻的另一端与接地端连接；所述第六电阻的一端与所述第四晶体管的控制极连接，所述第六电阻的另一端与接地端连接。
  12. 一种供电控制方法，应用于如权利要求1-11中任一项所述的供电控制电路，所述方法包括：
    在所述PMIC的电能输出端输出第一显示电压时，所述供电控制电路接收所述第一显示电压并将所述第一显示电压传输至所述显示面板，使所述显示面板亮屏显示；
    在所述PMIC的电能输出端未输出第一显示电压时，所述供电控制电路接收所述DDIC的电能输出端输出的第二显示电压并将所述第二电能传输至所述显示面板，使所述显示面板息屏显示。
  13. 一种显示装置，包括电源管理集成电路PMIC、驱动集成电路DDIC和显示面板，其中，所述显示装置还包括如权利要求1-11中任一项所述的供 电控制电路。
  14. 根据权利要求13所述的显示装置，其中，所述DDIC的控制端与所述PMIC的电能输出端连接；
    所述DDIC用于在所述PMIC的电能输出端未输出第一显示电压时，通过所述DDIC的电能输出端输出第二显示电压。
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