WO2020248277A1 - 一种时钟校准的方法及装置 - Google Patents

一种时钟校准的方法及装置 Download PDF

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Publication number
WO2020248277A1
WO2020248277A1 PCT/CN2019/091398 CN2019091398W WO2020248277A1 WO 2020248277 A1 WO2020248277 A1 WO 2020248277A1 CN 2019091398 W CN2019091398 W CN 2019091398W WO 2020248277 A1 WO2020248277 A1 WO 2020248277A1
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Prior art keywords
phase difference
threshold
clock
signal
pulse signal
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French (fr)
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张静
杨小刚
朱安华
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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Priority to PCT/CN2019/091398 priority Critical patent/WO2020248277A1/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems

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  • This application relates to the field of communication technology, and in particular to a method and device for clock calibration.
  • the time reference of the communication system comes from GNSS (Global Navigation Satellite System), and satellite signals are easily interfered by weather, shelters or electromagnetic fields. These interferences will cause the standard second pulse signal output by the GNSS chip to be unstable, so communication In order to obtain a stable time reference and better performance, the system must eliminate the interference of the standard second pulse.
  • the inventor of the present application has discovered in long-term research and development that the elimination of interference usually adopts the method of setting a threshold, that is, it is considered that the second pulse normally input to the system is periodic and will appear at a preset time, within the threshold range of the standard time.
  • the threshold for filtering interference signals is fixed, in order to adapt to all application environments, the threshold must be relatively large, so some interference signals cannot be filtered, which leads to the degradation of the clock system performance ;
  • the external second pulse is fixed to another position and the phase difference exceeds the threshold, it will be treated as an interference signal and filtered.
  • the main problem to be solved by this application is to provide a method and device for clock calibration, which can automatically adjust the threshold for filtering interference signals, reduce the influence of interference signals, and improve the stability of the local clock.
  • the technical solution adopted in this application is to provide a clock calibration method, which includes: receiving the standard second pulse signal; obtaining the first local second pulse signal; obtaining the first local second pulse signal and the standard second The first phase difference between the pulse signals; the threshold value for filtering the phase difference is obtained according to the first phase difference, and the interference signal in the standard second pulse signal is filtered by the threshold value.
  • a clock calibration device which at least includes: a clock source, a local clock generation circuit, a phase detector and a processor, a phase detector and a clock source Is coupled to the local clock generation circuit, one end of the processor is coupled to the phase detector, the other end of the processor is coupled to one end of the local clock generation circuit, the local clock generation circuit, the phase detector and the processor form negative feedback, the clock
  • the source is used to output the standard second pulse signal
  • the local clock generation circuit is used to obtain the first local second pulse signal
  • the phase detector is used to receive the standard second pulse signal and the first local second pulse signal, and obtain the first local second pulse signal
  • the processor is configured to obtain a threshold value of the filtered phase difference according to the first phase difference, and use the threshold value of the filtered phase difference to filter out interference signals in the standard second pulse signal.
  • the beneficial effects of the present application are: first receive the standard second pulse signal and the first clock signal, use the phase-locked loop to multiply the frequency of the first clock signal, generate the second clock signal, and then count the second clock signal, To generate the first local second pulse signal; then obtain the first phase difference between the first local second pulse signal and the standard second pulse signal; then use the first phase difference to obtain the threshold value of the filtered phase difference, and use the threshold value of the filtered phase difference Filter out the interference signal contained in the standard second pulse signal, which can automatically adjust the threshold for filtering out the interference signal.
  • the new phase can also be re-locked, which not only improves the effect of filtering interference, but also ensures the function of locking the standard second pulse, reducing the frequency change of the local clock and improving the local clock The stability.
  • Figure 1 is a signal timing diagram for filtering interference in the prior art
  • Figure 2 is another signal timing diagram for filtering interference in the prior art
  • FIG. 3 is a schematic flowchart of an embodiment of a method for clock calibration provided by the present application.
  • FIG. 5 is a schematic flowchart of another embodiment of the clock calibration method provided by the present application.
  • FIG. 6 is a signal timing diagram in another embodiment of the clock calibration method provided by the present application.
  • FIG. 7 is a schematic diagram of the state transition of the phase threshold in another embodiment of the clock calibration method provided by the present application.
  • FIG. 8 is a schematic diagram of the phase difference in another embodiment of the clock calibration method provided by the present application.
  • FIG. 9 is a schematic structural diagram of an embodiment of a clock calibration device provided by the present application.
  • FIG. 10 is a schematic structural diagram of another embodiment of the clock calibration device provided by the present application.
  • the second pulse within the preset threshold range is normal, and the second pulse outside the threshold range is interference
  • the preset threshold is the clock period of 20 counting pulses.
  • the interval between the two pulses is a normal signal within [2 ⁇ 10 6 -20, 2 ⁇ 10 6 +20] clock periods. If two The second pulse interval is 2 ⁇ 10 6 +30 clock cycles, which exceeds the normal range and is considered as an interference signal.
  • Both of these methods use a fixed threshold to filter interference signals.
  • the threshold is usually set to be relatively large, resulting in interference signals within the threshold range that cannot be filtered, making the filtering effect not good enough.
  • FIG. 3 is a schematic flowchart of an embodiment of a clock calibration method provided by the present application, and the method includes:
  • Step 31 Receive the standard second pulse signal.
  • Step 32 Obtain the first local second pulse signal.
  • An oscillator can be used to generate the first clock signal, which can be an oven-controlled crystal oscillator; then a phase-locked loop can be used to multiply the frequency of the first clock signal, generate the second clock signal, and then count the second clock signal to Generate the first local second pulse signal with a period of 1 second; for example: the period of the first clock signal is 100ns, and the second clock signal with a period of 10ns is generated using a phase-locked loop, and then the number of periods of the second clock signal is counted. After each 100*10 6 second clock signals are received, a first local second pulse signal is generated.
  • Step 33 Obtain the first phase difference between the first local second pulse signal and the standard second pulse signal.
  • the first phase between the first local second pulse signal and the standard second pulse signal needs to be obtained And reduce the first phase difference by adjusting the phase of the first local second pulse signal to realize the local clock signal following the standard second pulse signal.
  • Step 34 Obtain a threshold value of the filtered phase difference according to the first phase difference, and use the threshold value of the filtered phase difference to filter out interference signals in the standard second pulse signal.
  • the first phase difference is used to determine the threshold of the filtering phase difference to filter out the interference signal in the obtained standard second pulse signal , To prevent interference signals from affecting local pulse signals.
  • this embodiment provides a method for clock calibration.
  • the first clock signal is multiplied by the phase-locked loop, and the second clock signal is generated.
  • Count the second clock signal to generate the first local second pulse signal; then obtain the first phase difference between the first local second pulse signal and the standard second pulse signal; then use the first phase difference to obtain the threshold of the filtered phase difference, And use the threshold of the filtering phase difference to filter out the interference signal contained in the standard second pulse signal, which can automatically adjust the threshold of the filtering phase difference for filtering the interference signal.
  • FIG. 4 is a schematic flowchart of another embodiment of a clock calibration method provided by the present application, and the method includes:
  • Step 41 Receive the standard second pulse signal.
  • the standard second pulse signal is a pulse signal generated by a global navigation satellite system or a precision timing protocol (Precision Timing Protocol, PTP).
  • PTP Precision Timing Protocol
  • Step 42 Obtain the first local second pulse signal.
  • Step 43 Obtain a first phase difference between the first local second pulse signal and the standard second pulse signal.
  • steps 41-43 are the same as steps 31-33 in the foregoing embodiment, and will not be repeated here.
  • Step 44 Compare each first phase difference in the preset period with a preset phase difference threshold.
  • the preset period After acquiring the first phase difference between the first local second pulse signal and the standard second pulse signal, in order to obtain the threshold value of the filtering phase difference for filtering out the interference signal contained in the standard second pulse signal, the preset period
  • the first phase difference is compared with a preset phase difference threshold.
  • the preset phase difference threshold is a preset first filtered phase difference threshold.
  • the first filtered phase difference threshold is also a maximum filtered phase difference threshold.
  • the phase difference threshold can be infinity, and specific data can be used to represent infinity.
  • Step 45 After the system is powered on, the threshold of the filtered phase difference defaults to the preset first filtered phase difference threshold; when all the first phase differences in the preset period are less than the preset second filtered phase difference threshold, the filtered phase The threshold of the difference is set to the threshold of the preset second filtering phase difference; when all the first phase differences in the preset period are less than the threshold of the preset third filtering phase difference, the threshold of the filtering phase difference is set to the preset third filtering The threshold of the phase difference.
  • the preset first filtering The threshold of the phase difference is reduced to the preset threshold of the second filtered phase difference; if all the first phase differences in the preset period are less than the threshold of the preset third filtered phase difference, the threshold of the filtered phase difference is set to the preset The third filtered phase difference threshold; wherein the first filtered phase difference threshold is greater than the second filtered phase difference threshold, the second filtered phase difference threshold is greater than the third filtered phase difference threshold; in the preset period, all the first When the phase difference is greater than the preset first filtering phase difference threshold, the filtering is directly performed.
  • Step 46 Use the threshold of the filtered phase difference to filter out the interference signal in the standard second pulse signal.
  • the filtering phase difference threshold can be used to filter out interference signals in the standard second pulse signal, and signals other than the filtering phase difference threshold can be used as interference signals for filtering.
  • Step 47 Process the first phase difference after filtering the interference signal to obtain the second local second pulse signal, so that the second phase difference between the second local second pulse signal and the standard second pulse signal is smaller than the first phase difference .
  • the first phase difference after filtering the interference signal can be processed, and the frequency or phase of the first local second pulse signal can be adjusted , Turn it into the second local second pulse signal, so that the second phase difference between the second local second pulse signal and the standard second pulse signal is smaller than the first phase difference.
  • the above steps can be repeated to reduce the phase difference between the local second pulse signal and the standard second pulse signal, so that the phase difference between the two is close to 0, and achieve the purpose of following the standard second pulse signal.
  • this application provides a method for clock calibration.
  • each first phase difference in a preset period is compared with The preset phase difference threshold is compared.
  • the filtering is directly performed.
  • the first phase difference is less than the preset phase difference threshold, the phase is filtered
  • the threshold of the difference is reduced to realize the automatic adjustment of the threshold of the filtering phase difference to filter out the interference signal.
  • the threshold of the filtering phase difference can be adjusted according to the current first phase difference, instead of directly setting the threshold of the filtering phase difference to a fixed value, and By amplifying the threshold, the threshold can be amplified to infinity.
  • the phase of the standard second pulse signal changes suddenly and the phase difference with the first local second pulse signal exceeds the filtered phase difference threshold, it will not be treated as an interference signal and be filtered out. While reducing the influence of interference signals, it can effectively prevent the standard second pulse signal or the first local second pulse signal from being filtered out as interference signals, and improve the stability of the local clock.
  • FIG. 5 is a schematic flowchart of another embodiment of the clock calibration method provided by the present application, and the method includes:
  • Step 51 Receive the standard second pulse signal.
  • Step 52 Receive the first clock signal output by the oscillator.
  • steps 51-52 are the same as steps 31-32 in the foregoing embodiment, and will not be repeated here.
  • Step 53 Multiply the frequency of the first clock signal output by the oscillator, and count the multiplied first clock signal to generate a first local second pulse signal.
  • the frequency of the first clock signal output by the oscillator is 1MHz, then the first local second pulse signal will be generated after 1 ⁇ 10 6 clock cycles, as shown in Figure 6.
  • Step 54 Obtain a first phase difference between the first local second pulse signal and the standard second pulse signal.
  • Step 55 Obtain a threshold value of the filtered phase difference according to the first phase difference, and use the threshold value of the filtered phase difference to filter out the interference signal in the standard second pulse signal.
  • steps 54-55 are the same as steps 33-34 in the foregoing embodiment, and will not be repeated here.
  • Step 56 Use a clock calibration algorithm to process the first phase difference to obtain a digital signal, and convert the digital signal into an analog signal.
  • the clock calibration algorithm (such as PID algorithm, Proportion Integral Differential, proportional integral differentiation) can be used to process the first phase difference, convert the first phase difference into a digital signal, and convert the digital signal into an analog signal .
  • Step 57 Use the analog signal to make the oscillator output the first clock signal.
  • the analog signal can be a voltage signal, and the generated voltage can be used to adjust the oscillation frequency of the oscillator so that the oscillator outputs the first clock signal.
  • Step 58 Multiply the frequency of the first clock signal to generate a second clock signal.
  • Step 59 Count the second clock signal to generate a second local second pulse signal.
  • the threshold value of the filtered phase difference can be the maximum value by default after power-on, the threshold value of the filtered phase difference remains unchanged before the clock is locked, and the threshold value of the filtered phase difference starts to be adjusted after the clock is locked; first calculate the first local value within the preset time The maximum and minimum values of multiple first phase differences between the second pulse signal and the standard second pulse signal, and then determine whether to modify the phase difference according to the current filtered phase difference threshold and the current maximum and minimum value of the first phase difference Threshold.
  • the signal whose phase difference with the standard second pulse signal is greater than the modified phase difference threshold is regarded as a useless signal, and the signal whose phase difference with the standard second pulse signal is less than the modified phase difference threshold is regarded as a useful signal. So as to filter out the interference signal.
  • phase difference threshold The change of the phase difference threshold will be described in detail below, assuming there are three phase difference thresholds: the first phase difference threshold, the second phase difference threshold and the third phase difference threshold, the first phase difference threshold, the second phase difference threshold and the third phase difference
  • the state corresponding to the threshold is represented by State1, State2, and State3, respectively, and the automatic adjustment of the phase difference threshold is realized by state jump, as shown in Figure 7.
  • the clock After the clock is locked, it enters the first phase difference threshold, that is, the maximum allowable phase difference range. At this time, the threshold of the filtered phase difference is also at the maximum value (the first filtered phase difference threshold is preset).
  • the threshold of the filtering phase difference is reduced accordingly, and the threshold of the filtering phase difference is set to the preset second filtering phase difference threshold.
  • the state corresponding to the first phase difference threshold will remain unchanged, that is, the threshold of the filtered phase difference is the preset first filtered phase difference The threshold.
  • the state State2 corresponding to the second phase difference threshold is kept unchanged, that is, the threshold of the filtering phase difference is the preset second filtering phase The threshold of difference.
  • the threshold of the filtering phase difference is set to the preset second filtering phase difference threshold.
  • the state State3 corresponding to the third phase difference threshold is kept unchanged, that is, the threshold of the filtered phase difference is the preset third filtered phase difference threshold.
  • the phase difference threshold will decrease, and the threshold for filtering the phase difference will drop. Signals larger than the threshold for filtering the phase difference are considered as interference
  • the signal is filtered; if the first phase difference becomes larger and larger, the phase difference threshold will become larger, and the threshold for filtering the phase difference will increase; thus, it can be based on the actual local second pulse signal and the first phase of the standard second pulse signal
  • the difference data generates a threshold value for filtering phase difference that is more suitable for the actual environment.
  • the above three states may be continuously converted, and the current filtering phase difference threshold can be continuously adjusted according to the current first phase difference to realize automatic adjustment of the filtering phase difference The threshold value to improve the effect of filtering interference signals.
  • the default phase difference threshold is the maximum at this time, and the clock is locked after M seconds, and enters State1 corresponding to the first phase difference threshold.
  • the state rises to the state State1 corresponding to the first phase difference threshold.
  • the state drops to the state State2 corresponding to the second phase difference threshold.
  • this application provides a clock calibration method to obtain the first phase difference between the first local second pulse signal and the standard second pulse signal according to the difference between the first phase difference and the preset phase difference
  • the relationship between adjusting the threshold of the filtered phase difference can automatically adjust the threshold of the filtered phase difference to filter out the interference signal, reducing the influence of the interference signal, and then use the clock calibration algorithm to process the first phase difference to obtain the digital signal, and the digital signal Convert it into an analog signal, and then use the analog signal to control the oscillator to output a second clock signal to generate a second local second pulse signal.
  • the second phase difference between the regenerated second local second pulse signal and the standard second pulse is smaller than the first The phase difference achieves the purpose of locking the standard second pulse.
  • the clock calibration device includes at least a clock source 91, a local clock generation circuit 92, a phase detector 93 and a processor 94.
  • the phase detector 93 is coupled to the clock source 91 and the local clock generation circuit 92, one end of the processor 94 is coupled to the phase detector 93, the other end of the processor 94 is coupled to one end of the local clock generation circuit 92, and the local clock is generated
  • the circuit 92, the phase detector 93 and the processor 94 form negative feedback.
  • the clock source 91 is used to output the standard second pulse signal
  • the local clock generation circuit 92 is used to obtain the first local second pulse signal
  • the phase detector 93 is used to receive the standard second pulse signal and the first local second pulse signal, and obtain the first
  • the processor 94 is configured to obtain a threshold value of the filtered phase difference according to the first phase difference, and use the threshold value of the filtered phase difference to filter out interference in the standard second pulse signal signal.
  • this application provides a clock calibration device, which obtains the first pulse signal between the standard second pulse signal output by the clock source 91 and the first local second pulse signal output by the local clock generation circuit 92 through the phase detector 93.
  • the processor 94 adjusts the threshold of the filtered phase difference according to the first phase difference to automatically adjust the threshold of the filtered phase difference to filter out the interference signal, reducing the influence of the interference signal, and the processor 94 is used to control the local clock generation
  • the circuit 102 enables the first local second pulse output by the local clock generating circuit 102 to lock the clock source 91, which improves the stability of the local clock.
  • FIG. 10 is a schematic structural diagram of another embodiment of a clock calibration device provided by this application; the clock calibration device at least includes a clock source 101, a local clock generation circuit 102, a phase detector 103 and a processor 104.
  • the clock source 101 is a global navigation satellite system or a precision clock synchronization protocol, and is used to output a standard second pulse signal;
  • the local clock generating circuit 102 includes a frequency multiplication and counting circuit 1021 and an oscillator 1022 connected to each other.
  • the frequency multiplication and counting circuit 1021 is a local clock source, used to receive the first clock signal output by the oscillator 1022, generate a higher frequency clock through frequency multiplication, and then generate the first local second pulse signal by counting and output it to the phase detector ⁇ 103.
  • the phase detector 103 is coupled to the clock source 101 and the frequency multiplication and counting circuit 1021, and is used to receive the standard second pulse signal and the first local second pulse signal, and obtain the difference between the first local second pulse signal and the standard second pulse signal The first phase difference.
  • the processor 104 at least includes: an adjusting filter circuit 1041, a regulator 1042, a digital-to-analog converter 1043, and a clock state reporting circuit 1044.
  • the adjusting filter circuit 1041 is coupled to the phase detector 103, and is configured to obtain a threshold value of the filtered phase difference according to the first phase difference, and use the threshold value of the filtered phase difference to filter out interference signals in the standard second pulse signal;
  • the adjustment filter circuit 1041 is also used to compare the first phase difference in the preset period with the preset phase difference threshold.
  • the threshold of the filtered phase difference defaults to the preset first filtered phase difference threshold; When all the first phase differences in the period are less than the preset second filtered phase difference threshold, the threshold of the filtered phase difference is set to the preset second filtered phase difference threshold; when all the first phase differences in the preset period are less than the preset threshold.
  • setting the threshold of the third filtered phase difference set the threshold of the filtered phase difference to the threshold of the preset third filtered phase difference; according to the numerical interval of all the first phase differences in the preset period, decide whether to adjust the threshold and adjust to Which threshold.
  • the threshold of the first filtered phase difference is greater than the threshold of the second filtered phase difference
  • the threshold of the second filtered phase difference is greater than the threshold of the third filtered phase difference.
  • the clock state reporting circuit 1044 is coupled to the adjusting filter circuit 1041, and is used to upload the state of whether the clock is locked and the first phase difference to the central processing unit (not shown in the figure).
  • the regulator 1042 is coupled to the regulating filter circuit 1041, and is used for processing the first phase difference to obtain a digital signal by using a clock calibration algorithm.
  • the regulator 1042 may be a PID controller.
  • One end of the digital-to-analog converter 1043 is coupled to the regulator 1042 for converting the digital signal sent by the regulator 1042 into an analog signal.
  • the other end of the digital-to-analog converter 1043 is coupled to an oscillator 1022.
  • the oscillator 1022 is used to generate a first clock signal according to the analog signal and send the first clock signal to the frequency multiplication and counting circuit 1021.
  • the oscillator 1022 can be a voltage Controlled oscillator; specifically, the oscillator 1022 may be an oven controlled crystal oscillator, and the frequency of the first clock signal may be 10 MHz.
  • the frequency multiplication and counting circuit 1021 is connected to the phase detector 103, and is used for multiplying the frequency of the first clock signal output by the oscillator 1022, and counting the received multiplied first clock signal to generate the first local second Pulse signal.
  • the processor 104 uses the first phase difference output by the phase detector 103 to adjust the frequency of the first clock signal output by the oscillator 1022. Specifically, the processor 104 outputs different voltage signals according to different first phase differences, thereby controlling the oscillator The frequency of the first clock signal output by 1022; when the first phase difference output by the phase detector 103 is non-zero, the processor 104 adjusts the frequency of the first clock signal output, thereby adjusting the first clock signal output by the frequency multiplication and counting circuit 1021
  • the phase of the local second pulse signal is such that the phase difference between the adjusted frequency multiplication and the first local second pulse signal output by the counting circuit 1021 and the standard second pulse signal output by the clock source 101 is reduced.
  • the phase detector 103, the regulating filter circuit 1041, the regulator 1042, the digital-to-analog converter 1043, and the frequency multiplication and counting circuit 1021 form negative feedback; when the frequency of the clock signal output by the oscillator 1022 is greater than the standard frequency value, the phase detector 103 Compare the first phase difference between the standard second pulse signal output by the clock source 101 and the frequency multiplier and the first local second pulse signal output by the counting circuit 1021, and then use the adjustment filter circuit 1041 to determine the threshold of the filtered phase difference, and use the filtered phase The difference threshold filters out the interference signal, and then the first phase difference is input to the regulator 1042 to be processed into a digital signal.
  • the regulator 1042 transmits the digital signal to the digital-to-analog converter 1043, so that the analog signal output by the digital-to-analog converter 1043 is reduced. Small, so that the output frequency of the oscillator 1022 is reduced to approach the standard value.
  • the output frequency of the oscillator 1022 is 10MHz+10Hz, which is slightly larger than the preset value (10MHz).
  • the phase of the first local second pulse signal is obtained.
  • Standard second pulse signal and then use the PID regulator to reduce the value of the output digital signal, the voltage output by the digital-to-analog converter 1043 is also reduced accordingly, so the frequency output by the oscillator 1022 is also reduced accordingly, reducing the frequency to 10MHz +5 Hz, thereby reducing the first phase difference between the first local second pulse signal and the standard second pulse signal. Repeating this process can make the output frequency of the oscillator 1022 approach 10 MHz.
  • the output frequency of the oscillator 1022 is 10MHz-10Hz, which is smaller than the preset value, by comparing the first local second pulse signal with the standard second pulse signal, the phase of the local second pulse signal is lagging behind the phase of the standard second pulse signal.
  • the PID regulator increases the value of the output digital signal, and the voltage output by the digital-to-analog converter 1043 increases accordingly. Therefore, the frequency output by the oscillator 1022 also increases accordingly, increasing the frequency to 10MHz-5Hz, thereby reducing the first A first phase difference between a local second pulse signal and a standard second pulse signal. Repeat this process to obtain a local accurate 10M clock to provide an accurate clock for the communication system. .
  • this application provides a clock calibration device, which obtains the phase difference between the clock source 101 and the multiplication and counting circuit 1021 through the phase detector 103, and uses the adjustment filter circuit 1041 to automatically adjust and filter out the interference signal.
  • the threshold of the phase difference is filtered to reduce the influence of interference signals, and then the voltage in the input oscillator 1022 is adjusted by the regulator 1042 and the digital-to-analog converter 1043, thereby changing the output frequency of the oscillator 1022, making the frequency multiplication and counting circuit 1021
  • the output local second pulse phase changes to reduce the phase difference between the local second pulse signal and the standard second pulse signal, so that the local second pulse signal is locked to the standard second pulse signal, and finally an accurate and stable local clock is obtained.
  • the disclosed method and device may be implemented in other ways.
  • the device implementation described above is only illustrative, for example, the division of modules or units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of this embodiment.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

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Abstract

本申请公开了一种时钟校准的方法及装置，该方法包括接收到标准秒脉冲信号；获得第一本地秒脉冲信号；获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差；根据第一相位差获取过滤相位差的阈值，并利用过滤相位差的阈值滤除标准秒脉冲信号中的干扰信号。通过上述方式，本申请能够自动调整滤除干扰信号的过滤相位差的阈值，减少了干扰信号的影响，提高本地时钟的稳定性。

Description

一种时钟校准的方法及装置 【技术领域】
本申请涉及通信技术领域，具体涉及一种时钟校准的方法及装置。
【背景技术】
通讯系统的时间基准来自GNSS(Global Navigation Satellite System，全球导航卫星系统)，而卫星信号容易受到天气、遮蔽物或电磁场等干扰，这些干扰会导致GNSS芯片输出的标准秒脉冲信号不稳定，所以通讯系统为了获取稳定的时间基准，获得更优的性能，就要消除标准秒脉冲的干扰。本申请的发明人在长期研发中发现，消除干扰通常采用设置阈值的方式，即认为正常输入给系统的秒脉冲是周期性的，会在预设的时间出现，在标准时间的阈值范围内出现属于正常信号，否则认为是干扰信号，将其过滤；但是由于过滤干扰信号的阈值固定，为了适应所有的应用环境，阈值必须比较大，因而部分干扰信号不能被过滤，从而导致时钟系统性能的降低；此外当外部秒脉冲固定变化到另一个位置，而且相位差超过阈值时，就会被当做干扰信号而被过滤。
【发明内容】
本申请主要解决的问题是提供一种时钟校准的方法及装置，能够自动调整滤除干扰信号的阈值，减少了干扰信号的影响，提高本地时钟的稳定性。
为解决上述技术问题，本申请采用的技术方案是提供一种时钟校准的方法，该方法包括：接收到标准秒脉冲信号；获得第一本地秒脉冲信号；获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差；根据第一相位差获取过滤相位差的阈值，并利用阈值滤除标准秒脉冲信号中的干扰信号。
为解决上述技术问题，本申请采用的另一技术方案是提供一种时钟校准装置，该时钟校准装置至少包括：时钟源、本地时钟产生电路、鉴相器和处理器，鉴相器与时钟源和本地时钟产生电路耦接，处理器的一 端与鉴相器耦接，处理器的另一端与本地时钟产生电路的一端耦接，本地时钟产生电路、鉴相器和处理器形成负反馈，时钟源用于输出标准秒脉冲信号，本地时钟产生电路用于获得第一本地秒脉冲信号，鉴相器用于接收到标准秒脉冲信号和第一本地秒脉冲信号，并获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差，处理器用于根据第一相位差获取过滤相位差的阈值，并利用过滤相位差的阈值滤除标准秒脉冲信号中的干扰信号。
通过上述方案，本申请的有益效果是：首先接收标准秒脉冲信号和第一时钟信号，利用锁相环对第一时钟信号进行倍频，产生第二时钟信号后再对第二时钟信号计数，以产生第一本地秒脉冲信号；然后获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差；再利用第一相位差获取过滤相位差的阈值，并利用过滤相位差的阈值滤除标准秒脉冲信号中夹杂的干扰信号，能够实现自动调整滤除干扰信号的阈值，在外部输入的标准秒脉冲稳定时，产生小的阈值，达到较好的过滤效果；同时在外部输入的标准秒脉冲稳定切换到到另一个相位时，也能够重新锁定新的相位，这样既提高了过滤干扰的效果，又保证了锁定标准秒脉冲的功能，减少了本地时钟的频率变化，提高本地时钟的稳定性。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术中滤除干扰的信号时序图；
图2是现有技术中滤除干扰的另一信号时序图；
图3是本申请提供的时钟校准的方法一实施例的流程示意图；
图4是本申请提供的时钟校准的方法另一实施例的流程示意图；
图5是本申请提供的时钟校准的方法又一实施例的流程示意图；
图6是本申请提供的时钟校准的方法又一实施例中信号时序图；
图7是本申请提供的时钟校准的方法又一实施例中相位阈值的状态转化示意图；
图8是本申请提供的时钟校准的方法又一实施例中相位差的示意图；
图9是本申请提供的时钟校准装置一实施例的结构示意图；
图10是本申请提供的时钟校准装置另一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
目前对于滤除干扰信号的解决方式主要有两种方式，一种是产生一个窗口秒脉冲，如图1所示，如果GPS秒脉冲没有位于该窗口秒脉冲内，就认为是干扰信号，实际上它能过滤的范围就是这个窗口之外的脉冲，如果干扰信号在窗口秒脉冲内就无法实现过滤了；另一种是利用计数器实现消除干扰，例如它使用频率为2MHz的计数脉冲对GPS秒脉冲的周期进行计数，正常两个标准的GPS秒脉冲间隔就是2×10 6个计数脉冲，如图2所示，在预设阈值范围内出现秒脉冲属于正常，阈值范围外出现的秒脉冲属于干扰，例如：预设阈值为20个计数脉冲的时钟周期，两个脉冲的间隔在[2×10 6-20，2×10 6+20]个时钟周期内都属于正常信号，如果监控到两个秒脉冲间隔为2×10 6+30个时钟周期，则超出了正常范围，认为干扰信号。
这两种方式都是使用固定阈值的方法过滤干扰信号，为了实现滤除功能的稳定，阈值通常都设置得比较大，导致在阈值范围内的干扰信号不能被过滤，使得过滤效果不够好。
参阅图3，图3是本申请提供的时钟校准的方法一实施例的流程示意图，该方法包括：
步骤31：接收到标准秒脉冲信号。
为了实现时钟校准，首先需要接收标准秒脉冲信号。
步骤32：获得第一本地秒脉冲信号。
可以利用振荡器产生第一时钟信号，该振荡器可以为恒温晶体振荡器；然后可以利用锁相环对第一时钟信号进行倍频，产生第二时钟信号后再对第二时钟信号计数，以产生周期为1秒的第一本地秒脉冲信号；例如：第一时钟信号的周期为100ns，利用锁相环产生周期为10ns的第二时钟信号，然后对第二时钟信号的周期数进行统计，每接收到100*10 6个第二时钟信号之后，产生一个第一本地秒脉冲信号。
步骤33：获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差。
为了实现本地时钟信号对标准秒脉冲信号的跟踪，使得第一本地秒脉冲信号的相位与标准秒脉冲信号的相位一致，需要获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差，并通过调整第一本地秒脉冲信号的相位将第一相位差减小，以实现本地时钟信号对标准秒脉冲信号的跟随。
步骤34：根据第一相位差获取过滤相位差的阈值，并利用过滤相位差的阈值滤除标准秒脉冲信号中的干扰信号。
由于卫星信号容易受到干扰，标准秒脉冲信号的相位可能会发生突变，为防止本地时钟跟踪错误的输入信号，需要过滤掉相位错误的输入信号，即过滤干扰信号。
在获取到第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差之后，利用第一相位差确定过滤相位差的阈值，以将获取到的标准秒脉冲信号中的干扰信号滤除，避免干扰信号影响本地脉冲信号。
区别于现有技术，本实施例提供了一种时钟校准的方法，通过接收标准秒脉冲信号和第一时钟信号，利用锁相环对第一时钟信号进行倍频，产生第二时钟信号后再对第二时钟信号计数，以产生第一本地秒脉冲信号；然后获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差；再利用第一相位差获取过滤相位差的阈值，并利用过滤相位差的 阈值滤除标准秒脉冲信号中夹杂的干扰信号，能够实现自动调整滤除干扰信号的过滤相位差的阈值，在外部输入的标准秒脉冲稳定时，产生小的过滤相位差的阈值，达到较好的过滤效果；同时在外部输入的标准秒脉冲稳定切换到到另一个相位时，也能够重新锁定新的相位，这样既提高了过滤干扰的效果，又保证了锁定标准秒脉冲的功能，减少了本地时钟的频率变化，提高本地时钟的稳定性。
参阅图4，图4是本申请提供的时钟校准的方法另一实施例的流程示意图，该方法包括：
步骤41：接收到标准秒脉冲信号。
标准秒脉冲信号为全球导航卫星系统或精密时钟同步协议(Precision Timing Protocol，PTP)产生的脉冲信号。
步骤42：获得第一本地秒脉冲信号。
步骤43：获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差。
其中，步骤41-43与上述实施例中步骤31-33相同，在此不再赘述。
步骤44：将预设周期内每个第一相位差与预设的相位差阈值进行比较。
在获取了第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差之后，为了获得滤除标准秒脉冲信号中夹杂的干扰信号的过滤相位差的阈值，可以将预设周期内每个第一相位差与预设的相位差阈值进行比较，预设的相位差阈值为预设第一过滤相位差的阈值，第一过滤相位差的阈值同时也是最大过滤相位差的阈值，预设的相位差阈值可以是无穷大，可以使用特定的数据表示无穷大。
步骤45：系统上电后，过滤相位差的阈值默认为预设第一过滤相位差的阈值；当预设周期内所有第一相位差小于预设第二过滤相位差的阈值时，将过滤相位差的阈值设置为预设第二过滤相位差的阈值；当预设周期内所有第一相位差小于预设第三过滤相位差的阈值时，将过滤相位差的阈值设置为预设第三过滤相位差的阈值。
在预设周期内所有第一相位差小于预设第二过滤相位差阈值时，则 表明当前预设第一过滤相位差的阈值比较大，为了将干扰信号滤除，需要将预设第一过滤相位差的阈值调小至预设第二过滤相位差的阈值；如果预设周期内所有第一相位差均小于预设第三过滤相位差的阈值，则将过滤相位差的阈值设置为预设第三过滤相位差的阈值；其中，第一过滤相位差的阈值大于第二过滤相位差的阈值，第二过滤相位差的阈值大于第三过滤相位差的阈值；在预设周期内所有第一相位差大于预设第一过滤相位差的阈值时，直接进行滤除。
步骤46：利用过滤相位差的阈值滤除标准秒脉冲信号中的干扰信号。
在确定了当前过滤相位差的阈值之后，可以利用该过滤相位差的阈值将标准秒脉冲信号中的干扰信号滤除，将该过滤相位差的阈值之外的信号当做干扰信号进行滤除。
步骤47：对滤除干扰信号后的第一相位差进行处理，以得到第二本地秒脉冲信号，使得第二本地秒脉冲信号与标准秒脉冲信号之间的第二相位差小于第一相位差。
在滤除了干扰信号之后，为了实现第一本地秒脉冲信号对标准秒脉冲信号的跟随，可以对滤除干扰信号后的第一相位差进行处理，并调整第一本地秒脉冲信号的频率或相位，将其变成第二本地秒脉冲信号，以使得第二本地秒脉冲信号与标准秒脉冲信号之间的第二相位差小于第一相位差。
上述步骤可以重复执行，以缩小本地秒脉冲信号与标准秒脉冲信号之间的相位差，使得两者的相位差接近于0，达到对标准秒脉冲信号跟随的目的。
区别于现有技术，本申请提供了一种时钟校准的方法，通过获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差，将预设周期内每个第一相位差与预设的相位差阈值进行比较，在预设周期内所有第一相位差大于预设的相位差阈值时，直接进行滤除，在第一相位差小于预设的相位差阈值时，将过滤相位差的阈值调小，实现自动调整滤除干扰信号的过滤相位差的阈值，可以根据当前的第一相位差调整过滤相位差 的阈值，而不是直接将过滤相位差的阈值设置为定值，而且通过放大阈值，阈值可以放大到无穷大，当标准秒脉冲信号的相位突变而且与第一本地秒脉冲信号之间相位差超过过滤相位差的阈值时，不会被当做干扰信号而被滤除，在减少了干扰信号的影响的同时，可以有效地防止标准秒脉冲信号或第一本地秒脉冲信号被当做干扰信号滤除，提高本地时钟的稳定性。
参阅图5，图5是本申请提供的时钟校准的方法又一实施例的流程示意图，该方法包括：
步骤51：接收到标准秒脉冲信号。
步骤52：接收到振荡器输出的第一时钟信号。
其中，步骤51-52与上述实施例中步骤31-32相同，在此不再赘述。
步骤53：对振荡器输出的第一时钟信号进行倍频，并对倍频后的第一时钟信号进行计数，产生第一本地秒脉冲信号。
对振荡器输出的第一时钟信号进行倍频，并统计接收到的倍频后的第一时钟信号的数量，在预设周期内接收到第一时钟信号之后，产生一个第一本地秒脉冲信号；例如：振荡器输出的第一时钟信号的频率为1MHz，则在1×10 6个时钟周期后产生第一本地秒脉冲信号，如图6所示。
步骤54：获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差。
步骤55：根据第一相位差获取过滤相位差的阈值，并利用过滤相位差的阈值滤除标准秒脉冲信号中的干扰信号。
其中，步骤54-55与上述实施例中步骤33-34相同，在此不再赘述。
步骤56：利用时钟校准算法处理第一相位差以得到数字信号，并将数字信号转化为模拟信号。
在获得第一相位差之后，可以利用时钟校准算法(如PID算法，Proportion Integral Differential，比例积分微分)处理第一相位差，将第一相位差转化为数字信号，并将数字信号转化为模拟信号。
步骤57：利用模拟信号使得振荡器输出第一时钟信号。
该模拟信号可以为电压信号，利用产生的电压从而可以调整振荡器 的振荡频率，使得振荡器输出第一时钟信号。
步骤58：对第一时钟信号进行倍频，以产生第二时钟信号。
步骤59：对第二时钟信号进行计数，以产生第二本地秒脉冲信号。
在获取第一时钟信号之后，对该第一时钟信号进行倍频，以生成第二时钟信号，然后对第二时钟信号进行计数，获取周期为1秒的第二本地秒脉冲信号；第二本地秒脉冲信号与标准秒脉冲信号之间的第二相位差小于第一相位差，从而实现了本地秒脉冲信号对标准秒脉冲信号的跟随。
进一步地，可以在通电后默认过滤相位差的阈值为最大值，时钟锁定之前该过滤相位差的阈值不变，时钟锁定后开始调整过滤相位差的阈值；首先计算出预设时间内第一本地秒脉冲信号与标准秒脉冲信号之间的多个第一相位差的最大值和最小值，然后根据当前过滤相位差的阈值和当前第一相位差的最大值、最小值判断是否要修改相位差阈值。
将与标准秒脉冲信号之间的相位差大于修改后的相位差阈值的信号记作无用信号，将与标准秒脉冲信号之间的相位差小于修改后的相位差阈值的信号记作有用信号，从而将干扰信号滤除。
下面具体说明相位差阈值的变化，假设有三个相位差阈值：第一相位差阈值、第二相位差阈值和第三相位差阈值，第一相位差阈值、第二相位差阈值和第三相位差阈值对应的状态分别用State1、State2和State3表示，相位差阈值的自动调整通过状态跳转实现，如图7所示。
①时钟锁定后进入第一相位差阈值，即最大的相位差允许范围，此时过滤相位差的阈值也为最大值(预设第一过滤相位差的阈值)。
当预设时间内所有第一相位差均小于第二相位差阈值，则认为第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差在减小，需要跳到第二相位差阈值对应的状态State2，过滤相位差的阈值随之降低，将过滤相位差的阈值设置为预设第二过滤相位差的阈值。
若预设时间内所有第一相位差均小于第三相位差阈值，则跳到第三相位差阈值对应的状态State3，过滤相位差的阈值降得更低，将过滤相位差的阈值设置为预设第三过滤相位差的阈值。
若至少有一个第一相位差大于第二相位差阈值且小于第一相位差阈值，则保持在第一相位差阈值对应的状态不变，即过滤相位差的阈值为预设第一过滤相位差的阈值。
②当处于第二相位差阈值对应的状态State2时
若预设时间内所有第一相位差均大于第二相位差阈值，即预设时间内的相位差全部被过滤，则认为第一相位差在增大，则跳到第一相位差阈值对应的状态State1。
若预设时间内所有第一相位差均小于第三相位差阈值，则跳到第三相位差阈值对应的状态State3，过滤相位差的阈值进一步降低为第三过滤相位差的阈值。
若至少有一个第一相位差大于第三相位差阈值且小于第二相位差阈值，则保持在第二相位差阈值对应的状态State2不变，即过滤相位差的阈值为预设第二过滤相位差的阈值。
③当处于第三相位差阈值对应的状态State3时
若预设时间内的所有第一相位差均大于第三相位差阈值，即预设时间内的相位差全部被过滤，则认为第一相位差在增大，则跳到第二相位差阈值对应的状态State2，将过滤相位差的阈值设置为预设第二过滤相位差的阈值。
若预设时间内的所有第一相位差均大于第二相位差阈值，则跳到第一相位差阈值对应的状态State1，将过滤相位差的阈值设置为预设第一过滤相位差的阈值。
若至少有一个第一相位差小于第三相位差阈值，则保持在第三相位差阈值对应的状态State3不变，即过滤相位差的阈值为预设第三过滤相位差的阈值。
若第一相位差越来越小，表明本地时钟很好地跟踪了标准时钟，相位差阈值将减小，过滤相位差的阈值就会下降，比过滤相位差的阈值大的信号都认为是干扰信号而被过滤；若第一相位差越来越大，则相位差阈值将变大，过滤相位差的阈值就会增大；从而能够根据实际本地秒脉冲信号和标准秒脉冲信号的第一相位差数据，产生更贴合实际环境的过 滤相位差的阈值。
在第一本地秒脉冲信号对标准秒脉冲信号的跟随过程中，上述的三个状态可能会不断转换，可以根据当前的第一相位差不断调整当前过滤相位差的阈值，实现自动调整过滤相位差的阈值，提高滤除干扰信号的效果。
例如，如图8所示，第0秒开始上电，此时默认相位差的阈值最大，M秒后时钟锁定，进入第一相位差阈值对应的状态State1。
第一个N秒结束时，由于所有第一相位差都小于第二相位差阈值Diff2，所以跳转到第二相位差阈值对应的状态State2。
第二个N秒结束时，由于所有第一相位差都大于第二相位差阈值Diff2，所以状态升到第一相位差阈值对应的状态State1。
第三个N秒结束时，由于所有第一相位差都小于第二相位差阈值Diff2，所以状态降到第二相位差阈值对应的状态State2。
最后第四个N秒结束时，由于所有第一相位差都小于第三相位差阈值Diff3，所以状态降到第三相位差阈值对应的状态State3。
从上面可知，两个相邻状态(如：State2和State1)间的相互跳转虽然使用同一个判断数值Diff2，但一个条件是预设时间内所有第一相位差都大于第二相位差阈值Diff2，另一个条件是预设时间内所有第一相位差都小于第二相位差阈值Diff2，两者并不相同，可以区分不同的状态，从而更改过滤相位差的阈值。
总而言之，若当前处于第二相位差阈值对应的状态State2，要保持过滤相位差的阈值不变，那么预设时间内必须至少有一个第一相位差落在相位差阈值[Diff1，Diff2]之间；如果要降低相位差阈值到第三相位差阈值Diff3，则预设时间内所有的第一相位差都要小于第三相位差阈值Diff3；如果要增大相位差阈值到第一相位差阈值Diff1，那么预设时间内所有的第一相位差都要大于第二相位差阈值Diff2。
区别于现有技术，本申请提供了一种时钟校准的方法，获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差，根据第一相位差和预设的相位差之间的关系调整过滤相位差的阈值，能够实现自动调整滤 除干扰信号的过滤相位差的阈值，减少了干扰信号的影响，然后利用时钟校准算法处理第一相位差以得到数字信号，并将数字信号转化为模拟信号，然后利用该模拟信号控制振荡器输出第二时钟信号以产生第二本地秒脉冲信号，重新生成的第二本地秒脉冲信号与标准秒脉冲之间的第二相位差小于第一相位差，达到锁定标准秒脉冲的目的。
参阅图9，图9是本申请提供的时钟校准装置一实施例的结构示意图；该时钟校准装置至少包括时钟源91、本地时钟产生电路92、鉴相器93和处理器94。
鉴相器93与时钟源91和本地时钟产生电路92耦接，处理器94的一端与鉴相器93耦接，处理器94的另一端与本地时钟产生电路92的一端耦接，本地时钟产生电路92、鉴相器93和处理器94形成负反馈。
时钟源91用于输出标准秒脉冲信号，本地时钟产生电路92用于获得第一本地秒脉冲信号，鉴相器93用于接收到标准秒脉冲信号和第一本地秒脉冲信号，并获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差，处理器94用于根据第一相位差获取过滤相位差的阈值，并利用过滤相位差的阈值滤除标准秒脉冲信号中的干扰信号。
区别于现有技术，本申请提供了一种时钟校准装置，通过鉴相器93获取时钟源91输出的标准秒脉冲信号和本地时钟产生电路92输出的第一本地秒脉冲信号之间的第一相位差，并通过处理器94根据第一相位差调整过滤相位差的阈值，实现自动调整滤除干扰信号的过滤相位差的阈值，减少了干扰信号的影响，同时利用处理器94控制本地时钟产生电路102，使得本地时钟产生电路102输出的第一本地秒脉冲锁定时钟源91，提高了本地时钟的稳定性。
参阅图10，图10是本申请提供的时钟校准装置另一实施例的结构示意图；该时钟校准装置至少包括时钟源101、本地时钟产生电路102、鉴相器103和处理器104。
时钟源101为全球导航卫星系统或精密时钟同步协议，用于输出标准秒脉冲信号；本地时钟产生电路102包括互相连接的倍频与计数电路1021和振荡器1022。
倍频与计数电路1021为本地时钟源，用于接收到振荡器1022输出的第一时钟信号，通过倍频产生更高频的时钟，然后再通过计数产生第一本地秒脉冲信号输出给鉴相器103。
鉴相器103与时钟源101和倍频与计数电路1021耦接，用于接收到标准秒脉冲信号和第一本地秒脉冲信号，并获取第一本地秒脉冲信号与标准秒脉冲信号之间的第一相位差。
处理器104至少包括：调节过滤电路1041、调节器1042、数模转换器1043和时钟状态上报电路1044。
调节过滤电路1041与鉴相器103耦接，用于根据所述第一相位差获取过滤相位差的阈值，并利用所述过滤相位差的阈值滤除所述标准秒脉冲信号中的干扰信号；调节过滤电路1041还用于将预设周期内第一相位差与预设的相位差阈值进行比较，系统上电后，过滤相位差的阈值默认为预设第一过滤相位差的阈值；当预设周期内所有第一相位差小于预设第二过滤相位差的阈值时，将过滤相位差的阈值设置为预设第二过滤相位差的阈值；当预设周期内所有第一相位差小于预设第三过滤相位差的阈值时，将过滤相位差的阈值设置为预设第三过滤相位差的阈值；根据预设周期内所有第一相位差所在的数值区间，决定是否调整阈值及调整到哪一个阈值。其中，第一过滤相位差的阈值大于第二过滤相位差的阈值，第二过滤相位差的阈值大于第三过滤相位差的阈值。
时钟状态上报电路1044与调节过滤电路1041耦接，用于将时钟是否锁定的状态和第一相位差上传至中央处理器(图中未示出)中。
调节器1042与调节过滤电路1041耦接，用于利用时钟校准算法处理第一相位差以得到数字信号，该调节器1042可以为PID控制器。
数模转换器1043的一端与调节器1042耦接，用于将调节器1042发送的数字信号转化为模拟信号。
数模转换器1043的另一端与振荡器1022耦接，振荡器1022用于根据模拟信号产生第一时钟信号，并将第一时钟信号发送给倍频与计数电路1021，振荡器1022可以为压控振荡器；具体地，振荡器1022可以为恒温晶体振荡器，第一时钟信号的频率可为10MHz。
倍频与计数电路1021与鉴相器103连接，用于对振荡器1022输出的第一时钟信号进行倍频，并对接收到的倍频后的第一时钟信号进行计数，产生第一本地秒脉冲信号。
处理器104利用鉴相器103输出的第一相位差调整振荡器1022输出的第一时钟信号的频率，具体地，处理器104根据不同的第一相位差输出不同的电压信号，从而控制振荡器1022输出的第一时钟信号的频率；当鉴相器103输出的第一相位差非零时，处理器104调整输出的第一时钟信号的频率，从而调整倍频与计数电路1021输出的第一本地秒脉冲信号的相位，以使得调整后的倍频与计数电路1021输出的第一本地秒脉冲信号与时钟源101输出的标准秒脉冲信号之间的相位差减小。
鉴相器103、调节过滤电路1041、调节器1042、数模转换器1043和倍频与计数电路1021形成负反馈；当振荡器1022输出的时钟信号频率大于标准频率值时，通过鉴相器103比较时钟源101输出的标准秒脉冲信号和倍频与计数电路1021输出的第一本地秒脉冲信号之间的第一相位差，然后利用调节过滤电路1041确定过滤相位差的阈值，并利用过滤相位差的阈值滤除干扰信号，然后将第一相位差输入至调节器1042以处理成数字信号，调节器1042将数字信号传输给数模转换器1043，使得数模转换器1043输出的模拟信号减小，从而使得振荡器1022的输出频率减小，以逼近标准值。
例如，假设振荡器1022输出的频率为10MHz+10Hz，比预设值(10MHz)略大，通过比较第一本地秒脉冲信号和标准秒脉冲信号的相位，得到第一本地秒脉冲信号的相位提前标准秒脉冲信号，然后利用PID调节器减小输出的数字信号的数值，则数模转换器1043输出的电压也相应减小，因此振荡器1022输出的频率也相应减小，将频率降到10MHz+5Hz，从而减小了第一本地秒脉冲信号和标准秒脉冲信号之间的第一相位差，重复这个过程，即可以使得振荡器1022输出的频率逼近10MHz。
反之，如果振荡器1022输出的频率为10MHz-10Hz，比预设值小，通过比较第一本地秒脉冲信号和标准秒脉冲信号，得到本地秒脉冲信号 的相位落后标准秒脉冲信号的相位，利用PID调节器增加输出的数字信号的数值，则数模转换器1043输出的电压也相应增大，因此振荡器1022输出的频率也相应增大，将频率升到10MHz-5Hz，从而减小了第一本地秒脉冲信号和标准秒脉冲信号之间的第一相位差，重复这个过程，即可以得到本地精确的10M时钟，为通讯系统提供准确的时钟。。
区别于现有技术，本申请提供了一种时钟校准装置，通过鉴相器103获取时钟源101和倍频与计数电路1021之间的相位差，利用调节过滤电路1041实现自动调整滤除干扰信号的过滤相位差的阈值，减少了干扰信号的影响，然后通过调节器1042和数模转换器1043调节输入振荡器1022中的电压，从而改变振荡器1022的输出频率，使得倍频与计数电路1021输出的本地秒脉冲相位改变，缩小本地秒脉冲信号与标准秒脉冲信号之间的相位差，从而实现本地秒脉冲信号锁定标准秒脉冲信号，最终得到准确稳定的本地时钟。
在本申请所提供的几个实施方式中，应该理解到，所揭露的方法以及设备，可以通过其它的方式实现。例如，以上所描述的设备实施方式仅仅是示意性的，例如，模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施方式方案的目的。
另外，在本申请各个实施方式中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范 围内。

Claims (10)

  1. 一种时钟校准的方法，其特征在于，包括：
    接收到标准秒脉冲信号；
    获得第一本地秒脉冲信号；
    获取所述第一本地秒脉冲信号与所述标准秒脉冲信号之间的第一相位差；
    根据所述第一相位差获取过滤相位差的阈值，并利用所述过滤相位差的阈值滤除所述标准秒脉冲信号中的干扰信号。
  2. 根据权利要求1所述的时钟校准的方法，其特征在于，所述根据所述第一相位差获取过滤相位差的阈值的步骤，包括：
    系统上电后，过滤相位差的阈值默认为预设第一过滤相位差的阈值；
    当所述预设周期内所有所述第一相位差小于所述预设第二过滤相位差的阈值时，将过滤相位差的阈值设置为预设第二过滤相位差的阈值；
    当所述预设周期内所有所述第一相位差小于所述预设第三过滤相位差的阈值时，将过滤相位差的阈值设置为预设第三过滤相位差的阈值；
    其中，所述第一过滤相位差的阈值大于所述第二过滤相位差的阈值，所述第二过滤相位差的阈值大于所述第三过滤相位差的阈值，所述标准秒脉冲信号为全球导航卫星系统或精密时钟同步协议产生的脉冲信号。
  3. 根据权利要求1所述的时钟校准的方法，其特征在于，所述方法还包括：
    对滤除所述干扰信号后的所述第一相位差进行处理，以得到第二本地秒脉冲信号，使得所述第二本地秒脉冲信号与所述标准秒脉冲信号之间的第二相位差小于所述第一相位差。
  4. 根据权利要求3所述的时钟校准的方法，其特征在于，所述对滤 除所述干扰信号后的所述第一相位差进行处理，以得到第二本地秒脉冲信号，使得所述第二本地秒脉冲信号与所述标准秒脉冲信号之间的第二相位差小于所述第一相位差的步骤，包括：
    利用时钟校准算法处理所述第一相位差以得到数字信号，并将数字信号转化为模拟信号；
    利用所述模拟信号使得振荡器输出所述第一时钟信号；
    对所述第一时钟信号进行倍频，以产生第二时钟信号；
    对所述第二时钟信号进行计数，以产生所述第二本地秒脉冲信号。
  5. 根据权利要求1所述的时钟校准的方法，其特征在于，所述获得第一本地秒脉冲信号的步骤，包括：
    对振荡器输出的第一时钟信号进行倍频，并对倍频后的第一时钟信号进行计数，产生所述第一本地秒脉冲信号。
  6. 一种时钟校准装置，其特征在于，至少包括时钟源、鉴相器、本地时钟产生电路和处理器，所述鉴相器与所述时钟源和本地时钟产生电路耦接，所述处理器的一端与所述鉴相器耦接，所述处理器的另一端与所述本地时钟产生电路的一端耦接，所述本地时钟产生电路、所述鉴相器和所述处理器形成负反馈，所述时钟源用于输出标准秒脉冲信号，所述本地时钟产生电路用于获得第一本地秒脉冲信号，所述鉴相器用于接收到标准秒脉冲信号和所述第一本地秒脉冲信号，并获取所述第一本地秒脉冲信号与所述标准秒脉冲信号之间的第一相位差，所述处理器用于根据所述第一相位差获取过滤相位差的阈值，并利用所述过滤相位差的阈值滤除所述标准秒脉冲信号中的干扰信号。
  7. 根据权利要求6所述的时钟校准装置，其特征在于，
    所述时钟源为全球导航卫星系统或精密时钟同步协议。
  8. 根据权利要求6所述的时钟校准装置，其特征在于，所述本地时钟产生电路包括互相连接的振荡器以及倍频与计数电路，所述处理器至少包括：调节过滤电路、调节器、数模转换器和时钟状态上报电路，
    其中，所述调节过滤电路与所述鉴相器耦接，用于根据所述第一相位差获取过滤相位差的阈值，并利用所述过滤相位差的阈值滤除所述标 准秒脉冲信号中的干扰信号；所述时钟状态上报电路与所述调节过滤电路耦接，用于将所述第一相位差上传至中央处理器中；所述调节器与所述调节过滤电路耦接，用于利用时钟校准算法处理所述第一相位差以得到数字信号；所述数模转换器的一端与所述调节器耦接，用于将所述调节器发送的所述数字信号转化为模拟信号；所述振荡器的一端与所述数模转换器耦接，所述振荡器用于根据所述模拟信号产生所述第一时钟信号，并将所述第一时钟信号发送给所述倍频与计数电路；所述倍频与计数电路与所述鉴相器连接，用于对所述振荡器输出的所述第一时钟信号进行倍频，并对倍频后的第一时钟信号进行计数，产生所述第一本地秒脉冲信号。
  9. 根据权利要求8所述的时钟校准装置，其特征在于，
    系统上电后，过滤相位差的阈值默认为预设第一过滤相位差的阈值；当所述预设周期内所有所述第一相位差小于所述预设第二过滤相位差的阈值时，将过滤相位差的阈值设置为预设第二过滤相位差的阈值；当所述预设周期内所有所述第一相位差小于所述预设第三过滤相位差的阈值时，将过滤相位差的阈值设置为预设第三过滤相位差的阈值；其中，所述第一过滤相位差的阈值大于所述第二过滤相位差的阈值，所述第二过滤相位差的阈值大于所述第三过滤相位差的阈值。
  10. 根据权利要求8所述的时钟校准装置，其特征在于，
    所述振荡器为恒温晶体振荡器，所述第一时钟信号的频率为10MHz。
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