WO2020238919A1 - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置 Download PDF

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WO2020238919A1
WO2020238919A1 PCT/CN2020/092442 CN2020092442W WO2020238919A1 WO 2020238919 A1 WO2020238919 A1 WO 2020238919A1 CN 2020092442 W CN2020092442 W CN 2020092442W WO 2020238919 A1 WO2020238919 A1 WO 2020238919A1
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layer
pixel
quantum dot
display sub
light
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PCT/CN2020/092442
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English (en)
French (fr)
Inventor
舒适
李翔
徐传祥
于勇
黄海涛
岳阳
姚琪
黄睿
石戈
郭康
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京东方科技集团股份有限公司
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Priority to US17/263,984 priority Critical patent/US11327380B2/en
Publication of WO2020238919A1 publication Critical patent/WO2020238919A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133528—Polarisers
    • G02F1/133548—Wire-grid polarisers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13318—Circuits comprising a photodetector
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133614—Illuminating devices using photoluminescence, e.g. phosphors illuminated by UV or blue light
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133617—Illumination with ultraviolet light; Luminescent elements or materials associated to the cell
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/36—Micro- or nanomaterials

Definitions

  • the embodiments of the present disclosure relate to an array substrate, a display panel, and a display device.
  • the transmittance and color gamut of the liquid crystal display panel have encountered bottlenecks, and the method of wavelength conversion has to be selected to improve the transmittance and color gamut of the liquid crystal display panel to meet the display requirements.
  • Quantum dot material is an excellent wavelength conversion material.
  • the quantum dot material is made into a quantum dot pattern with pixel level size, which can specifically convert the light from the backlight into the color required by the pixel, which can meet the transmittance And the requirements of color gamut can increase the utilization of backlight.
  • the best built-in polarizers are metal nano-gratings. Since the metal nanograting is made of metal materials, if the metal nanograting is made on the upper substrate, an electric field will be formed between the metal nanograting and the pixel electrode in the lower substrate. For liquid crystal display products in In Plane Switching (IPS) or Advanced Super Dimension Switch (ADS) display modes, the electric field will greatly reduce the efficiency of the liquid crystal display. Therefore, the metal nanograting is usually arranged on the lower substrate; if the metal nanograting is arranged on the lower substrate, in order to realize normal display, the quantum dot pattern must also be placed on the lower substrate.
  • IPS In Plane Switching
  • ADS Advanced Super Dimension Switch
  • an array substrate including: a base substrate; a thin film transistor layer disposed on the base substrate; a first thin film transistor layer disposed on the side of the thin film transistor layer away from the base substrate Passivation layer; a quantum dot layer disposed on the side of the first passivation layer away from the base substrate and located in the display area of the array substrate; disposed on the quantum dot layer away from the base substrate
  • One side of the color filter layer, the orthographic projection of the quantum dot layer on the base substrate is located in the orthographic projection of the color filter layer on the base substrate; and is arranged in the first passivation A flat layer on the side facing away from the base substrate and the color filter layer on the side facing away from the base substrate; a metal wire grid polarizing layer disposed on the side of the flat layer facing away from the base substrate.
  • the thin film transistor layer includes a driving transistor part and a light sensing compensation transistor part, each of the driving transistor part and the light sensing compensation transistor part includes a gate, a gate insulating layer, an active layer, a source and a drain.
  • the array substrate also includes a photoelectric conversion device configured to receive the part of the excitation light generated by the quantum dot layer that is reflected by the metal wire grid polarizing layer and convert it into an electrical signal
  • the photoelectric conversion device includes an upper electrode and a lower electrode, and a photoelectric conversion layer sandwiched between the upper electrode and the lower electrode, and the lower electrode is electrically connected to the source or drain of the photosensitive compensation transistor portion.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines cross each other to define a plurality of display sub-pixels; each of the display sub-pixels includes the driving In the transistor part, the gate of the driving transistor part is electrically connected to the corresponding gate line, and the source or drain of the driving transistor is electrically connected to the corresponding data line; in each of the display sub-pixels, the The metal wire grid polarizing layer is provided with a pixel electrode on a side away from the base substrate, and the pixel electrode passes through a second via hole and a second lead filled in the second via hole and the drain of the driving transistor part. The electrode or source electrode is electrically connected.
  • the light sensing compensation transistor part and the photoelectric conversion device are located in at least one display sub-pixel among the plurality of display sub-pixels; the array substrate further includes a sensing device arranged in parallel with the plurality of gate lines. A control line and a signal read line arranged in parallel with the plurality of data lines; the gate of the light sensing compensation transistor part is electrically connected to the sensing control line, and the drain or source of the light sensing compensation transistor part The pole is electrically connected to the signal reading line.
  • the array substrate further includes a common electrode line arranged in parallel with the plurality of gate lines; in each of the display sub-pixels, the metal wire grid polarizing layer is filled in the first via hole and The first lead in a via hole is electrically connected to the common electrode line so that the metal wire grid polarizing layer also serves as a common electrode; and in the at least one display sub-pixel, the metal wire grid polarizing layer passes The third via hole and the third lead line filled in the third via hole are electrically connected with the upper electrode of the photoelectric conversion device.
  • the at least one display sub-pixel is a blue sub-pixel.
  • the orthographic projection of the color filter layer on the base substrate covers the orthographic projection of the active layer of the driving transistor portion on the base substrate and the active layer of the photosensitive compensation transistor portion Orthographic projection on the base substrate.
  • the array substrate further includes a black matrix layer disposed between the color filter layer and the thin film transistor layer; the orthographic projection of the black matrix layer on the base substrate covers the driving transistor part The orthographic projection of the active layer on the base substrate and the orthographic projection of the active layer of the photosensitive compensation transistor part on the base substrate.
  • the black matrix layer also covers the side surface of the photoelectric conversion layer, and an extension line of the side surface intersects the base substrate.
  • the array substrate further includes a second passivation layer located between the first passivation layer and the thin film transistor layer; the second passivation layer covers the driving transistor portion and the light sensing compensation transistor portion
  • the photoelectric conversion device is located between the first passivation layer and the second passivation layer, and the lower electrode of the photoelectric conversion device passes through the fourth via hole penetrating the second passivation layer and the The source or drain of the light sensing compensation transistor part is electrically connected.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines cross each other to define a plurality of display sub-pixels;
  • the plurality of display sub-pixels includes a first display Sub-pixels, second display sub-pixels, and third display sub-pixels;
  • the quantum dot layer includes a first quantum dot pattern located in the first display sub-pixel, and second quantum dots located in the second display sub-pixel The dot pattern and the third quantum dot pattern located in the third display sub-pixel, the first quantum dot pattern, the second quantum dot pattern, and the third quantum dot pattern emit light under the excitation of light from the backlight, so that the first The display sub-pixel, the second display sub-pixel and the third display sub-pixel respectively emit light of three different colors.
  • the light from the backlight source is ultraviolet light
  • the first display sub-pixel is a red sub-pixel, and the first quantum dot pattern generates red light under the excitation of the ultraviolet light
  • the second display sub-pixel The pixel is a green sub-pixel, and the second quantum dot pattern generates green light under the excitation of the ultraviolet light
  • the third display sub-pixel is a blue sub-pixel, and the third quantum dot pattern is in the ultraviolet Blue light is generated under the excitation of light.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines cross each other to define a plurality of display sub-pixels;
  • the plurality of display sub-pixels includes a first display Sub-pixels, second display sub-pixels, and third display sub-pixels;
  • the quantum dot layer includes a first quantum dot pattern located in the first display sub-pixel and a second quantum dot pattern located in the second display sub-pixel Dot pattern;
  • the array substrate further includes a light diffusion pattern located in the third display sub-pixel, the light diffusion pattern is arranged in the same layer as the first quantum dot pattern and the second quantum dot pattern;
  • the first quantum dot pattern and the second quantum dot pattern emit light under the excitation of light from a backlight source, and the light from the backlight source passes through the light diffusion pattern and is uniformized by the light diffusion pattern, so that the first The one display sub-pixel, the second display sub-pixel and the third display sub-pixel respectively
  • the third display subpixel is a blue subpixel, and the light from the backlight source is blue light; the first display subpixel is a red subpixel, and the first quantum dot pattern is excited by the blue light Red light is generated; the second display sub-pixel is a green sub-pixel, and the second quantum dot pattern generates green light under the excitation of the blue light.
  • the light diffusion pattern includes an organic matrix and inorganic particles dispersed in the organic matrix.
  • the metal wire grid polarizing layer includes an etch stop layer disposed on the side of the flat layer away from the base substrate, and a metal wire grid disposed on the side of the etching stop layer away from the base substrate Layer and a protective layer disposed on the side of the metal wire grid layer away from the base substrate.
  • the metal wire grid layer includes a plurality of metal strips arranged in parallel, and the protective layer covers two adjacent metal strips among the plurality of metal strips and covers the metal strips located between the two adjacent metal strips. Area, but the protection layer does not contact the etch barrier layer exposed in the area between the two adjacent metal strips.
  • the flat layer includes a thermosetting layer and a photocuring layer, the thermosetting layer is closer to the base substrate than the photocuring layer, and a surface of the photocuring layer away from the base substrate is flat.
  • a display panel including the above-mentioned array substrate, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the accompanying substrate .
  • a display device including the display panel as described above.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of another structure of an array substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic structural diagram of a display panel provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic circuit diagram of an array substrate provided by an embodiment of the present invention.
  • an array substrate including:
  • the first passivation layer 9 arranged on the side of the thin film transistor layer away from the base substrate 1;
  • the quantum dot layer 10 disposed on the side of the first passivation layer 9 away from the base substrate 1 and located in the display area of the array substrate;
  • the metal wire grid polarizing layer 13 is disposed on the side of the flat layer 12 away from the base substrate 1.
  • the above-mentioned array substrate includes a base substrate and a thin film transistor layer, a first passivation layer 9, a quantum dot layer 10, a color filter layer 11, a flat layer 12, and a metal wire grid polarizing layer 13 which are sequentially arranged on the array substrate;
  • the quantum dot layer 10 is arranged in the display area, the quantum dot layer 10 is provided with a color filter layer 11 on the side away from the base substrate 1, and the orthographic projection of the color filter layer 11 on the base substrate 1 covers the quantum dot layer 10
  • the color filter layer 11 and the first passivation layer 9 are provided with a flat layer 12 on the side facing away from the base substrate 1, and the flat layer 12 is provided with metal on the side facing away from the base substrate 1.
  • the thin film transistor layer includes many electrical components, and the first passivation layer 9 covers the thin film transistor layer to provide protection for the thin film transistor layer and achieve required electrical insulation between the electrical components in the thin film transistor layer and other electrical components.
  • the quantum dot layer 10 is located in the display area and generates excitation light under the excitation of light from the backlight. The excitation light is modulated by the liquid crystal layer 21 (see below) to realize the display function; by using the quantum dot layer 10, the display device can be significantly improved The display effect and improve the utilization rate of light from the backlight.
  • the quantum dot layer 10 may not be able to convert all the light from the backlight, so part of the light from the backlight may pass through the quantum dot layer 10 and mix with the excitation light, resulting in the monochromaticity of the excitation light.
  • light from the external environment may also be incident on the quantum dot layer 10 from the side of the metal wire grid polarizing layer 13 away from the base substrate 1, causing the quantum dot layer 10 to be undesirably excited by external ambient light Glow.
  • a color filter layer 11 is provided on the side of the quantum dot layer 10 away from the base substrate 1, and the orthographic projection of the color filter layer 11 on the base substrate 1 covers the quantum dots.
  • the orthographic projection of the layer 10 on the base substrate 1 is to shield the part of the light from the external environment and the light from the backlight that passes through the quantum dot layer 10, ensuring the monochromaticity of the excitation light emitted by the quantum dot layer 10, which is remarkable
  • the display effect of the display panel including the array substrate is improved.
  • the metal wire grid polarizing layer 13 is provided on the side of the quantum dot layer 10 away from the base substrate 1, so that the excitation light from the quantum dot layer 10 has polarization characteristics, ensuring that the array substrate is included.
  • the LCD panel realizes normal display.
  • the structure obtained after the quantum dot layer 10 is formed on the base substrate 1 has a large surface level difference, so that the production of the metal wire grid polarizing layer 13 with a nanometer-scale fine structure cannot be performed normally.
  • the first passivation layer 9 is disposed on the side facing away from the base substrate 1 and the color filter layer 11 is disposed on the side facing away from the base substrate 1.
  • the metal wire grid polarizing layer 13 is disposed on the flat layer 12, so that a high-quality metal wire grid polarizing layer 13 can be obtained.
  • the array substrate includes both the quantum dot layer 10 and the metal wire grid polarizing layer 13, and the orthographic projection of the color filter layer 11 on the base substrate 1 covers the quantum dot layer 10 on the base substrate 1. Orthographic projection can significantly improve the display effect of the display panel using the array substrate.
  • the quantum dot layer 10 located in the display area of the array substrate can be understood as: the quantum dot layer 10 includes a plurality of quantum dot patterns (for example, the first quantum dot pattern 10a, the second quantum dot pattern 10b described below And the third quantum dot pattern 10c), the plurality of quantum dot patterns are respectively located in the display area of a plurality of display sub-pixels (for example, the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel as described below) Inside.
  • the plurality of quantum dot patterns respectively located in the display regions of the plurality of display sub-pixels are spaced apart from each other.
  • the color filter layer 11 is arranged on the side of the quantum dot layer 10 away from the base substrate 1, and the orthographic projection of the quantum dot layer 10 on the base substrate 1 is located on the color filter layer 11 on the base substrate 1.
  • the orthographic projection can be understood as: in the display sub-pixels, the color filter layer 11 is arranged on the side of the quantum dot pattern away from the base substrate 1 and the orthographic projection of the quantum dot pattern on the base substrate 1 is located on the color filter layer 11 In the orthographic projection on the base substrate 1.
  • the color filter layer 11 includes a plurality of parts respectively located in a plurality of display sub-pixels, the plurality of parts are spaced apart from each other, and the plurality of parts respectively cover a plurality of quantum dot patterns.
  • the excitation light generated by the excitation of the quantum dot layer 10 (that is, the quantum dot pattern in the display sub-pixel) is monochromatic light, and the color of the excitation light and the color that can be transmitted through the color
  • the color of the light of the filter layer 11 is the same, so that the color filter layer 11 only allows the excitation light to pass and does not allow the light with a color different from that of the excitation light to pass.
  • the flat layer 12 includes a thermosetting layer and a photocuring layer.
  • the thermosetting layer is closer to the base substrate 1 than the photocuring layer, and the surface of the photocuring layer away from the base substrate 1 is flat.
  • the thermal curing process is slow, allowing the material to be cured to flow sufficiently to eliminate as much surface gap as possible; the light curing process is faster, and the material to be cured can be shaped as soon as possible when the material to be cured reaches a flat state to obtain a flat surface.
  • the planarization layer 12 adopts a double-layer structure of a thermosetting layer and a photocuring layer, which can make the surface of the planarization layer 12 away from the base substrate 1 have excellent planarization characteristics, and ensure the yield rate of the metal wire grid polarizing layer 13 The metal wire grid polarizing layer 13 is obtained well.
  • the thin film transistor layer includes a driving transistor part and a light sensing compensation transistor part.
  • Each of the driving transistor part and the light sensing compensation transistor part includes a gate 2 and a gate formed on the base substrate 1.
  • the array substrate further includes a photoelectric conversion device disposed on the base substrate 1.
  • the photoelectric conversion device is configured to receive the excitation light generated by the quantum dot layer 10 by the metal wire grid polarizing layer. 13 and convert it into an electrical signal;
  • the photoelectric conversion device includes an upper electrode 8 and a lower electrode 8'and a photoelectric conversion layer 7 sandwiched between the upper electrode 8 and the lower electrode 8', the lower electrode 8'and the light
  • the source or drain of the sensing compensation transistor part is electrically connected.
  • the excitation light generated by the excitation of the quantum dot layer 10 is incident on the metal wire grid polarizing layer 13 after passing through the color filter layer 11, a part of which is transmitted through the metal wire grid polarizing layer 13 to become polarized light, and a part is polarized by the metal wire grid polarizing layer. 13 reflection becomes reflected light.
  • the amount of polarized light increases, the amount of reflected light decreases; when the amount of polarized light decreases, the amount of reflected light increases.
  • the reflected light is incident on the photoelectric conversion device and converted into an electric signal by the photoelectric conversion device, and the electric signal is output to the detection circuit through the light sensing compensation transistor part and the signal reading line to be described below.
  • the detection circuit judges the magnitude of the electrical signal, can judge the magnitude of the reflected light, and thus can judge the magnitude of the polarized light.
  • the area where the amount of polarized light is abnormal can be found in real time, and the abnormal area can be compensated through an electrical compensation method to ensure the uniformity of the display screen.
  • FIG. 4 is a circuit diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes a plurality of gate lines 111 and a plurality of data lines 121 disposed on the base substrate 1.
  • the plurality of gate lines 111 and the plurality of data lines 121 cross each other to define a plurality of display sub-pixels 100; each The display sub-pixel 100 includes a driving transistor part (see area A in FIG.
  • the gate of the driving transistor part is electrically connected to the corresponding gate line 111, and the source or drain of the driving transistor is electrically connected to the corresponding data line 121;
  • a pixel electrode 20 is provided on the side of the metal wire grid polarizing layer 13 away from the base substrate. The pixel electrode 20 passes through the second via hole 17 and the second via hole 17 filled in.
  • the lead 192 is electrically connected to the drain or source of the driving transistor part.
  • the photosensitive compensation transistor part (see area B in FIG. 4) and the photoelectric conversion device (see area C in FIG. 4) are located in at least one display sub-pixel among the plurality of display sub-pixels 100; the array substrate It also includes a sensing control line 112 arranged in parallel with the plurality of gate lines 111 and a signal reading line 122 arranged in parallel with the plurality of data lines 121; the gate of the light sensing compensation transistor part is electrically connected to the sensing control line 112, The drain or source of the sensing compensation transistor part is electrically connected to the signal reading line 122. A control signal is applied to the sensing touch line 112 to control the turn-on and turn-off of the light sensing compensation transistor part.
  • the light compensation transistor is partially turned on, and the electrical signal generated by the photoelectric conversion device is output to the signal reading line 122 through the light compensation transistor, and then output to the external detection circuit through the signal reading line 122, and the external detection circuit detects the electrical signal.
  • the size is judged. According to the signal fed back by the detection circuit, it is determined whether there is an area with uneven display brightness, so as to determine whether to perform electrical compensation.
  • the array substrate further includes a common electrode line 15 arranged in parallel with the plurality of gate lines 111; in each display sub-pixel 100, the metal wire grid polarizing layer 13 passes through the first via hole 16 and the first lead 191 filled in the first via 16 are electrically connected to the common electrode line 15 so that the metal wire grid polarizing layer 13 is also used as a common electrode.
  • the metal wire grid polarizing layer 13 includes a plurality of metal strips. The width of the metal strips is on the order of nanometers and the width of the area between adjacent metal strips is also on the order of nanometers. In this case, the metal wire grid polarizing layer 13 It can be regarded as a plate electrode as a whole.
  • one electrode plate of the liquid crystal capacitor Clc is a pixel electrode 20, and the other electrode plate is a common electrode, such as a metal wire grid polarizing layer 13 used as a common electrode.
  • An electric field is formed between the pixel electrode 20 and the common electrode to control the deflection state of the liquid crystal molecules in the liquid crystal layer 21 (see FIG. 3), thereby controlling the polarization of the polarized light transmitted through the metal wire grid polarizing layer 13 through the liquid crystal layer 21 Transmittance to achieve image display.
  • the metal wire grid polarizing layer 13 passes through the third via 18 and the third via filled in the third via 18
  • the lead 193 is electrically connected to the upper electrode 8 of the photoelectric conversion device, thereby providing a bias voltage for the photoelectric conversion device.
  • the gate line 111, the sensing control line 112, the common electrode line 15, the gate of the driving transistor part, and the gate of the light sensing compensation transistor part are arranged in the same layer and with the same material.
  • the source and drain of the driving transistor part, the source and drain of the light compensation transistor part, the data line 121 and the signal reading line 122 are arranged in the same layer and with the same material.
  • the light-sensing compensation transistor part and the photoelectric conversion device do not have to be provided in each display sub-pixel 100, but are selectively provided in one or a part of the display sub-pixels 100;
  • the setting position and setting number of the conversion device can be flexibly selected according to actual needs.
  • the at least one display sub-pixel provided with the light-sensing compensation transistor part and the photoelectric conversion device is, for example, a blue sub-pixel, so as to reduce the light-sensing compensation transistor part and the photoelectric conversion device as much as possible. There is an impact on the display brightness.
  • the metal wire grid polarizing layer 13 includes an etching stopper layer 131 disposed on the side of the flat layer 12 away from the base substrate 1, and an etching stopper layer 131 disposed on the side facing away from the base substrate 1.
  • the formation process of the metal wire grid layer 132 is as follows: a metal film is formed on the etching stop layer 131; a photoresist layer is formed on the metal film; the photoresist layer is imprinted using a nanoimprint template to form Photoresist pattern; the metal film is etched with the photoresist pattern as a mask pattern to form a metal wire grid layer 132.
  • the etching stop layer 131 By providing the etching stop layer 131, the over-etching phenomenon can be prevented during the above-mentioned etching process, and the underlying flat layer 12 can be protected.
  • a protective layer 133 is provided on the metal wire grid layer 132 to protect the metal wire grid layer 132 and prevent the metal wire grid layer 132 from being damaged in subsequent manufacturing processes.
  • the protective layer 133 is located between the metal wire grid layer 132 and the pixel electrode 20, so the protective layer 133 also has the function of achieving electrical insulation between the metal wire grid layer 132 and the pixel electrode 20.
  • the metal wire grid layer 132 includes a plurality of metal strips arranged in parallel.
  • the protective layer 133 covers two adjacent metal strips among the plurality of metal strips and covers the area between the two adjacent metal strips, but the protective layer 133 is not in contact with the The exposed etch stop layer 131 in the area between two adjacent metal bars is in contact; in this case, the area between two adjacent metal bars is not filled with any dielectric, which can improve the metal wire grid layer 132
  • the polarization characteristics of, make more light can pass through the metal wire grid layer 132 to become polarized light.
  • the material of the protective layer 133 may be oxide, nitride, or oxynitride, such as silicon oxide.
  • a suitable forming process such as a chemical vapor deposition method, can be selected so that the protective layer 133 has the structure shown in FIG. 2.
  • the orthographic projection of the color filter layer 11 on the base substrate 1 covers the orthographic projection of the channel portion in the thin film transistor layer on the base substrate 1.
  • the orthographic projection of the color filter layer 11 on the base substrate 1 covers the orthographic projection of the active layer (for example, the channel region in the active layer) of the driving transistor portion on the base substrate 1 and
  • the orthographic projection of the active layer (for example, the channel region in the active layer) of the photosensitive compensation transistor part on the base substrate 1 to avoid glare in the subsequent manufacturing process, such as glare in the process of making the flat layer 12 It affects the characteristics of the driving transistor part and the light sensing compensation transistor part, and prevents the driving transistor part and the light sensing compensation transistor part from generating undesired leakage current.
  • the array substrate further includes a black matrix layer 14 disposed between the color filter layer 11 and the thin film transistor layer.
  • the orthographic projection of the black matrix layer 14 on the base substrate 1 covers the orthographic projection of the active layer of the driving transistor part (for example, the channel region in the active layer) on the base substrate 1 and the photosensitive compensation transistor part.
  • the orthographic projection of the active layer (for example, the channel region in the active layer) on the base substrate 1 to avoid strong light in the subsequent process, such as the strong light in the process of making the flat layer 12, which affects the driving transistor part And the characteristics of the photosensitive compensation transistor part, and prevent the driving transistor part and the photosensitive compensation transistor part from generating undesired leakage current.
  • both the color filter layer 11 and the black matrix layer 14 or any one of them can be selected to cover the active layer (for example, the channel region in the active layer) of the driving transistor.
  • the active layer of the photosensitive compensation transistor part for example, the channel region in the active layer.
  • the black matrix layer 14 also covers these traces; the area where the driving transistor part is located, the area where the photosensitive compensation transistor part is located, and other areas covered by the black matrix are the non-display areas of the display sub-pixels, and the non-display areas of the display sub-pixels The other area is the display area, and the quantum dot pattern included in the quantum dot layer 10 as described above is located in the display area of the display sub-pixel.
  • the quantum dot layer 10 the light sensing compensation transistor part and the photoelectric conversion device are placed on the array substrate.
  • the quantum dot layer 10 emits light stably and is not affected by the gray scale, which facilitates the collection of stable signals by the photoelectric conversion device. Realize accurate real-time monitoring and compensation for areas with uneven display brightness.
  • the black matrix layer 14 also covers the side surface of the photoelectric conversion layer 7, and the extension line of the side surface intersects the base substrate 1.
  • the area where the amount of polarized light is not uniform can be found in real time and the gray scale compensation can be performed according to the feedback signal; the sidewall of the photoelectric conversion layer 7 can be shielded by the black matrix layer 14
  • the light from other areas is shielded from incident to the photoelectric conversion layer 7, to ensure that the photoelectric conversion layer 7 only receives the reflected light in and around it, so as to realize the uniformity compensation of the metal wire grid polarizing layer 13 and the compensation of the efficiency attenuation of the quantum dot layer 10 to avoid Burning screen problem.
  • the metal wire grid polarizing layer 13 passes through the metal wire grid polarizing layer 13, the planarization layer 12, the first passivation layer 9 and the gate insulating layer 3 through the first via 16 and filling
  • the first lead 191 in the first via 16 is electrically connected to the common electrode line 15.
  • the metal wire grid polarizing layer 13 is electrically connected to the common electrode line 15 through the first via 16 and the first lead 191 provided in the first via 16 in the non-display area, and the electrical connection in this way hardly affects the pixel aperture ratio;
  • the metal wire grid layer 132 is exposed at the opening of the first via hole 16 to ensure that the first lead 191 and the metal wire grid layer 132 are electrically connected.
  • the pixel electrode 20 passes through the second via 17 penetrating the metal wire grid polarizing layer 13, the planarization layer 12, and the first passivation layer 9, and the second via 17 filled in the second via 17
  • the two leads 192 are electrically connected to the drain or source of the driving transistor part.
  • the metal wire grid layer 132 is not exposed at the opening of the second via hole 17 to prevent the metal wire grid layer 132 from being short-circuited with the pixel electrode 20 when it is used as a common electrode.
  • first lead 191 and the second lead 192 are arranged in the same layer and the same material to simplify the manufacturing process.
  • the material of the pixel electrode 20 can be a transparent conductive metal oxide, such as ITO, IGZO, and so on.
  • a transparent conductive metal oxide such as ITO, IGZO, and so on.
  • high temperature annealing above 200° C. is not performed, and only annealing at 100-200° C. is performed, which can prevent the quantum dot layer 10 from being affected by the high temperature process.
  • the pixel electrode 20 is electrically connected to the source electrode or the drain electrode 5 through a via hole and a lead, and the connection method is simple.
  • the metal wire grid polarizing layer 13 passes through the metal wire grid polarizing layer 13, the third via 18 of the flat layer 12, and the third lead 193 filled in the third via 18 and The upper electrode 8 is electrically connected.
  • the metal wire grid polarizing layer 13 is connected to the upper electrode 8 through via holes to reduce the influence on the aperture ratio as much as possible.
  • the metal wire grid layer 132 is exposed at the opening of the third via hole 18 to ensure that the third lead 193 and the upper electrode 8 are electrically connected.
  • the protective layer 133 also covers the third lead 193, but the protective layer 133 does not cover the first lead 191 nor the second lead 192.
  • the material of the first lead 191, the second lead 192, and the third lead 193 is metal or transparent conductive metal oxide.
  • the array substrate further includes a second passivation layer 6 located between the first passivation layer 9 and the thin film transistor layer; the second passivation layer 6 covers the driving transistor part and the photosensitive compensation transistor.
  • the photoelectric conversion device is located between the first passivation layer 9 and the second passivation layer 6, and the lower electrode 8'of the photoelectric conversion device passes through the fourth via hole 60 penetrating the second passivation layer 6 and the photosensitive compensation transistor Part of the source or drain is electrically connected.
  • the array substrate according to the embodiment of the present disclosure includes a plurality of gate lines 111 and a plurality of data lines 121, and the plurality of gate lines 111 and the plurality of data lines 121 cross each other to define a plurality of display sub-pixels 100.
  • the plurality of display sub-pixels 100 includes a first display sub-pixel 101, a second display sub-pixel 102, and a third display sub-pixel 103;
  • the quantum dot layer 10 includes a first quantum dot pattern 10a located in the first display sub-pixel 101 , The second quantum dot pattern 10b in the second display sub-pixel 102 and the third quantum dot pattern 10c in the third display sub-pixel 103, the first quantum dot pattern 10a, the second quantum dot pattern 10b and the third quantum dot pattern
  • the dot pattern 10c emits light under the excitation of the light from the backlight source, so that the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel respectively emit light of three different colors. For example, three different colors of light can be combined into white light.
  • the first quantum dot pattern 10a, the second quantum dot pattern 10b, and the third quantum dot pattern 10c are respectively formed of different materials.
  • the light from the backlight source is ultraviolet light
  • the first display sub-pixel 101 is a red sub-pixel
  • the first quantum dot pattern 10a generates red light under the excitation of ultraviolet light
  • the second display sub-pixel 102 is a green sub-pixel
  • the second quantum dot pattern 10b generates green light under the excitation of ultraviolet light
  • the third display sub-pixel 103 is a blue sub-pixel, and the third quantum dot pattern 10c generates blue light under the excitation of the ultraviolet light.
  • the height of the first quantum dot pattern 10a, the height of the second quantum dot pattern 10b, and the height of the third quantum dot pattern 10c are equal to each other, so as to reduce the difficulty of manufacturing the flat layer 12 .
  • the quantum dot layer 10 includes a first quantum dot pattern 10a located in the first display sub-pixel 101 and a second quantum dot pattern 10b located in the second display sub-pixel 102; the array substrate further includes a third display sub-pixel 103
  • the light diffusion pattern 10d is arranged in the same layer as the first quantum dot pattern 10a and the second quantum dot pattern 10b; the first quantum dot pattern 10a and the second quantum dot pattern 10b are excited by the light from the backlight
  • the light from the backlight passes through the light diffusion pattern 10d and is uniformized by the light diffusion pattern 10d, so that the first display sub-pixel 101, the second display sub-pixel 102, and the third display sub-pixel 103 emit three different colors respectively Of light.
  • the first quantum dot pattern 10a and the second quantum dot pattern 10b are respectively formed of different materials.
  • the light diffusion pattern 10d includes an organic matrix and inorganic particles dispersed in the organic matrix; the material of the organic matrix is, for example, a resin material with stable chemical properties, and the material of the inorganic particles is, for example, titanium dioxide, silicon dioxide, zirconium dioxide, and aluminum oxide. and many more.
  • the third display sub-pixel 103 is a blue sub-pixel, and the light from the backlight is blue; the first display sub-pixel 101 is a red sub-pixel, and the first quantum dot pattern 10a generates red light under the excitation of the blue; The second display sub-pixel 102 is a green sub-pixel, and the second quantum dot pattern 10b generates green light under the excitation of blue light.
  • the height of the light diffusion pattern 10d, the height of the first quantum dot pattern 10a, and the height of the second quantum dot pattern 10b are equal to each other, so as to reduce the manufacturing difficulty of the flat layer 12.
  • the embodiment of the present disclosure also provides a display panel, as shown in FIG. 3, which includes the array substrate provided in the above technical solution, a counter substrate 22 disposed opposite to the array substrate, and a display panel disposed between the array substrate and the counter substrate 22.
  • Liquid crystal layer 21 is located on the side of the array substrate 1 away from the counter substrate 22.
  • the backlight source may be a direct type backlight source or an edge type backlight source.
  • the backlight uses a light source emitting blue or ultraviolet light, such as OLED lamp beads or light bars.
  • the embodiment of the present disclosure also provides a display device, including the display panel provided in the above technical solution.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display device including the display panel provided in the above technical solution.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the embodiment of the present disclosure does not limit this.

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Abstract

一种阵列基板、显示面板和显示装置。阵列基板包括：衬底基板(1)以及依次设置于衬底基板(1)上的薄膜晶体管层、第一钝化层(9)、量子点层(10)、彩色滤光层(11)、平坦层(12)以及金属线栅偏光层(13)。量子点层(10)位于阵列基板的显示区域内，并且量子点层(10)在衬底基板(1)上的正投影位于彩色滤光层(11)在衬底基板(1)上的正投影内。

Description

阵列基板、显示面板和显示装置
本申请要求于2019年5月27日递交的第201910444498.3号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板、显示面板和显示装置。
背景技术
随着液晶显示产品的发展，液晶显示面板的透过率和色域已经遇到瓶颈，不得不选择通过波长转换的方式来提高液晶显示面板的透过率和色域，进而满足显示需求。
量子点材料是优秀的波长转换材料，将量子点材料做成具有像素级别尺寸的量子点图案，可以针对性的将来自背光源的光转换为该像素所需要的颜色，既可以满足透过率和色域的要求又可以提高背光的利用率。
由于量子点材料的荧光特性，会完全破坏光的偏振状态，因此必须搭配内置偏光片使用，目前效果最好的内置偏光片是金属纳米光栅。由于金属纳米光栅是金属材料制作的，如果在上基板制作金属纳米光栅，金属纳米光栅与下基板中的像素电极之间会形成电场。对于平面转换(In Plane Switching，IPS)或高级超维场开关(AdvancedSuper Dimension Switch，ADS)显示模式的液晶显示产品，该电场会导致液晶显示效率大幅降低。因此，通常将金属纳米光栅设置在下基板上；如果金属纳米光栅设置在下基板上，为了实现正常显示，量子点图案也必须放置在下基板上。
发明内容
根据本公开的实施例，提供一种阵列基板，包括：衬底基板；设置于所述衬底基板上的薄膜晶体管层；设置于所述薄膜晶体管层背离所述衬底基板一侧的第一钝化层；设置于所述第一钝化层背离所述衬底基板一侧、且位于 所述阵列基板的显示区域内的量子点层；设置于所述量子点层背离所述衬底基板一侧的彩色滤光层，所述量子点层在所述衬底基板上的正投影位于所述彩色滤光层在所述衬底基板上的正投影内；设置于所述第一钝化层背离所述衬底基板一侧和所述彩色滤光层背离所述衬底基板一侧的平坦层；设置于所述平坦层背离所述衬底基板一侧的金属线栅偏光层。
例如，所述薄膜晶体管层包括驱动晶体管部分和光感补偿晶体管部分，所述驱动晶体管部分和所述光感补偿晶体管部分的每个包括栅极、栅极绝缘层、有源层、源极和漏极；所述阵列基板还包括光电转换器件，所述光电转换器件构造为接收所述量子点层受激发产生的激发光当中被所述金属线栅偏光层反射的部分并将其转换成电信号；所述光电转换器件包括上电极和下电极以及夹置在上电极和下电极之间的光电转换层，所述下电极与所述光感补偿晶体管部分的源极或漏极电连接。
例如，所述阵列基板包括多条栅线以及多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个显示子像素；每个所述显示子像素包括所述驱动晶体管部分，所述驱动晶体管部分的栅极与对应的栅线电连接，所述驱动晶体管的源极或漏极与对应的数据线电连接；在每个所述显示子像素中，在位于所述金属线栅偏光层背离所述衬底基板一侧设置有像素电极，所述像素电极通过第二过孔以及填充于所述第二过孔内的第二引线与所述驱动晶体管部分的漏极或源极电连接。
例如，所述光感补偿晶体管部分和所述光电转换器件位于所述多个显示子像素当中的至少一个显示子像素中；所述阵列基板还包括与所述多条栅线平行设置的感测控制线以及与所述多条数据线平行设置的信号读取线；所述光感补偿晶体管部分的栅极与所述感测控制线电连接，所述光感补偿晶体管部分的漏极或源极与所述信号读取线电连接。
例如，所述阵列基板还包括与所述多条栅线平行设置的公共电极线；在每个所述显示子像素中，所述金属线栅偏光层通过第一过孔及填充于所述第一过孔内的第一引线与所述公共电极线电连接以使得所述金属线栅偏光层还用作公共电极；并且在所述至少一个显示子像素中，所述金属线栅偏光层通过第三过孔以及填充于所述第三过孔内的第三引线与所述光电转换器件的上电极电连接。
例如，所述至少一个显示子像素为蓝色子像素。
例如，所述彩色滤光层在所述衬底基板上的正投影覆盖所述驱动晶体管部分的有源层在所述衬底基板上的正投影以及所述光感补偿晶体管部分的有源层在所述衬底基板上的正投影。
例如，所述阵列基板还包括设置于所述彩色滤光层与所述薄膜晶体管层之间的黑矩阵层；所述黑矩阵层在所述衬底基板上的正投影覆盖所述驱动晶体管部分的有源层在所述衬底基板上的正投影以及所述光感补偿晶体管部分的有源层在所述衬底基板上的正投影。
例如，所述黑矩阵层还覆盖所述光电转换层的侧表面，所述侧表面的延长线与所述衬底基板相交。
例如，所述阵列基板还包括位于所述第一钝化层和薄膜晶体管层之间的第二钝化层；所述第二钝化层覆盖所述驱动晶体管部分和所述光感补偿晶体管部分；所述光电转换器件位于所述第一钝化层和所述第二钝化层之间，且所述光电转换器件的下电极通过贯穿所述第二钝化层的第四过孔与所述光感补偿晶体管部分的源极或漏极电连接。
例如，所述阵列基板包括多条栅线以及多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个显示子像素；所述多个显示子像素包括第一显示子像素、第二显示子像素和第三显示子像素；所述量子点层包括位于所述第一显示子像素中的第一量子点图案、位于所述第二显示子像素中的第二量子点图案以及位于所述第三显示子像素中的第三量子点图案，第一量子点图案、第二量子点图案和第三量子点图案在来自背光源的光的激发下发光，从而第一显示子像素、第二显示子像素和第三显示子像素分别发出三种不同颜色的光。
例如，所述来自背光源的光为紫外光；所述第一显示子像素为红色子像素，所述第一量子点图案在所述紫外光的激发下产生红光；所述第二显示子像素为绿色子像素，所述第二量子点图案在所述紫外光的激发下产生绿光；并且所述第三显示子像素为蓝色子像素，所述第三量子点图案在所述紫外光的激发下产生蓝光。
例如，所述阵列基板包括多条栅线以及多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个显示子像素；所述多个显示子像素包括第一 显示子像素、第二显示子像素和第三显示子像素；所述量子点层包括位于所述第一显示子像素中的第一量子点图案以及位于所述第二显示子像素中的第二量子点图案；所述阵列基板还包括位于所述第三显示子像素中的光扩散图案，所述光扩散图案与所述第一量子点图案和所述第二量子点图案同层设置；所述第一量子点图案和所述第二量子点图案在来自背光源的光的激发下发光，来自所述背光源的光透过所述光扩散图案并被所述光扩散图案均匀化，从而第一显示子像素、第二显示子像素和第三显示子像素分别发出三种不同颜色的光。
例如，所述第三显示子像素为蓝色子像素，并且来自所述背光源的光为蓝光；第一显示子像素为红色子像素，所述第一量子点图案在所述蓝光的激发下产生红光；所述第二显示子像素为绿色子像素，所述第二量子点图案在所述蓝光的激发下产生绿光。
例如，所述光扩散图案包括有机基体以及分散在有机基体中的无机颗粒。
例如，所述金属线栅偏光层包括设置于所述平坦层背离所述衬底基板一侧的刻蚀阻挡层、设置于所述刻蚀阻挡层背离所述衬底基板一侧的金属线栅层和设置于所述金属线栅层背离所述衬底基板一侧的保护层。
例如，所述金属线栅层包括平行设置的多个金属条，所述保护层覆盖所述多个金属条中相邻的两个金属条并覆盖位于该相邻的两个金属条之间的区域，但是所述保护层不与该相邻的两个金属条之间的区域中露出的所述刻蚀阻挡层接触。
例如，所述平坦层包括热固化层和光固化层，所述热固化层比所述光固化层靠近所述衬底基板，所述光固化层的远离所述衬底基板的表面是平坦的。
根据本公开的实施例，提供一种显示面板，包括如上所述的阵列基板、与所述阵列基板相对设置的对置基板以及设置于所述阵列基板与所述随之基板之间的液晶层。
根据本公开的实施例，提供一种显示装置，包括如上所述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述的附图仅仅涉及本公开的一些实施例， 而非对本公开的限制。
图1为本公开实施例提供的一种阵列基板的结构示意图；
图2为本公开实施例提供的阵列基板的另一结构示意图；
图3为本公开实施例提供的一种显示面板的结构示意图；以及
图4为本发明实施例提供的阵列基板的电路示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
请参考图1，本公开的实施例提供一种阵列基板，包括：
衬底基板1；
设置于衬底基板1上的薄膜晶体管层；
设置于薄膜晶体管层背离衬底基板1一侧的第一钝化层9；
设置于第一钝化层9背离衬底基板1一侧、且位于阵列基板的显示区域内的量子点层10；
设置于量子点层10背离衬底基板1一侧的彩色滤光层11，量子点层10在衬底基板1上的正投影位于彩色滤光层11在衬底基板1上的正投影内；
设置于第一钝化层9背离衬底基板1一侧和彩色滤光层11背离衬底基板1一侧的平坦层12；
设置于平坦层12背离衬底基板1一侧的金属线栅偏光层13。
上述阵列基板包括衬底基板和依次设置于阵列基板上的薄膜晶体管层、第一钝化层9、量子点层10、彩色滤光层11、平坦层12和金属线栅偏光层13；其中，量子点层10设置于显示区域内，量子点层10背离衬底基板1一侧设置有彩色滤光层11，且彩色滤光层11在衬底基板1上的正投影覆盖量子点层10在衬底基板1上的正投影，彩色滤光层11和第一钝化层9中背离衬底基板1的一侧设置有平坦层12，平坦层12背离衬底基板1的一侧设置有金属线栅偏光层13。薄膜晶体管层包括许多电学部件，第一钝化层9覆盖 在薄膜晶体管层上以对薄膜晶体管层提供保护并实现薄膜晶体管层中的电学部件与其他电学部件之间所需的电绝缘。量子点层10位于显示区域，在来自背光源的光的激发下产生激发光，该激发光经液晶层21(参见下文)调制之后实现显示功能；通过采用量子点层10，可以显著改善显示装置的显示效果并提高来自背光源的光的利用率。
然而，一方面，量子点层10可能不能将来自背光源的光全部进行转化，因此来自背光源的光的一部分可能会透过量子点层10而与激发光混合，导致激发光的单色性变差；另一方面，来自外部环境的光也可能从金属线栅偏光层13的远离衬底基板1的一侧入射至量子点层10上导致量子点层10不期望地被外部环境光激发发光。为了解决上述问题，根据本公开的实施例，在量子点层10背离衬底基板1一侧设置有彩色滤光层11，且彩色滤光层11在衬底基板1上的正投影覆盖量子点层10在衬底基板1上的正投影，以屏蔽来自外部环境的光以及背光源的光当中透过量子点层10的部分，保证了量子点层10发出的激发光的单色性，显著改善了包括阵列基板的显示面板的显示效果。
量子点层10所包括的量子点材料的荧光特性会完全破坏光的偏振状态，因此必须为了实现正常显示，必须为量子点层10搭配设置内置偏光片。因此，根据本公开的实施例，在量子点层10的远离衬底基板1的一侧设置了金属线栅偏光层13，以使得来自量子点层10的激发光具有偏振特性，保证包括阵列基板的液晶显示面板实现正常显示。在衬底基板1上形成量子点层10之后所得的结构具有较大的表面段差，使得具有纳米级精细结构的金属线栅偏光层13的制作无法正常进行。因此，在本公开实施例中，在衬底基板上形成量子点层10之后，在第一钝化层9背离衬底基板1的一侧和彩色滤光层11背离衬底基板1一侧设置了平坦层12，金属线栅偏光层13设置在该平坦层12，从而可以获得高质量的金属线栅偏光层13。
本公开实施例中，阵列基板包括量子点层10和金属线栅偏光层13二者，且彩色滤光层11在衬底基板1上的正投影覆盖量子点层10在衬底基板1上的正投影，可以显著改善采用该阵列基板的显示面板的显示效果。
需要说明的是，量子点层10位于阵列基板的显示区域内可以理解为：量子点层10包括多个量子点图案(例如，如下所述的第一量子点图案10a、第 二量子点图案10b以及第三量子点图案10c)，该多个量子点图案分别位于多个显示子像素(例如，如下所述的第一显示子像素、第二显示子像素以及第三显示子像素)的显示区域内。例如，分别位于多个显示子像素的显示区域的多个量子点图案彼此间隔开。
需要说明的是，彩色滤光层11设置在量子点层10背离衬底基板1一侧且量子点层10在衬底基板1上的正投影位于彩色滤光层11在衬底基板1上的正投影内可以理解为：在显示子像素内，彩色滤光层11设置在量子点图案背离衬底基板1一侧且量子点图案在衬底基板1上的正投影位于彩色滤光层11在衬底基板1上的正投影内。例如，彩色滤光层11包括分别位于多个显示子像素的多个部分，该多个部分彼此间隔开，该多个部分分别覆盖多个量子点图案。
需要说明的是，在显示子像素内，量子点层10(也就是，显示子像素内的量子点图案)受激发产生的激发光为单色光，且该激发光的颜色与能透射通过彩色滤光层11的光的颜色相同，从而彩色滤光层11只允许激发光通过而不允许颜色与激发光的颜色不同的光通过。
例如，平坦层12包括热固化层和光固化层，热固化层比光固化层靠近衬底基板1，光固化层的远离衬底基板1的表面是平坦的。热固化的过程较慢，允许待固化材料充分流动从而尽可能多地消除表面段差；光固化的过程较快，可以将在待固化材料达到平整状态时将待固化材料尽快定形，获得平坦表面。平坦层12采用热固化层和光固化层的双层结构，可以使得平坦层12的的远离衬底基板1的表面具有优良的平坦特性，确保了形成金属线栅偏光层13的良率，以更好地获得金属线栅偏光层13。
例如，如图1和图2所示，薄膜晶体管层包括驱动晶体管部分和光感补偿晶体管部分，驱动晶体管部分和光感补偿晶体管部分的每个包括形成于衬底基板1上的栅极2、栅极绝缘层3、有源层4、源极和漏极。由于源极和漏极为对称结构且可以互换，因此在图中源极和漏极均用附图标记5来指示。
例如，如图1和图2所示，阵列基板还包括设置于衬底基板1上的光电转换器件，光电转换器件构造为接收量子点层10受激发产生的激发光当中被金属线栅偏光层13反射的部分并将其转换成电信号；光电转换器件包括上电极8和下电极8’以及夹置在上电极8和下电极8’之间的光电转换层7，下 电极8’与光感补偿晶体管部分的源极或漏极电连接。
量子点层10受激发产生的激发光在透射通过彩色滤光层11之后入射到金属线栅偏光层13上，一部分透射通过金属线栅偏光层13而成为偏振光，一部分被金属线栅偏光层13反射成为反射光。偏振光的量增大，则反射光的量减小；偏振光的量减小，则反射光的量增大。反射光入射到光电转换器件上并被光电转化器件转换成电信号，该电信号通过光感补偿晶体管部分以及下面要描述的信号读取线被输出至检测电路。检测电路判断电信号的大小，可以判断出反射光的量的大小，从而可以判断出偏振光的量的大小。由此，可以实时发现偏振光的量发生异常的区域，并通过电学补偿方式对该异常区域进行补偿，确保显示画面的均匀性。
下面，将对驱动晶体管部分、光感补偿晶体管部分以及光转换器件的电连接关系进行进一步描述。图4为根据本公开实施例阵列基板的电路图。参见图4，阵列基板包括设置于衬底基板1上的多条栅线111以及多条数据线121，多条栅线111和多条数据线121彼此交叉限定多个显示子像素100；每个显示子像素100包括驱动晶体管部分(参见图4中的区域A)，驱动晶体管部分的栅极与对应的栅线111电连接，驱动晶体管的源极或漏极与对应的数据线121电连接；在每个显示子像素中，在位于金属线栅偏光层13的背离衬底基板一侧设置有像素电极20，像素电极20通过第二过孔17以及填充于第二过孔17内的第二引线192与驱动晶体管部分的漏极或源极电连接。
继续参见图4，光感补偿晶体管部分(参见图4中的区域B)和光电转换器件(参见图4中的区域C)位于多个显示子像素100当中的至少一个显示子像素中；阵列基板还包括与多条栅线111平行设置的感测控制线112以及与多条数据线121平行设置的信号读取线122；光感补偿晶体管部分的栅极与感测控制线112电连接，光感补偿晶体管部分的漏极或源极与信号读取线122电连接。在感测触控线112上施加控制信号以控制光感补偿晶体管部分的开启和关断。例如，光感补偿晶体管部分开启，光电转换器件产生的电信号经光感补偿晶体管部分输出至信号读取线122，然后经信号读取线122输出至外部检测电路，由外部检测电路对电信号的大小进行判断。根据检测电路反馈的信号来确定是否存在显示亮度不均匀的区域，从而确定是否进行电学补偿。
例如，参见图1、图2和图4，阵列基板还包括与多条栅线111平行设置的公共电极线15；在每个显示子像素100中，金属线栅偏光层13通过第一过孔16及填充于第一过孔16内的第一引线191与公共电极线15电连接以使得金属线栅偏光层13还用作公共电极。例如，金属线栅偏光层13包括多个金属条，金属条的宽度为纳米量级且相邻金属条之间的区域的宽度也为纳米量级，在此情形下，金属线栅偏光层13整体上可以看做为板状电极。例如，参见图4，液晶电容Clc的一个电极板为像素电极20，另一个电极板为公共电极，例如用作公共电极的金属线栅偏光层13。像素电极20与公共电极之间形成电场，以对液晶层21(参见图3)中的液晶分子的偏转状态进行控制，从而控制透射通过金属线栅偏光层13的偏振光透过液晶层21的透过率，以实现图像显示。
进一步地，例如，在具有光感补偿晶体管部分和光电转换器件的所述至少一个显示子像素中，金属线栅偏光层13通过第三过孔18以及填充于第三过孔18内的第三引线193与光电转换器件的上电极8电连接，由此为光电转换器件提供偏置电压。
例如，为了制作方便，栅线111、感测控制线112、公共电极线15、驱动晶体管部分的栅极以及光感补偿晶体管部分的栅极同层且同材料设置。
例如，为了制作方便，驱动晶体管部分的源极和漏极、光感补偿晶体管部分的源极和漏极、数据线121以及信号读取线122同层且同材料设置。
例如，为了增加开口率，光感补偿晶体管部分和光电转换器件不必设置在每个显示子像素100中，而是选择性地设置在一个或者一部分显示子像素100中；光感补偿晶体管部分和光电转换器件的设置位置以及设置数量可以根据实际需要灵活选择。
由于人眼对蓝光的敏感度较低，设置有光感补偿晶体管部分和光电转换器件的至少一个显示子像素例如为蓝色子像素，以尽可能地降低光感补偿晶体管部分和光电转换器件的存在对显示亮度的影响。
例如，如图1和图2所示，金属线栅偏光层13包括设置于平坦层12背离衬底基板1一侧的刻蚀阻挡层131、设置于刻蚀阻挡层131背离衬底基板1一侧的金属线栅层132和设置于金属线栅层132背离衬底基板1一侧的保护层133。例如，金属线栅层132的形成过程如下：在刻蚀阻挡层131上形成 一层金属膜；在金属膜上形成光刻胶层；采用纳米压印模板对光刻胶层进行压印以形成光刻胶图案；以光刻胶图案作为掩模图形对金属膜进行刻蚀以形成金属线栅层132。通过设置刻蚀阻挡层131可以防止在上述刻蚀工艺中出现过刻现象，保护在下的平坦层12。
例如，在金属线栅层132上设置保护层133，以对金属线栅层132进行保护，防止金属线栅层132在后续制程中被破坏。参见图1和图2，保护层133位于金属线栅层132与像素电极20之间，因此保护层133还兼具实现金属线栅层132与像素电极20之间的电绝缘的功能。
例如，如图1和图2所示，金属线栅层132包括平行设置的多个金属条。进一步地，例如，如图2所示，保护层133覆盖多个金属条中相邻的两个金属条并覆盖位于该相邻的两个金属条之间的区域，但是保护层133不与该相邻的两个金属条之间的区域中露出的刻蚀阻挡层131接触；在此情形下，相邻的两个金属条之间的区域不被任何介质填充，可以改善金属线栅层132的偏振特性，使得更多的光能透过金属线栅层132而成为偏振光。例如，保护层133的材料可以选用氧化物、氮化物或氮氧化物，诸如氧化硅。例如，可以选择合适的形成工艺，例如化学气相沉积法，以使得保护层133具有图2所示的结构。
例如，如图1和图2所示，彩色滤光层11在衬底基板1上的正投影覆盖薄膜晶体管层中的沟道部分在衬底基板1上的正投影。具体而言，例如，彩色滤光层11在衬底基板1上的正投影覆盖驱动晶体管部分的有源层(例如，有源层中的沟道区)在衬底基板1上的正投影以及光感补偿晶体管部分的有源层(例如，有源层中的沟道区)在衬底基板1上的正投影，避免后续制程中的强光，例如制作平坦层12的过程中的强光，影响驱动晶体管部分和光感补偿晶体管部分的特性，并防止驱动晶体管部分和光感补偿晶体管部分产生不期望的泄露电流。
例如，如图2所示，阵列基板还包括设置于彩色滤光层11与薄膜晶体管层之间的黑矩阵层14。例如，黑矩阵层14在衬底基板1上的正投影覆盖驱动晶体管部分的有源层(例如，有源层中的沟道区)在衬底基板1上的正投影以及光感补偿晶体管部分的有源层(例如，有源层中的沟道区)在衬底基板1上的正投影，避免后续制程中的强光，例如制作平坦层12的过程中的强 光，影响驱动晶体管部分和光感补偿晶体管部分的特性，并防止驱动晶体管部分和光感补偿晶体管部分产生不期望的泄露电流。
需要说明的是，根据实际需要，可以选择彩色滤光层11和黑矩阵层14两者或者它们中的任一者覆盖驱动晶体管部分的有源层(例如，有源层中的沟道区)以及光感补偿晶体管部分的有源层(例如，有源层中的沟道区)。
需要说明的是，由于相邻的显示子像素100之间设置有走线，如上所述的栅线111、数据线121、感测控制线11、信号读取线122以及公共电极线15，因此黑矩阵层14还覆盖这些走线；驱动晶体管部分所在的区域、光感补偿晶体管部分所在的区域以及被黑矩阵覆盖的其他区域为显示子像素的非显示区域，而显示子像素的除非显示区域之外的区域为显示区域，如上所述的量子点层10所包括的量子点图案即位于显示子像素的显示区域中。
采用本公开实施例的结构，将量子点层10和光感补偿晶体管部分以及光电转换器件置于阵列基板上，量子点层10发光稳定，不受灰阶影响，利于光电转换器件收集稳定的信号，实现对显示亮度不均匀的区域实现精确的实时监控和补偿。
例如，黑矩阵层14还覆盖光电转换层7的侧表面，该侧表面的延长线与衬底基板1相交。如上所述，通过光感补偿晶体管部分以及光电转换器件，可以实时发现偏振光的量不均匀的区域并根据反馈信号进行灰阶补偿；通过黑矩阵层14遮蔽光电转换层7的侧壁，可以屏蔽其他区域的光入射至光电转换层7，保证光电转换层7仅接受到其所在区域及附近的反射光，实现金属线栅偏光层13均匀性补偿及量子点层10效率衰减的补偿，避免烧屏问题。
例如，如图1和图2所示，金属线栅偏光层13通过贯穿金属线栅偏光层13、平坦层12、第一钝化层9和栅极绝缘层3的第一过孔16及填充于第一过孔16内的第一引线191与公共电极线15电连接。
金属线栅偏光层13在非显示区通过第一过孔16及设置于第一过孔16中的第一引线191电连接公共电极线15，通过这种方式电连接几乎不影响像素开口率；第一过孔16的开口处露出金属线栅层132，确保第一引线191和金属线栅层132电连接。
例如，如图1和图2所示，像素电极20通过贯穿金属线栅偏光层13、平坦层12和第一钝化层9的第二过孔17以及填充于第二过孔17内的第二引 线192与驱动晶体管部分的漏极或源极电连接。第二过孔17的开口处不露出金属线栅层132，以防止金属线栅层132在用作公共电极的情形下与像素电极20短路。
例如，第一引线191和第二引线192同层且同材料设置，以简化制作工艺。
例如，像素电极20的材质可以选用透明导电金属氧化物，例如ITO、IGZO等等。采用透明导电金属氧化物制作像素电极20时不进行200℃以上高温退火，仅进行100～200℃条件下退火，可以防止量子点层10受到高温工艺的影响。像素电极20通过过孔和引线与源极或漏极5电连接，连接方式简单。
例如，如图1和图2所示，金属线栅偏光层13通过贯穿金属线栅偏光层13、平坦层12的第三过孔18以及填充于第三过孔18内的第三引线193与上电极8电连接。金属线栅偏光层13通过过孔连接上电极8，以尽可能地降低对开口率的影响。例如，如图1和图2所示，在第三过孔18的开口处露出金属线栅层132，确保第三引线193和上电极8电连接。例如，保护层133还覆盖第三引线193，但是保护层133不覆盖第一引线191也不覆盖第二引线192。
例如，第一引线191、第二引线192以及第三引线193的材料为金属或者透明导电金属氧化物。
例如，如图1和图2所示，阵列基板还包括位于第一钝化层9和薄膜晶体管层之间的第二钝化层6；第二钝化层6覆盖驱动晶体管部分和光感补偿晶体管部分；光电转换器件位于第一钝化层9和第二钝化层6之间，且光电转换器件的下电极8’通过贯穿第二钝化层6的第四过孔60与光感补偿晶体管部分的源极或漏极电连接。
继续参见图4，根据本公开实施例的阵列基板包括多条栅线111以及多条数据线121，多条栅线111和多条数据线121彼此交叉限定多个显示子像素100。例如，多个显示子像素100包括第一显示子像素101、第二显示子像素102和第三显示子像素103；量子点层10包括位于第一显示子像素101中的第一量子点图案10a、位于第二显示子像素102中的第二量子点图案10b以及位于第三显示子像素103中的第三量子点图案10c，第一量子点图案10a、第二量子点图案10b和第三量子点图案10c在来自背光源的光的激发下发光， 从而第一显示子像素、第二显示子像素和第三显示子像素分别发出三种不同颜色的光。例如，三种不同颜色的光可以组合为白光。例如，第一量子点图案10a、第二量子点图案10b和第三量子点图案10c分别由不同的材料形成。
例如，来自背光源的光为紫外光；第一显示子像素101为红色子像素，第一量子点图案10a在紫外光的激发下产生红光；第二显示子像素102为绿色子像素，第二量子点图案10b在紫外光的激发下产生绿光；并且第三显示子像素103为蓝色子像素，第三量子点图案10c在所述紫外光的激发下产生蓝光。例如，在垂直于衬底基板的方向上，第一量子点图案10a的高度、第二量子点图案10b的高度、以及第三量子点图案10c的高度彼此相等，以降低平坦层12的制作难度。
例如，量子点层10包括位于第一显示子像素101中的第一量子点图案10a以及位于第二显示子像素102中的第二量子点图案10b；阵列基板还包括位于第三显示子像素103中的光扩散图案10d，光扩散图案10d与第一量子点图案10a和第二量子点图案10b同层设置；第一量子点图案10a和第二量子点图案10b在来自背光源的光的激发下发光，来自背光源的光透过光扩散图案10d并被光扩散图案10d均匀化，从而第一显示子像素101、第二显示子像素102和第三显示子像素103分别发出三种不同颜色的光。例如，三种不同颜色的光可以组合为白光。例如，第一量子点图案10a和第二量子点图案10b分别由不同的材料形成。例如，光扩散图案10d包括有机基体以及分散在有机基体中的无机颗粒；有机基体的材料例如为化学性质稳定的树脂材料，无机颗粒的材料例如为二氧化钛、二氧化硅、二氧化锆、氧化铝等等。
例如，第三显示子像素103为蓝色子像素，并且来自背光源的光为蓝光；第一显示子像素101为红色子像素，第一量子点图案10a在蓝光的激发下产生红光；第二显示子像素102为绿色子像素，第二量子点图案10b在蓝光的激发下产生绿光。例如，在垂直于衬底基板的方向上，光扩散图案10d的高度、第一量子点图案10a的高度、以及第二量子点图案10b的高度彼此相等，以降低平坦层12的制作难度。
本公开实施例还提供一种显示面板，如图3所示，包括上述技术方案中提供的阵列基板、与阵列基板相对设置的对置基板22和设置于阵列基板与对置基板22之间的液晶层21。例如，背光源位于阵列基板1的远离对置基板 22的一侧。例如，背光源可以为直下式背光源或者侧入式背光源。例如，背光源采用发射蓝光或紫外光的光源，例如OLED灯珠或灯条。
本公开实施例还提供一种显示装置，包括上述技术方案中提供的显示面板。例如，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不做限定。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    设置于所述衬底基板上的薄膜晶体管层；
    设置于所述薄膜晶体管层背离所述衬底基板一侧的第一钝化层；
    设置于所述第一钝化层背离所述衬底基板一侧、且位于所述阵列基板的显示区域内的量子点层；
    设置于所述量子点层背离所述衬底基板一侧的彩色滤光层，所述量子点层在所述衬底基板上的正投影位于所述彩色滤光层在所述衬底基板上的正投影内；
    设置于所述第一钝化层背离所述衬底基板一侧和所述彩色滤光层背离所述衬底基板一侧的平坦层；
    设置于所述平坦层背离所述衬底基板一侧的金属线栅偏光层。
  2. 根据权利要求1所述的阵列基板，其中，
    所述薄膜晶体管层包括驱动晶体管部分和光感补偿晶体管部分，所述驱动晶体管部分和所述光感补偿晶体管部分的每个包括栅极、栅极绝缘层、有源层、源极和漏极；
    所述阵列基板还包括光电转换器件，所述光电转换器件构造为接收所述量子点层受激发产生的激发光当中被所述金属线栅偏光层反射的部分并将其转换成电信号；
    所述光电转换器件包括上电极和下电极以及夹置在上电极和下电极之间的光电转换层，所述下电极与所述光感补偿晶体管部分的源极或漏极电连接。
  3. 根据权利要求2所述的阵列基板，包括多条栅线以及多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个显示子像素，其中，
    每个所述显示子像素包括所述驱动晶体管部分，所述驱动晶体管部分的栅极与对应的栅线电连接，所述驱动晶体管的源极或漏极与对应的数据线电连接；
    在每个所述显示子像素中，在位于所述金属线栅偏光层背离所述衬底基板一侧设置有像素电极，所述像素电极通过第二过孔以及填充于所述第二过 孔内的第二引线与所述驱动晶体管部分的漏极或源极电连接。
  4. 根据权利要求3所述的阵列基板，其中，
    所述光感补偿晶体管部分和所述光电转换器件位于所述多个显示子像素当中的至少一个显示子像素中；
    所述阵列基板还包括与所述多条栅线平行设置的感测控制线以及与所述多条数据线平行设置的信号读取线；
    所述光感补偿晶体管部分的栅极与所述感测控制线电连接，所述光感补偿晶体管部分的漏极或源极与所述信号读取线电连接。
  5. 根据权利要求4所述的阵列基板，还包括与所述多条栅线平行设置的公共电极线，其中，
    在每个所述显示子像素中，所述金属线栅偏光层通过第一过孔及填充于所述第一过孔内的第一引线与所述公共电极线电连接以使得所述金属线栅偏光层还用作公共电极；并且
    在所述至少一个显示子像素中，所述金属线栅偏光层通过第三过孔以及填充于所述第三过孔内的第三引线与所述光电转换器件的上电极电连接。
  6. 根据权利要求5所述的阵列基板，其中，所述至少一个显示子像素为蓝色子像素。
  7. 根据权利要求2-6任一项所述的阵列基板，其中，
    所述彩色滤光层在所述衬底基板上的正投影覆盖所述驱动晶体管部分的有源层在所述衬底基板上的正投影以及所述光感补偿晶体管部分的有源层在所述衬底基板上的正投影。
  8. 根据权利要求2-7任一项所述的阵列基板，还包括设置于所述彩色滤光层与所述薄膜晶体管层之间的黑矩阵层，其中，
    所述黑矩阵层在所述衬底基板上的正投影覆盖所述驱动晶体管部分的有源层在所述衬底基板上的正投影以及所述光感补偿晶体管部分的有源层在所述衬底基板上的正投影。
  9. 根据权利要求8所述的阵列基板，其中，所述黑矩阵层还覆盖所述光电转换层的侧表面，所述侧表面的延长线与所述衬底基板相交。
  10. 根据权利要求2-9任一项所述的阵列基板，还包括位于所述第一钝化层和薄膜晶体管层之间的第二钝化层，其中，
    所述第二钝化层覆盖所述驱动晶体管部分和所述光感补偿晶体管部分；
    所述光电转换器件位于所述第一钝化层和所述第二钝化层之间，且所述光电转换器件的下电极通过贯穿所述第二钝化层的第四过孔与所述光感补偿晶体管部分的源极或漏极电连接。
  11. 根据权利要求1所述的阵列基板，包括多条栅线以及多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个显示子像素，其中，
    所述多个显示子像素包括第一显示子像素、第二显示子像素和第三显示子像素；
    所述量子点层包括位于所述第一显示子像素中的第一量子点图案、位于所述第二显示子像素中的第二量子点图案以及位于所述第三显示子像素中的第三量子点图案，第一量子点图案、第二量子点图案和第三量子点图案在来自背光源的光的激发下发光，从而第一显示子像素、第二显示子像素和第三显示子像素分别发出三种不同颜色的光。
  12. 根据权利要求11所述的阵列基板，其中，
    所述来自背光源的光为紫外光；
    所述第一显示子像素为红色子像素，所述第一量子点图案在所述紫外光的激发下产生红光；
    所述第二显示子像素为绿色子像素，所述第二量子点图案在所述紫外光的激发下产生绿光；并且
    所述第三显示子像素为蓝色子像素，所述第三量子点图案在所述紫外光的激发下产生蓝光。
  13. 根据权利要求1所述的阵列基板，包括多条栅线以及多条数据线，所述多条栅线和所述多条数据线彼此交叉限定多个显示子像素，其中，
    所述多个显示子像素包括第一显示子像素、第二显示子像素和第三显示子像素；
    所述量子点层包括位于所述第一显示子像素中的第一量子点图案以及位于所述第二显示子像素中的第二量子点图案；
    所述阵列基板还包括位于所述第三显示子像素中的光扩散图案，所述光扩散图案与所述第一量子点图案和所述第二量子点图案同层设置；
    所述第一量子点图案和所述第二量子点图案在来自背光源的光的激发下 发光，来自所述背光源的光透过所述光扩散图案并被所述光扩散图案均匀化，从而第一显示子像素、第二显示子像素和第三显示子像素分别发出三种不同颜色的光。
  14. 根据权利要求13所述的阵列基板，其中，
    所述第三显示子像素为蓝色子像素，并且来自所述背光源的光为蓝光；
    第一显示子像素为红色子像素，所述第一量子点图案在所述蓝光的激发下产生红光；
    所述第二显示子像素为绿色子像素，所述第二量子点图案在所述蓝光的激发下产生绿光。
  15. 根据权利要求13所述的阵列基板，其中所述光扩散图案包括有机基体以及分散在有机基体中的无机颗粒。
  16. 根据权利要求1-15任一项所述的阵列基板，其中，
    所述金属线栅偏光层包括设置于所述平坦层背离所述衬底基板一侧的刻蚀阻挡层、设置于所述刻蚀阻挡层背离所述衬底基板一侧的金属线栅层和设置于所述金属线栅层背离所述衬底基板一侧的保护层。
  17. 根据权利要求16所述的阵列基板，其中，
    所述金属线栅层包括平行设置的多个金属条，所述保护层覆盖所述多个金属条中相邻的两个金属条并覆盖位于该相邻的两个金属条之间的区域，但是所述保护层不与该相邻的两个金属条之间的区域中露出的所述刻蚀阻挡层接触。
  18. 根据权利要求1-17任一项所述的阵列基板，其中，
    所述平坦层包括热固化层和光固化层，所述热固化层比所述光固化层靠近所述衬底基板，所述光固化层的远离所述衬底基板的表面是平坦的。
  19. 一种显示面板，包括如权利要求1-18任一项所述的阵列基板、与所述阵列基板相对设置的对置基板以及设置于所述阵列基板与所述随之基板之间的液晶层。
  20. 一种显示装置，其中，包括如权利要求19所述的显示面板。
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