WO2020238557A1 - 薄膜晶体管及其制备方法、电子装置基板及电子装置 - Google Patents

薄膜晶体管及其制备方法、电子装置基板及电子装置 Download PDF

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WO2020238557A1
WO2020238557A1 PCT/CN2020/088117 CN2020088117W WO2020238557A1 WO 2020238557 A1 WO2020238557 A1 WO 2020238557A1 CN 2020088117 W CN2020088117 W CN 2020088117W WO 2020238557 A1 WO2020238557 A1 WO 2020238557A1
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layer
thin film
film transistor
active layer
metal layer
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PCT/CN2020/088117
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English (en)
French (fr)
Inventor
汪军
王东方
王海涛
李广耀
王庆贺
胡迎宾
张扬
宋威
张涛
钱国平
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2020238557A1 publication Critical patent/WO2020238557A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the embodiments of the present disclosure relate to a thin film transistor and a manufacturing method thereof, an electronic device substrate, and an electronic device.
  • Thin film transistors include structures such as gate, source, drain, gate insulating layer, and semiconductor layer.
  • the gate is separated from the semiconductor layer by a gate insulating layer, and the source and drain are in direct contact with the semiconductor layer.
  • the voltage applied to the gate reaches a predetermined value, the channel region of the semiconductor layer between the source and drain becomes conductive or non-conductive.
  • the A current can be generated between the drains, so that the thin film transistor can function as a switching element.
  • At least one embodiment of the present disclosure provides a method for manufacturing a thin film transistor.
  • the manufacturing method includes: providing a base substrate; and forming a metal layer on the base substrate, wherein the metal layer includes a first portion and a second portion that are insulated from each other. Two parts; forming an active layer on the metal layer, wherein the active layer includes a source region and a drain region, the first part of the metal layer contacts the source region, the metal layer The second part contacts the drain region; and the active layer is conductive through the metal layer, so that the source region and the drain region are conductive.
  • forming the active layer on the metal layer includes: forming a first insulating layer on the metal layer so that the first insulating layer An insulating layer covers the metal layer and exposes the first part and the second part; and forming the active layer on the first insulating layer so that the first part of the metal layer contacts the The source region of the source layer, and the second portion of the metal layer contacts the drain region of the active layer.
  • the conductive treatment of the active layer through the metal layer includes annealing the metal layer and the active layer to The source region and the drain region are made conductive.
  • the temperature of the annealing treatment is 100° C.-400° C.
  • the time of the annealing treatment is 10 min-500 min.
  • the material of the metal layer includes any one selected from the group consisting of aluminum, copper, titanium, molybdenum or alloys.
  • the method for manufacturing a thin film transistor provided by at least one embodiment of the present disclosure further includes: forming a source electrode and a drain electrode, wherein the source electrode is electrically connected to the source region of the active layer, and the drain electrode is electrically connected to the source region of the active layer.
  • the drain region of the active layer is electrically connected.
  • the metal layer further includes a third part, and the third part is insulated from the first part and the second part.
  • the orthographic projection of the three parts on the base substrate is located within the orthographic projection of the active layer on the base substrate.
  • the third part is configured as a gate of the thin film transistor.
  • the manufacturing method further includes: A gate insulating layer is formed on the active layer; a gate is formed on the gate insulating layer; and a second insulating layer is formed on the gate.
  • the manufacturing method before the conductive treatment of the active layer by the metal layer, with respect to the base substrate, the manufacturing method further includes: A gate insulating layer is formed on the active layer; a gate is formed on the gate insulating layer; and a second insulating layer is formed on the gate.
  • the manufacturing method before the conductive treatment of the active layer by the metal layer, with respect to the base substrate, the manufacturing method further includes: A gate insulating layer is formed on the active layer; after the active layer is conductive by the metal layer, with respect to the base substrate, the preparation method further includes: on the gate A gate is formed on the insulating layer, and a second insulating layer is formed on the gate.
  • At least one embodiment of the present disclosure further provides a thin film transistor, comprising: a metal layer, an active layer, a source electrode and a drain electrode, wherein the metal layer is an opaque metal layer, and the active layer is located on the metal layer
  • the metal layer includes a first part and a second part insulated from each other, the first part contacts the source region of the active layer, the second part contacts the drain region of the active layer, and the source
  • the electrode region and the drain region are conductive with respect to the channel region of the active layer, the source electrode is electrically connected to the source region of the active layer, and the drain electrode is electrically connected to the active layer.
  • the drain region of the source layer is electrically connected.
  • the material of the metal layer includes any one selected from the group consisting of aluminum, copper, titanium, molybdenum or alloys.
  • the thin film transistor provided by at least one embodiment of the present disclosure further includes a first insulating layer, wherein the first insulating layer is disposed between the metal layer and the active layer, and the first insulating layer covers the The other part of the metal layer except the first part and the second part, and the first part and the second part are exposed, so that the first part contacts the source region of the active layer, so The second part contacts the drain region of the active layer.
  • the metal layer further includes a third part, the third part is insulated from the first part and the second part, and the third part is located at The active layer is in an orthographic projection on the metal layer.
  • the third part is configured as a gate of the thin film transistor.
  • the thin film transistor provided by at least one embodiment of the present disclosure further includes a gate insulating layer, a gate, and a second insulating layer, wherein the gate insulating layer is located on a side of the active layer away from the metal layer, The gate is located on a side of the gate insulating layer away from the active layer, and the second insulating layer is located on a side of the gate away from the gate insulating layer.
  • At least one embodiment of the present disclosure further provides an electronic device substrate, including the thin film transistor according to any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides an electronic device, including the electronic device substrate according to any embodiment of the present disclosure.
  • FIG. 1 is a flowchart of a method for manufacturing a thin film transistor according to some embodiments of the disclosure
  • FIG. 2 is a schematic diagram of a partial cross-sectional structure of a thin film transistor provided by some embodiments of the present disclosure
  • FIG. 3 is an exemplary flowchart of a method for manufacturing the thin film transistor shown in FIG. 2 provided by some embodiments of the disclosure;
  • 4A-4F are schematic diagrams corresponding to specific steps of the manufacturing method of the thin film transistor shown in FIG. 3;
  • FIG. 5 is a broken line diagram of the sheet resistance of the conductive area of the active layer at different temperatures obtained by two conductive methods
  • FIG. 6 is a schematic diagram of a partial cross-sectional structure of another thin film transistor provided by some embodiments of the present disclosure.
  • FIG. 7 is an exemplary flowchart of a method for manufacturing the thin film transistor shown in FIG. 6 provided by some embodiments of the present disclosure
  • FIG. 8 is a schematic partial plan view of an electronic device substrate provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of a partial circuit structure of an electronic device provided by some embodiments of the disclosure.
  • plasma such as plasma of helium or argon
  • the active layer of the thin film transistor where the source and drain overlap ie, the source of the active layer.
  • Region and drain region conduct conductorization.
  • the conductorized area of the active layer still has a large impedance, and is easily affected by the fluctuation of the conductorization process, and cannot achieve a good conduction effect, which leads to the source and drain electrodes. There is a risk of poor contact with the active layer. Therefore, the manufacturing process of thin film transistors has instability.
  • At least one embodiment of the present disclosure provides a method for manufacturing a thin film transistor.
  • the manufacturing method uses a metal layer to conduct a conductive treatment on the region where the active layer of the thin film transistor needs to be conductive, thereby reducing the active layer and the source and drain.
  • the sheet resistance at the junction enables the conductive area of the active layer to achieve a good conduction effect, thereby reducing or avoiding possible poor contact between the source, drain and the active layer Risks improve the stability of the manufacturing process of thin film transistors.
  • FIG. 1 is a flowchart of a method for manufacturing a thin film transistor according to some embodiments of the disclosure. As shown in Figure 1, the preparation method includes the following steps.
  • Step S10 Provide a base substrate.
  • Step S20 forming a metal layer on the base substrate.
  • the metal layer includes a first part and a second part insulated from each other.
  • Step S30 forming an active layer on the metal layer.
  • the active layer includes a source region and a drain region, a first part of the metal layer contacts the source region, and a second part of the metal layer contacts the drain region.
  • Step S40 Conducting the active layer through the metal layer, so that the source region and the drain region are conductive.
  • FIG. 2 is a schematic diagram of a partial cross-sectional structure of a thin film transistor provided by some embodiments of the present disclosure.
  • FIG. 3 is an exemplary flow chart of a method for manufacturing the thin film transistor shown in FIG. 2 provided by some embodiments of the present disclosure.
  • FIG. 4A- 4F is a schematic diagram corresponding to specific steps of the manufacturing method of the thin film transistor shown in FIG. 3.
  • FIGS. 2, 3, and 4A-4F some embodiments of the present disclosure will be described with reference to FIGS. 2, 3, and 4A-4F.
  • the thin film transistor 100 includes a metal layer 120, a first insulating layer 130, an active layer 140, a gate insulating layer 151, a gate 152, and a second insulating layer sequentially disposed on a base substrate 110. 153, source 161 and drain 162.
  • the first insulating layer 130 is located on the side of the metal layer 120 away from the base substrate 110
  • the active layer 140 is located on the side of the first insulating layer 130 away from the metal layer 120
  • the gate insulating layer 151 and the gate 152 are located on the active side.
  • the layer 140 is on a side away from the first insulating layer 130
  • the second insulating layer 153 is located on a side of the gate insulating layer 151 and the gate 152 away from the active layer 140.
  • the source electrode 161 is in contact with the source region 141 of the active layer 140
  • the drain electrode 162 is in contact with the drain region 142 of the active layer 140.
  • the metal layer 120 includes a first portion 121 and a second portion 122 that are insulated from each other.
  • the first portion 121 contacts the source region 141 from the lower side of the active layer 140 (ie, the side close to the base substrate 110).
  • the second portion 122 contacts the drain region 142 from the lower side of the active layer 140.
  • the specific structure of the thin film transistor 100 shown in FIG. 2 is taken as an example to describe the method of manufacturing the thin film transistor 100.
  • the method for manufacturing the thin film transistor 100 includes steps S101 to S109 as described below.
  • Step S101 Provide a base substrate 110.
  • Step S102 forming a metal layer 120 on the base substrate 110.
  • the base substrate 110 may be a glass substrate, a plastic substrate, etc.
  • the material of the base substrate 110 may be polyimide (PI), polyethylene (PE), polypropylene (PP), triacetate cellulose (TAC). ) Etc.
  • PI polyimide
  • PE polyethylene
  • PP polypropylene
  • TAC triacetate cellulose
  • Etc Etc
  • the metal layer 120 includes a first portion 121 and a second portion 122 insulated from each other.
  • the first portion 121 corresponds to the source region 141 of the active layer 140 (as shown in FIG. 2)
  • the second portion 122 corresponds to the drain region 142 of the active layer 140 ( As shown in FIG. 2)
  • the active layer 140 includes a channel region between the source region 141 and the drain region 142.
  • the material of the metal layer 120 may be metals or alloys such as aluminum, copper, titanium, and molybdenum, which are not limited in the embodiments of the present disclosure.
  • the metal layer 120 may be formed by methods such as physical vapor deposition, chemical vapor deposition, or the like.
  • the metal layer 120 may be processed through a patterning process to form the first part 121 and the second part 122, and the specific method of forming the first part 121 and the second part 122 is not limited in the embodiment of the present disclosure.
  • the metal layer 120 may be an opaque metal layer. As described below, in other examples, the metal layer 120 may further include a portion for forming a light shielding layer of the thin film transistor 100.
  • the active layer of the thin film transistor will increase photo-generated carriers after being irradiated with light from the side of the base substrate, which is likely to cause the thin film transistor to generate threshold voltage drift and increase leakage current. Therefore, it is necessary to provide a light shielding layer on the side of the active layer of the thin film transistor close to the base substrate to reduce or avoid the above-mentioned adverse phenomena.
  • the part of the metal layer 120 as a light shielding layer can block, for example, ambient light (such as blue light) incident from the base substrate 110 away from the metal layer 120, Reduce or prevent light from irradiating other structures or functional components (such as the active layer) of the thin film transistor 100 disposed on the metal layer 120, thereby reducing the possible interference of external light on the thin film transistor 100 and improving the stability of the thin film transistor 100 The performance of the thin film transistor 100 is improved.
  • the metal layer 120 plays a light-shielding effect
  • the thin-film transistor 100 since the thin-film transistor 100 does not need to separately prepare a separate light-shielding layer and corresponding insulating layer, the overall structure of the thin-film transistor 100 is simplified, and the manufacturing cost of the thin-film transistor 100 is reduced.
  • the manufacturing process of the thin film transistor 100 is optimized, and the process uncertainty that may exist in the manufacturing process is reduced. Therefore, the stability of the manufacturing process of the thin film transistor 100 is further improved, and the characteristics of the thin film transistor 100 are more stable.
  • the metal layer 120 further includes a third portion 123.
  • the third portion 123 is located between the first portion 121 and the second portion 122 and is connected to the first portion 121 and the second portion. 122 are insulated from each other.
  • the orthographic projection of the third portion 123 on the base substrate 110 is within the orthographic projection of the active layer 140 on the base substrate 110.
  • the third portion 123 corresponds to the channel region of the active layer 140, for example, the width of the third portion 123 in the direction from the source 161 to the drain 162 is smaller than the width of the active layer 140 .
  • the metal layer 120 further includes a fourth portion 124 and a fifth portion 125, and the fourth portion 124 and the fifth portion 125 are insulated from the first portion 121, the second portion 122 and the third portion 123.
  • the fourth portion 124 and the fifth portion 125 of the opaque metal layer 120 may cover most of the surface of the base substrate 110 to reduce or Preventing ambient light from the base substrate 110 away from the metal layer 120 from interfering with the structure or functional components of the thin film transistor 100 arranged on the metal layer 120, thereby enhancing the stability of the thin film transistor 100 and improving the thin film transistor 100 working performance.
  • Step S103 forming a first insulating layer 130 on the metal layer 120 so that the first insulating layer 130 covers the metal layer 120 and exposes the first portion 121 and the second portion 122.
  • the first insulating layer 130 is disposed between the metal layer 120 and the active layer 140, and the first insulating layer 130 covers the metal layer 120 except for the first portion 121 and the second portion 122. section.
  • the first insulating layer 130 is patterned through a patterning process, so that the first insulating layer 130 exposes the first part 121 and the second part 122 of the metal layer 120, so that the first part 121 and the second part 122 can be compared with those in subsequent processes.
  • the source region 141 and the drain region 142 of the formed active layer 140 are in contact with each other, and the metal layer 120 can be used to conduct a conductive treatment on the source region 141 and the drain region 142 in a subsequent process.
  • the first insulating layer 130 is generally formed of an organic insulating material (for example, acrylic resin) or an inorganic insulating material (for example, silicon nitride SiNx or silicon oxide SiOx).
  • the first insulating layer 130 may have a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer structure composed of silicon nitride and silicon oxide.
  • the first insulating layer 130 may be formed by a suitable method such as a physical vapor deposition method, a chemical vapor deposition method, or coating, which is not limited in the embodiments of the present disclosure.
  • Step S104 forming an active layer 140 on the first insulating layer 130.
  • the first insulating layer 130 covers the metal layer 120 and exposes the first portion 121 and the second portion 122, the first portion 121 of the metal layer 120 contacts The source region 141 of the active layer 140 and the second portion 122 of the metal layer 120 contact the drain region 142 of the active layer 140, and then the first portion 121 and the second portion 122 of the metal layer 120 can be paired with each other in the subsequent steps.
  • the source region 141 and the drain region 142 of the active layer 140 are subjected to a conductive treatment to obtain a conductive source region 141 and a drain region 142.
  • the active layer 140 may be formed of a semiconductor material, such as amorphous silicon, microcrystalline silicon, polysilicon, oxide semiconductor, etc., and the oxide semiconductor material may be, for example, indium gallium zinc oxide (IGZO), zinc oxide. (ZnO) and so on.
  • the active layer 140 may be patterned by, for example, a photolithography process to form a semiconductor pattern, which is not limited in the embodiment of the present disclosure.
  • Step S105 annealing the metal layer 120 and the active layer 140, so that the source region 141 and the drain region 142 are conductive.
  • the annealing treatment can be carried out using compressed air (CDA).
  • CDA compressed air
  • the temperature of the annealing treatment may be 100°C-400°C, for example, it may be set between 100°C and 300°C.
  • the annealing treatment time may be 10 min-500 min, which is not limited in the embodiment of the present disclosure.
  • the source region 141 and the first part 121 diffuse each other, for example, the first part 121 diffuses its own metal atoms into the source region 141 to induce the source region 141 to become conductive;
  • the drain region 142 and the second portion 122 are mutually diffused.
  • the second portion 122 diffuses its own metal atoms into the drain region 142 to induce the drain region 142 to become conductive.
  • the sheet resistance of the source region 141 of the active layer 140 that is in contact with the source electrode 161 and The sheet resistance of the drain region 142 contacted by the drain 162 can be reduced, thereby the contact resistance between the source 161 and the source region 141 is reduced, and the contact resistance between the drain 162 and the drain region 142 is reduced. Therefore, when the thin film transistor 100 is working, the electrical signal transmission between the source electrode 161, the drain electrode 162 and the active layer 140 can be better realized, the stability of the thin film transistor 100 is improved, and the working performance of the thin film transistor 100 is improved.
  • Step S106 forming a gate insulating layer 151 on the active layer 140.
  • the material of the gate insulating layer 151 includes silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN) or other suitable materials.
  • the gate insulating layer 152 may be formed by a suitable method such as a physical vapor deposition method, a chemical vapor deposition method, or coating. The embodiment of the present disclosure does not limit this.
  • Step S107 forming a gate electrode 152 on the gate insulating layer 151.
  • the gate electrode 152 is formed on the gate insulating layer 151.
  • the width of the gate electrode 152 is equal to that of the metal layer 120.
  • the width of the portion 123 is the same or smaller than the width of the third portion 123; for another example, the orthographic projection of the gate 152 on the base substrate 110 is within the orthographic projection of the third portion 123 on the base substrate 110.
  • the material of the gate 152 may be a copper-based metal, such as copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum titanium alloy (Cu/Mo/Ti), Copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.
  • copper copper
  • Cu/Mo copper-molybdenum alloy
  • Cu/Ti copper-titanium alloy
  • Cu/Mo/Ti copper-molybdenum titanium alloy
  • Cu/Mo/W Copper-molybdenum-tungsten alloy
  • Cu/Mo/Nb copper-molybdenum-niobium alloy
  • the material of the gate 152 may also be a chromium-based metal, such as chromium-molybdenum alloy (Cr/Mo), chromium-titanium alloy (Cr/Ti), chromium-molybdenum titanium alloy (Cr/Mo/Ti), and the like.
  • the material of the gate 152 may also be aluminum or aluminum alloy, or other suitable materials.
  • the gate 152 and the gate insulating layer 151 may be patterned using the same patterning process, or both may be patterned in two patterning processes, which is not limited in the embodiment of the present disclosure.
  • Step S108 forming a second insulating layer 153 on the gate 152.
  • the second insulating layer 153 is usually formed of an organic insulating material (for example, acrylic resin) or an inorganic insulating material (for example, silicon nitride SiNx or silicon oxide SiOx).
  • an organic insulating material for example, acrylic resin
  • an inorganic insulating material for example, silicon nitride SiNx or silicon oxide SiOx.
  • it may be a single layer made of silicon nitride or silicon oxide. Layer structure, or double-layer structure composed of silicon nitride and silicon oxide, etc.
  • the second insulating layer 153 may be formed by a physical vapor deposition method, a chemical vapor deposition method, or a coating method. The embodiment of the present disclosure does not limit this.
  • the second insulating layer 153 is patterned to form two via holes exposing the source region 141 and the drain region 142 respectively, so as to realize the source 161 and the source region 141 formed in the subsequent steps. And the electrical connection between the drain 162 and the drain region 142 formed in a subsequent step.
  • step S106, step S107, and step S108 may also be performed before step S105, that is, step S105 may be performed after step S108. That is, before the metal layer 120 and the active layer 140 are annealed to induce the source region 141 and the drain region 142 to become conductive by the metal layer 120, the gate insulating layer 151 is formed on the active layer 140 to insulate the gate A gate electrode 152 is formed on the layer 151, and a second insulating layer 153 is formed on the gate electrode 152.
  • the thin film transistor 100 is annealed to use the metal layer 120 to induce the source region 141 and the drain region 142 of the active layer 140 to become conductive, since both sides of the gate 152 are covered by the gate insulating layer 151 and Covered by the second insulating layer 153, the gate 152 and the active layer 140 are insulated from each other. Therefore, when the annealing process is performed after the step S107, the adverse effect on the performance of the gate 152 can be reduced or avoided.
  • step S105 may also be executed between step S106 and step S107. That is, before the source region 141 and the drain region 142 of the active layer 140 are made conductive by the metal layer 120, the gate insulating layer 151 is formed on the active layer 140; After the source region 141 and the drain region 142 are conductive, a gate 152 is formed on the gate insulating layer 151, and a second insulating layer 153 is formed on the gate 152.
  • step S105 can be adjusted flexibly accordingly.
  • the annealing process in step S105 can be performed after forming an insulating layer. The embodiment of the present disclosure does not limit this.
  • Step S109 forming a source electrode 161 and a drain electrode 162.
  • the source electrode 161 is electrically connected to the source region 141 of the active layer 140
  • the drain electrode 162 is electrically connected to the drain region 142 of the active layer 140.
  • the source electrode 161 and the drain electrode 162 are insulated from each other.
  • the material of the source electrode 161 and the drain electrode 162 may be a copper-based metal, such as copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum titanium alloy (Cu/Mo /Ti), copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.; or, it can also be a chromium-based metal, for example, chromium-molybdenum alloy (Cr/Mo), chromium Titanium alloy (Cr/Ti), chromium molybdenum titanium alloy (Cr/Mo/Ti), etc. or other suitable materials are not limited in the embodiments of the present disclosure.
  • a source-drain electrode layer film may be deposited on the second insulating layer 153 and subjected to a patterning process to form a source-drain electrode layer.
  • the source and drain electrode layers include a source electrode 161 and a drain electrode 162, which are not limited in the embodiment of the present disclosure.
  • the manufacturing method of the thin film transistor 100 may further include forming, for example, a third insulating layer (not shown) on the source electrode 161 and the drain electrode 162. Shows).
  • the annealing process in step S105 may also be performed after forming the third insulating layer, which is not limited in the embodiment of the present disclosure.
  • step S105 when the thin film transistor 100 is annealed, since the source electrode 161 and the source region 141 contact surface areas can penetrate each other, the drain electrode 162 and The surface regions contacted by the drain region 142 can penetrate each other, so the contact resistance between the source electrode 161 and the source region 141 can be further reduced, and the contact resistance between the drain electrode 162 and the drain region 142 can be further reduced, so that The conductorized source region 141 and drain region 142 can better transmit electrical signals and achieve better conduction effects. As a result, the risk of poor contact that may exist in the thin film transistor 100 can be greatly reduced, thereby significantly improving the stability of the thin film transistor 100 and improving the working performance of the thin film transistor 100.
  • the method for manufacturing the thin film transistor 100 provided by some embodiments of the present disclosure may further include more or fewer steps, and the sequence of the steps is not limited, and may be determined according to different actual requirements.
  • FIG. 5 shows the conductive regions of the active layer 140 (that is, the source region 141 and the drain region 142) obtained by two conductive methods respectively at different temperatures.
  • broken line 1 represents the sheet resistance of the conductive area obtained by the plasma method at different temperatures
  • broken line 2 represents the corresponding sheet resistance of the conductive area obtained by the metal induction method at different temperatures. The sheet resistance.
  • the sheet resistance of the conductive regions (such as the source region 141 and the drain region 142) of the active layer 140 obtained by the metal layer induction method is lower than that of the plasma
  • the sheet resistance of the conductive area of the active layer 140 obtained by the bulk method is lower than that of the plasma.
  • the sheet resistance of the conductive area obtained by the method of metal layer induction is between 1.E+06 ⁇ / ⁇ 1.E+07 ⁇ / ⁇ , while the value of the sheet resistance of the conductive area obtained by the method of plasma
  • the value of the sheet resistance of the conductorized area obtained by the method is between 1.E+03 ⁇ / ⁇ 1.E+04 ⁇ / ⁇ , that is, the sheet resistance of the conductorized area obtained by the method of metal layer induction is higher than that obtained by plasma
  • the sheet resistance of the conductorized area obtained by the method is about 3 orders of magnitude lower.
  • the method of metal layer induction to conduct the conductive treatment on the area of the active layer that needs to be conductive can greatly reduce the sheet resistance of the conductive area, and make the conductive area of the active layer.
  • a good conduction effect is achieved, thereby reducing the risk of poor contact that may exist when the source region is in electrical contact with the source or the drain region is in electrical contact with the drain of the active layer, and the stability of the thin film transistor is significantly improved , Improve the working performance of the thin film transistor, at the same time improve the stability of the preparation process of the thin film transistor, and optimize the process of the thin film transistor.
  • the annealing treatment may be performed by a compressed air (CDA) method.
  • the temperature of the annealing treatment may be 100°C-400°C, for example, it may be set between 100°C and 300°C.
  • the annealing treatment time can be 10min-500min.
  • the metal layer 120 is disposed on the side of the active layer 140 close to the base substrate 110 (that is, the side far away from the source electrode 161 and the drain electrode 162), it is The metal oxide (such as aluminum oxide) that may be generated by the metal layer 120 due to high temperature is located on the side of the active layer 140 close to the base substrate 110, so the metal oxide will not affect the active layer 140 and the source electrode 161.
  • the source region 141 in contact and the drain region 142 in contact with the active layer 140 and the drain 162 have adverse effects. Therefore, the uncertainty that may exist in the manufacturing process of the thin film transistor 100 is reduced, the stability of the manufacturing process of the thin film transistor 100 is improved, and the working performance of the thin film transistor 100 is improved.
  • the microstructure of the material of the active layer 140 may change, which in turn changes the apparent properties of the active layer 140.
  • the atoms in the active layer 140 gain energy, and the lattice position with lower energy can be reselected, thereby reducing the defects of the microstructure in the active layer 140 and making the thin film transistor 100 more effective. The characteristics are more stable and achieve better working performance.
  • an annealing process is used to make the metal layer 120 induce the source region 141 and the drain region 142 of the active layer 140 to become conductive, so that the source region 141 and drain region 141 and drain region after the conductive treatment are made conductive.
  • the sheet resistance of the electrode region 142 is greatly reduced, so that the electrical signal transmission between the source region 141 and the drain region 142 of the active layer 140 can be better realized when the thin film transistor 100 is working, and the stability of the thin film transistor 100 is improved.
  • other high-temperature processing methods or other suitable process methods can also be used according to different actual needs to realize the use of the metal layer 120 to induce the source region 141 and the drain electrode of the active layer 140.
  • the region 142 is conductive, which is not limited in the embodiment of the present disclosure.
  • FIGS. 2 and 3 only show a partial structure of the thin film transistor 100 and a corresponding exemplary manufacturing method.
  • the thin film transistor 100 may also include other structures or functional layers. Accordingly, the manufacturing method may also include other corresponding manufacturing steps, which are not limited in the embodiments of the present disclosure.
  • the thin film transistor 100 shown in FIGS. 2 and 3 is a thin film transistor with a top gate structure, and in some other embodiments of the present disclosure, the thin film transistor 100 may also be a thin film transistor with a bottom gate structure. The embodiment of the present disclosure does not limit this.
  • FIG. 6 is a schematic diagram of a partial cross-sectional structure of another thin film transistor 200 provided by some embodiments of the present disclosure.
  • FIG. 7 is an exemplary flow chart of a method for manufacturing the thin film transistor 200 shown in FIG. 6 provided by some embodiments of the present disclosure.
  • the structure of the thin film transistor 200 shown in FIG. 6 is substantially the same as the structure of the thin film transistor 100 shown in FIG. 2 and will not be repeated here.
  • the third portion 223 of the metal layer 220 is insulated from the first portion 221 and the second portion 222, and the orthographic projection of the third portion 223 on the base substrate 210 is located
  • the source layer 240 is in the orthographic projection on the base substrate 210, so the third part 223 may also be configured as the gate of the thin film transistor 200, that is, the third part 223 may be multiplexed as the gate of the thin film transistor 200. Therefore, compared with the situation shown in FIG.
  • the manufacturing method of the thin film transistor 200 may include the following steps S201 to S207.
  • Step S201 Provide a base substrate 210.
  • Step S202 forming a metal layer 220 on the base substrate 210.
  • the metal layer 220 includes a first portion 221, a second portion 222, and a third portion 223 that are insulated from each other.
  • Step S203 forming a first insulating layer 230 on the metal layer 220 so that the first insulating layer 230 covers the metal layer 220 and exposing the first portion 221 and the second portion 222.
  • Step S204 forming an active layer 240 on the first insulating layer 230.
  • Step S205 annealing the metal layer 220 and the active layer 240 to make the source region 241 and the drain region 242 conductive.
  • Step S206 forming a fourth insulating layer 254 on the active layer 240.
  • Step S207 forming a source electrode 261 and a drain electrode 262.
  • the source electrode 261 is electrically connected to the source region 241 of the active layer 240
  • the drain electrode 262 is electrically connected to the drain region 242 of the active layer 240.
  • the fourth insulating layer 254 is usually formed of an organic insulating material (for example, acrylic resin) or an inorganic insulating material (for example, silicon nitride SiNx or silicon oxide SiOx).
  • an organic insulating material for example, acrylic resin
  • an inorganic insulating material for example, silicon nitride SiNx or silicon oxide SiOx.
  • it may be a single layer made of silicon nitride or silicon oxide. Layer structure, or double-layer structure composed of silicon nitride and silicon oxide, etc.
  • the fourth insulating layer 254 may be formed by a physical vapor deposition method, a chemical vapor deposition method, or a coating method, which is not limited in the embodiment of the present disclosure.
  • an array substrate for a liquid crystal display device it is also possible to continue to prepare structures such as pixel electrodes and common electrodes on the base substrate, and to prepare gate lines while preparing the gate. While preparing the source and drain, data lines and the like can be prepared.
  • structures such as pixel electrodes and common electrodes on the base substrate, and to prepare gate lines while preparing the gate. While preparing the source and drain, data lines and the like can be prepared.
  • OLED organic light emitting diodes
  • other components may be prepared as needed, including but not limited to signal lines, capacitors, photosensitive elements, and the like.
  • At least one embodiment of the present disclosure further provides a thin film transistor including: a metal layer, an active layer, a source electrode and a drain electrode.
  • the metal layer is an opaque metal layer.
  • the active layer is located on the metal layer.
  • the metal layer includes a first part and a second part insulated from each other. The first part contacts the source region of the active layer, and the second part contacts the drain region of the active layer.
  • the source region and the drain region are conductive relative to the channel region of the active layer, the source is electrically connected to the source region of the active layer, and the drain is electrically connected to the drain region of the active layer.
  • the opaque metal layer may be configured as, for example, a light shielding layer of the thin film transistor.
  • the opaque metal layer can also be used to induce the The source region and the drain region are conductive. Therefore, the opaque metal layer can not only shield the structure or functional components of the thin film transistor disposed thereon, to provide protection, but also can be used to induce the source and drain regions of the active layer under high temperature conditions, for example. District conductorization.
  • the thin film transistor provided by some embodiments of the present disclosure does not need to additionally prepare a new metal layer as a light shielding layer and Corresponding insulating layer, or no need to provide an additional metal layer to induce the source and drain regions of the active layer to become conductive, thereby simplifying the structure of the thin film transistor, reducing the manufacturing cost of the thin film transistor, and simplifying
  • the preparation process of the thin film transistor is reduced, the process uncertainty that may exist in the preparation process of the thin film transistor is reduced, and the characteristics of the thin film transistor are more stable.
  • the thin film transistor may be the thin film transistor 100 shown in FIG. 2 or the thin film transistor 200 shown in FIG. 6.
  • the thin film transistor 100 shown in FIG. 2 or the thin film transistor 200 shown in FIG. 6 may be the thin film transistor 100 shown in FIG. 2 or the thin film transistor 200 shown in FIG. 6, which will not be repeated here.
  • the material of the metal layer may be an opaque metal or alloy such as aluminum, copper, titanium, and molybdenum.
  • the thin film transistor provided by at least one embodiment of the present disclosure further includes a first insulating layer.
  • the first insulating layer is disposed between the metal layer and the active layer, and the first insulating layer covers other parts of the metal layer except the first part and the second part.
  • the metal layer further includes a third part, the third part is insulated from the first part and the second part, and the third part is located in the active layer. Inside the orthographic projection on the metal layer.
  • the third part is configured as the gate of the thin film transistor, so that it is above the active layer (that is, the active layer is away from the substrate). There is no need to form a gate on the side of the substrate, so that a bottom-gate thin film transistor can be formed, or a second gate can be formed to obtain a double-gate transistor.
  • the thin film transistor provided by at least one embodiment of the present disclosure further includes a gate insulating layer, a gate, and a second insulating layer.
  • the gate insulating layer is located on the side of the active layer away from the metal layer, the gate is located on the side of the gate insulating layer away from the active layer, and the second insulating layer is located on the side of the gate away from the gate insulating layer.
  • At least one embodiment of the present disclosure further provides an electronic device substrate.
  • the electronic device substrate includes the thin film transistor described in any embodiment of the present disclosure, for example, the thin film transistor 100 shown in FIG. 2 or the thin film transistor shown in FIG. 6 200.
  • the electronic device substrate including the thin film transistor 100 shown in FIG. 2 is taken as an example below to describe the electronic device substrate provided by some embodiments of the present disclosure.
  • FIG. 8 is a schematic partial plan view of an electronic device substrate provided by some embodiments of the disclosure.
  • FIG. 2 can be understood as a cross-sectional view of some examples of the electronic device substrate 30 shown in FIG. 8 along the line A-A', that is, FIG. 2 is a schematic diagram of the cross-sectional structure along the line A-A' in FIG.
  • the insulating layer for example, the first insulating layer 130, the gate insulating layer 151, the second insulating layer 153, etc.
  • the metal layer 120 and other structures are omitted in FIG.
  • the embodiment of the present disclosure is described by taking the electronic device substrate 30 including the thin film transistor 100 shown in FIG. 2 as an example, and the embodiment of the present disclosure includes but is not limited to this.
  • the cross-sectional view of some examples of the electronic device substrate 30 along the line A-A' shown in FIG. 8 may also be as shown in FIG. 6.
  • the source electrode 161 is electrically connected to the source region 141 of the active layer 140 through the first via 171 provided in the second insulating layer 153, and the drain electrode 162 It is electrically connected to the drain region 142 of the active layer 140 through the second via hole 172 provided in the second insulating layer 153.
  • the electronic device substrate 30 further includes a pixel electrode 310 disposed on the base substrate 110, and the pixel electrode 310 and the drain electrode 162 are electrically connected to each other.
  • the surface of the second insulating layer 153 may be provided with a groove (not shown), and the pixel electrode 310 is formed in the groove.
  • the electronic device substrate 30 further includes a common electrode 320 disposed on the base substrate 110, and the common electrode 320 is covered by the second insulating layer 153.
  • the pixel electrode 310 and the common electrode 320 may be plate electrodes or slit electrodes.
  • the pixel electrode 310 and the common electrode 320 may respectively include a plurality of branch electrodes, that is, both have a comb-like structure, and the branch electrodes of the pixel electrode 310 and the branch electrodes of the common electrode 320 overlap each other or are arranged alternately with each other, for example.
  • the pixel electrode 310 is a slit electrode, and includes a plurality of branch electrodes, for example, parallel to each other, the branch electrodes are separated by slits;
  • the common electrode 320 is a plate electrode.
  • the pixel electrode 310 is formed on the common electrode 320, and the electronic device substrate 30 may be used, for example, in an Advanced Super Dimension Switch (ADS) type liquid crystal panel.
  • ADS Advanced Super Dimension Switch
  • the electrode device substrate 30 further includes a gate line 330.
  • the gate line 330 may be integrally provided with the gate 152 and covered by the second insulating layer 153.
  • the electrode device substrate 30 further includes a data line 340.
  • the data line 340 extends in the longitudinal direction, and the gate line 330 extends in the horizontal direction.
  • the data line 340 and the gate line 330 are insulated and crossed with each other.
  • the thin film transistor 100 is formed on the data line 340, for example. At a position where it crosses the gate line 330.
  • the material of the data line 340 may include copper-based metal, aluminum-based metal, nickel-based metal, and the like.
  • the copper-based metal may be copper (Cu), or may also be a copper-based metal alloy with stable properties such as copper-zinc alloy (CuZn), copper-nickel alloy (CuNi), or copper-zinc-nickel alloy (CuZnNi).
  • the data line 340 may be disposed on the second insulating layer 153, so that the source electrode 161 and the data line 340 may be electrically connected to each other, for example, may be formed as one body.
  • the data line 340 may be disposed on the base substrate 110 and covered by the second insulating layer 153 (ensure that the data line 340 and the gate line 330 are insulated from each other, for example, at a position where the data line 340 and the gate line 330 cross each other.
  • the insulating layer is provided and, for example, the respective line segments of the data line 340 separated by the gate line 330 are electrically connected to each other through the bridge electrode), so that the second insulating layer 153 may further include a via hole (not shown) through which the source electrode 161 passes.
  • the via is electrically connected to the data line 340.
  • the source electrode 161 and the drain electrode 162 are electrically connected through the active layer 140, and the thin film transistor 100 is turned on, so that the pixel electrode 310 is electrically connected to the data line 340, and the data line 340 is electrically connected.
  • the applied signal may be transmitted to the pixel electrode 310; when the off signal is applied to the gate line 330, the thin film transistor 100 is turned off, so that the pixel electrode 310 is electrically disconnected from the data line 340.
  • the electronic device substrate 30 includes a plurality of such pixel areas, and the plurality of pixel areas are arranged in an array to form a display. area.
  • the electronic device substrate 30 shown in FIG. 8 may be applied to, for example, a liquid crystal panel, and in some other embodiments of the present disclosure, the electronic device substrate may also include other structures, and may be applied to, for example, an OLED panel. In other types of display panels such as QLED panels, the embodiments of the present disclosure do not limit this.
  • the technical effect and implementation principle of the electronic device substrate 30 are basically the same as those of the thin film transistor (such as the thin film transistor 100 or the thin film transistor 200) described in the embodiments of the present disclosure, and will not be repeated here.
  • At least one embodiment of the present disclosure further provides an electronic device, which includes the electronic device substrate according to any embodiment of the present disclosure.
  • the electronic device provided by the embodiment of the present disclosure may include the electronic device substrate 30 shown in FIG. 8. Taking an electronic device with a photosensitive function including the electronic device substrate 30 shown in FIG. 8 as an example, the electronic device provided by some embodiments of the present disclosure will be described below.
  • FIG. 9 is a schematic diagram of a partial circuit structure of an electronic device provided by some embodiments of the disclosure.
  • the electronic device 40 includes a plurality of pixel regions (for example, pixel units) shown in FIG. 8.
  • each pixel unit includes a photodiode 410 and a thin film transistor 100.
  • the thin film transistor 100 of each pixel unit is electrically connected to a gate line 330 adjacent thereto, and the photodiode 410 of each pixel unit passes through the thin film transistor 100 in the pixel unit.
  • An adjacent data line 340 (or read line) is electrically connected.
  • the gate 152 of each thin film transistor 100 in each row of pixel units is electrically connected to an adjacent gate line 330, and the source 161 of each thin film transistor 100 in each column of pixel unit Is electrically connected to a data line 340 adjacent thereto, the drain 162 of the thin film transistor 100 of each pixel unit is electrically connected to the cathode of the photodiode 410 of the pixel unit, and the anode of the photodiode 410 of the pixel unit can be connected to, for example,
  • the bias line 420 is electrically connected.
  • the bias line 420 is parallel to the gate line 330, and each row of pixel units shares the same bias line 420.
  • each gate line 330 is electrically connected to the gate driving circuit
  • each data line 340 is electrically connected to the data driving circuit.
  • the electronic device 40 when the photodiode 410 directly or indirectly senses, for example, a photoelectric signal, the electronic device 40 applies a scanning signal to each pixel unit through a gate line 330 to control the film
  • the switching state of the transistor 100 can indirectly control the reading function of the photoelectric signal generated by each photodiode 410 through the data line 340 by the data driving circuit, so that the electronic device 40 can realize the photosensitive function.
  • the photoelectric signal generated by the photodiode 410 corresponding to the thin film transistor 100 can be collected by the data line 340 connected to the source 161 of the thin film transistor 100, thereby realizing the photoelectric signal of the photodiode 410 collection.
  • the electronic device 40 may also be an electronic device with other functions. Accordingly, each pixel unit of the electronic device 40 may include other corresponding functional components, etc., which is not limited in the embodiment of the present disclosure.
  • the technical effects and implementation principles of the electronic device 40 are basically the same as the electronic device substrate (such as the electronic device substrate 30) or the thin film transistor (such as the thin film transistor 100 or the thin film transistor 200) described in the embodiments of the present disclosure, and will not be repeated here.
  • the electronic device 40 may be any product or component with a display function, such as a liquid crystal panel, electronic paper, OLED panel, QLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • a display function such as a liquid crystal panel, electronic paper, OLED panel, QLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • the embodiment does not limit this.

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Abstract

一种薄膜晶体管及其制备方法、电子装置基板及电子装置，该薄膜晶体管的制备方法包括：提供衬底基板；在衬底基板上形成金属层，金属层包括彼此绝缘的第一部分和第二部分；在金属层上形成有源层，有源层包括源极区和漏极区，金属层的第一部分接触源极区，金属层的第二部分接触漏极区；以及通过金属层对有源层导体化处理，以使源极区和漏极区被导体化。该制备方法降低了薄膜晶体管的有源层的导体化区域可能存在的接触不良的风险。

Description

薄膜晶体管及其制备方法、电子装置基板及电子装置
本申请要求于2019年5月30日递交的中国专利申请第201910463831.5号的优先权，该中国专利申请的全文以引入的方式并入以作为本申请的一部分。
技术领域
本公开的实施例涉及一种薄膜晶体管及其制备方法、电子装置基板及电子装置。
背景技术
薄膜晶体管(TFT)包括栅极、源极、漏极、栅极绝缘层和半导体层等结构。栅极通过栅极绝缘层与半导体层隔开，源极和漏极与半导体层直接接触。当栅极上施加的电压达到预定值时，位于源极和漏极之间的半导体层的沟道区域变得导电或不导电，当半导体层的沟道区域变得导电时，在源极和漏极之间可以产生电流，由此薄膜晶体管可以起到开关元件的作用。
发明内容
本公开至少一个实施例提供一种薄膜晶体管的制备方法，该制备方法包括：提供衬底基板；在所述衬底基板上形成金属层，其中，所述金属层包括彼此绝缘的第一部分和第二部分；在所述金属层上形成有源层，其中，所述有源层包括源极区和漏极区，所述金属层的所述第一部分接触所述源极区，所述金属层的所述第二部分接触所述漏极区；以及通过所述金属层对所述有源层导体化处理，以使所述源极区和所述漏极区被导体化。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，在所述金属层上形成所述有源层，包括：在所述金属层上形成第一绝缘层，使所述第一绝缘层覆盖所述金属层且暴露所述第一部分和所述第二部分；以及在所述第一绝缘层上形成所述有源层，使得所述金属层的所述第一部分接触所述有源层的源极区，所述金属层的所述第二部分接触所述有源层的漏极区。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，通过 所述金属层对所述有源层导体化处理，包括：对所述金属层和所述有源层退火处理，以使所述源极区和所述漏极区被导体化。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，所述退火处理的温度为100℃-400℃，所述退火处理的时间为10min-500min。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，所述金属层的材料包括选自由铝、铜、钛、钼金属或合金构成的组中任一。
例如，本公开至少一个实施例提供的薄膜晶体管的制备方法还包括：形成源极和漏极，其中，所源极与所述有源层的所述源极区电连接，所述漏极与所述有源层的所述漏极区电连接。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，所述金属层还包括第三部分，所述第三部分与所述第一部分及所述第二部分彼此绝缘，所述第三部分在所述衬底基板上的正投影位于所述有源层在所述衬底基板上的正投影内。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，所述第三部分被配置为所述薄膜晶体管的栅极。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，在通过所述金属层对所述有源层导体化处理之后，相对于所述衬底基板，所述制备方法还包括：在所述有源层上形成栅极绝缘层；在所述栅极绝缘层上形成栅极；以及在所述栅极上形成第二绝缘层。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，在通过所述金属层对所述有源层导体化处理之前，相对于所述衬底基板，所述制备方法还包括：在所述有源层上形成栅极绝缘层；在所述栅极绝缘层上形成栅极；以及在所述栅极上形成第二绝缘层。
例如，在本公开至少一个实施例提供的薄膜晶体管的制备方法中，在通过所述金属层对所述有源层导体化处理之前，相对于所述衬底基板，所述制备方法还包括：在所述有源层上形成栅极绝缘层；在通过所述金属层对所述有源层导体化处理之后，相对于所述衬底基板，所述制备方法还包括：在所述栅极绝缘层上形成栅极，以及在所述栅极上形成第二绝缘层。
本公开至少一个实施例还提供一种薄膜晶体管，包括：金属层、有源层、源极和漏极，其中，所述金属层为不透明金属层，所述有源层位于所述金属层上，所述金属层包括彼此绝缘的第一部分和第二部分，所述第一部分接触 所述有源层的源极区，所述第二部分接触所述有源层的漏极区，所述源极区和所述漏极区相对于所述有源层的沟道区被导体化，所述源极与所述有源层的所述源极区电连接，所述漏极与所述有源层的所述漏极区电连接。
例如，在本公开至少一个实施例提供的薄膜晶体管中，所述金属层的材料包括选自由铝、铜、钛、钼金属或合金构成的组中任一。
例如，本公开至少一个实施例提供的薄膜晶体管还包括第一绝缘层，其中，所述第一绝缘层设置在所述金属层和所述有源层之间，所述第一绝缘层覆盖所述金属层除所述第一部分和所述第二部分外的其他部分，且暴露所述第一部分和所述第二部分，以使得所述第一部分接触所述有源层的源极区，所述第二部分接触所述有源层的漏极区。
例如，在本公开至少一个实施例提供的薄膜晶体管中，所述金属层还包括第三部分，所述第三部分与所述第一部分及所述第二部分彼此绝缘，所述第三部分位于所述有源层在所述金属层上的正投影内。
例如，在本公开至少一个实施例提供的薄膜晶体管中，所述第三部分被配置为所述薄膜晶体管的栅极。
例如，本公开至少一个实施例提供的薄膜晶体管还包括栅极绝缘层、栅极和第二绝缘层，其中，所述栅极绝缘层位于所述有源层远离所述金属层的一侧，所述栅极位于所述栅极绝缘层远离所述有源层的一侧，所述第二绝缘层位于所述栅极远离所述栅极绝缘层的一侧。
本公开至少一个实施例还提供一种电子装置基板，包括本公开任一实施例所述的薄膜晶体管。
本公开至少一个实施例还提供一种电子装置，包括本公开任一实施例所述的电子装置基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种薄膜晶体管的制备方法的流程图；
图2为本公开一些实施例提供的一种薄膜晶体管的部分截面结构示意图；
图3为本公开一些实施例提供的图2中所示的薄膜晶体管的制备方法的示例性流程图；
图4A-4F为对应图3中所示的薄膜晶体管的制备方法的具体步骤的示意图；
图5为分别通过两种导体化方法得到的有源层的导体化区域在不同温度下的方块电阻的折线图；
图6为本公开一些实施例提供的另一种薄膜晶体管的部分截面结构示意图；
图7为本公开一些实施例提供的图6中所示的薄膜晶体管的制备方法的示例性流程图；
图8为本公开一些实施例提供的一种电子装置基板的部分平面示意图；以及
图9为本公开一些实施例提供的一种电子装置的部分电路结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
目前，在制备薄膜晶体管的过程中，可以采用等离子体(例如氦气或氩气的等离子体)对薄膜晶体管的有源层中与源极、漏极搭接处(即有源层的源极区和漏极区)进行导体化。但是，在利用等离子体方法导体化后，有源层的导体化区域仍然具有较大的阻抗，并且容易受到导体化工艺波动的影 响，无法达到良好的导通效果，进而导致源极、漏极与有源层之间产生接触不良的风险。因此，薄膜晶体管的制备工艺存在不稳定性。
本公开至少一个实施例提供一种薄膜晶体管的制备方法，该制备方法通过利用金属层对薄膜晶体管的有源层需要被导体化的区域进行导体化处理，降低了有源层与源极、漏极搭接处(即接触区域)的方块电阻，使有源层的导体化区域能够达到良好的导通效果，进而减弱或避免源极、漏极与有源层之间可能产生的接触不良的风险，提升了薄膜晶体管的制备工艺的稳定性。
下面，将参考附图详细地说明本公开的一些实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
图1为本公开一些实施例提供的一种薄膜晶体管的制备方法的流程图。如图1所示，该制备方法包括以下步骤。
步骤S10：提供衬底基板。
步骤S20：在衬底基板上形成金属层。金属层包括彼此绝缘的第一部分和第二部分。
步骤S30：在金属层上形成有源层。该有源层包括源极区和漏极区，金属层的第一部分接触源极区，金属层的第二部分接触漏极区。
步骤S40：通过金属层对有源层导体化处理，以使源极区和漏极区被导体化。
下面将结合一些薄膜晶体管的具体结构，对本公开一些实施例提供的薄膜晶体管的制备方法进行说明。
图2为本公开一些实施例提供的一种薄膜晶体管的部分截面结构示意图，图3为本公开一些实施例提供的图2中所示的薄膜晶体管的制备方法的示例性流程图，图4A-4F为对应图3中所示的薄膜晶体管的制备方法的具体步骤的示意图。下面将结合图2、图3以及图4A-4F对本公开的一些实施例进行说明。
例如，如图2所示，薄膜晶体管100包括在衬底基板110上依次设置的金属层120、第一绝缘层130、有源层140、栅极绝缘层151、栅极152、第二绝缘层153、源极161和漏极162。
例如，第一绝缘层130位于金属层120远离衬底基板110的一侧，有源层140位于第一绝缘层130远离金属层120的一侧，栅极绝缘层151和栅极152位于有源层140远离第一绝缘层130的一侧，第二绝缘层153位于栅极 绝缘层151和栅极152远离有源层140的一侧。源极161与有源层140的源极区141接触，漏极162与有源层140的漏极区142接触。
例如，金属层120包括彼此绝缘的第一部分121和第二部分122，在图2中，第一部分121从有源层140的下侧(即靠近衬底基板110的一侧)接触源极区141，第二部分122从有源层140的下侧接触漏极区142。
下面以图2中所示的薄膜晶体管100的具体结构为例，对薄膜晶体管100的制备方法进行说明。
例如，结合图3和图4A-图4F所示，薄膜晶体管100的制备方法包括如下所述的步骤S101～S109。
步骤S101：提供衬底基板110。
步骤S102：在衬底基板110上形成金属层120。
例如，衬底基板110可以为玻璃基板、塑料基板等，例如衬底基板110的材料可以采用聚酰亚胺(PI)、聚乙烯(PE)、聚丙烯(PP)、三醋酸纤维素(TAC)等，本公开的实施例对此不作限制。
如图4A所示，例如，金属层120包括彼此绝缘的第一部分121和第二部分122。对于后续步骤中将形成的有源层140，第一部分121与有源层140的源极区141(如图2中所示)对应，第二部分122与有源层140的漏极区142(如图2中所示)对应，该有源层140在源极区141和漏极区142之间包括沟道区。
例如，金属层120的材料可以为铝、铜、钛、钼等金属或合金，本公开的实施例对此不作限制。
例如，金属层120可以通过物理气相沉积、化学气相沉积等方法形成。例如，金属层120可以通过构图工艺进行处理以形成第一部分121和第二部分122，本公开的实施例对形成第一部分121和第二部分122的具体方法不作限制。
例如，金属层120可以为不透明金属层。如下所述，另一些示例中，该金属层120还可以包括用于形成薄膜晶体管100的遮光层的部分。例如，对于薄膜晶体管为底栅型的情形，薄膜晶体管的有源层在受到来自衬底基板一侧的光照射后会使得光生载流子增加，容易造成薄膜晶体管产生阈值电压漂移、漏电流增加等不良现象，因此需要在薄膜晶体管的有源层靠近衬底基板的一侧设置遮光层，以减弱或避免上述不良现象。在另一些示例中，在金属 层120为不透明金属层的情形，金属层120的作为遮光层的部分可以遮挡从衬底基板110远离金属层120的方向射入的例如环境光(例如蓝光)，减弱或避免光线照射到设置在金属层120上的薄膜晶体管100的其他结构或功能部件(例如有源层)，进而减弱了外部光线对薄膜晶体管100可能产生的干扰，提升了薄膜晶体管100的稳定性，改善了薄膜晶体管100的工作性能。
此外，在金属层120起到遮光作用的情形，由于薄膜晶体管100无需再另行制备单独的遮光层以及对应的绝缘层，因此薄膜晶体管100的整体结构得到简化，使薄膜晶体管100的制备成本降低，并且还优化了薄膜晶体管100的制备工艺，减小了在制备过程中可能存在的工艺不确定性。由此，进一步提升了薄膜晶体管100制备工艺的稳定性，使薄膜晶体管100的特性更加稳定。
例如，具体而言，如图2和图4A所示，金属层120还包括第三部分123，第三部分123位于第一部分121和第二部分122之间，且与第一部分121及第二部分122彼此绝缘。第三部分123在衬底基板110上的正投影位于有源层140在衬底基板110上的正投影内。例如，在至少一个示例中，第三部分123与有源层140的沟道区对应，例如，第三部分123在从源极161到漏极162的方向上的宽度小于有源层140的宽度。
例如，在另一些示例中，金属层120还包括第四部分124和第五部分125，第四部分124和第五部分125与第一部分121、第二部分122及第三部分123彼此绝缘。例如，在金属层120为不透明金属层且作为薄膜晶体管100的遮光层使用的情形，不透明金属层120的第四部分124和第五部分125可以覆盖衬底基板110的大部分表面，以减少或防止从衬底基板110远离金属层120的方向射入的例如环境光对设置在金属层120上的例如薄膜晶体管100的结构或功能部件产生干扰，进而提升薄膜晶体管100的稳定性，改善薄膜晶体管100的工作性能。
步骤S103：在金属层120上形成第一绝缘层130，使第一绝缘层130覆盖金属层120且暴露第一部分121和第二部分122。
例如，如图2和图4B所示，第一绝缘层130设置在金属层120和有源层140之间，第一绝缘层130覆盖金属层120除第一部分121和第二部分122外的其他部分。例如，通过构图工艺对第一绝缘层130构图，从而使得第一绝缘层130暴露金属层120的第一部分121和第二部分122，以使第一部分 121和第二部分122可以分别与后续工艺中形成的有源层140的源极区141和漏极区142接触，进而在后续工艺中可以利用金属层120对源极区141和漏极区142进行导体化处理。
例如，第一绝缘层130通常采用有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅SiNx或者氧化硅SiOx)形成。例如，第一绝缘层130可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层结构。
例如，第一绝缘层130可以通过物理气相沉积方法、化学气相沉积方法、或涂覆等适合的方法形成，本公开的实施例对此不作限制。
步骤S104：在第一绝缘层130上形成有源层140。
如图2和图4C所示，例如，在本公开的一些实施例中，由于第一绝缘层130覆盖金属层120且暴露第一部分121和第二部分122，因此金属层120的第一部分121接触有源层140的源极区141，金属层120的第二部分122接触有源层140的漏极区142，进而在后续的步骤中可以通过金属层120的第一部分121和第二部分122对有源层140的源极区141和漏极区142进行导体化处理，以得到导体化的源极区141和漏极区142。
例如，有源层140可以采用半导体材料形成，该半导体材料例如为非晶硅、微晶硅、多晶硅、氧化物半导体等，氧化物半导体材料例如可以为铟镓锌氧化物(IGZO)、氧化锌(ZnO)等。例如，有源层140可以通过例如光刻工艺被构图而形成半导体图案，本公开的实施例对此不作限制。
步骤S105：对金属层120和有源层140退火处理，以使源极区141和漏极区142被导体化。
例如，退火处理可以采用压缩空气(CDA)的方法进行。退火处理的温度可以为100℃-400℃，例如可以设置在100℃-300℃之间。退火处理的时间可以为10min-500min，本公开的实施例对此不作限制。
如图4D所示，例如，在对金属层120和有源层140进行退火处理时，由于源极区141和金属层120的第一部分121接触，漏极区142和金属层120的第二部分122接触，因此，在退火工艺的高温作用下，源极区141和第一部分121互相扩散，例如第一部分121将自身的金属原子扩散到源极区141中，以诱导源极区141导体化；漏极区142和第二部分122互相扩散，例如第二部分122将自身的金属原子扩散到漏极区142中，以诱导漏极区142导 体化。
例如，在进行退火处理以利用金属层120诱导有源层140的源极区141和漏极区142导体化后，有源层140的与源极161接触的源极区141的方块电阻以及与漏极162接触的漏极区142的方块电阻都可以得到降低，由此源极161和源极区141之间的接触电阻降低，漏极162和漏极区142之间的接触电阻降低。因此，在薄膜晶体管100工作时，能够更好地实现源极161、漏极162与有源层140之间的电信号传输，提高薄膜晶体管100的稳定性，改善薄膜晶体管100的工作性能。
步骤S106：在有源层140上形成栅极绝缘层151。
如图4E所示，例如，栅极绝缘层151的材料包括氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al 2O 3)、氮化铝(AlN)或其他适合的材料。例如，栅极绝缘层152可以通过物理气相沉积方法、化学气相沉积方法、或涂覆等适合的方法形成。本公开的实施例对此不作限制。
步骤S107：在栅极绝缘层151上形成栅极152。
如图4E所示，栅极152形成在栅极绝缘层151之上，在至少一个示例中，在从源极161到漏极162的方向上，栅极152的宽度与金属层120的第三部分123的宽度相同，或者小于第三部分123的宽度；又例如，栅极152在衬底基板110上的正投影在第三部分123在衬底基板110上的正投影之内。
例如，栅极152的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等。例如，栅极152的材料也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等。例如，栅极152的材料还可以为铝或铝合金等，或者为其他适合的材料。
例如，栅极152可以与栅极绝缘层151采用同一个构图工艺被构图，或者二者可以分别在两个构图工艺中被构图，本公开的实施例对此不作限制。
步骤S108：在栅极152上形成第二绝缘层153。
例如，第二绝缘层153通常采用有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅SiNx或者氧化硅SiOx)形成，例如可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层结构等。例如，第二绝缘层153可以通过物理气相沉积方法、化学气相沉积 方法、或涂覆方法形成。本公开的实施例对此不作限制。
并且如图4E所示，第二绝缘层153被构图形成分别暴露源极区141和漏极区142的两个过孔，以用于实现在后续步骤中形成的源极161与源极区141之间的电连接，以及在后续步骤中形成的漏极162与漏极区142之间的电连接。
例如，在本公开的其他一些实施例中，步骤S106、步骤S107和步骤S108也可以在步骤S105之前进行，也就是说，步骤S105可以在步骤S108之后执行。即，在对金属层120和有源层140退火处理以利用金属层120诱导源极区141和漏极区142导体化之前，在有源层140上形成栅极绝缘层151，在栅极绝缘层151上形成栅极152，以及在栅极152上形成第二绝缘层153。
例如，在对薄膜晶体管100进行退火处理以利用金属层120诱导有源层140的源极区141和漏极区142导体化时，由于栅极152的两侧表面分别被栅极绝缘层151和第二绝缘层153所覆盖，栅极152与有源层140彼此绝缘，因此，在步骤S107后再进行退火工艺时，可以减弱或避免对栅极152的性能造成不良的影响。
例如，在本公开的其他一些实施例中，步骤S105还可以在步骤S106和步骤S107之间执行。即，在通过金属层120对有源层140的源极区141和漏极区142导体化处理之前，在有源层140上形成栅极绝缘层151；在通过金属层120对有源层140的源极区141和漏极区142导体化处理之后，在栅极绝缘层151上形成栅极152，以及在栅极152上形成第二绝缘层153。
例如，在本公开的其他一些实施例中，步骤S105的执行顺序还可以相应地灵活调整，例如可以根据不同的实际需求，只要满足步骤S105中的退火工艺在形成一层绝缘层之后进行即可，本公开的实施例对此不作限制。
步骤S109：形成源极161和漏极162。源极161与有源层140的源极区141电连接，漏极162与有源层140的漏极区142电连接。
如图4F所示，源极161和漏极162彼此绝缘。例如，源极161和漏极162的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；或者，也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等或者其他适合的材料，本公开的实施例对此不作限制。
例如，在本公开的一些实施例中，可以在第二绝缘层153上沉积源漏电极层薄膜并对其进行构图工艺以形成源漏电极层。该源漏电极层包括源极161和漏极162，本公开的实施例对此不作限制。
例如，在本公开的一些实施例中，在步骤S109形成源极161和漏极162后，薄膜晶体管100的制备方法还可以包括在源极161和漏极162上形成例如第三绝缘层(未示出)。例如，步骤S105中的退火工艺还可以在形成第三绝缘层之后执行，本公开的实施例对此不作限制。
例如，在步骤S105在形成第三绝缘层之后执行的情形下，在对薄膜晶体管100进行退火处理时，由于源极161和源极区141接触的表面区域之间可以互相渗透，漏极162和漏极区142接触的表面区域之间可以互相渗透，因此源极161和源极区141之间的接触电阻可以进一步降低，漏极162和漏极区142之间的接触电阻可以进一步降低，使导体化后的源极区141和漏极区142能够更好地传输电信号，达到更好的导通效果。由此，可以大大降低薄膜晶体管100可能存在的接触不良的风险，进而显著地提升薄膜晶体管100的稳定性，改善薄膜晶体管100的工作性能。
例如，本公开的一些实施例提供的薄膜晶体管100的制备方法还可以包括更多或更少的步骤，且各个步骤之间的顺序不受限制，可以根据不同的实际需求而定。
例如，以金属层120采用的材料为铝金属为例，图5为分别通过两种导体化方法得到的有源层140的导体化区域(即源极区141和漏极区142)在不同温度下的方块电阻的折线图。
例如，如图5所示，折线1表示通过等离子体的方法得到的导体化区域在不同温度下所对应的方块电阻，折线2表示通过金属诱导的方法得到的导体化区域在不同温度下所对应的方块电阻。
如图5所示，在温度大于100℃左右的情形，利用金属层诱导的方法得到的有源层140的导体化区域(例如源极区141和漏极区142)的方块电阻低于利用等离子体的方法得到的有源层140的导体化区域的方块电阻。例如，在温度为250℃的情形，利用金属层诱导的方法得到的导体化区域的方块电阻的数值在1.E+06Ω/□～1.E+07Ω/□之间，而利用等离子体的方法得到的导体化区域的方块电阻的数值在1.E+03Ω/□～1.E+04Ω/□之间，即利用金属层诱导的方法得到的导体化区域的方块电阻比利用等离子体的方法得到的导体化 区域的方块电阻低3个数量级左右。
因此，利用金属层诱导的方法对有源层需要被导体化的区域(例如源极区和漏极区)进行导体化处理可以大大降低导体化区域的方块电阻，使有源层的导体化区域达到良好的导通效果，进而降低了有源层的例如源极区与源极电接触或漏极区与漏极电接触时可能存在的接触不良的风险，显著地提升了薄膜晶体管的稳定性，改善薄膜晶体管的工作性能，同时也提高了薄膜晶体管的制备工艺的稳定性，优化了薄膜晶体管的工艺制程。
例如，在本公开的一些实施例中，退火处理可以采用压缩空气(CDA)的方法进行。退火处理的温度可以为100℃-400℃，例如可以设置在100℃-300℃之间。退火处理的时间可以为10min-500min。
例如，在本公开的一些实施例中，由于金属层120设置在有源层140靠近衬底基板110的一侧(即远离源极161和漏极162的一侧)，因此在退火处理的过程中，金属层120因高温作用而可能产生的金属氧化物(例如氧化铝)位于有源层140靠近衬底基板110的一侧，因而该金属氧化物不会对有源层140与源极161接触的源极区141以及有源层140与漏极162接触的漏极区142产生不良影响。因而，降低了薄膜晶体管100在制备过程中可能存在的不确定性，提升了薄膜晶体管100的制备工艺的稳定性，改善了薄膜晶体管100的工作性能。
此外，在退火工艺的高温作用下，有源层140的材料的微观结构可能会发生变化，进而使有源层140的表观性质发生改变。例如，在退火工艺的高温作用下，有源层140内的原子获得能量，可以重新选择能量更低的晶格位置，进而可以减少有源层140内的微观结构的缺陷，使薄膜晶体管100的特性更加稳定，达到更好的工作性能。
例如，在本公开的一些实施例中，采用退火处理的方法使金属层120诱导有源层140的源极区141和漏极区142导体化，使导体化处理后的源极区141和漏极区142的方块电阻大大降低，进而在薄膜晶体管100工作时能够更好地实现有源层140的源极区141和漏极区142之间的电信号传输，提升薄膜晶体管100的稳定性。在本公开的其他一些实施例中，还可以根据不同的实际需求，采用其他高温处理的方法或其他适合的工艺方法，以实现利用金属层120诱导有源层140的源极区141和漏极区142导体化，本公开的实施例对此不作限制。
需要说明的是，图2和图3仅示出了薄膜晶体管100的部分结构以及对应的示例性制备方法。薄膜晶体管100还可以包括其他结构或功能层，相应地，该制备方法还可以包括其他对应的制备步骤，本公开的实施例对此不作限制。
需要说明的是，图2和图3中所示的薄膜晶体管100为顶栅型结构的薄膜晶体管，而在本公开的其他一些实施例中，薄膜晶体管100还可以为底栅型结构的薄膜晶体管，本公开的实施例对此不作限制。
图6为本公开一些实施例提供的另一种薄膜晶体管200的部分截面结构示意图，图7为本公开一些实施例提供的图6中所示的薄膜晶体管200的制备方法的示例性流程图。
例如，除栅极、栅极绝缘层及第二绝缘层外，图6中所示的薄膜晶体管200的结构与图2中所示的薄膜晶体管100的结构大体相同，这里不再赘述。
例如，在图6所示的薄膜晶体管200中，由于金属层220的第三部分223与第一部分221和第二部分222彼此绝缘，且第三部分223在衬底基板210上的正投影位于有源层240在衬底基板210上的正投影内，因此第三部分223还可以被配置为薄膜晶体管200的栅极，即第三部分223可以被复用为薄膜晶体管200的栅极。因此，与图2所示的情形相比，在薄膜晶体管200中，无需再另外制备栅极及栅极绝缘层等结构，从而简化了薄膜晶体管200的整体结构，降低了薄膜晶体管200的制备成本，同时还优化了薄膜晶体管200的制备工艺。
例如，如图7所示，以图6所示的薄膜晶体管200的具体结构为例，薄膜晶体管200的制备方法可以包括以下步骤S201～S207。
步骤S201：提供衬底基板210。
步骤S202：在衬底基板210上形成金属层220。金属层220包括彼此绝缘的第一部分221、第二部分222和第三部分223。
步骤S203：在金属层220上形成第一绝缘层230，使第一绝缘层230覆盖金属层220且暴露第一部分221和第二部分222。
步骤S204：在第一绝缘层230上形成有源层240。
步骤S205：对金属层220和有源层240退火处理，以使源极区241和漏极区242被导体化。
步骤S206：在有源层240上形成第四绝缘层254。
步骤S207：形成源极261和漏极262。源极261与有源层240的源极区241电连接，漏极262与有源层240的漏极区242电连接。
例如，第四绝缘层254通常采用有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅SiNx或者氧化硅SiOx)形成，例如可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层结构等。例如，第四绝缘层254可以通过物理气相沉积方法、化学气相沉积方法、或涂覆等方法形成，本公开的实施例对此不作限制。
本公开的实施例提供的薄膜晶体管200的制备方法的详细内容和技术效果可以参考上文中关于薄膜晶体管100的制备方法的相应描述，这里不再赘述。
根据需要，例如在制备用于液晶显示装置(LCD)的阵列基板的情形，还可以继续在衬底基板上制备例如像素电极、公共电极等结构，并且在制备栅极的同时可以制备栅线，在制备源极和漏极的同时，可以制备数据线等。例如在制备用于有机发光二极管(OLED)的阵列基板的情形，还可以继续在衬底基板上制备例如像素界定层、阳极、发光层、阴极等，并且还可以制备其他薄膜晶体管、电容等结构。例如，在制备用于其他类型的电子装置(例如成像装置)的基板的情形，根据需要还可以制备其他部件，包括但不限于信号线、电容、感光元件等。
本公开至少一个实施例还提供一种薄膜晶体管，该薄膜晶体管包括：金属层、有源层、源极和漏极。金属层为不透明金属层，有源层位于金属层上，金属层包括彼此绝缘的第一部分和第二部分，第一部分接触有源层的源极区，第二部分接触有源层的漏极区，源极区和漏极区相对于有源层的沟道区被导体化，源极与有源层的源极区电连接，漏极与有源层的漏极区电连接。
例如，在本公开一些实施例提供的薄膜晶体管中，该不透明金属层可以被配置为薄膜晶体管的例如遮光层。例如，由于该不透明金属层的第一部分和第二部分分别与有源层的源极区和漏极区接触，因而在一定制备工艺条件下，该不透明金属层还可以用于诱导有源层的源极区和漏极区导体化。因此，该不透明金属层既可以对设置其上的薄膜晶体管的结构或功能部件起到遮光的作用以提供保护，同时也可以在例如高温条件下用于诱导有源层的源极区和漏极区导体化。
因此，在利用该不透明金属层诱导薄膜晶体管的有源层的源极区和漏极 区导体化的情形，本公开一些实施例提供的薄膜晶体管无需再额外制备例如新的金属层作为遮光层以及相应的绝缘层，或者无需再额外提供新的金属层以实现诱导有源层的源极区和漏极区导体化，进而简化了薄膜晶体管的结构，降低了薄膜晶体管的制备成本，同时还简化了薄膜晶体管的制备工艺，降低了在薄膜晶体管的制备过程中可能存在的工艺不确定性，使薄膜晶体管的特性更加稳定。
例如，在本公开的一些实施例中，薄膜晶体管可以为图2中所示的薄膜晶体管100或图6中所示的薄膜晶体管200。本公开实施例提供的薄膜晶体管的具体结构和技术效果可以参考关于图2中所示的薄膜晶体管100或图6中所示的薄膜晶体管200的相应描述，这里不再赘述。
例如，在本公开至少一个实施例提供的薄膜晶体管中，金属层的材料可以为铝、铜、钛、钼等不透明金属或合金。
如图2和图6所示，例如，本公开至少一个实施例提供的薄膜晶体管还包括第一绝缘层。第一绝缘层设置在金属层和有源层之间，第一绝缘层覆盖金属层除第一部分和第二部分外的其他部分。
如图2所示，例如，在本公开至少一个实施例提供的薄膜晶体管中，金属层还包括第三部分，第三部分与第一部分及第二部分彼此绝缘，第三部分位于有源层在金属层上的正投影内。
如图6所示，例如，在本公开至少一个实施例提供的薄膜晶体管中，第三部分被配置为薄膜晶体管的栅极，因而在有源层之上(也即在有源层远离衬底基板一侧)无需再形成栅极，由此可以形成底栅型薄膜晶体管，亦或者可以形成有第二栅极由此得到双栅型晶体管。
如图2所示，例如，本公开至少一个实施例提供的薄膜晶体管还包括栅极绝缘层、栅极和第二绝缘层。栅极绝缘层位于有源层远离金属层的一侧，栅极位于栅极绝缘层远离有源层的一侧，第二绝缘层位于栅极远离栅极绝缘层的一侧。
本公开至少一个实施例还提供一种电子装置基板，该电子装置基板包括本公开任一实施例所述的薄膜晶体管，例如可以包括图2所示的薄膜晶体管100或图6所示的薄膜晶体管200。
下面以包括图2所示的薄膜晶体管100的电子装置基板为例，对本公开一些实施例提供的电子装置基板进行说明。
图8为本公开一些实施例提供的一种电子装置基板的部分平面示意图。例如，图2可以理解为图8所示的电子装置基板30沿A-A’线的一些示例的剖面图，也即，图2为图8中沿A-A’线的截面结构示意图。需要说明的是，为表示清楚、简洁，图8中省去了绝缘层(例如第一绝缘层130、栅极绝缘层151、第二绝缘层153等)、金属层120等结构。
需要说明的是，本公开的实施例以电子装置基板30包括图2所示的薄膜晶体管100为例进行说明，本公开的实施例包括但并不仅限于此。例如，图8所示的电子装置基板30沿A-A’线的一些示例的剖面图也可以如图6所示。
结合图2和图8所示，在电子装置基板30中，源极161通过设置在第二绝缘层153内的第一过孔171与有源层140的源极区141电连接，漏极162通过设置在第二绝缘层153内的第二过孔172与有源层140的漏极区142电连接。
例如，电子装置基板30还包括设置在衬底基板110上的像素电极310，像素电极310与漏极162彼此电连接。例如，第二绝缘层153的表面可以设置有凹槽(未示出)，像素电极310形成在该凹槽中。
例如，电子装置基板30还包括设置在衬底基板110上的公共电极320，公共电极320被第二绝缘层153覆盖。
例如，像素电极310和公共电极320可以为板状电极，也可以为狭缝电极。例如，像素电极310和公共电极320可以分别包括多个分支电极，即二者均具有梳状结构，且像素电极310的分支电极和公共电极320的分支电极例如彼此重叠或彼此交错布置。如图8所示，像素电极310为狭缝电极，包括多个例如彼此平行的分支电极，分支电极由狭缝间隔开；公共电极320为板状电极。例如，在本实施例中，像素电极310形成在公共电极320之上，该电子装置基板30例如可以用于高级超维场转换技术(Advanced Super Dimension Switch，简称ADS)型液晶面板。
如图8所示，电极装置基板30还包括栅线330，例如，栅线330可以和栅极152一体设置且被第二绝缘层153所覆盖。
例如，电极装置基板30还包括数据线340，数据线340在纵向上延伸，而栅线330在水平方向上延伸，数据线340与栅线330彼此绝缘交叉，薄膜晶体管100例如形成在数据线340与栅线330交叉的位置处。
例如，数据线340的材料可以包括铜基金属、铝基金属、镍基金属等。例如，该铜基金属可以为铜(Cu)，或者也可以为铜锌合金(CuZn)、铜镍合金(CuNi)或铜锌镍合金(CuZnNi)等性能稳定的铜基金属合金。
例如，数据线340可以设置在第二绝缘层153上，从而源极161可以与数据线340彼此电连接，例如可以形成为一体。或者，数据线340可以设置在衬底基板110上且被第二绝缘层153覆盖(保证数据线340与栅线330彼此绝缘设置即可，例如在数据线340与栅线330彼此交叉的位置处设置绝缘层且例如数据线340被栅线330隔开的各个线段通过桥接电极彼此电连接)，从而在第二绝缘层153上还可以包括一过孔(未示出)，源极161通过该过孔与数据线340电连接。
例如，当栅线330上被施加开启信号时，源极161与漏极162通过有源层140电连接，薄膜晶体管100导通，从而使得像素电极310与数据线340电连接，数据线340上施加的信号可以被传递至像素电极310；当栅线330上被施加关闭信号时，薄膜晶体管100截止，从而使得像素电极310与数据线340断开电连接。
需要说明的是，图8中仅示出了一个像素区域，但是本领域的普通技术人员可以知道，该电子装置基板30包括多个这样的像素区域，该多个像素区域排列为阵列以构成显示区域。
需要说明的是，图8所示的电子装置基板30例如可以应用于液晶面板中，而在本公开的其他一些实施例中，电子装置基板还可以包括其他的结构，并且可以应用于例如OLED面板、QLED面板等其他类型的显示面板中，本公开的实施例对此不作限制。
电子装置基板30的技术效果以及实现原理与本公开实施例所述的薄膜晶体管(例如薄膜晶体管100或薄膜晶体管200)基本相同，在此不再赘述。
本公开至少一个实施例还提供一种电子装置，该电子装置包括本公开任一实施例所述的电子装置基板。
例如，本公开实施例提供的电子装置可以包括图8中所示的电子装置基板30。下面以一种包括图8所示的电子装置基板30的具有感光功能的电子装置为例，对本公开一些实施例提供的电子装置进行说明。
图9为本公开一些实施例提供的一种电子装置的部分电路结构示意图。如图9所示，电子装置40包括多个图8中所示的像素区域(例如像素单元)。 例如，每个像素单元包括光电二极管410和薄膜晶体管100。
例如，结合图8和图9所示，每个像素单元的薄膜晶体管100和与其相邻的一条栅线330电连接，每个像素单元的光电二极管410经由该像素单元内的薄膜晶体管100和与其相邻的一条数据线340(或读取线)电连接。在多个像素单元组成的矩阵中，每一行像素单元中的各个薄膜晶体管100的栅极152和与其相邻的一条栅线330电连接，每一列像素单元中的各个薄膜晶体管100的源极161和与其相邻的一条数据线340电连接，每个像素单元的薄膜晶体管100的漏极162与该像素单元的光电二极管410的负极电连接，而该像素单元的光电二极管410的正极可以和例如偏压线420电连接。例如，偏压线420与栅线330平行，且每一行像素单元共用同一条偏压线420。例如，各条栅线330与栅极驱动电路电连接，各条数据线340与数据驱动电路电连接。
例如，以图9所示的具有感光功能的电子装置40为例，在光电二极管410直接或间接地感应例如光电信号时，电子装置40通过栅线330对每个像素单元施加扫描信号以控制薄膜晶体管100的开关状态，从而达到间接控制数据驱动电路通过数据线340对每个光电二极管410产生的光电信号的读取功能，进而使电子装置40实现感光功能。例如，当薄膜晶体管100被打开时，与薄膜晶体管100对应的光电二极管410产生的光电信号可以被连接到薄膜晶体管100的源极161的数据线340所采集，进而实现对光电二极管410光电信号的采集。
例如，电子装置40还可以为具有其他功能的电子装置，相应地，电子装置40的每个像素单元内可以包括其他对应的功能部件等，本公开的实施例对此不作限制。
电子装置40的技术效果以及实现原理与本公开实施例所述的电子装置基板(例如电子装置基板30)或薄膜晶体管(例如薄膜晶体管100或薄膜晶体管200)基本相同，在此不再赘述。
例如，电子装置40可以为液晶面板、电子纸、OLED面板、QLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他 结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，则该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (19)

  1. 一种薄膜晶体管的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上形成金属层，其中，所述金属层包括彼此绝缘的第一部分和第二部分；
    在所述金属层上形成有源层，其中，所述有源层包括源极区和漏极区，所述金属层的所述第一部分接触所述源极区，所述金属层的所述第二部分接触所述漏极区；以及
    通过所述金属层对所述有源层导体化处理，以使所述源极区和所述漏极区被导体化。
  2. 根据权利要求1所述的薄膜晶体管的制备方法，其中，在所述金属层上形成所述有源层，包括：
    在所述金属层上形成第一绝缘层，使所述第一绝缘层覆盖所述金属层且暴露所述第一部分和所述第二部分；以及
    在所述第一绝缘层上形成所述有源层，使得所述金属层的所述第一部分接触所述有源层的源极区，所述金属层的所述第二部分接触所述有源层的漏极区。
  3. 根据权利要求1或2所述的薄膜晶体管的制备方法，其中，通过所述金属层对所述有源层导体化处理，包括：
    对所述金属层和所述有源层退火处理，以使所述源极区和所述漏极区被导体化。
  4. 根据权利要求3所述的薄膜晶体管的制备方法，其中，所述退火处理的温度为100℃-400℃，所述退火处理的时间为10min-500min。
  5. 根据权利要求1-4任一所述的薄膜晶体管的制备方法，其中，所述金属层的材料包括选自由铝、铜、钛、钼金属或合金构成的组中任一。
  6. 根据权利要求1-5任一所述的薄膜晶体管的制备方法，还包括：形成源极和漏极，
    其中，所源极与所述有源层的所述源极区电连接，所述漏极与所述有源层的所述漏极区电连接。
  7. 根据权利要求1-6任一所述的薄膜晶体管的制备方法，其中，所述 金属层还包括第三部分，
    所述第三部分与所述第一部分及所述第二部分彼此绝缘，所述第三部分在所述衬底基板上的正投影位于所述有源层在所述衬底基板上的正投影内。
  8. 根据权利要求7所述的薄膜晶体管的制备方法，其中，所述第三部分被配置为所述薄膜晶体管的栅极。
  9. 根据权利要求1-8任一所述的薄膜晶体管的制备方法，其中，在通过所述金属层对所述有源层导体化处理之后，相对于所述衬底基板，所述制备方法还包括：
    在所述有源层上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极；以及
    在所述栅极上形成第二绝缘层。
  10. 根据权利要求1-8任一所述的薄膜晶体管的制备方法，其中，在通过所述金属层对所述有源层导体化处理之前，相对于所述衬底基板，所述制备方法还包括：
    在所述有源层上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极；以及
    在所述栅极上形成第二绝缘层。
  11. 根据权利要求1-8任一所述的薄膜晶体管的制备方法，其中，在通过所述金属层对所述有源层导体化处理之前，相对于所述衬底基板，所述制备方法还包括：
    在所述有源层上形成栅极绝缘层；
    在通过所述金属层对所述有源层导体化处理之后，相对于所述衬底基板，所述制备方法还包括：
    在所述栅极绝缘层上形成栅极，以及
    在所述栅极上形成第二绝缘层。
  12. 一种薄膜晶体管，包括：金属层、有源层、源极和漏极，
    其中，所述金属层为不透明金属层，所述有源层位于所述金属层上，
    所述金属层包括彼此绝缘的第一部分和第二部分，所述第一部分接触所述有源层的源极区，所述第二部分接触所述有源层的漏极区，
    所述源极区和所述漏极区相对于所述有源层的沟道区被导体化，所述源极与所述有源层的所述源极区电连接，所述漏极与所述有源层的所述漏极区 电连接。
  13. 根据权利要求12所述的薄膜晶体管，其中，所述金属层的材料包括选自由铝、铜、钛、钼金属或合金构成的组中任一。
  14. 根据权利要求12或13所述的薄膜晶体管，还包括第一绝缘层，
    其中，所述第一绝缘层设置在所述金属层和所述有源层之间，所述第一绝缘层覆盖所述金属层除所述第一部分和所述第二部分外的其他部分，且暴露所述第一部分和所述第二部分，以使得所述第一部分接触所述有源层的源极区，所述第二部分接触所述有源层的漏极区。
  15. 根据权利要求12-14任一所述的薄膜晶体管，其中，所述金属层还包括第三部分，
    所述第三部分与所述第一部分及所述第二部分彼此绝缘，
    所述第三部分位于所述有源层在所述金属层上的正投影内。
  16. 根据权利要求15所述的薄膜晶体管，其中，所述第三部分被配置为所述薄膜晶体管的栅极。
  17. 根据权利要求12-16任一所述的薄膜晶体管，还包括栅极绝缘层、栅极和第二绝缘层，
    其中，所述栅极绝缘层位于所述有源层远离所述金属层的一侧，
    所述栅极位于所述栅极绝缘层远离所述有源层的一侧，
    所述第二绝缘层位于所述栅极远离所述栅极绝缘层的一侧。
  18. 一种电子装置基板，包括如权利要求12-17任一所述的薄膜晶体管。
  19. 一种电子装置，包括如权利要求18所述的电子装置基板。
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CN106876481A (zh) * 2017-05-04 2017-06-20 京东方科技集团股份有限公司 一种氧化物薄膜晶体管及其制造方法、阵列基板、显示装置
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CN110137084A (zh) * 2019-05-30 2019-08-16 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、电子装置基板及电子装置

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CN113745342B (zh) * 2021-08-23 2023-09-26 深圳市华星光电半导体显示技术有限公司 薄膜晶体管、其制作方法及显示面板
GB2612901A (en) * 2021-10-21 2023-05-17 Lg Display Co Ltd Thin film transistor substrate and display device comprising the same
GB2612901B (en) * 2021-10-21 2024-09-11 Lg Display Co Ltd Thin film transistor substrate and display device comprising the same

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