WO2020235676A1 - Silicon carbide semiconductor device and manufacturing method therefor - Google Patents
Silicon carbide semiconductor device and manufacturing method therefor Download PDFInfo
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- WO2020235676A1 WO2020235676A1 PCT/JP2020/020300 JP2020020300W WO2020235676A1 WO 2020235676 A1 WO2020235676 A1 WO 2020235676A1 JP 2020020300 W JP2020020300 W JP 2020020300W WO 2020235676 A1 WO2020235676 A1 WO 2020235676A1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 70
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 70
- 239000004065 semiconductor Substances 0.000 title claims description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims description 198
- 238000005468 ion implantation Methods 0.000 claims description 54
- 239000012535 impurity Substances 0.000 claims description 38
- 239000011229 interlayer Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 79
- 239000010409 thin film Substances 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 description 21
- 230000005684 electric field Effects 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000002344 surface layer Substances 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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Definitions
- the present disclosure relates to a SiC semiconductor device having a vertical semiconductor element having a trench gate structure composed of silicon carbide (hereinafter referred to as SiC) and a method for manufacturing the same.
- SiC silicon carbide
- a SiC semiconductor device having a trench gate structure.
- a p-type base region and an n + -type source region are sequentially formed on the n-type drift layer, and the n-type drift layer is formed by penetrating the p-type base region from the surface of the n + -type source region.
- a trench gate structure is formed to reach.
- an n-type impurity is implanted back into the p-type base region by ion implantation to make a part of the p-type base region n-type. It is inverted to form an n + type source region (see, for example, Patent Document 1).
- the film thickness variation during epitaxial growth increases as the film thickness to be grown increases, but the ion implantation range variation is not so large. Therefore, the film thickness variation of the p-type base region after ion implantation is the variation corresponding to the epitaxially grown film thickness.
- the threshold value Vt varies.
- the present inventors have studied the formation of not only the p-type base region but also the n + -type source region by epitaxial growth. By doing so, since the variation in thickness is distributed to each of the p-type base region and the n + -type source region, it is possible to reduce the variation in thickness of the p-type base region and suppress the variation in the threshold value Vt. it can. Further, when the n + type source region is formed by epitaxial growth, the side surface of the trench gate structure can be cut off substantially perpendicular to the surface of the n + type source region.
- the gate insulating film becomes thin at the corner on the trench inlet side, and when a large electric field is applied, the gate insulating film is destroyed at the thinned portion, and the gate life may be shortened. It was confirmed that there was.
- an object of the present disclosure is to provide a SiC semiconductor device having a structure capable of suppressing variation in threshold value Vt and suppressing a decrease in gate life, and a method for manufacturing the same.
- the SiC semiconductor device is formed on a substrate made of first or second conductive type silicon carbide having a main surface and on the main surface side of the substrate, and has a lower impurity concentration than the substrate.
- the first conductive type source region which has a higher impurity concentration than the drift layer and is composed of an epitaxial layer of silicon carbide at least in contact with the base region, and the surface of the source region deeper than the base region in one direction.
- the side surface of the gate trench is relative to the normal direction with respect to the main surface of the substrate as compared with the portion composed of the epitaxial layer in contact with the base region of the source region in the cell portion. Is tilted.
- the portion of the source region in contact with the base region is composed of the epitaxial growth layer, it is possible to reduce the variation in the thickness of the base region and suppress the variation in the threshold value Vt.
- the outside of the cell portion is compared with the portion composed of the epitaxial layer in contact with the base region of the source region in the cell portion in the normal direction with respect to the main surface of the substrate. It is tilted. Therefore, even if the gate insulating film is a thin thin film portion inside the cell portion, it can be formed as a thick thick film portion outside the cell portion. Therefore, it is possible to suppress the destruction of the gate insulating film due to the application of a large electric field at both ends of the trench gate structure in the longitudinal direction, and it is possible to suppress a decrease in the life of the gate insulating film.
- a method for manufacturing a SiC semiconductor device is to prepare a substrate made of first or second conductive type silicon carbide having a main surface, and to prepare a substrate on the substrate. Forming a drift layer composed of first conductive type silicon carbide having a lower impurity concentration, forming a base region made of second conductive type silicon carbide on the drift layer, and forming a base region. On top of this, a source region composed of first conductive type silicon carbide having a higher concentration of first conductive type impurities than the drift layer is formed by epitaxial growth, and the surface of the source region is deeper than the base region.
- a gate insulating film is formed on the inner wall surface of the gate trench and the gate insulating film is formed.
- a trench gate structure is formed by forming a gate electrode on the surface, an interlayer insulating film having a contact hole connected to the source region is formed on the source region and the trench gate structure, and the contact hole is formed in the source region. It includes forming a first electrode that is electrically connected and forming a second electrode on the back surface side of the substrate.
- the side surface of the gate trench is compared with the portion composed of the epitaxial layer which is in contact with the base region of the source region in the cell portion on the outside of the cell portion. Tilt with respect to the normal direction to the main surface.
- the source region on the base region by epitaxial growth in this way, it is possible to reduce the variation in the thickness of the base region and suppress the variation in the threshold value Vt.
- the side surface of the gate trench is compared with the portion composed of the epitaxial layer which is in contact with the base region of the source region in the cell portion on the outside of the cell portion. It is tilted with respect to the normal direction with respect to the main surface. Therefore, even if the gate insulating film is a thin thin film portion inside the cell portion, it can be formed as a thick thick film portion outside the cell portion. Therefore, it is possible to suppress the destruction of the gate insulating film due to the application of a large electric field at both ends of the trench gate structure in the longitudinal direction, and it is possible to suppress a decrease in the life of the gate insulating film.
- FIG. 2 is a sectional view taken along line II-II of FIG.
- FIG. 3 is a cross-sectional perspective view showing the cross section of FIG. 1 III-III with the upper part omitted from the interlayer insulating film.
- FIG. 6 is a sectional view taken along line IV-IV of FIG. It is a VV cross-sectional view of FIG. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which concerns on 1st Embodiment. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which follows FIG. 6A. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which follows FIG. 6B.
- the SiC semiconductor device shown in FIG. 1 has a configuration in which a cell portion in which a MOSFET having a trench gate structure is formed and an outer peripheral portion RO surrounding the cell portion RC are provided.
- the outer peripheral portion RO has a configuration having a guard ring portion RG and a connecting portion RJ arranged inside the guard ring portion RG, that is, between the cell portion RC and the guard ring portion RG.
- FIG. 1 is not a cross-sectional view, hatching is partially shown to make the figure easier to see.
- the SiC semiconductor device is formed by using an n + type substrate 1 made of SiC. made of SiC on the main surface of the n + -type substrate 1 n - -type impurity layer 2 and the n-type current spreading layer 2a and the p-type base region 3, and, n + -type source region 4 is then epitaxially grown in order.
- the n + type substrate 1 has, for example, an n-type impurity concentration of 1.0 ⁇ 10 19 / cm 3 and a surface of (0001) Si surface.
- the n - type impurity layer 2 has, for example, an n-type impurity concentration of 0.5 to 2.0 ⁇ 10 16 / cm 3 .
- the n-type current dispersion layer 2a has a higher n-type impurity concentration, that is, a lower resistance than the n - type impurity layer 2, and has a role of reducing the JFET resistance by distributing and flowing a current over a wider range. Fulfill.
- the n-type current dispersion layer 2a has a thickness of, for example, 8 ⁇ 10 16 / cm 3 and a thickness of 0.5 ⁇ m.
- the n - type impurity layer 2 and the n-type current dispersion layer 2a are described as different layers, but all of them form a drift layer.
- the p-type base region 3 is a portion where a channel region is formed, and the p-type impurity concentration is, for example, about 2.0 ⁇ 10 17 / cm 3 , and the thickness is 300 nm.
- the n + type source region 4 has a higher impurity concentration than the n ⁇ type impurity layer 2, and the n-type impurity concentration in the surface layer portion is, for example, 2.5 ⁇ 10 18 to 1.0 ⁇ 10 19 / cm 3 , and the thickness. It is composed of about 0.5 ⁇ m.
- the p-type base region 3 and the n + -type source region 4 are left on the surface side of the n + -type substrate 1, and in the connecting portion RJ, the n + -type source region 4 is the ion implantation layer 31 described later. Has been changed to. Further, in the guard ring portion RG, a recess 20 is formed so as to penetrate the n + type source region 4 or the ion implantation layer 31 and the p type base region 3 and reach the n type current dispersion layer 2a.
- the p-type deep layer 5 is formed so as to penetrate the n + type source region 4 and the p-type base region 3 and reach the n-type current dispersion layer 2a.
- the p-type deep layer 5 has a higher p-type impurity concentration than the p-type base region 3.
- the p-type deep layer 5 is provided in a striped trench 5a in which a plurality of p-type deep layers 5 are arranged at equal intervals in the n-type current dispersion layer 2a and are arranged apart from each other without intersections, and the p-type deep layer 5 is provided by epitaxial growth. It is composed of an epitaxial film of.
- the trench 5a has, for example, a width of 1 ⁇ m or less and an aspect ratio of 2 or more.
- each p-type deep layer 5 has a p-type impurity concentration of, for example, 1.0 ⁇ 10 17 to 1.0 ⁇ 10 19 cm 3 , a width of 0.7 ⁇ m, and a depth of about 2.0 ⁇ m.
- the deepest bottom of each p-type deep layer 5 is located at the same position as the boundary position between the n-type current dispersion layer 2a and the n - type impurity layer 2, or is located closer to the p-type base region 3 than that. .. That is, the p-type deep layer 5 and the n-type current dispersion layer 2a are formed to the same depth, or the n-type current dispersion layer 2a is formed to a position deeper than the p-type deep layer 5.
- the p-type deep layer 5 is formed from one end to the other end of the cell portion RC.
- the p-type deep layer 5 is extended with the same direction as the trench gate structure described later as the longitudinal direction, and is further extended from both ends of the trench gate structure to the outside of the cell portion RC with the p-type connecting layer 30 described later. linked.
- a gate trench 6 having a width of 0.8 ⁇ m and a depth of 1.0 ⁇ m is formed so as to penetrate the p-type base region 3 and the n + -type source region 4 and reach the n - type impurity layer 2. There is.
- the gate trench 6 is formed not only in the cell portion RC but also protruding from the cell portion RC to the connecting portion RJ.
- the above-mentioned p-type base region 3, n + -type source region 4, and ion implantation layer 31 are arranged so as to be in contact with the side surface of the gate trench 6.
- the side surface on the inlet side of the gate trench 6 is composed of the n + type source region 4, and in the connecting portion RJ, the side surface on the inlet side of the gate trench 6 is composed of the ion implantation layer 31.
- the gate trench 6 is formed in a layout having a linear portion having a width direction in the left-right direction of the paper surface, a longitudinal direction in the vertical direction of the paper surface, and a depth direction in the vertical direction of the paper surface in FIG. Further, as shown in FIG. 1, the gate trench 6 is composed of only a linear portion in the cell portion RC, but in the present embodiment, the gate trench 6 is also composed of only a linear portion in the connecting portion RJ.
- a plurality of gate trenches 6 are provided, and each of them is arranged so as to be sandwiched between the p-type deep layers 5 and is arranged in parallel at equal intervals to form a stripe shape.
- the shape of the side surface of the gate trench 6 is different between the inside of the cell portion RC and the inside of the connecting portion RJ.
- the side surface of the gate trench 6 is perpendicular to the main surface of the n + type substrate 1 in the cell portion RC, and the trench inlet side is wider than the bottom side in the connecting portion RJ. Therefore, the n + type substrate 1 is inclined with respect to the normal direction with respect to the main surface.
- the tip of the gate trench 6 has a trench inlet side inclined with respect to the normal direction with respect to the main surface of the n + type substrate 1, similar to the shape of the side surface of the connecting portion RJ.
- the inclined portion of the side surface and the tip portion of the gate trench 6 is referred to as an inclined portion.
- the portion of the p-type base region 3 located on the side surface of the gate trench 6 is used as a channel region connecting the n + type source region 4 and the n - type impurity layer 2 when the vertical MOSFET is operated.
- a gate insulating film 7 is formed on the inner wall surface of the gate trench 6 including the above.
- the gate insulating film 7 is composed of a thermal oxide film.
- a gate electrode 8 made of doped Poly—Si is formed on the surface of the gate insulating film 7, and the gate trench 6 is filled with the gate insulating film 7 and the gate electrode 8. As a result, a trench gate structure is constructed.
- the gate insulating film 7 is formed on the entire inner wall surface of the gate trench 6, but the thickness varies depending on the location. Specifically, the portion of the gate trench 6 located in the cell portion RC, that is, the n + type source region 4 is formed on the side surface, and the side surface is perpendicular to the main surface of the n + type substrate 1. In the portion where the gate insulating film 7 is formed, the gate insulating film 7 is thinned at the corner of the trench entrance.
- the gate insulating film 7 thinned in this portion is referred to as a thin film portion 7a.
- the gate insulating film 7 is thicker than that of the portion 7a.
- the gate insulating film 7 in this portion is referred to as a thick film portion 7b.
- a source electrode 9 corresponding to the first electrode is formed on the surface of the n + type source region 4 and the p-type deep layer 5 and on the gate electrode 8 via the interlayer insulating film 10.
- the source electrode 9 is made of a plurality of metals such as Ni / Al.
- the portion of the plurality of metals that contacts at least n-type SiC, specifically the n + -type source region 4, is composed of a metal that can make ohmic contact with n-type SiC.
- at least the portion that contacts the p-type SiC, specifically, the p-type deep layer 5 is composed of a metal that can make ohmic contact with the p-type SiC.
- the source electrodes 9 are electrically insulated by being formed on the interlayer insulating film 10. Then, the source electrode 9 is electrically brought into contact with the n + type source region 4 and the p-type deep layer 5 through the contact hole formed in the interlayer insulating film 10.
- the drain electrode 11 corresponding to the second electrode electrically connected to the n + -type substrate 1 is formed on the back side of the n + -type substrate 1 .
- a MOSFET having an n-channel type inverted trench gate structure is configured on the back side of the n + -type substrate 1 .
- the cell portion RC is configured by arranging a plurality of such MOSFETs.
- the recess 20 is formed so as to penetrate the ion implantation layer 31 and the p-type base region 3 described later and reach the n-type current dispersion layer 2a. Therefore, the ion implantation layer 31 and the p-type base region 3 are removed at a position away from the cell portion RC, and the n-type current dispersion layer 2a is exposed. Then, in the thickness direction of the n + type substrate 1, the cell portion RC and the connecting portion RJ located inside the recess 20 form an island-shaped protruding mesa portion RM.
- the corner portion of the mesa portion RM is inclined.
- a gate insulating film 7 is also formed in the recess 20, and an interlayer insulating film 10 is formed on the gate insulating film 7.
- the gate electrode 8 is located at the boundary between the recess 20 and the mesa portion RM. Residue 8a of Poly-Si used for the formation of the above may remain.
- a plurality of p-type guard rings 21 are provided on the surface layer portion of the n-type current dispersion layer 2a located below the recess 20 so as to surround the cell portion RC.
- the p-shaped guard ring 21 has a quadrangular shape with four corners rounded, but may be formed in another frame shape such as a circular shape.
- the p-type guard ring 21 is arranged in the trench 21a formed in the n-type current dispersion layer 2a, and is composed of a p-type epitaxial film formed by epitaxial growth.
- the trench 21a has, for example, a width of 1 ⁇ m or less and an aspect ratio of 2 or more.
- Each part constituting the p-type guard ring 21 has the same configuration as the p-type deep layer 5 described above.
- the p-type guard ring 21 is different from the linearly formed p-type deep layer 5 in that the upper surface shape is a frame-shaped line shape surrounding the cell portion RC and the connecting portion RJ, but other than that. The same is true. That is, the p-type guard ring 21 has the same width and the same thickness as the p-type deep layer 5, that is, the same depth.
- the intervals of the p-type guard rings 21 may be equal, but the p-type guards are arranged so that the electric field concentration is relaxed on the inner peripheral side, that is, the cell portion RC side, and the equipotential lines are directed toward the outer peripheral side.
- the distance between the rings 21 is narrower on the RC side of the cell portion and is increased toward the outer peripheral side.
- guard ring portion RG having an outer peripheral pressure resistant structure surrounding the cell portion RC is configured by providing an EQR structure on the outer periphery of the p-type guard ring 21 as needed. ..
- a plurality of p-type connecting layers 30 are formed on the surface layer portion of the n - type impurity layer 2 in the connecting portion RJ as the connecting portion RJ from the cell portion RC to the guard ring portion RG.
- the connecting portion RJ is formed on the outer periphery of the cell portion RC so as to surround the cell portion RC, and further surrounds the outside of the connecting portion RJ.
- a plurality of quadrangular p-shaped guard rings 21 having rounded four corners are formed.
- a plurality of p-type connecting layers 30 are arranged side by side in parallel with the p-type deep layers 5 formed in the cell portion RC, and in the present embodiment, the intervals between the adjacent p-type deep layers 5 are equal to each other. Is located in. Further, in a place where the distance from the cell portion RC to the p-type guard ring 21 is large, the p-type connecting layer 30 extends from the p-type deep layer 5, and the p-type guard is extended from the tip of the p-type connecting layer 30. The distance to the ring 21 is shortened.
- Each p-type connecting layer 30 is arranged in a trench 30a that penetrates the n + type source region 4 and the p-type base region 3 and reaches the n - type impurity layer 2, and is composed of a p-type epitaxial film by epitaxial growth. There is.
- a p-type connecting layer 30 is formed by being connected to the tip of the p-type deep layer 5 between the cell portion RC and the guard ring portion RG in the longitudinal direction of the p-type deep layer 5.
- the trench 30a has, for example, a width of 1 ⁇ m or less and an aspect ratio of 2 or more. Since the p-type connecting layer 30 is in contact with the p-type base region 3, it is fixed at the source potential.
- Each part constituting the p-type connecting layer 30 has the same structure as the p-type deep layer 5 and the p-type guard ring 21 described above, and the upper surface shape of the p-type connecting layer 30 is linear. , It is different from the p-shaped guard ring 21 formed in the frame shape, but the others are the same. That is, the p-type connecting layer 30 has the same width and the same thickness as the p-type deep layer 5 and the p-type guard ring 21, that is, the same depth. Further, the spacing between the p-type connecting layers 30 is equal to the spacing between the p-type deep layers 5 in the cell portion RC in the present embodiment, but may be different.
- the p-type connecting layer 30 By forming such a p-type connecting layer 30 and setting the distance between the p-type connecting layers 30 at a predetermined interval, for example, equal to or less than the p-type deep layer 5, the p-type connecting layer 30 It is possible to prevent the equipotential lines from rising excessively between them. As a result, it is possible to suppress the formation of a portion where electric field concentration occurs between the p-type connecting layers 30, and it is possible to suppress a decrease in withstand voltage.
- the ion implantation layer 31 is formed by implanting ions into the portion defined as the n + type source region 4 in the cell portion RC.
- the entire upper part of the p-type base region 3 is the ion implantation layer 31.
- the conductive type of the portion of the ion-implanted layer 31 located on the side surface of the gate trench 6 is arbitrary, but here, it is conductive by ion-implanting a p-type impurity into the epitaxially grown n + type source region 4. The mold is inverted to form a p-type.
- the gate liner 8b is pulled out from the gate electrode 8 at the tip of the trench gate structure extending to the connecting portion RJ.
- An interlayer insulating film 10 is also formed on the surfaces of the gate liner 8b and the ion implantation layer 31, and the gate pad shown in FIG. 1 is placed on the interlayer insulating film 10 at a position away from the cell portion RC in the connecting portion RJ. 32 and a drawing pad 33 for pulling out a hole are formed.
- the gate pad 32 is electrically connected to the gate liner 8b through a contact hole (not shown) formed in the interlayer insulating film 10.
- the drawing pad 33 is also electrically connected to the p-type connecting layer 30 and the ion implantation layer 31 through a contact hole (not shown) formed in the interlayer insulating film 10.
- the connecting portion RJ inclined portions are formed on the side surface and the tip portion of the gate trench 6.
- the position of the gate trench 6 corresponding to the ion implantation layer 31 is defined as an inclined portion, and the inclined portion extends to the depth of the boundary position between the ion implantation layer 31 and the p-type base region 3. ..
- the ion implantation layer 31 is formed in the entire area inside the connecting portion RJ, but at least outside the cell portion RC, the ion implantation layer is formed on the side surface and the tip portion of the gate trench 6. It suffices if 31 is formed. In this way, it is possible to form a state in which all the inclined portions are formed on the side surface and the tip portion of the gate trench 6 at positions overlapping with the gate liner 8b.
- the ion implantation layer 31 is provided on the entire circumference of the outer edge portion of the connecting portion RJ, as shown in FIG. 2, the boundary position with the outer edge portion of the mesa portion RM, that is, the recess 20 is above. It is composed of the ion implantation layer 31, the p-type base region 3, and the n-type current dispersion layer 2a in this order. Therefore, the ion implantation layer 31 is composed of the n + type source region 4, the p-type base region 3, and the n-type current dispersion layer 2a in this order from the top, as in the case where the n + type source region 4 is left as it is. The npn structure can be prevented.
- the SiC semiconductor device is configured.
- the SiC semiconductor device configured in this way forms a channel region on the surface portion of the p-type base region 3 located on the side surface of the gate trench 6 by controlling the voltage applied to the gate electrode 8. To do.
- a current is passed between the source electrode 9 and the drain electrode 11 via the n + type source region 4 and the n ⁇ type impurity layer 2.
- the p-type deep layer 5 formed to a position deeper than the trench gate structure suppresses the entry of the electric field into the bottom of the gate trench, and the bottom of the gate trench Electric field concentration is relaxed. As a result, the gate insulating film 7 is prevented from being destroyed.
- the rising of the equipotential lines is suppressed, and the joint portion RJ is directed toward the guard ring portion RG side.
- the equipotential lines can be terminated by the p-type guard ring 21 so that the intervals thereof spread toward the outer peripheral direction, and the guard ring portion RG can also obtain a desired withstand voltage. ..
- the side surface on the inlet side of the gate trench 6 constituting the trench gate structure stands out perpendicularly to the main surface of the n + type substrate 1 in the cell portion RC. , It is an inclined part in the connecting part RJ.
- the gate insulating film 7 is a thin thin film portion 7a in the cell portion RC, it can be formed into a thick thick film portion 7b in the connecting portion RJ. Therefore, it is possible to prevent the gate insulating film 7 from being destroyed by applying a large electric field at both ends of the trench gate structure in the longitudinal direction, and it is possible to suppress a decrease in the life of the gate insulating film 7.
- the withstand capacity of the SiC semiconductor device is lowered. If the connecting portion RJ is not provided with the ion implantation layer 31, and the uppermost portion of the semiconductor has a structure in which the n + type source region 4 is formed as in the cell portion RC, p. Since the structure is such that a PN junction is formed with the mold base region 3, the hole cannot be pulled out.
- the uppermost portion of the semiconductor is an ion implantation layer 31 composed of a p-type layer. Therefore, by electrically connecting the extraction pad 33 formed on the interlayer insulating film 10 and the ion implantation layer 31, the ion implantation layer 31 is removed from the p-type base region 3 and the hole is extracted through the extraction pad 33. It becomes possible. Therefore, when the avalanche breakdown of the vertical MOSFET is performed, the holes are satisfactorily pulled out from the outer periphery of the cell portion RC, and it is possible to suppress a decrease in the withstand capacity of the SiC semiconductor device.
- the boundary position between the mesa portion RM and the recess 20 is configured by the ion implantation layer 31, the p-type base region 3, and the n-type current dispersion layer 2a in this order from the top.
- the ion implantation layer 31 is composed of the n + type source region 4, the p-type base region 3, and the n-type current dispersion layer 2a in this order from the top, as in the case where the n + type source region 4 is left as it is. It is designed so that it does not have an npn structure.
- the gate insulating film 7 and the gate electrode 8 are formed after the recess 20 and the gate trench 6 are formed, a similar trench gate structure is formed not only in the gate trench 6 but also in the recess 20. Will be done. Therefore, Poly—Si, which is the material of the gate electrode 8 remaining in the recess 20, is later removed. However, as shown in FIG. 2, the Poly—Si residue 8a may remain at the boundary position between the recess 20 and the mesa portion RM.
- the boundary portion between the mesa portion RM and the recess 20 has an npn structure
- the residue 8a having a floating potential rises in potential due to an external charge or the like, and is p-type.
- An inverted channel is formed in the base region 3. Therefore, there may be a problem that a leak current flows through a source electrode 9 or the like electrically connected to the n + type source region 4.
- the ion implantation layer 31 composed of the p-type layer as in the present embodiment, it is possible to prevent the npn structure from being formed, so that it is possible to suppress the leakage current from flowing even if there is a residue 8a. It becomes.
- n + type substrate 1 is prepared as the semiconductor substrate. Then, an n - type impurity layer 2 made of SiC is epitaxially grown on the main surface of the n + type substrate 1.
- the n-type current dispersion layer 2a, the p-type base region 3 and the n + -type source region 4 are epitaxially grown on the n - type impurity layer 2 in this order. Since the n + type source region 4 is formed by epitaxial growth in this way, the thickness variation of the p-type base region 3 and the n + type source region 4 is distributed to each of the p-type base region 3 and the thickness of the p-type base region 3. The variation of the threshold value can be reduced, and the variation of the threshold value Vt can be suppressed.
- the region to be formed of the ion implantation layer 31 in the mask is opened.
- the ion implantation layer 31 is formed by ion-implanting p-type impurities such as aluminum using the mask.
- the crystal structure of the ion-implanted portion is in a state of being damaged such as being distorted.
- a mask (not shown) is placed on the surface of the n + type source region 4 and the ion implantation layer 31, and the regions to be formed of the p-type deep layer 5, the p-type guard ring 21, and the p-type connecting layer 30 of the mask are formed. Open it. Then, trenches 5a, 21a, and 30a are formed by performing anisotropic etching such as RIE (Reactive IonEtching) using a mask.
- anisotropic etching such as RIE (Reactive IonEtching)
- Step shown in FIG. 6D After removing the mask to form a p-type layer, etching back is performed so that the portion of the p-type layer formed above the surface of the n + type source region 4 is removed, and the p-type deep layer 5 and p. The mold guard ring 21 and the p-type connecting layer 30 are formed.
- the p-type layer is embedded in the trenches 5a, 21a, and 30a due to the embedding epi, but since the trenches 5a, 21a, and 30a are formed with the same width, the surface of the p-type layer is formed. It is possible to suppress the occurrence of shape abnormalities and unevenness. Therefore, the p-type layer can be reliably embedded in each of the trenches 5a, 21a, and 30a, and the surface of the p-type layer has a flat shape with few irregularities.
- the ion implantation layer 31 is formed in the step shown in FIG. 6B. After forming the p-type deep layer 5, the p-type guard ring 21, and the p-type connecting layer 30, ions are formed. The implantation layer 31 may be formed. In this way, it is possible to prevent damage repair from being performed due to the high temperature during epitaxial growth and excessive etching of the ion-implanted layer 31 that is damaged during etching back.
- Step shown in FIG. 6E After forming a mask (not shown) on the n + type source region 4 or the like, the region to be formed of the gate trench 6 in the mask is opened. Then, the gate trench 6 is formed by performing anisotropic etching such as RIE using a mask.
- a mask (not shown) is formed again, and a region to be formed of the recess 20 in the mask is opened. Then, the recess 20 is formed by performing anisotropic etching such as RIE using a mask. As a result, at the position where the recess 20 is formed, the n-type current dispersion layer 2a is exposed through the n + type source region 4 and the p-type base region 3, and a plurality of n-type current dispersion layers 2a are exposed from the surface of the n-type current dispersion layer 2a.
- a structure in which the p-type guard ring 21 is arranged is configured.
- gate trench 6 and the recess 20 are formed as separate steps using separate masks here, they can also be formed at the same time using the same mask.
- the gate insulating film 7 is formed by thermal oxidation, and the gate insulating film 7 covers the inner wall surface of the gate trench 6 and the surface of the n + type source region 4.
- the n + type source region 4 that has not been damaged by ion implantation is thermally oxidized to the same extent as the p-type base region 3, but the damaged ion implantation layer 31 is the p-type base. It is more susceptible to thermal oxidation than region 3.
- the inlet side of the gate trench 6 remains erected substantially perpendicular to the main surface of the n + type substrate 1, and in the connecting portion RJ, the inlet side of the gate trench 6 becomes an inclined portion. Therefore, at the corner portion on the inlet side of the gate trench 6, the gate insulating film 7 becomes a thin thin film portion 7a in the cell portion RC, but becomes a thicker film portion 7b in the connecting portion RJ.
- the inlet side of the gate trench 6 is made to be an inclined portion in the connecting portion RJ by performing thermal oxidation, but the shape can be obtained by performing heat treatment.
- the ion implantation layer 31 in the connecting portion RJ promotes oxidation more than the n + type source region 4 in the cell portion RC, so that the inlet side of the gate trench 6 in the connecting portion RJ is It becomes an inclined part.
- the gate insulating film 7 when the gate insulating film 7 is not formed by thermal oxidation, for example, even if it is formed by CVD (chemical vapor deposition), the gate insulating film 7 becomes a thin thin film portion 7a in the cell portion RC, and it becomes a thin film portion 7a in the connecting portion RJ.
- the thick film portion 7b can be made thicker than that.
- the trench gate structure may be formed only in the gate trench 6, but since the recess 20 is formed to form the mesa portion RM, a similar structure is also formed in the recess 20. .. This portion is removed by etchingback Poly-Si, but a residue 8a may remain at the boundary position between the mesa portion RM and the recess 20.
- An interlayer insulating film 10 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 8 and the gate insulating film 7. Then, after forming a mask (not shown) on the surface of the interlayer insulating film 10, a portion of the mask located between the gate electrodes 8, that is, a portion corresponding to the p-type deep layer 5 and its vicinity are opened. After that, the interlayer insulating film 10 is patterned using a mask to form a contact hole that exposes the p-type deep layer 5 and the n + -type source region 4. Further, a contact hole for partially exposing the gate electrode 8 and the ion implantation layer 31 is also formed in a cross section different from that shown in this figure.
- Step shown in FIG. 6H An electrode material composed of, for example, a laminated structure of a plurality of metals is formed on the surface of the interlayer insulating film 10. Then, the source electrode 9 and the drawing pad 33 are formed by patterning the electrode material. Further, the gate pad 32 is also formed in a cross section different from that shown in this figure. A gate liner 8b connected to the gate electrode 8 of each cell is provided in a cross section different from that shown in this figure. A contact hole is opened in the interlayer insulating film 10 at the position where the gate liner 8b is extended, so that the gate pad 32 and the gate electrode 8 are electrically connected. Similarly, a contact hole connected to the ion implantation layer 31 is formed in a cross section different from that in the drawing, and the extraction pad 33 and the ion implantation layer 31 are electrically connected through the contact hole.
- the SiC semiconductor device according to the present embodiment is completed by performing steps such as forming the drain electrode 11 on the back surface side of the n + type substrate 1.
- the side surface of the gate trench 6 constituting the trench gate structure on the inlet side is steeply formed in the cell portion RC perpendicular to the main surface of the n + type substrate 1. It is an inclined part in the connecting part RJ.
- the gate insulating film 7 is a thin thin film portion 7a in the cell portion RC, it can be formed into a thick thick film portion 7b in the connecting portion RJ. Therefore, it is possible to prevent the gate insulating film 7 from being destroyed by applying a large electric field at both ends of the trench gate structure in the longitudinal direction, and it is possible to suppress a decrease in the life of the gate insulating film 7.
- the SiC semiconductor device having a structure capable of suppressing the variation in the threshold value Vt and suppressing the decrease in the gate life can be obtained.
- the n + type source region 4 is composed of only the epitaxial growth layer, but in order to increase the concentration of n-type impurities on the surface layer portion while the n + type source region 4 is composed of the epitaxial growth layer. It may include an ion-implanted region. Even in this case, since the boundary position between the n + type source region 4 and the p-type base region 3 and their thickness are defined by epitaxial growth, the effect of suppressing the variation of the threshold value Vt can be obtained. Further, in the case of such a structure, the side surface of the gate trench 6 may be inclined in the surface layer portion of the n + type source region 4.
- the side surface of the gate trench 6 is composed of the ion implantation layer 31 rather than the portion composed of the n + type source region 4. The part becomes an inclined part to a deeper position. Then, at the lower position of the n + type source region 4, that is, the portion in contact with the p-type base region 3, the side surface of the gate trench 6 has a structure that stands perpendicular to the main surface of the n + type substrate 1.
- each of the above embodiments is merely an example of a vertical semiconductor element having a trench gate structure, and a current is applied between the first electrode provided on the front surface side and the second electrode provided on the back surface side of the semiconductor substrate.
- it may have another structure or a conductive type.
- an n-channel type MOSFET in which the first conductive type is n-type and the second conductive type is p-type has been described as an example, but the conductive type of each component is inverted. It may be a p-channel type MOSFET.
- MOSFET is taken as an example as a semiconductor element, but the present disclosure can be applied to an IGBT having a similar structure. The IGBT only changes the conductive type of the n + type substrate 1 from the n type to the p type for each of the above embodiments, and is the same as each of the above embodiments in terms of other structures and manufacturing methods.
- the trench gate structure is formed only by a mere linear portion.
- both ends of the adjacent gate trench 6 are connected in a semicircular shape on the outside of the cell portion RC, that is, in the connecting portion RJ, and the gate trench 6 is viewed from the upper surface. May have an oval shape. Even in that case, the entire area around the semicircular portion located at the tip of the gate trench 6 rather than the linear portion may be the ion implantation layer 31, and the side surface of the gate trench 6 may be inclined.
- the ion implantation layer 31 is a p-type layer, but it does not necessarily have to be a p-type layer if the purpose is to incline the side surface of the gate trench 6. It may be an n-type layer.
- aluminum has been mentioned as an example of the doping source for ion implantation, an n-type impurity such as nitrogen may be used, or an inert element such as carbon, silicon, or argon that does not become an impurity may be used.
Abstract
According to the present invention, configuring a source region (4) with an epitaxial layer reduces a variation in the thickness of a base region (3), and suppresses a variation in a threshold value Vt. Furthermore, a side surface of a gate trench (6) is inclined with respect to a normal direction of a main surface of a substrate (1) outside a cell portion (RC) as compared with a part configured with a base region-contacting epitaxial layer of the source region inside the cell portion. Accordingly, a gate insulation film (7) becomes a thick film part having a large thickness outside the cell portion even when the gate insulation film (7) has a thin film part having a small thickness inside the cell portion.
Description
本出願は、２０１９年５月２３日に出願された日本特許出願番号２０１９－９６８６４号に基づくもので、ここにその記載内容が参照により組み入れられる。
This application is based on Japanese Patent Application No. 2019-96864 filed on May 23, 2019, the contents of which are incorporated herein by reference.
本開示は、炭化珪素（以下、ＳｉＣという）にて構成されるトレンチゲート構造の縦型半導体素子を有したＳｉＣ半導体装置およびその製造方法に関する。
The present disclosure relates to a SiC semiconductor device having a vertical semiconductor element having a trench gate structure composed of silicon carbide (hereinafter referred to as SiC) and a method for manufacturing the same.
従来より、大電流が流せるようにチャネル密度を高くした構造として、トレンチゲート構造を有するＳｉＣ半導体装置がある。このＳｉＣ半導体装置は、ｎ型ドリフト層の上にｐ型ベース領域とｎ＋型ソース領域とが順に形成され、ｎ＋型ソース領域の表面からｐ型ベース領域を貫通してｎ型ドリフト層に達するようにトレンチゲート構造が形成される。具体的には、ｎ型ドリフト層の上にｐ型ベース領域をエピタキシャル成長させたのち、ｐ型ベース領域に対してｎ型不純物をイオン注入で打ち返すことでｐ型ベース領域の一部をｎ型に反転させ、ｎ＋型ソース領域を形成している（例えば、特許文献１参照）。
Conventionally, as a structure in which the channel density is increased so that a large current can flow, there is a SiC semiconductor device having a trench gate structure. In this SiC semiconductor device, a p-type base region and an n + -type source region are sequentially formed on the n-type drift layer, and the n-type drift layer is formed by penetrating the p-type base region from the surface of the n + -type source region. A trench gate structure is formed to reach. Specifically, after epitaxially growing a p-type base region on an n-type drift layer, an n-type impurity is implanted back into the p-type base region by ion implantation to make a part of the p-type base region n-type. It is inverted to form an n + type source region (see, for example, Patent Document 1).
しかしながら、エピタキシャル成長させるときの膜厚バラツキは、成長させる膜厚が厚いほど大きくなるが、イオン注入の飛程のバラツキはあまり大きくない。このため、イオン注入後のｐ型ベース領域の膜厚バラツキは、エピタキシャル成長させた膜厚に対応するバラツキとなる。これにより、ｐ型ベース領域に対してｎ＋型ソース領域をイオン注入で形成した場合、ｎ＋型ソース領域の厚みのバラツキは少なく、チャネル領域が形成されるｐ型ベース領域の厚みのバラツキが大きくなる。したがって、閾値Ｖｔのバラツキを生じさせるという課題がある。
However, the film thickness variation during epitaxial growth increases as the film thickness to be grown increases, but the ion implantation range variation is not so large. Therefore, the film thickness variation of the p-type base region after ion implantation is the variation corresponding to the epitaxially grown film thickness. Thus, when the n + -type source region with respect to the p-type base region formed by ion implantation, n + -type variations in the thickness of the source region is small, the variation in thickness of the p-type base region in which a channel region is formed growing. Therefore, there is a problem that the threshold value Vt varies.
そこで、本発明者らは、ｐ型ベース領域だけでなく、ｎ＋型ソース領域についてもエピタキシャル成長によって形成することについて検討を行った。このようにすれば、ｐ型ベース領域とｎ＋型ソース領域それぞれに厚みのバラツキが分配されることから、ｐ型ベース領域の厚みのバラツキを小さくすることが可能となり、閾値Ｖｔのバラツキを抑制できる。また、ｎ＋型ソース領域をエピタキシャル成長で形成する場合、トレンチゲート構造における側面をｎ＋型ソース領域の表面に対してほぼ垂直に切り立たせることが可能となる。
Therefore, the present inventors have studied the formation of not only the p-type base region but also the n + -type source region by epitaxial growth. By doing so, since the variation in thickness is distributed to each of the p-type base region and the n + -type source region, it is possible to reduce the variation in thickness of the p-type base region and suppress the variation in the threshold value Vt. it can. Further, when the n + type source region is formed by epitaxial growth, the side surface of the trench gate structure can be cut off substantially perpendicular to the surface of the n + type source region.
ところが、このような構造とする場合、トレンチ入口側の角部においてゲート絶縁膜が薄くなり、大きな電界が加わったときに薄くなった部分でゲート絶縁膜が破壊され、ゲート寿命が低下することがあることが確認された。
However, in the case of such a structure, the gate insulating film becomes thin at the corner on the trench inlet side, and when a large electric field is applied, the gate insulating film is destroyed at the thinned portion, and the gate life may be shortened. It was confirmed that there was.
トレンチゲート構造では、長手方向の両端の少なくとも一方にゲート電極をゲートトレンチの外部まで引き出したゲートライナーが備えられ、ゲートライナーがゲート絶縁膜のうち薄くなった部分の上にも形成された構造となる。このため、ゲート絶縁膜のうちゲートライナーが備えられた部分において大きな電界が加わり、ゲート絶縁膜が破壊されると考えられる。
本開示は、閾値Ｖｔのバラツキの抑制が図れると共に、ゲート寿命の低下を抑制できる構造のＳｉＣ半導体装置およびその製造方法を提供することを目的とする。 In the trench gate structure, at least one of both ends in the longitudinal direction is provided with a gate liner in which the gate electrode is pulled out to the outside of the gate trench, and the gate liner is also formed on the thinned portion of the gate insulating film. Become. Therefore, it is considered that a large electric field is applied to the portion of the gate insulating film provided with the gate liner, and the gate insulating film is destroyed.
An object of the present disclosure is to provide a SiC semiconductor device having a structure capable of suppressing variation in threshold value Vt and suppressing a decrease in gate life, and a method for manufacturing the same.
本開示は、閾値Ｖｔのバラツキの抑制が図れると共に、ゲート寿命の低下を抑制できる構造のＳｉＣ半導体装置およびその製造方法を提供することを目的とする。 In the trench gate structure, at least one of both ends in the longitudinal direction is provided with a gate liner in which the gate electrode is pulled out to the outside of the gate trench, and the gate liner is also formed on the thinned portion of the gate insulating film. Become. Therefore, it is considered that a large electric field is applied to the portion of the gate insulating film provided with the gate liner, and the gate insulating film is destroyed.
An object of the present disclosure is to provide a SiC semiconductor device having a structure capable of suppressing variation in threshold value Vt and suppressing a decrease in gate life, and a method for manufacturing the same.
本開示の１つの観点にかかるＳｉＣ半導体装置は、主表面を有する第１または第２導電型の炭化珪素で構成された基板と、基板の主表面側に形成され、基板よりも低不純物濃度とされた第１導電型の炭化珪素で構成されたドリフト層と、ドリフト層の上に形成された第２導電型の炭化珪素で構成されたベース領域と、セル部内におけるベース領域の上に形成され、ドリフト層よりも高不純物濃度とされ、少なくともベース領域と接する部分が炭化珪素のエピタキシャル層で構成された第１導電型のソース領域と、ソース領域の表面からベース領域よりも深く、一方向を長手方向とする直線状部分を有していてセル部から該セル部の外側まで形成されたゲートトレンチ内に形成され、該ゲートトレンチの内壁面に形成されたゲート絶縁膜と、ゲート絶縁膜の上に形成されたゲート電極と、を有して構成されたトレンチゲート構造と、ソース領域およびトレンチゲート構造の上に、ソース領域に繋がるコンタクトホールが形成された層間絶縁膜と、層間絶縁膜の上に形成され、コンタクトホールを通じてソース領域に電気的に接続された第１電極と、基板の裏面側に電気的に接続された第２電極と、を備えている。そして、ゲートトレンチの側面は、セル部の外側では、セル部内におけるソース領域のうちのベース領域と接しているエピタキシャル層で構成された部分と比較して、基板の主表面に対する法線方向に対して傾斜している。
The SiC semiconductor device according to one aspect of the present disclosure is formed on a substrate made of first or second conductive type silicon carbide having a main surface and on the main surface side of the substrate, and has a lower impurity concentration than the substrate. A drift layer made of the first conductive type silicon carbide formed, a base region made of the second conductive type silicon carbide formed on the drift layer, and a base region formed in the cell portion. The first conductive type source region, which has a higher impurity concentration than the drift layer and is composed of an epitaxial layer of silicon carbide at least in contact with the base region, and the surface of the source region deeper than the base region in one direction. A gate insulating film having a linear portion in the longitudinal direction and formed in a gate trench formed from the cell portion to the outside of the cell portion, and a gate insulating film formed on the inner wall surface of the gate trench, and a gate insulating film. A trench gate structure having a gate electrode formed on the surface, an interlayer insulating film in which a contact hole connected to the source region is formed on the source region and the trench gate structure, and an interlayer insulating film. It includes a first electrode formed above and electrically connected to the source region through a contact hole, and a second electrode electrically connected to the back surface side of the substrate. Then, on the outside of the cell portion, the side surface of the gate trench is relative to the normal direction with respect to the main surface of the substrate as compared with the portion composed of the epitaxial layer in contact with the base region of the source region in the cell portion. Is tilted.
このように、ソース領域のうち少なくともベース領域と接する部分がエピタキシャル成長層で構成されるようにしていることから、ベース領域の厚みのバラツキを小さくすることが可能となり、閾値Ｖｔのバラツキを抑制できる。また、ゲートトレンチの側面について、セル部の外側ではセル部内におけるソース領域のうちのベース領域と接しているエピタキシャル層で構成された部分と比較して、基板の主表面に対する法線方向に対して傾斜させている。このため、ゲート絶縁膜が、セル部内では厚みの薄い薄膜部となっていても、セル部の外部においては厚みの厚い厚膜部にできる。したがって、トレンチゲート構造の長手方向の両端位置で大きな電界が加わることでゲート絶縁膜が破壊されることを抑制でき、ゲート絶縁膜の寿命低下を抑制することが可能となる。
In this way, since at least the portion of the source region in contact with the base region is composed of the epitaxial growth layer, it is possible to reduce the variation in the thickness of the base region and suppress the variation in the threshold value Vt. Further, regarding the side surface of the gate trench, the outside of the cell portion is compared with the portion composed of the epitaxial layer in contact with the base region of the source region in the cell portion in the normal direction with respect to the main surface of the substrate. It is tilted. Therefore, even if the gate insulating film is a thin thin film portion inside the cell portion, it can be formed as a thick thick film portion outside the cell portion. Therefore, it is possible to suppress the destruction of the gate insulating film due to the application of a large electric field at both ends of the trench gate structure in the longitudinal direction, and it is possible to suppress a decrease in the life of the gate insulating film.
また、本開示のもう１つの観点にかかるＳｉＣ半導体装置の製造方法は、主表面を有する第１または第２導電型の炭化珪素で構成された基板を用意することと、基板の上に、基板よりも低不純物濃度の第１導電型の炭化珪素で構成されたドリフト層を形成することと、ドリフト層の上に、第２導電型の炭化珪素からなるベース領域を形成することと、ベース領域の上に、エピタキシャル成長により、ドリフト層よりも第１導電型不純物濃度が高くされた第１導電型の炭化珪素で構成されるソース領域を形成することと、ソース領域の表面からベース領域よりも深く、一方向を長手方向とした直線状部を有すると共にセル部から該セル部の外側に至るゲートトレンチを形成したのち、ゲートトレンチの内壁面にゲート絶縁膜を形成すると共に、ゲート絶縁膜の上にゲート電極を形成することでトレンチゲート構造を形成することと、ソース領域およびトレンチゲート構造の上に、ソース領域に繋がるコンタクトホールを有する層間絶縁膜を形成することと、コンタクトホールを通じてソース領域に電気的に接続される第１電極を形成することと、基板の裏面側に第２電極を形成することと、を含んでいる。そして、トレンチゲート構造を形成することでは、ゲートトレンチの側面を、セル部の外側ではセル部内におけるソース領域のうちのベース領域と接しているエピタキシャル層で構成された部分と比較して、基板の主表面に対する法線方向に対して傾斜させる。
Further, a method for manufacturing a SiC semiconductor device according to another aspect of the present disclosure is to prepare a substrate made of first or second conductive type silicon carbide having a main surface, and to prepare a substrate on the substrate. Forming a drift layer composed of first conductive type silicon carbide having a lower impurity concentration, forming a base region made of second conductive type silicon carbide on the drift layer, and forming a base region. On top of this, a source region composed of first conductive type silicon carbide having a higher concentration of first conductive type impurities than the drift layer is formed by epitaxial growth, and the surface of the source region is deeper than the base region. After forming a gate trench extending from the cell portion to the outside of the cell portion while having a linear portion with one direction as the longitudinal direction, a gate insulating film is formed on the inner wall surface of the gate trench and the gate insulating film is formed. A trench gate structure is formed by forming a gate electrode on the surface, an interlayer insulating film having a contact hole connected to the source region is formed on the source region and the trench gate structure, and the contact hole is formed in the source region. It includes forming a first electrode that is electrically connected and forming a second electrode on the back surface side of the substrate. Then, by forming the trench gate structure, the side surface of the gate trench is compared with the portion composed of the epitaxial layer which is in contact with the base region of the source region in the cell portion on the outside of the cell portion. Tilt with respect to the normal direction to the main surface.
このように、ベース領域の上にエピタキシャル成長によってソース領域を形成することで、ベース領域の厚みのバラツキを小さくすることが可能となり、閾値Ｖｔのバラツキを抑制できる。また、トレンチゲート構造を形成する際に、ゲートトレンチの側面を、セル部の外側ではセル部内におけるソース領域のうちのベース領域と接しているエピタキシャル層で構成された部分と比較して、基板の主表面に対する法線方向に対して傾斜させている。このため、ゲート絶縁膜が、セル部内では厚みの薄い薄膜部となっていても、セル部の外部においては厚みの厚い厚膜部にできる。したがって、トレンチゲート構造の長手方向の両端位置で大きな電界が加わることでゲート絶縁膜が破壊されることを抑制でき、ゲート絶縁膜の寿命低下を抑制することが可能となる。
By forming the source region on the base region by epitaxial growth in this way, it is possible to reduce the variation in the thickness of the base region and suppress the variation in the threshold value Vt. Further, when forming the trench gate structure, the side surface of the gate trench is compared with the portion composed of the epitaxial layer which is in contact with the base region of the source region in the cell portion on the outside of the cell portion. It is tilted with respect to the normal direction with respect to the main surface. Therefore, even if the gate insulating film is a thin thin film portion inside the cell portion, it can be formed as a thick thick film portion outside the cell portion. Therefore, it is possible to suppress the destruction of the gate insulating film due to the application of a large electric field at both ends of the trench gate structure in the longitudinal direction, and it is possible to suppress a decrease in the life of the gate insulating film.
なお、各構成要素等に付された括弧付きの参照符号は、その構成要素等と後述する実施形態に記載の具体的な構成要素等との対応関係の一例を示すものである。
Note that the reference reference numerals in parentheses attached to each component or the like indicate an example of the correspondence between the component or the like and the specific component or the like described in the embodiment described later.
以下、本開示の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。
Hereinafter, embodiments of the present disclosure will be described with reference to the figures. In each of the following embodiments, parts that are the same or equal to each other will be described with the same reference numerals.
（第１実施形態）
第１実施形態について説明する。ここではトレンチゲート構造の縦型半導体素子として反転型のＭＯＳＦＥＴが形成されたＳｉＣ半導体装置を例に挙げて説明する。 (First Embodiment)
The first embodiment will be described. Here, a SiC semiconductor device in which an inverting MOSFET is formed as a vertical semiconductor element having a trench gate structure will be described as an example.
第１実施形態について説明する。ここではトレンチゲート構造の縦型半導体素子として反転型のＭＯＳＦＥＴが形成されたＳｉＣ半導体装置を例に挙げて説明する。 (First Embodiment)
The first embodiment will be described. Here, a SiC semiconductor device in which an inverting MOSFET is formed as a vertical semiconductor element having a trench gate structure will be described as an example.
図１に示すＳｉＣ半導体装置は、トレンチゲート構造のＭＯＳＦＥＴが形成されるセル部と、このセル部ＲＣを囲む外周部ＲＯとを有した構成とされている。外周部ＲＯは、ガードリング部ＲＧと、ガードリング部ＲＧよりも内側、つまりセル部ＲＣとガードリング部ＲＧとの間に配置される繋ぎ部ＲＪとを有した構成とされている。なお、図１は断面図ではないが、図を見やすくするために部分的にハッチングを示してある。
The SiC semiconductor device shown in FIG. 1 has a configuration in which a cell portion in which a MOSFET having a trench gate structure is formed and an outer peripheral portion RO surrounding the cell portion RC are provided. The outer peripheral portion RO has a configuration having a guard ring portion RG and a connecting portion RJ arranged inside the guard ring portion RG, that is, between the cell portion RC and the guard ring portion RG. Although FIG. 1 is not a cross-sectional view, hatching is partially shown to make the figure easier to see.
図２に示すように、ＳｉＣ半導体装置は、ＳｉＣからなるｎ＋型基板１を用いて形成される。ｎ＋型基板１の主表面上にＳｉＣからなるｎ－型不純物層２とｎ型電流分散層２ａとｐ型ベース領域３、および、ｎ＋型ソース領域４が順にエピタキシャル成長させられている。
As shown in FIG. 2, the SiC semiconductor device is formed by using an n + type substrate 1 made of SiC. made of SiC on the main surface of the n + -type substrate 1 n - -type impurity layer 2 and the n-type current spreading layer 2a and the p-type base region 3, and, n + -type source region 4 is then epitaxially grown in order.
ｎ＋型基板１は、例えばｎ型不純物濃度が１．０×１０１９／ｃｍ３とされ、表面が（０００１）Ｓｉ面とされている。ｎ－型不純物層２は、例えばｎ型不純物濃度が０．５～２．０×１０１６／ｃｍ３とされている。ｎ型電流分散層２ａは、ｎ－型不純物層２よりもｎ型不純物濃度が高濃度、つまり低抵抗とされており、より広範囲に電流を分散して流すことで、ＪＦＥＴ抵抗を低減する役割を果たす。例えば、ｎ型電流分散層２ａは、例えば８×１０１６／ｃｍ３とされ、厚みが０．５μｍとされている。なお、ここでは便宜上、ｎ－型不純物層２とｎ型電流分散層２ａという異なる層として説明しているが、これらはいずれもドリフト層を構成するものである。
The n + type substrate 1 has, for example, an n-type impurity concentration of 1.0 × 10 19 / cm 3 and a surface of (0001) Si surface. The n - type impurity layer 2 has, for example, an n-type impurity concentration of 0.5 to 2.0 × 10 16 / cm 3 . The n-type current dispersion layer 2a has a higher n-type impurity concentration, that is, a lower resistance than the n - type impurity layer 2, and has a role of reducing the JFET resistance by distributing and flowing a current over a wider range. Fulfill. For example, the n-type current dispersion layer 2a has a thickness of, for example, 8 × 10 16 / cm 3 and a thickness of 0.5 μm. Here, for convenience, the n - type impurity layer 2 and the n-type current dispersion layer 2a are described as different layers, but all of them form a drift layer.
また、ｐ型ベース領域３は、チャネル領域が形成される部分で、ｐ型不純物濃度が例えば２．０×１０１７／ｃｍ３程度とされ、厚みが３００ｎｍで構成されている。ｎ＋型ソース領域４は、ｎ－型不純物層２よりも高不純物濃度とされ、表層部におけるｎ型不純物濃度が例えば２．５×１０１８～１．０×１０１９／ｃｍ３、厚さ０．５μｍ程度で構成されている。
Further, the p-type base region 3 is a portion where a channel region is formed, and the p-type impurity concentration is, for example, about 2.0 × 10 17 / cm 3 , and the thickness is 300 nm. The n + type source region 4 has a higher impurity concentration than the n − type impurity layer 2, and the n-type impurity concentration in the surface layer portion is, for example, 2.5 × 10 18 to 1.0 × 10 19 / cm 3 , and the thickness. It is composed of about 0.5 μm.
セル部ＲＣでは、ｎ＋型基板１の表面側においてｐ型ベース領域３およびｎ＋型ソース領域４が残されており、繋ぎ部ＲＪでは、ｎ＋型ソース領域４が後述するイオン注入層３１に変えられている。また、ガードリング部ＲＧでは、これらｎ＋型ソース領域４もしくはイオン注入層３１およびｐ型ベース領域３を貫通してｎ型電流分散層２ａに達するように凹部２０が形成されている。
In the cell portion RC, the p-type base region 3 and the n + -type source region 4 are left on the surface side of the n + -type substrate 1, and in the connecting portion RJ, the n + -type source region 4 is the ion implantation layer 31 described later. Has been changed to. Further, in the guard ring portion RG, a recess 20 is formed so as to penetrate the n + type source region 4 or the ion implantation layer 31 and the p type base region 3 and reach the n type current dispersion layer 2a.
また、セル部ＲＣでは、ｎ＋型ソース領域４やｐ型ベース領域３を貫通してｎ型電流分散層２ａに達するようにｐ型ディープ層５が形成されている。ｐ型ディープ層５は、ｐ型ベース領域３よりもｐ型不純物濃度が高くされている。具体的には、ｐ型ディープ層５は、ｎ型電流分散層２ａに複数本が等間隔に配置され、互いに交点なく離れて配置されたストライプ状のトレンチ５ａ内に備えられ、エピタキシャル成長によるｐ型のエピタキシャル膜によって構成されている。なお、このトレンチ５ａは、例えば幅が１μｍ以下、アスペクト比が２以上の深さとされている。
Further, in the cell portion RC, the p-type deep layer 5 is formed so as to penetrate the n + type source region 4 and the p-type base region 3 and reach the n-type current dispersion layer 2a. The p-type deep layer 5 has a higher p-type impurity concentration than the p-type base region 3. Specifically, the p-type deep layer 5 is provided in a striped trench 5a in which a plurality of p-type deep layers 5 are arranged at equal intervals in the n-type current dispersion layer 2a and are arranged apart from each other without intersections, and the p-type deep layer 5 is provided by epitaxial growth. It is composed of an epitaxial film of. The trench 5a has, for example, a width of 1 μm or less and an aspect ratio of 2 or more.
例えば、各ｐ型ディープ層５は、ｐ型不純物濃度が例えば１．０×１０１７～１．０×１０１９ｃｍ３、幅０．７μｍ、深さ２．０μｍ程度で構成されている。各ｐ型ディープ層５は、最も深い底部の位置がｎ型電流分散層２ａとｎ－型不純物層２との境界位置と同じ位置、もしくはそれよりもｐ型ベース領域３側に位置している。すなわち、ｐ型ディープ層５とｎ型電流分散層２ａとが同じ深さ、もしくはｐ型ディープ層５よりもｎ型電流分散層２ａの方が深い位置まで形成されている。ｐ型ディープ層５は、図１に示すようにセル部ＲＣの一端から他端に渡って形成されている。そして、ｐ型ディープ層５は、後述するトレンチゲート構造と同方向を長手方向として延設され、トレンチゲート構造の両端から更にセル部ＲＣの外側に延設された後述するｐ型繋ぎ層３０とつながっている。
For example, each p-type deep layer 5 has a p-type impurity concentration of, for example, 1.0 × 10 17 to 1.0 × 10 19 cm 3 , a width of 0.7 μm, and a depth of about 2.0 μm. The deepest bottom of each p-type deep layer 5 is located at the same position as the boundary position between the n-type current dispersion layer 2a and the n - type impurity layer 2, or is located closer to the p-type base region 3 than that. .. That is, the p-type deep layer 5 and the n-type current dispersion layer 2a are formed to the same depth, or the n-type current dispersion layer 2a is formed to a position deeper than the p-type deep layer 5. As shown in FIG. 1, the p-type deep layer 5 is formed from one end to the other end of the cell portion RC. The p-type deep layer 5 is extended with the same direction as the trench gate structure described later as the longitudinal direction, and is further extended from both ends of the trench gate structure to the outside of the cell portion RC with the p-type connecting layer 30 described later. linked.
また、ｐ型ベース領域３およびｎ＋型ソース領域４を貫通してｎ－型不純物層２に達するように、例えば幅が０．８μｍ、深さが１．０μｍのゲートトレンチ６が形成されている。ゲートトレンチ６は、セル部ＲＣ内のみでなく、セル部ＲＣから繋ぎ部ＲＪに突き出して形成されている。このゲートトレンチ６の側面と接するように上述したｐ型ベース領域３やｎ＋型ソース領域４およびイオン注入層３１が配置されている。より詳しくは、セル部ＲＣでは、ゲートトレンチ６の入口側の側面がｎ＋型ソース領域４で構成され、繋ぎ部ＲＪでは、ゲートトレンチ６の入口側の側面がイオン注入層３１で構成されている。ゲートトレンチ６は、図２の紙面左右方向を幅方向、紙面垂直方向を長手方向、紙面上下方向を深さ方向とする直線状部分を有したレイアウトで形成されている。また、図１に示すように、ゲートトレンチ６は、セル部ＲＣ内においては直線状部分のみで構成されるが、本実施形態では繋ぎ部ＲＪにおいても直線状部分のみで構成されている。ゲートトレンチ６は複数本備えられており、それぞれがｐ型ディープ層５の間に挟まれるように配置されていると共に平行に等間隔で並べられることでストライプ状とされている。
Further, a gate trench 6 having a width of 0.8 μm and a depth of 1.0 μm is formed so as to penetrate the p-type base region 3 and the n + -type source region 4 and reach the n - type impurity layer 2. There is. The gate trench 6 is formed not only in the cell portion RC but also protruding from the cell portion RC to the connecting portion RJ. The above-mentioned p-type base region 3, n + -type source region 4, and ion implantation layer 31 are arranged so as to be in contact with the side surface of the gate trench 6. More specifically, in the cell portion RC, the side surface on the inlet side of the gate trench 6 is composed of the n + type source region 4, and in the connecting portion RJ, the side surface on the inlet side of the gate trench 6 is composed of the ion implantation layer 31. There is. The gate trench 6 is formed in a layout having a linear portion having a width direction in the left-right direction of the paper surface, a longitudinal direction in the vertical direction of the paper surface, and a depth direction in the vertical direction of the paper surface in FIG. Further, as shown in FIG. 1, the gate trench 6 is composed of only a linear portion in the cell portion RC, but in the present embodiment, the gate trench 6 is also composed of only a linear portion in the connecting portion RJ. A plurality of gate trenches 6 are provided, and each of them is arranged so as to be sandwiched between the p-type deep layers 5 and is arranged in parallel at equal intervals to form a stripe shape.
さらに、本実施形態では、図２、図３および図５に示すように、セル部ＲＣ内と繋ぎ部ＲＪ内とにおいて、ゲートトレンチ６の側面の形状が異なっている。具体的には、ゲートトレンチ６の側面は、セル部ＲＣ内ではｎ＋型基板１の主表面に対して垂直になっており、繋ぎ部ＲＪ内ではトレンチ入口側が底部側よりも幅広となっていて、ｎ＋型基板１の主表面に対する法線方向に対して傾斜している。ゲートトレンチ６の先端部は、図４に示すように、繋ぎ部ＲＪにおける側面の形状と同様、トレンチ入口側がｎ＋型基板１の主表面に対する法線方向に対して傾斜している。以下、これらゲートトレンチ６の側面や先端部のうち傾斜した部分を傾斜部という。
Further, in the present embodiment, as shown in FIGS. 2, 3 and 5, the shape of the side surface of the gate trench 6 is different between the inside of the cell portion RC and the inside of the connecting portion RJ. Specifically, the side surface of the gate trench 6 is perpendicular to the main surface of the n + type substrate 1 in the cell portion RC, and the trench inlet side is wider than the bottom side in the connecting portion RJ. Therefore, the n + type substrate 1 is inclined with respect to the normal direction with respect to the main surface. As shown in FIG. 4, the tip of the gate trench 6 has a trench inlet side inclined with respect to the normal direction with respect to the main surface of the n + type substrate 1, similar to the shape of the side surface of the connecting portion RJ. Hereinafter, the inclined portion of the side surface and the tip portion of the gate trench 6 is referred to as an inclined portion.
ｐ型ベース領域３のうちゲートトレンチ６の側面に位置している部分を、縦型ＭＯＳＦＥＴの作動時にｎ＋型ソース領域４とｎ－型不純物層２との間を繋ぐチャネル領域として、チャネル領域を含むゲートトレンチ６の内壁面にはゲート絶縁膜７が形成されている。ゲート絶縁膜７は、熱酸化膜によって構成されている。そして、ゲート絶縁膜７の表面にはドープドＰｏｌｙ－Ｓｉにて構成されたゲート電極８が形成されており、これらゲート絶縁膜７およびゲート電極８によってゲートトレンチ６内が埋め尽くされている。これにより、トレンチゲート構造が構成されている。
The portion of the p-type base region 3 located on the side surface of the gate trench 6 is used as a channel region connecting the n + type source region 4 and the n - type impurity layer 2 when the vertical MOSFET is operated. A gate insulating film 7 is formed on the inner wall surface of the gate trench 6 including the above. The gate insulating film 7 is composed of a thermal oxide film. A gate electrode 8 made of doped Poly—Si is formed on the surface of the gate insulating film 7, and the gate trench 6 is filled with the gate insulating film 7 and the gate electrode 8. As a result, a trench gate structure is constructed.
ゲート絶縁膜７は、ゲートトレンチ６の内壁面の全面に形成されているが、厚みが場所によって異なっている。具体的には、ゲートトレンチ６のうちセル部ＲＣ内に位置している部分、つまり側面にｎ＋型ソース領域４が形成されていて、側面がｎ＋型基板１の主表面に対して垂直になっている部分では、トレンチ入口の角部においてゲート絶縁膜７が薄くなっている。以下、この部分で薄くなったゲート絶縁膜７を薄膜部７ａという。そして、ゲートトレンチ６のうちセル部ＲＣの外側の繋ぎ部ＲＪに位置している部分、つまり側面に後述するイオン注入層３１が形成されていて、側面が傾斜部となっている部分では、薄膜部７ａよりもゲート絶縁膜７の厚みが厚くなっている。以下、この部分のゲート絶縁膜７を厚膜部７ｂという。
The gate insulating film 7 is formed on the entire inner wall surface of the gate trench 6, but the thickness varies depending on the location. Specifically, the portion of the gate trench 6 located in the cell portion RC, that is, the n + type source region 4 is formed on the side surface, and the side surface is perpendicular to the main surface of the n + type substrate 1. In the portion where the gate insulating film 7 is formed, the gate insulating film 7 is thinned at the corner of the trench entrance. Hereinafter, the gate insulating film 7 thinned in this portion is referred to as a thin film portion 7a. Then, in the portion of the gate trench 6 located at the connecting portion RJ outside the cell portion RC, that is, the portion where the ion implantation layer 31 described later is formed on the side surface and the side surface is an inclined portion, a thin film is formed. The thickness of the gate insulating film 7 is thicker than that of the portion 7a. Hereinafter, the gate insulating film 7 in this portion is referred to as a thick film portion 7b.
また、ｎ＋型ソース領域４およびｐ型ディープ層５の表面やゲート電極８の上には、層間絶縁膜１０を介して第１電極に相当するソース電極９が形成されている。ソース電極９は、複数の金属、例えばＮｉ／Ａｌ等にて構成されている。そして、複数の金属のうち少なくともｎ型ＳｉＣ、具体的にはｎ＋型ソース領域４と接触する部分はｎ型ＳｉＣとオーミック接触可能な金属で構成されている。また、複数の金属のうち少なくともｐ型ＳｉＣ、具体的にはｐ型ディープ層５と接触する部分はｐ型ＳｉＣとオーミック接触可能な金属で構成されている。なお、これらソース電極９は、層間絶縁膜１０上に形成されることで電気的に絶縁されている。そして、層間絶縁膜１０に形成されたコンタクトホールを通じて、ソース電極９はｎ＋型ソース領域４およびｐ型ディープ層５と電気的に接触させられている。
Further, a source electrode 9 corresponding to the first electrode is formed on the surface of the n + type source region 4 and the p-type deep layer 5 and on the gate electrode 8 via the interlayer insulating film 10. The source electrode 9 is made of a plurality of metals such as Ni / Al. The portion of the plurality of metals that contacts at least n-type SiC, specifically the n + -type source region 4, is composed of a metal that can make ohmic contact with n-type SiC. Further, of the plurality of metals, at least the portion that contacts the p-type SiC, specifically, the p-type deep layer 5, is composed of a metal that can make ohmic contact with the p-type SiC. The source electrodes 9 are electrically insulated by being formed on the interlayer insulating film 10. Then, the source electrode 9 is electrically brought into contact with the n + type source region 4 and the p-type deep layer 5 through the contact hole formed in the interlayer insulating film 10.
さらに、ｎ＋型基板１の裏面側にはｎ＋型基板１と電気的に接続された第２電極に相当するドレイン電極１１が形成されている。このような構造により、ｎチャネルタイプの反転型のトレンチゲート構造のＭＯＳＦＥＴが構成されている。そして、このようなＭＯＳＦＥＴが複数セル配置されることでセル部ＲＣが構成されている。
Further, on the back side of the n + -type substrate 1 the drain electrode 11 corresponding to the second electrode electrically connected to the n + -type substrate 1 is formed. With such a structure, a MOSFET having an n-channel type inverted trench gate structure is configured. Then, the cell portion RC is configured by arranging a plurality of such MOSFETs.
一方、ガードリング部ＲＧでは、上記したように、後述するイオン注入層３１およびｐ型ベース領域３を貫通してｎ型電流分散層２ａに達するように凹部２０が形成されている。このため、セル部ＲＣから離れた位置ではイオン注入層３１およびｐ型ベース領域３が除去されて、ｎ型電流分散層２ａが露出させられている。そして、ｎ＋型基板１の厚み方向において、凹部２０よりも内側に位置するセル部ＲＣや繋ぎ部ＲＪが島状に突き出したメサ部ＲＭとなっている。この凹部２０の側面、つまりメサ部ＲＭと凹部２０との境界位置では、メサ部ＲＭの角部が傾斜している。そして、凹部２０内にも、ゲート絶縁膜７が形成されており、その上に層間絶縁膜１０が形成された状態となっているが、凹部２０とメサ部ＲＭとの境界位置にゲート電極８の形成に用いたＰｏｌｙ－Ｓｉの残渣８ａが残っている場合がある。
On the other hand, in the guard ring portion RG, as described above, the recess 20 is formed so as to penetrate the ion implantation layer 31 and the p-type base region 3 described later and reach the n-type current dispersion layer 2a. Therefore, the ion implantation layer 31 and the p-type base region 3 are removed at a position away from the cell portion RC, and the n-type current dispersion layer 2a is exposed. Then, in the thickness direction of the n + type substrate 1, the cell portion RC and the connecting portion RJ located inside the recess 20 form an island-shaped protruding mesa portion RM. At the side surface of the recess 20, that is, at the boundary position between the mesa portion RM and the recess 20, the corner portion of the mesa portion RM is inclined. A gate insulating film 7 is also formed in the recess 20, and an interlayer insulating film 10 is formed on the gate insulating film 7. However, the gate electrode 8 is located at the boundary between the recess 20 and the mesa portion RM. Residue 8a of Poly-Si used for the formation of the above may remain.
また、凹部２０の下方に位置するｎ型電流分散層２ａの表層部には、セル部ＲＣを囲むように、複数本のｐ型ガードリング２１が備えられている。本実施形態の場合、ｐ型ガードリング２１を四隅が丸められた四角形状としているが、円形状など他の枠形状で構成されていても良い。ｐ型ガードリング２１は、ｎ型電流分散層２ａに形成されたトレンチ２１ａ内に配置され、エピタキシャル成長によるｐ型のエピタキシャル膜によって構成されている。なお、このトレンチ２１ａは、例えば幅が１μｍ以下、アスペクト比が２以上の深さとされている。
Further, a plurality of p-type guard rings 21 are provided on the surface layer portion of the n-type current dispersion layer 2a located below the recess 20 so as to surround the cell portion RC. In the case of the present embodiment, the p-shaped guard ring 21 has a quadrangular shape with four corners rounded, but may be formed in another frame shape such as a circular shape. The p-type guard ring 21 is arranged in the trench 21a formed in the n-type current dispersion layer 2a, and is composed of a p-type epitaxial film formed by epitaxial growth. The trench 21a has, for example, a width of 1 μm or less and an aspect ratio of 2 or more.
ｐ型ガードリング２１を構成する各部は、上記したｐ型ディープ層５と同様の構成とされている。ｐ型ガードリング２１は、上面形状がセル部ＲＣおよび繋ぎ部ＲＪを囲む枠形状のライン状とされている点において、直線状に形成されたｐ型ディープ層５と異なっているが、他は同様である。すなわち、ｐ型ガードリング２１はｐ型ディープ層５と同様の幅、同様の厚さ、つまり同様の深さとされている。また、各ｐ型ガードリング２１の間隔については等間隔でも良いが、より内周側、つまりセル部ＲＣ側において電界集中を緩和して等電位線がより外周側に向かうように、ｐ型ガードリング２１の間隔がセル部ＲＣ側で狭く外周側に向かうほど大きくされている。
Each part constituting the p-type guard ring 21 has the same configuration as the p-type deep layer 5 described above. The p-type guard ring 21 is different from the linearly formed p-type deep layer 5 in that the upper surface shape is a frame-shaped line shape surrounding the cell portion RC and the connecting portion RJ, but other than that. The same is true. That is, the p-type guard ring 21 has the same width and the same thickness as the p-type deep layer 5, that is, the same depth. Further, the intervals of the p-type guard rings 21 may be equal, but the p-type guards are arranged so that the electric field concentration is relaxed on the inner peripheral side, that is, the cell portion RC side, and the equipotential lines are directed toward the outer peripheral side. The distance between the rings 21 is narrower on the RC side of the cell portion and is increased toward the outer peripheral side.
なお、図示していないが、必要に応じてｐ型ガードリング２１よりも外周にＥＱＲ構造が備えられることにより、セル部ＲＣを囲む外周耐圧構造が備えられたガードリング部ＲＧが構成されている。
Although not shown, the guard ring portion RG having an outer peripheral pressure resistant structure surrounding the cell portion RC is configured by providing an EQR structure on the outer periphery of the p-type guard ring 21 as needed. ..
さらに、セル部ＲＣからガードリング部ＲＧに至るまでの間を繋ぎ部ＲＪとして、繋ぎ部ＲＪにおいて、ｎ－型不純物層２の表層部に複数本のｐ型繋ぎ層３０が形成されている。本実施形態の場合、図１中の破線ハッチングに示すように、セル部ＲＣの外周に位置し、セル部ＲＣを囲むように繋ぎ部ＲＪが形成されており、さらに繋ぎ部ＲＪの外側を囲むように、四隅が丸められた四角形状のｐ型ガードリング２１が複数本形成されている。ｐ型繋ぎ層３０は、セル部ＲＣに形成されるｐ型ディープ層５と平行に複数本並べて配置されており、本実施形態では、隣り合うｐ型ディープ層５同士の間の間隔と等間隔に配置されている。また、セル部ＲＣからｐ型ガードリング２１までの距離が離れている場所では、ｐ型ディープ層５からｐ型繋ぎ層３０を延設しており、ｐ型繋ぎ層３０の先端からｐ型ガードリング２１までの距離が短くなるようにしている。
Further, a plurality of p-type connecting layers 30 are formed on the surface layer portion of the n - type impurity layer 2 in the connecting portion RJ as the connecting portion RJ from the cell portion RC to the guard ring portion RG. In the case of the present embodiment, as shown by the broken line hatching in FIG. 1, the connecting portion RJ is formed on the outer periphery of the cell portion RC so as to surround the cell portion RC, and further surrounds the outside of the connecting portion RJ. As described above, a plurality of quadrangular p-shaped guard rings 21 having rounded four corners are formed. A plurality of p-type connecting layers 30 are arranged side by side in parallel with the p-type deep layers 5 formed in the cell portion RC, and in the present embodiment, the intervals between the adjacent p-type deep layers 5 are equal to each other. Is located in. Further, in a place where the distance from the cell portion RC to the p-type guard ring 21 is large, the p-type connecting layer 30 extends from the p-type deep layer 5, and the p-type guard is extended from the tip of the p-type connecting layer 30. The distance to the ring 21 is shortened.
各ｐ型繋ぎ層３０は、ｎ＋型ソース領域４およびｐ型ベース領域３を貫通してｎ－型不純物層２に達するトレンチ３０ａ内に配置され、エピタキシャル成長によるｐ型のエピタキシャル膜によって構成されている。ｐ型ディープ層５の長手方向におけるセル部ＲＣとガードリング部ＲＧとの間では、ｐ型繋ぎ層３０がｐ型ディープ層５の先端に繋げられて形成されている。なお、このトレンチ３０ａは、例えば幅が１μｍ以下、アスペクト比が２以上の深さとされている。ｐ型繋ぎ層３０は、ｐ型ベース領域３に接触させられていることから、ソース電位に固定される。
Each p-type connecting layer 30 is arranged in a trench 30a that penetrates the n + type source region 4 and the p-type base region 3 and reaches the n - type impurity layer 2, and is composed of a p-type epitaxial film by epitaxial growth. There is. A p-type connecting layer 30 is formed by being connected to the tip of the p-type deep layer 5 between the cell portion RC and the guard ring portion RG in the longitudinal direction of the p-type deep layer 5. The trench 30a has, for example, a width of 1 μm or less and an aspect ratio of 2 or more. Since the p-type connecting layer 30 is in contact with the p-type base region 3, it is fixed at the source potential.
ｐ型繋ぎ層３０を構成する各部は、上記したｐ型ディープ層５やｐ型ガードリング２１と同様の構成とされており、ｐ型繋ぎ層３０の上面形状が直線状とされている点において、枠形状に形成されたｐ型ガードリング２１と異なっているが、他は同様である。すなわち、ｐ型繋ぎ層３０は、ｐ型ディープ層５やｐ型ガードリング２１と同様の幅、同様の厚さ、つまり同様の深さとされている。また、各ｐ型繋ぎ層３０の間隔については、本実施形態ではセル部ＲＣにおけるｐ型ディープ層５同士の間隔と等間隔とされているが、異なる間隔であっても良い。
Each part constituting the p-type connecting layer 30 has the same structure as the p-type deep layer 5 and the p-type guard ring 21 described above, and the upper surface shape of the p-type connecting layer 30 is linear. , It is different from the p-shaped guard ring 21 formed in the frame shape, but the others are the same. That is, the p-type connecting layer 30 has the same width and the same thickness as the p-type deep layer 5 and the p-type guard ring 21, that is, the same depth. Further, the spacing between the p-type connecting layers 30 is equal to the spacing between the p-type deep layers 5 in the cell portion RC in the present embodiment, but may be different.
このようなｐ型繋ぎ層３０を形成し、かつ、ｐ型繋ぎ層３０同士の間を所定間隔、例えばｐ型ディープ層５と等間隔もしくはそれ以下に設定することで、ｐ型繋ぎ層３０の間において等電位線が過剰にせり上がることを抑制できる。これにより、ｐ型繋ぎ層３０の間において電界集中が発生する部位が形成されることを抑制でき、耐圧低下を抑制することが可能となる。
By forming such a p-type connecting layer 30 and setting the distance between the p-type connecting layers 30 at a predetermined interval, for example, equal to or less than the p-type deep layer 5, the p-type connecting layer 30 It is possible to prevent the equipotential lines from rising excessively between them. As a result, it is possible to suppress the formation of a portion where electric field concentration occurs between the p-type connecting layers 30, and it is possible to suppress a decrease in withstand voltage.
さらに、繋ぎ部ＲＪにおいては、セル部ＲＣでｎ＋型ソース領域４とされていた部分にイオン注入がなされることでイオン注入層３１が構成されている。本実施形態では、ｐ型ベース領域３の上部の全域がイオン注入層３１とされている。イオン注入層３１のうちのゲートトレンチ６の側面に位置する部分の導電型は任意であるが、ここでは、エピタキシャル成長させたｎ＋型ソース領域４に対してｐ型不純物をイオン注入することで導電型を反転させてｐ型としている。
Further, in the connecting portion RJ, the ion implantation layer 31 is formed by implanting ions into the portion defined as the n + type source region 4 in the cell portion RC. In the present embodiment, the entire upper part of the p-type base region 3 is the ion implantation layer 31. The conductive type of the portion of the ion-implanted layer 31 located on the side surface of the gate trench 6 is arbitrary, but here, it is conductive by ion-implanting a p-type impurity into the epitaxially grown n + type source region 4. The mold is inverted to form a p-type.
また、図３および図４に示すように、繋ぎ部ＲＪに延設されたトレンチゲート構造の先端部において、ゲート電極８からゲートライナー８ｂが引き出されている。そして、ゲートライナー８ｂやイオン注入層３１の表面にも層間絶縁膜１０が形成されており、繋ぎ部ＲＪにおけるセル部ＲＣから離れた位置の層間絶縁膜１０の上に、図１に示すゲートパッド３２やホール引き抜き用の引抜パッド３３が形成されている。ゲートパッド３２は、層間絶縁膜１０に形成された図示しないコンタクトホールを通じて、ゲートライナー８ｂに電気的に接続されている。引抜パッド３３も、層間絶縁膜１０に形成された図示しないコンタクトホールを通じてｐ型繋ぎ層３０やイオン注入層３１と電気的に接続されている。
Further, as shown in FIGS. 3 and 4, the gate liner 8b is pulled out from the gate electrode 8 at the tip of the trench gate structure extending to the connecting portion RJ. An interlayer insulating film 10 is also formed on the surfaces of the gate liner 8b and the ion implantation layer 31, and the gate pad shown in FIG. 1 is placed on the interlayer insulating film 10 at a position away from the cell portion RC in the connecting portion RJ. 32 and a drawing pad 33 for pulling out a hole are formed. The gate pad 32 is electrically connected to the gate liner 8b through a contact hole (not shown) formed in the interlayer insulating film 10. The drawing pad 33 is also electrically connected to the p-type connecting layer 30 and the ion implantation layer 31 through a contact hole (not shown) formed in the interlayer insulating film 10.
上記したように、繋ぎ部ＲＪ内において、ゲートトレンチ６の側面および先端部には傾斜部が構成されている。具体的には、ゲートトレンチ６のうちイオン注入層３１と対応する位置が傾斜部とされており、概ねイオン注入層３１とｐ型ベース領域３との境界位置の深さまで傾斜部となっている。本実施形態の場合、繋ぎ部ＲＪ内の全域にイオン注入層３１を形成しているが、少なくともセル部ＲＣの外側において、ゲートトレンチ６の側面や先端部を構成している部分にイオン注入層３１が形成されていれば良い。このようにすれば、ゲートトレンチ６の側面および先端部のうちゲートライナー８ｂと重なる位置にすべて傾斜部が形成された状態にできる。
As described above, in the connecting portion RJ, inclined portions are formed on the side surface and the tip portion of the gate trench 6. Specifically, the position of the gate trench 6 corresponding to the ion implantation layer 31 is defined as an inclined portion, and the inclined portion extends to the depth of the boundary position between the ion implantation layer 31 and the p-type base region 3. .. In the case of the present embodiment, the ion implantation layer 31 is formed in the entire area inside the connecting portion RJ, but at least outside the cell portion RC, the ion implantation layer is formed on the side surface and the tip portion of the gate trench 6. It suffices if 31 is formed. In this way, it is possible to form a state in which all the inclined portions are formed on the side surface and the tip portion of the gate trench 6 at positions overlapping with the gate liner 8b.
また、イオン注入層３１は、繋ぎ部ＲＪの外縁部の全周に設けられていることから、図２に示すようにメサ部ＲＭのうちの外縁部、つまり凹部２０との境界位置は、上から順にイオン注入層３１、ｐ型ベース領域３、ｎ型電流分散層２ａで構成されることになる。このため、イオン注入層３１がｎ＋型ソース領域４のままとされていた場合のような、上から順にｎ＋型ソース領域４、ｐ型ベース領域３、ｎ型電流分散層２ａで構成されるｎｐｎ構造にはならないようにできる。
Further, since the ion implantation layer 31 is provided on the entire circumference of the outer edge portion of the connecting portion RJ, as shown in FIG. 2, the boundary position with the outer edge portion of the mesa portion RM, that is, the recess 20 is above. It is composed of the ion implantation layer 31, the p-type base region 3, and the n-type current dispersion layer 2a in this order. Therefore, the ion implantation layer 31 is composed of the n + type source region 4, the p-type base region 3, and the n-type current dispersion layer 2a in this order from the top, as in the case where the n + type source region 4 is left as it is. The npn structure can be prevented.
以上のようにして、本実施形態にかかるＳｉＣ半導体装置が構成されている。このように構成されるＳｉＣ半導体装置は、ＭＯＳＦＥＴをオンするときには、ゲート電極８への印加電圧を制御することでゲートトレンチ６の側面に位置するｐ型ベース領域３の表面部にチャネル領域を形成する。これにより、ｎ＋型ソース領域４およびｎ－型不純物層２を介して、ソース電極９およびドレイン電極１１の間に電流を流す。
As described above, the SiC semiconductor device according to the present embodiment is configured. When the MOSFET is turned on, the SiC semiconductor device configured in this way forms a channel region on the surface portion of the p-type base region 3 located on the side surface of the gate trench 6 by controlling the voltage applied to the gate electrode 8. To do. As a result, a current is passed between the source electrode 9 and the drain electrode 11 via the n + type source region 4 and the n − type impurity layer 2.
また、ＭＯＳＦＥＴのオフ時には、高電圧が印加されたとしても、トレンチゲート構造よりも深い位置まで形成されたｐ型ディープ層５によってゲートトレンチ底部への電界の入り込みが抑制されて、ゲートトレンチ底部での電界集中が緩和される。これにより、ゲート絶縁膜７の破壊が防止される。
Further, when the MOSFET is off, even if a high voltage is applied, the p-type deep layer 5 formed to a position deeper than the trench gate structure suppresses the entry of the electric field into the bottom of the gate trench, and the bottom of the gate trench Electric field concentration is relaxed. As a result, the gate insulating film 7 is prevented from being destroyed.
さらに、繋ぎ部ＲＪでは、等電位線のせり上がりが抑制され、ガードリング部ＲＧ側に向かうようにされる。また、ガードリング部ＲＧにおいて、ｐ型ガードリング２１によって等電位線をその間隔が外周方向に向かって広がるようにしながら終端させられるようになり、ガードリング部ＲＧでも所望の耐圧を得ることができる。
Further, in the connecting portion RJ, the rising of the equipotential lines is suppressed, and the joint portion RJ is directed toward the guard ring portion RG side. Further, in the guard ring portion RG, the equipotential lines can be terminated by the p-type guard ring 21 so that the intervals thereof spread toward the outer peripheral direction, and the guard ring portion RG can also obtain a desired withstand voltage. ..
そして、このような構造のＳｉＣ半導体装置において、トレンチゲート構造を構成するゲートトレンチ６の入口側の側面が、セル部ＲＣ内ではｎ＋型基板１の主表面に対して垂直に切り立っているが、繋ぎ部ＲＪ内では傾斜部となっている。これにより、ゲート絶縁膜７が、セル部ＲＣ内では厚みの薄い薄膜部７ａとなっていても、繋ぎ部ＲＪにおいては厚みの厚い厚膜部７ｂにできる。したがって、トレンチゲート構造の長手方向の両端位置で大きな電界が加わることでゲート絶縁膜７が破壊されることを抑制でき、ゲート絶縁膜７の寿命低下を抑制することが可能となる。
Then, in the SiC semiconductor device having such a structure, the side surface on the inlet side of the gate trench 6 constituting the trench gate structure stands out perpendicularly to the main surface of the n + type substrate 1 in the cell portion RC. , It is an inclined part in the connecting part RJ. As a result, even if the gate insulating film 7 is a thin thin film portion 7a in the cell portion RC, it can be formed into a thick thick film portion 7b in the connecting portion RJ. Therefore, it is possible to prevent the gate insulating film 7 from being destroyed by applying a large electric field at both ends of the trench gate structure in the longitudinal direction, and it is possible to suppress a decrease in the life of the gate insulating film 7.
また、縦型ＭＯＳＦＥＴのアバランシェブレークダウン時にセル部ＲＣの外周からのホールの引き抜きが良好に行われないと、ＳｉＣ半導体装置の耐量を低下させてしまう。仮に、繋ぎ部ＲＪに、イオン注入層３１を備えておらず、半導体のうちの最も上層の部分がセル部ＲＣと同様にｎ＋型ソース領域４が形成された構造になっていると、ｐ型ベース領域３との間にＰＮ接合が形成された構造になるため、ホールの引き抜きが行えない。
Further, if the holes are not properly pulled out from the outer periphery of the cell portion RC at the time of the avalanche breakdown of the vertical MOSFET, the withstand capacity of the SiC semiconductor device is lowered. If the connecting portion RJ is not provided with the ion implantation layer 31, and the uppermost portion of the semiconductor has a structure in which the n + type source region 4 is formed as in the cell portion RC, p. Since the structure is such that a PN junction is formed with the mold base region 3, the hole cannot be pulled out.
これに対して、本実施形態では、半導体のうちの最も上層の部分がｐ型層で構成されたイオン注入層３１となっている。このため、層間絶縁膜１０の上に形成した引抜パッド３３とイオン注入層３１とを電気的に接続することで、ｐ型ベース領域３からイオン注入層３１を抜け、引抜パッド３３を通じてホールを引き抜くことが可能となる。よって、縦型ＭＯＳＦＥＴのアバランシェブレークダウン時にセル部ＲＣの外周からのホールの引き抜きが良好に行われ、ＳｉＣ半導体装置の耐量の低下を抑制することが可能となる。
On the other hand, in the present embodiment, the uppermost portion of the semiconductor is an ion implantation layer 31 composed of a p-type layer. Therefore, by electrically connecting the extraction pad 33 formed on the interlayer insulating film 10 and the ion implantation layer 31, the ion implantation layer 31 is removed from the p-type base region 3 and the hole is extracted through the extraction pad 33. It becomes possible. Therefore, when the avalanche breakdown of the vertical MOSFET is performed, the holes are satisfactorily pulled out from the outer periphery of the cell portion RC, and it is possible to suppress a decrease in the withstand capacity of the SiC semiconductor device.
さらに、本実施形態のＳｉＣ半導体装置では、メサ部ＲＭと凹部２０との境界位置が、上から順にイオン注入層３１、ｐ型ベース領域３、ｎ型電流分散層２ａで構成されるようにしている。つまり、イオン注入層３１がｎ＋型ソース領域４のままとされていた場合のような、上から順にｎ＋型ソース領域４、ｐ型ベース領域３、ｎ型電流分散層２ａで構成されるｎｐｎ構造にはならないようにしている。
Further, in the SiC semiconductor device of the present embodiment, the boundary position between the mesa portion RM and the recess 20 is configured by the ion implantation layer 31, the p-type base region 3, and the n-type current dispersion layer 2a in this order from the top. There is. That is, the ion implantation layer 31 is composed of the n + type source region 4, the p-type base region 3, and the n-type current dispersion layer 2a in this order from the top, as in the case where the n + type source region 4 is left as it is. It is designed so that it does not have an npn structure.
後述するように、凹部２０やゲートトレンチ６が形成されてからゲート絶縁膜７やゲート電極８を形成しているため、ゲートトレンチ６内だけでなく凹部２０内にも同様のトレンチゲート構造が形成されることになる。このため、凹部２０内に残ったゲート電極８の材料となるＰｏｌｙ－Ｓｉについては後で除去している。しかしながら、図２に示したように、Ｐｏｌｙ－Ｓｉの残渣８ａが凹部２０とメサ部ＲＭの境界位置に残ることがある。
As will be described later, since the gate insulating film 7 and the gate electrode 8 are formed after the recess 20 and the gate trench 6 are formed, a similar trench gate structure is formed not only in the gate trench 6 but also in the recess 20. Will be done. Therefore, Poly—Si, which is the material of the gate electrode 8 remaining in the recess 20, is later removed. However, as shown in FIG. 2, the Poly—Si residue 8a may remain at the boundary position between the recess 20 and the mesa portion RM.
このような構造となった場合、メサ部ＲＭと凹部２０との境界部がｎｐｎ構造になっていると、フローティング電位となっている残渣８ａが外来電荷等の原因によって電位が上がると、ｐ型ベース領域３に反転型チャネルが形成されてしまう。このため、ｎ＋型ソース領域４と電気的に接続されたソース電極９などを通じてリーク電流が流れてしまうという課題を発生させ得る。
In the case of such a structure, if the boundary portion between the mesa portion RM and the recess 20 has an npn structure, the residue 8a having a floating potential rises in potential due to an external charge or the like, and is p-type. An inverted channel is formed in the base region 3. Therefore, there may be a problem that a leak current flows through a source electrode 9 or the like electrically connected to the n + type source region 4.
しかしながら、本実施形態のようにｐ型層で構成されたイオン注入層３１を備えることで、ｎｐｎ構造が構成されないようにできるため残渣８ａがあってもリーク電流が流れることを抑制することが可能となる。
However, by providing the ion implantation layer 31 composed of the p-type layer as in the present embodiment, it is possible to prevent the npn structure from being formed, so that it is possible to suppress the leakage current from flowing even if there is a residue 8a. It becomes.
続いて、本実施形態に係るＳｉＣ半導体装置の製造方法について図６Ａ～図６Ｈを参照して説明する。
Subsequently, a method for manufacturing the SiC semiconductor device according to the present embodiment will be described with reference to FIGS. 6A to 6H.
〔図６Ａに示す工程〕
まず、半導体基板として、ｎ＋型基板１を用意する。そして、このｎ＋型基板１の主表面上にＳｉＣからなるｎ－型不純物層２をエピタキシャル成長させる。 [Step shown in FIG. 6A]
First, an n + type substrate 1 is prepared as the semiconductor substrate. Then, an n -type impurity layer 2 made of SiC is epitaxially grown on the main surface of the n + type substrate 1.
まず、半導体基板として、ｎ＋型基板１を用意する。そして、このｎ＋型基板１の主表面上にＳｉＣからなるｎ－型不純物層２をエピタキシャル成長させる。 [Step shown in FIG. 6A]
First, an n + type substrate 1 is prepared as the semiconductor substrate. Then, an n -
〔図６Ｂに示す工程〕
続いて、ｎ－型不純物層２の上に、ｎ型電流分散層２ａ、ｐ型ベース領域３およびｎ＋型ソース領域４を順にエピタキシャル成長させる。このように、ｎ＋型ソース領域４をエピタキシャル成長によって形成しているため、ｐ型ベース領域３とｎ＋型ソース領域４それぞれに厚みのバラツキが分配されることから、ｐ型ベース領域３の厚みのバラツキを小さくでき、閾値Ｖｔのバラツキを抑制できる。 [Step shown in FIG. 6B]
Subsequently, the n-typecurrent dispersion layer 2a, the p-type base region 3 and the n + -type source region 4 are epitaxially grown on the n - type impurity layer 2 in this order. Since the n + type source region 4 is formed by epitaxial growth in this way, the thickness variation of the p-type base region 3 and the n + type source region 4 is distributed to each of the p-type base region 3 and the thickness of the p-type base region 3. The variation of the threshold value can be reduced, and the variation of the threshold value Vt can be suppressed.
続いて、ｎ－型不純物層２の上に、ｎ型電流分散層２ａ、ｐ型ベース領域３およびｎ＋型ソース領域４を順にエピタキシャル成長させる。このように、ｎ＋型ソース領域４をエピタキシャル成長によって形成しているため、ｐ型ベース領域３とｎ＋型ソース領域４それぞれに厚みのバラツキが分配されることから、ｐ型ベース領域３の厚みのバラツキを小さくでき、閾値Ｖｔのバラツキを抑制できる。 [Step shown in FIG. 6B]
Subsequently, the n-type
そして、ｎ＋型ソース領域４の上に図示しないマスクを配置したのち、マスクのうちのイオン注入層３１の形成予定領域を開口させる。そして、そのマスクを用いてｐ型不純物、例えばアルミニウムをイオン注入することで、イオン注入層３１を形成する。このとき、イオン注入された部分の結晶構造に歪みが入るなどのダメージが生じた状態になる。
Then, after arranging a mask (not shown) on the n + type source region 4, the region to be formed of the ion implantation layer 31 in the mask is opened. Then, the ion implantation layer 31 is formed by ion-implanting p-type impurities such as aluminum using the mask. At this time, the crystal structure of the ion-implanted portion is in a state of being damaged such as being distorted.
〔図６Ｃに示す工程〕
次に、ｎ＋型ソース領域４やイオン注入層３１の表面に図示しないマスクを配置し、マスクのうちのｐ型ディープ層５、ｐ型ガードリング２１およびｐ型繋ぎ層３０の形成予定領域を開口させる。そして、マスクを用いてＲＩＥ（Reactive IonEtching）などの異方性エッチングを行うことにより、トレンチ５ａ、２１ａ、３０ａを形成する。 [Step shown in FIG. 6C]
Next, a mask (not shown) is placed on the surface of the n +type source region 4 and the ion implantation layer 31, and the regions to be formed of the p-type deep layer 5, the p-type guard ring 21, and the p-type connecting layer 30 of the mask are formed. Open it. Then, trenches 5a, 21a, and 30a are formed by performing anisotropic etching such as RIE (Reactive IonEtching) using a mask.
次に、ｎ＋型ソース領域４やイオン注入層３１の表面に図示しないマスクを配置し、マスクのうちのｐ型ディープ層５、ｐ型ガードリング２１およびｐ型繋ぎ層３０の形成予定領域を開口させる。そして、マスクを用いてＲＩＥ（Reactive IonEtching）などの異方性エッチングを行うことにより、トレンチ５ａ、２１ａ、３０ａを形成する。 [Step shown in FIG. 6C]
Next, a mask (not shown) is placed on the surface of the n +
〔図６Ｄに示す工程〕
マスクを除去してｐ型層を成膜したのち、ｐ型層のうちｎ＋型ソース領域４の表面より上に形成された部分が取り除かれるようにエッチバックし、ｐ型ディープ層５、ｐ型ガードリング２１およびｐ型繋ぎ層３０を形成する。 [Step shown in FIG. 6D]
After removing the mask to form a p-type layer, etching back is performed so that the portion of the p-type layer formed above the surface of the n +type source region 4 is removed, and the p-type deep layer 5 and p. The mold guard ring 21 and the p-type connecting layer 30 are formed.
マスクを除去してｐ型層を成膜したのち、ｐ型層のうちｎ＋型ソース領域４の表面より上に形成された部分が取り除かれるようにエッチバックし、ｐ型ディープ層５、ｐ型ガードリング２１およびｐ型繋ぎ層３０を形成する。 [Step shown in FIG. 6D]
After removing the mask to form a p-type layer, etching back is performed so that the portion of the p-type layer formed above the surface of the n +
このとき、埋込エピにより、トレンチ５ａ、２１ａ、３０ａ内にｐ型層が埋め込まれることになるが、トレンチ５ａ、２１ａ、３０ａを同じ幅で形成していることから、ｐ型層の表面に形状異常が発生したり凹凸が発生することを抑制できる。したがって、各トレンチ５ａ、２１ａ、３０ａ内にｐ型層を確実に埋め込むことが可能になると共に、ｐ型層の表面は凹凸が少ない平坦な形状となる。
At this time, the p-type layer is embedded in the trenches 5a, 21a, and 30a due to the embedding epi, but since the trenches 5a, 21a, and 30a are formed with the same width, the surface of the p-type layer is formed. It is possible to suppress the occurrence of shape abnormalities and unevenness. Therefore, the p-type layer can be reliably embedded in each of the trenches 5a, 21a, and 30a, and the surface of the p-type layer has a flat shape with few irregularities.
なお、上記したように、図６Ｂに示す工程において、イオン注入層３１を形成するようにしているが、これらｐ型ディープ層５、ｐ型ガードリング２１およびｐ型繋ぎ層３０を形成した後にイオン注入層３１を形成するようにしても良い。このようにすれば、エピタキシャル成長時の高温によってダメージ修復が行われたり、エッチバック時にダメージが生じているイオン注入層３１が過剰にエッチングされたりすることを抑制できる。
As described above, the ion implantation layer 31 is formed in the step shown in FIG. 6B. After forming the p-type deep layer 5, the p-type guard ring 21, and the p-type connecting layer 30, ions are formed. The implantation layer 31 may be formed. In this way, it is possible to prevent damage repair from being performed due to the high temperature during epitaxial growth and excessive etching of the ion-implanted layer 31 that is damaged during etching back.
〔図６Ｅに示す工程〕
ｎ＋型ソース領域４などの上に図示しないマスクを形成したのち、マスクのうちのゲートトレンチ６の形成予定領域を開口させる。そして、マスクを用いてＲＩＥなどの異方性エッチングを行うことで、ゲートトレンチ６を形成する。 [Step shown in FIG. 6E]
After forming a mask (not shown) on the n +type source region 4 or the like, the region to be formed of the gate trench 6 in the mask is opened. Then, the gate trench 6 is formed by performing anisotropic etching such as RIE using a mask.
ｎ＋型ソース領域４などの上に図示しないマスクを形成したのち、マスクのうちのゲートトレンチ６の形成予定領域を開口させる。そして、マスクを用いてＲＩＥなどの異方性エッチングを行うことで、ゲートトレンチ６を形成する。 [Step shown in FIG. 6E]
After forming a mask (not shown) on the n +
さらに、マスクを除去したのち、再び図示しないマスクを形成し、マスクのうちの凹部２０の形成予定領域を開口させる。そして、マスクを用いてＲＩＥなどの異方性エッチングを行うことで凹部２０を形成する。これにより、凹部２０が形成された位置において、ｎ＋型ソース領域４およびｐ型ベース領域３を貫通してｎ型電流分散層２ａが露出させられ、ｎ型電流分散層２ａの表面から複数本のｐ型ガードリング２１が配置された構造が構成される。
Further, after removing the mask, a mask (not shown) is formed again, and a region to be formed of the recess 20 in the mask is opened. Then, the recess 20 is formed by performing anisotropic etching such as RIE using a mask. As a result, at the position where the recess 20 is formed, the n-type current dispersion layer 2a is exposed through the n + type source region 4 and the p-type base region 3, and a plurality of n-type current dispersion layers 2a are exposed from the surface of the n-type current dispersion layer 2a. A structure in which the p-type guard ring 21 is arranged is configured.
なお、ここではゲートトレンチ６と凹部２０を別々のマスクを用いた別工程として形成したが、同じマスクを用いて同時に形成することもできる。
Although the gate trench 6 and the recess 20 are formed as separate steps using separate masks here, they can also be formed at the same time using the same mask.
〔図６Ｆに示す工程〕
マスクを除去した後、熱酸化を行うことによって、ゲート絶縁膜７を形成し、ゲート絶縁膜７によってゲートトレンチ６の内壁面上およびｎ＋型ソース領域４の表面上を覆う。このとき、イオン注入のダメージを受けていないｎ＋型ソース領域４についてはｐ型ベース領域３と同程度熱酸化されることになるが、ダメージが生じているイオン注入層３１についてはｐ型ベース領域３よりも熱酸化されやすくなる。このため、セル部ＲＣではゲートトレンチ６の入口側がｎ＋型基板１の主表面に対してほぼ垂直に切り立ったままの状態となり、繋ぎ部ＲＪでは、ゲートトレンチ６の入口側が傾斜部となる。したがって、ゲートトレンチ６の入口側の角部においてゲート絶縁膜７は、セル部ＲＣでは薄くなった薄膜部７ａとなるが、繋ぎ部ＲＪではそれよりも厚い厚膜部７ｂとなる。 [Step shown in FIG. 6F]
After removing the mask, thegate insulating film 7 is formed by thermal oxidation, and the gate insulating film 7 covers the inner wall surface of the gate trench 6 and the surface of the n + type source region 4. At this time, the n + type source region 4 that has not been damaged by ion implantation is thermally oxidized to the same extent as the p-type base region 3, but the damaged ion implantation layer 31 is the p-type base. It is more susceptible to thermal oxidation than region 3. Therefore, in the cell portion RC, the inlet side of the gate trench 6 remains erected substantially perpendicular to the main surface of the n + type substrate 1, and in the connecting portion RJ, the inlet side of the gate trench 6 becomes an inclined portion. Therefore, at the corner portion on the inlet side of the gate trench 6, the gate insulating film 7 becomes a thin thin film portion 7a in the cell portion RC, but becomes a thicker film portion 7b in the connecting portion RJ.
マスクを除去した後、熱酸化を行うことによって、ゲート絶縁膜７を形成し、ゲート絶縁膜７によってゲートトレンチ６の内壁面上およびｎ＋型ソース領域４の表面上を覆う。このとき、イオン注入のダメージを受けていないｎ＋型ソース領域４についてはｐ型ベース領域３と同程度熱酸化されることになるが、ダメージが生じているイオン注入層３１についてはｐ型ベース領域３よりも熱酸化されやすくなる。このため、セル部ＲＣではゲートトレンチ６の入口側がｎ＋型基板１の主表面に対してほぼ垂直に切り立ったままの状態となり、繋ぎ部ＲＪでは、ゲートトレンチ６の入口側が傾斜部となる。したがって、ゲートトレンチ６の入口側の角部においてゲート絶縁膜７は、セル部ＲＣでは薄くなった薄膜部７ａとなるが、繋ぎ部ＲＪではそれよりも厚い厚膜部７ｂとなる。 [Step shown in FIG. 6F]
After removing the mask, the
なお、ここでは、熱酸化を行うことで、繋ぎ部ＲＪにおいてゲートトレンチ６の入口側が傾斜部となるようにしたが、熱処理を行えばその形状とすることができる。例えば、犠牲酸化などを行っても、繋ぎ部ＲＪにおけるイオン注入層３１の方がセル部ＲＣにおけるｎ＋型ソース領域４よりも酸化が促進されるため、繋ぎ部ＲＪにおいてゲートトレンチ６の入口側が傾斜部となる。したがって、熱酸化によってゲート絶縁膜７を形成しない場合、例えばＣＶＤ（chemical vapordeposition）などで形成したとしても、ゲート絶縁膜７について、セル部ＲＣでは薄くなった薄膜部７ａとなり、繋ぎ部ＲＪではそれよりも厚い厚膜部７ｂとなるようにできる。
Here, the inlet side of the gate trench 6 is made to be an inclined portion in the connecting portion RJ by performing thermal oxidation, but the shape can be obtained by performing heat treatment. For example, even if sacrificial oxidation is performed, the ion implantation layer 31 in the connecting portion RJ promotes oxidation more than the n + type source region 4 in the cell portion RC, so that the inlet side of the gate trench 6 in the connecting portion RJ is It becomes an inclined part. Therefore, when the gate insulating film 7 is not formed by thermal oxidation, for example, even if it is formed by CVD (chemical vapor deposition), the gate insulating film 7 becomes a thin thin film portion 7a in the cell portion RC, and it becomes a thin film portion 7a in the connecting portion RJ. The thick film portion 7b can be made thicker than that.
この後、ｐ型不純物もしくはｎ型不純物がドープされたＰｏｌｙ－Ｓｉをデポジションした後、これをエッチバックし、少なくともゲートトレンチ６内にＰｏｌｙ－Ｓｉを残すことでゲート電極８を形成する。これにより、トレンチゲート構造が構成される。
After that, Poly-Si doped with p-type impurities or n-type impurities is deposited, and then etched back to form the gate electrode 8 by leaving Poly-Si at least in the gate trench 6. As a result, a trench gate structure is constructed.
なお、トレンチゲート構造については、ゲートトレンチ６内にのみ形成すれば良いが、メサ部ＲＭを構成するために凹部２０を形成しているため、この凹部２０内にも同様の構造が形成される。この部分については、Ｐｏｌｙ－Ｓｉをエッチバックすることで除去するようにしているが、メサ部ＲＭと凹部２０との境界位置において残渣８ａが残ることがある。
The trench gate structure may be formed only in the gate trench 6, but since the recess 20 is formed to form the mesa portion RM, a similar structure is also formed in the recess 20. .. This portion is removed by etchingback Poly-Si, but a residue 8a may remain at the boundary position between the mesa portion RM and the recess 20.
〔図６Ｇに示す工程〕
ゲート電極８およびゲート絶縁膜７の表面を覆うように、例えば酸化膜などによって構成される層間絶縁膜１０を形成する。そして、層間絶縁膜１０の表面上に図示しないマスクを形成したのち、マスクのうち各ゲート電極８の間に位置する部分、つまりｐ型ディープ層５と対応する部分およびその近傍を開口させる。この後、マスクを用いて層間絶縁膜１０をパターニングすることでｐ型ディープ層５、ｎ＋型ソース領域４を露出させるコンタクトホールを形成する。また、本図とは異なる断面において、ゲート電極８およびイオン注入層３１を部分的に露出させるコンタクトホールも形成する。 [Step shown in FIG. 6G]
An interlayer insulatingfilm 10 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 8 and the gate insulating film 7. Then, after forming a mask (not shown) on the surface of the interlayer insulating film 10, a portion of the mask located between the gate electrodes 8, that is, a portion corresponding to the p-type deep layer 5 and its vicinity are opened. After that, the interlayer insulating film 10 is patterned using a mask to form a contact hole that exposes the p-type deep layer 5 and the n + -type source region 4. Further, a contact hole for partially exposing the gate electrode 8 and the ion implantation layer 31 is also formed in a cross section different from that shown in this figure.
ゲート電極８およびゲート絶縁膜７の表面を覆うように、例えば酸化膜などによって構成される層間絶縁膜１０を形成する。そして、層間絶縁膜１０の表面上に図示しないマスクを形成したのち、マスクのうち各ゲート電極８の間に位置する部分、つまりｐ型ディープ層５と対応する部分およびその近傍を開口させる。この後、マスクを用いて層間絶縁膜１０をパターニングすることでｐ型ディープ層５、ｎ＋型ソース領域４を露出させるコンタクトホールを形成する。また、本図とは異なる断面において、ゲート電極８およびイオン注入層３１を部分的に露出させるコンタクトホールも形成する。 [Step shown in FIG. 6G]
An interlayer insulating
〔図６Ｈに示す工程〕
層間絶縁膜１０の表面上に例えば複数の金属の積層構造により構成される電極材料を形成する。そして、電極材料をパターニングすることで、ソース電極９や引抜パッド３３を形成する。また、本図とは異なる断面においてゲートパッド３２も形成する。なお、本図とは異なる断面において各セルのゲート電極８に繋がるゲートライナー８ｂが設けられている。そのゲートライナー８ｂが延設された位置において層間絶縁膜１０にコンタクトホールが開けられることで、ゲートパッド３２とゲート電極８との電気的接続が行われるようになっている。同様に、本図とは異なる断面においてイオン注入層３１に繋がるコンタクトホールが形成されており、そのコンタクトホールを通じて引抜パッド３３とイオン注入層３１との電気的接続が行われるようになっている。 [Step shown in FIG. 6H]
An electrode material composed of, for example, a laminated structure of a plurality of metals is formed on the surface of theinterlayer insulating film 10. Then, the source electrode 9 and the drawing pad 33 are formed by patterning the electrode material. Further, the gate pad 32 is also formed in a cross section different from that shown in this figure. A gate liner 8b connected to the gate electrode 8 of each cell is provided in a cross section different from that shown in this figure. A contact hole is opened in the interlayer insulating film 10 at the position where the gate liner 8b is extended, so that the gate pad 32 and the gate electrode 8 are electrically connected. Similarly, a contact hole connected to the ion implantation layer 31 is formed in a cross section different from that in the drawing, and the extraction pad 33 and the ion implantation layer 31 are electrically connected through the contact hole.
層間絶縁膜１０の表面上に例えば複数の金属の積層構造により構成される電極材料を形成する。そして、電極材料をパターニングすることで、ソース電極９や引抜パッド３３を形成する。また、本図とは異なる断面においてゲートパッド３２も形成する。なお、本図とは異なる断面において各セルのゲート電極８に繋がるゲートライナー８ｂが設けられている。そのゲートライナー８ｂが延設された位置において層間絶縁膜１０にコンタクトホールが開けられることで、ゲートパッド３２とゲート電極８との電気的接続が行われるようになっている。同様に、本図とは異なる断面においてイオン注入層３１に繋がるコンタクトホールが形成されており、そのコンタクトホールを通じて引抜パッド３３とイオン注入層３１との電気的接続が行われるようになっている。 [Step shown in FIG. 6H]
An electrode material composed of, for example, a laminated structure of a plurality of metals is formed on the surface of the
この後の工程については図示しないが、ｎ＋型基板１の裏面側にドレイン電極１１を形成するなどの工程を行うことで、本実施形態にかかるＳｉＣ半導体装置が完成する。
Although the subsequent steps are not shown, the SiC semiconductor device according to the present embodiment is completed by performing steps such as forming the drain electrode 11 on the back surface side of the n + type substrate 1.
以上説明したように、本実施形態では、トレンチゲート構造を構成するゲートトレンチ６の入口側の側面が、セル部ＲＣ内ではｎ＋型基板１の主表面に対して垂直に切り立っているが、繋ぎ部ＲＪ内では傾斜部となっている。これにより、ゲート絶縁膜７が、セル部ＲＣ内では厚みの薄い薄膜部７ａとなっていても、繋ぎ部ＲＪにおいては厚みの厚い厚膜部７ｂにできる。したがって、トレンチゲート構造の長手方向の両端位置で大きな電界が加わることでゲート絶縁膜７が破壊されないようにでき、ゲート絶縁膜７の寿命低下を抑制することが可能となる。そして、ｎ＋型ソース領域４をエピタキシャル成長によって形成しているため、ｐ型ベース領域３とｎ＋型ソース領域４それぞれに厚みのバラツキが分配されることから、ｐ型ベース領域３の厚みのバラツキを小さくでき、閾値Ｖｔのバラツキを抑制できる。よって、閾値Ｖｔのバラツキの抑制が図れると共に、ゲート寿命の低下を抑制できる構造のＳｉＣ半導体装置にできる。
As described above, in the present embodiment, the side surface of the gate trench 6 constituting the trench gate structure on the inlet side is steeply formed in the cell portion RC perpendicular to the main surface of the n + type substrate 1. It is an inclined part in the connecting part RJ. As a result, even if the gate insulating film 7 is a thin thin film portion 7a in the cell portion RC, it can be formed into a thick thick film portion 7b in the connecting portion RJ. Therefore, it is possible to prevent the gate insulating film 7 from being destroyed by applying a large electric field at both ends of the trench gate structure in the longitudinal direction, and it is possible to suppress a decrease in the life of the gate insulating film 7. Since the n + type source region 4 is formed by epitaxial growth, the thickness variation is distributed to each of the p-type base region 3 and the n + type source region 4, so that the thickness variation of the p-type base region 3 is distributed. Can be reduced, and variation in the threshold value Vt can be suppressed. Therefore, the SiC semiconductor device having a structure capable of suppressing the variation in the threshold value Vt and suppressing the decrease in the gate life can be obtained.
（他の実施形態）
本開示は、上記した実施形態に準拠して記述されたが、当該実施形態に限定されるものではなく、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 (Other embodiments)
Although the present disclosure has been described in accordance with the above-described embodiment, the present disclosure is not limited to the embodiment, and includes various modifications and modifications within an equal range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are also within the scope of the present disclosure.
本開示は、上記した実施形態に準拠して記述されたが、当該実施形態に限定されるものではなく、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 (Other embodiments)
Although the present disclosure has been described in accordance with the above-described embodiment, the present disclosure is not limited to the embodiment, and includes various modifications and modifications within an equal range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are also within the scope of the present disclosure.
（１）上記実施形態では、ｎ＋型ソース領域４をエピタキシャル成長層のみで構成したが、ｎ＋型ソース領域４をエピタキシャル成長層で構成しつつも、表層部にｎ型不純物濃度を濃くするためにイオン注入した領域を備えていても良い。この場合でも、ｎ＋型ソース領域４とｐ型ベース領域３との境界位置やこれらの厚みは、エピタキシャル成長によって規定されるため、閾値Ｖｔのバラツキ抑制効果は得られる。また、このような構造とする場合、ｎ＋型ソース領域４の表層部においては、ゲートトレンチ６の側面が傾斜した状態になり得る。しかし、ｎ＋型ソース領域４の表層部にしかイオン注入がなされていないため、ゲートトレンチ６の側面がｎ＋型ソース領域４で構成されている部分よりもイオン注入層３１で構成されている部分の方がより深い位置まで傾斜部となる。そして、ｎ＋型ソース領域４の下方位置、つまりｐ型ベース領域３と接している部分では、ゲートトレンチ６の側面がｎ＋型基板１の主表面に対して垂直に切り立った構造になる。
(1) In the above embodiment, the n + type source region 4 is composed of only the epitaxial growth layer, but in order to increase the concentration of n-type impurities on the surface layer portion while the n + type source region 4 is composed of the epitaxial growth layer. It may include an ion-implanted region. Even in this case, since the boundary position between the n + type source region 4 and the p-type base region 3 and their thickness are defined by epitaxial growth, the effect of suppressing the variation of the threshold value Vt can be obtained. Further, in the case of such a structure, the side surface of the gate trench 6 may be inclined in the surface layer portion of the n + type source region 4. However, since ion implantation is performed only on the surface layer portion of the n + type source region 4, the side surface of the gate trench 6 is composed of the ion implantation layer 31 rather than the portion composed of the n + type source region 4. The part becomes an inclined part to a deeper position. Then, at the lower position of the n + type source region 4, that is, the portion in contact with the p-type base region 3, the side surface of the gate trench 6 has a structure that stands perpendicular to the main surface of the n + type substrate 1.
（２）上記実施形態では、縦型のパワー素子としてｎチャネルタイプの反転型のトレンチゲート構造のＭＯＳＦＥＴを例に挙げて説明した。しかしながら、上記各実施形態はトレンチゲート構造の縦型半導体素子の一例を示したに過ぎず、半導体基板の表面側に設けられる第１電極と裏面側に設けられる第２電極との間に電流を流す縦型半導体素子であれば、他の構造もしくは導電型のものであっても良い。
(2) In the above embodiment, a MOSFET having an n-channel type inverted trench gate structure as an example of a vertical power element has been described. However, each of the above embodiments is merely an example of a vertical semiconductor element having a trench gate structure, and a current is applied between the first electrode provided on the front surface side and the second electrode provided on the back surface side of the semiconductor substrate. As long as it is a vertical semiconductor element to flow, it may have another structure or a conductive type.
例えば、上記第１実施形態等では、第１導電型をｎ型、第２導電型をｐ型としたｎチャネルタイプのＭＯＳＦＥＴを例に挙げて説明したが、各構成要素の導電型を反転させたｐチャネルタイプのＭＯＳＦＥＴとしても良い。また、上記説明では、半導体素子としてＭＯＳＦＥＴを例に挙げて説明したが、同様の構造のＩＧＢＴに対しても本開示を適用することができる。ＩＧＢＴは、上記各実施形態に対してｎ＋型基板１の導電型をｎ型からｐ型に変更するだけであり、その他の構造や製造方法に関しては上記各実施形態と同様である。
For example, in the first embodiment and the like, an n-channel type MOSFET in which the first conductive type is n-type and the second conductive type is p-type has been described as an example, but the conductive type of each component is inverted. It may be a p-channel type MOSFET. Further, in the above description, MOSFET is taken as an example as a semiconductor element, but the present disclosure can be applied to an IGBT having a similar structure. The IGBT only changes the conductive type of the n + type substrate 1 from the n type to the p type for each of the above embodiments, and is the same as each of the above embodiments in terms of other structures and manufacturing methods.
（３）また、上記実施形態では、トレンチゲート構造を単なる直線状部分のみで形成している。これに対して、図７に示すように、セル部ＲＣよりも外側、つまり繋ぎ部ＲＪ内において、隣り合うゲートトレンチ６の両端が半円状に繋げられ、上面からゲートトレンチ６を見た形状が長円形状となるようにしても良い。その場合でも、ゲートトレンチ６のうち直線状部分よりも先端に位置する半円状の部分の周囲の全域がイオン注入層３１とされ、ゲートトレンチ６の側面が傾斜させられるようにすればよい。
(3) Further, in the above embodiment, the trench gate structure is formed only by a mere linear portion. On the other hand, as shown in FIG. 7, both ends of the adjacent gate trench 6 are connected in a semicircular shape on the outside of the cell portion RC, that is, in the connecting portion RJ, and the gate trench 6 is viewed from the upper surface. May have an oval shape. Even in that case, the entire area around the semicircular portion located at the tip of the gate trench 6 rather than the linear portion may be the ion implantation layer 31, and the side surface of the gate trench 6 may be inclined.
（５）また、上記実施形態では、イオン注入層３１をｐ型層としているが、ゲートトレンチ６の側面を傾斜させることを目的とするのであれば、必ずしもｐ型層となっていなくても良くｎ型層であっても良い。また、イオン注入のドープ源としてアルミニウムを例に挙げたが、窒素などのｎ型不純物を用いても良いし、不純物にならない炭素、シリコン、アルゴンなどの不活性元素を用いても良い。
(5) Further, in the above embodiment, the ion implantation layer 31 is a p-type layer, but it does not necessarily have to be a p-type layer if the purpose is to incline the side surface of the gate trench 6. It may be an n-type layer. Further, although aluminum has been mentioned as an example of the doping source for ion implantation, an n-type impurity such as nitrogen may be used, or an inert element such as carbon, silicon, or argon that does not become an impurity may be used.
Claims (14)
- セル部（ＲＣ）にトレンチゲート構造の反転型の縦型半導体素子を備えた炭化珪素半導体装置であって、
主表面を有する第１または第２導電型の炭化珪素で構成された基板（１）と、
前記基板の主表面側に形成され、前記基板よりも低不純物濃度とされた第１導電型の炭化珪素で構成されたドリフト層（２、２ａ）と、
前記ドリフト層の上に形成された第２導電型の炭化珪素で構成されたベース領域（３）と、
前記セル部内における前記ベース領域の上に形成され、前記ドリフト層よりも高不純物濃度とされ、少なくとも前記ベース領域と接する部分が炭化珪素のエピタキシャル層で構成された第１導電型のソース領域（４）と、
前記ソース領域の表面から前記ベース領域よりも深く、一方向を長手方向とする直線状部分を有していて前記セル部から該セル部の外側まで形成されたゲートトレンチ（６）内に形成され、該ゲートトレンチの内壁面に形成されたゲート絶縁膜（７）と、前記ゲート絶縁膜の上に形成されたゲート電極（８）と、を有して構成された前記トレンチゲート構造と、
前記ソース領域および前記トレンチゲート構造の上に、前記ソース領域に繋がるコンタクトホールが形成された層間絶縁膜（１０）と、
前記層間絶縁膜の上に形成され、前記コンタクトホールを通じて前記ソース領域に電気的に接続された第１電極（９）と、
前記基板の裏面側に電気的に接続された第２電極（１１）と、を備え、
前記ゲートトレンチの側面は、前記セル部の外側では、前記セル部内における前記ソース領域のうちの前記ベース領域と接している前記エピタキシャル層で構成された部分と比較して、前記基板の主表面に対する法線方向に対して傾斜している炭化珪素半導体装置。 A silicon carbide semiconductor device provided with an inverted vertical semiconductor element having a trench gate structure in a cell portion (RC).
A substrate (1) made of first or second conductive type silicon carbide having a main surface and
A drift layer (2, 2a) formed on the main surface side of the substrate and made of first conductive type silicon carbide having a lower impurity concentration than the substrate.
A base region (3) made of second conductive type silicon carbide formed on the drift layer, and
A first conductive type source region (4) formed on the base region in the cell portion, having a higher impurity concentration than the drift layer, and having at least a portion in contact with the base region composed of an epitaxial layer of silicon carbide. )When,
It is formed in a gate trench (6) that is deeper than the surface of the source region and is deeper than the base region and has a linear portion having a longitudinal direction in one direction and is formed from the cell portion to the outside of the cell portion. The trench gate structure formed by the gate insulating film (7) formed on the inner wall surface of the gate trench and the gate electrode (8) formed on the gate insulating film.
An interlayer insulating film (10) in which a contact hole connected to the source region is formed on the source region and the trench gate structure.
A first electrode (9) formed on the interlayer insulating film and electrically connected to the source region through the contact hole,
A second electrode (11) electrically connected to the back surface side of the substrate is provided.
The side surface of the gate trench is relative to the main surface of the substrate on the outside of the cell portion as compared to a portion of the source region in the cell portion that is in contact with the base region and is composed of the epitaxial layer. A silicon carbide semiconductor device that is inclined with respect to the normal direction. - 前記セル部の外側では、前記ゲートトレンチの入口側における該ゲートトレンチの側面がイオン注入層（３１）によって構成されており、該ゲートトレンチの側面は前記イオン注入層の部分において前記基板の主表面に対する法線方向に対して傾斜している、請求項１に記載の炭化珪素半導体装置。 On the outside of the cell portion, the side surface of the gate trench on the inlet side of the gate trench is formed by an ion implantation layer (31), and the side surface of the gate trench is the main surface of the substrate in the portion of the ion implantation layer. The silicon carbide semiconductor device according to claim 1, which is inclined with respect to the direction normal to.
- 前記セル部の外側において、前記ゲート電極のゲートライナー（８ｂ）が備えられており、該ゲートライナーが備えられた位置では、前記ゲートトレンチの入口側における該ゲートトレンチの側面が前記イオン注入層によって構成されている、請求項２に記載の炭化珪素半導体装置。 A gate liner (8b) of the gate electrode is provided on the outside of the cell portion, and at the position where the gate liner is provided, the side surface of the gate trench on the inlet side of the gate trench is formed by the ion implantation layer. The silicon carbide semiconductor device according to claim 2, which is configured.
- 前記イオン注入層は、第２導電型層によって構成されている、請求項２または３に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 2 or 3, wherein the ion implantation layer is composed of a second conductive type layer.
- 前記セル部を囲む外周部（ＲＯ）を有し、
前記外周部にも、前記ベース領域の上に、第２導電型層で構成された前記イオン注入層と、前記イオン注入層の上に形成された前記層間絶縁膜と、が備えられていると共に、さらに、前記層間絶縁膜の上に形成された引抜パッド（３３）が備えられ、
前記層間絶縁膜に形成されたコンタクトホールを通じて前記イオン注入層と前記引抜パッドとが電気的に接続されている、請求項４に記載の炭化珪素半導体装置。 It has an outer peripheral portion (RO) surrounding the cell portion and has an outer peripheral portion (RO).
The outer peripheral portion is also provided with the ion-implanted layer composed of the second conductive layer and the interlayer insulating film formed on the ion-implanted layer on the base region. Further, a drawing pad (33) formed on the interlayer insulating film is provided.
The silicon carbide semiconductor device according to claim 4, wherein the ion implantation layer and the extraction pad are electrically connected through a contact hole formed in the interlayer insulating film. - 前記外周部は、前記セル部の外周を囲むガードリング部（ＲＧ）と、前記セル部と前記ガードリング部との間に位置する繋ぎ部（ＲＪ）とを有し、前記ガードリング部において、前記セル部よりも前記ドリフト層が凹んだ凹部（２０）が形成されることで、前記基板の厚み方向において、前記セル部および前記繋ぎ部が前記ガードリング部よりも突き出した島状のメサ部（ＲＭ）が構成され、
前記繋ぎ部の外縁部には前記イオン注入層が形成され、前記メサ部と前記凹部との境界位置では、前記イオン注入層と前記ベース領域および前記ドリフト層が順に形成された構造となっている、請求項５に記載の炭化珪素半導体装置。 The outer peripheral portion has a guard ring portion (RG) that surrounds the outer periphery of the cell portion and a connecting portion (RJ) located between the cell portion and the guard ring portion. By forming a recess (20) in which the drift layer is recessed from the cell portion, an island-shaped mesa portion in which the cell portion and the connecting portion protrude from the guard ring portion in the thickness direction of the substrate is formed. (RM) is configured
The ion-implanted layer is formed on the outer edge of the connecting portion, and the ion-implanted layer, the base region, and the drift layer are sequentially formed at the boundary position between the mesa portion and the recess. , The silicon carbide semiconductor device according to claim 5. - 前記繋ぎ部の全域に前記イオン注入層が形成されている、請求項６に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 6, wherein the ion implantation layer is formed in the entire area of the connecting portion.
- セル部（ＲＣ）にトレンチゲート構造の反転型の縦型半導体素子を備えた炭化珪素半導体装置の製造方法であって、
主表面を有する第１または第２導電型の炭化珪素で構成された基板（１）を用意することと、
前記基板の上に、前記基板よりも低不純物濃度の第１導電型の炭化珪素で構成されたドリフト層（２、２ａ）を形成することと、
前記ドリフト層の上に、第２導電型の炭化珪素からなるベース領域（３）を形成することと、
前記ベース領域の上に、エピタキシャル成長により、前記ドリフト層よりも第１導電型不純物濃度が高くされた第１導電型の炭化珪素で構成されるソース領域（４）を形成することと、
前記ソース領域の表面から前記ベース領域よりも深く、一方向を長手方向とした直線状部を有すると共に前記セル部から該セル部の外側に至るゲートトレンチ（６）を形成したのち、前記ゲートトレンチの内壁面にゲート絶縁膜（７）を形成すると共に、前記ゲート絶縁膜の上にゲート電極（８）を形成することで前記トレンチゲート構造を形成することと、
前記ソース領域および前記トレンチゲート構造の上に、前記ソース領域に繋がるコンタクトホールを有する層間絶縁膜（１０）を形成することと、
前記コンタクトホールを通じて前記ソース領域に電気的に接続される第１電極（９）を形成することと、
前記基板の裏面側に第２電極（１１）を形成することと、を含み、
前記トレンチゲート構造を形成することでは、前記ゲートトレンチの側面を、前記セル部の外側では前記セル部内における前記ソース領域のうちの前記ベース領域と接している前記エピタキシャル成長で形成された部分と比較して、前記基板の主表面に対する法線方向に対して傾斜させる炭化珪素半導体装置の製造方法。 A method for manufacturing a silicon carbide semiconductor device having a trench gate structure inverted vertical semiconductor element in a cell portion (RC).
To prepare a substrate (1) made of first or second conductive type silicon carbide having a main surface, and
On the substrate, a drift layer (2, 2a) composed of first conductive type silicon carbide having a lower impurity concentration than the substrate is formed.
By forming a base region (3) made of second conductive type silicon carbide on the drift layer,
A source region (4) composed of first conductive type silicon carbide having a higher concentration of first conductive type impurities than the drift layer is formed on the base region by epitaxial growth.
After forming a gate trench (6) deeper than the surface of the source region and having a linear portion with one direction as the longitudinal direction and extending from the cell portion to the outside of the cell portion, the gate trench The trench gate structure is formed by forming the gate insulating film (7) on the inner wall surface of the gate and forming the gate electrode (8) on the gate insulating film.
To form an interlayer insulating film (10) having a contact hole connected to the source region on the source region and the trench gate structure.
To form a first electrode (9) that is electrically connected to the source region through the contact hole.
Including forming a second electrode (11) on the back surface side of the substrate.
In forming the trench gate structure, the side surface of the gate trench is compared with a portion formed by the epitaxial growth outside the cell portion and in contact with the base region of the source region in the cell portion. A method for manufacturing a silicon carbide semiconductor device that is inclined with respect to the normal direction with respect to the main surface of the substrate. - 前記ソース領域を形成したのち、
前記セル部の外側に、イオン注入を行うことでイオン注入層（３１）を形成することを含み、
前記トレンチゲート構造を形成することでは、前記ゲートトレンチの長手方向の両端において、前記ゲートトレンチの側面が前記イオン注入層によって構成されるようにし、前記ゲートトレンチを形成した後に熱処理を行うことで、前記ゲートトレンチの側面のうちの前記イオン注入層で構成された部分を前記基板の主表面に対する法線方向に対して傾斜させる、請求項８に記載の炭化珪素半導体装置の製造方法。 After forming the source region,
It includes forming an ion implantation layer (31) by implanting ions on the outside of the cell portion.
In forming the trench gate structure, the side surfaces of the gate trench are formed by the ion implantation layer at both ends in the longitudinal direction of the gate trench, and heat treatment is performed after the gate trench is formed. The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein a portion of the side surface of the gate trench formed by the ion-implanted layer is inclined with respect to the normal direction with respect to the main surface of the substrate. - 前記トレンチゲート構造を形成することでは、前記セル部の外側において、前記ゲート電極のゲートライナー（８ｂ）を形成し、該ゲートライナーが備えられた位置では、前記ゲートトレンチの入口側における該ゲートトレンチの側面が前記イオン注入層によって構成されるようにする、請求項９に記載の炭化珪素半導体装置の製造方法。 By forming the trench gate structure, a gate liner (8b) of the gate electrode is formed outside the cell portion, and at a position where the gate liner is provided, the gate trench on the inlet side of the gate trench is formed. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein the side surface thereof is formed by the ion-implanted layer.
- 前記トレンチゲート構造を形成することでは、前記熱処理となる熱酸化を行うことで前記ゲート絶縁膜を形成する、請求項９または１０に記載の炭化珪素半導体装置の製造方法。 The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein in forming the trench gate structure, the gate insulating film is formed by performing thermal oxidation that is the heat treatment.
- 前記イオン注入層を形成することでは、第２導電型不純物をイオン注入することによって前記イオン注入層を形成すると共に、該イオン注入層を第２導電型層とする、請求項９ないし１１のいずれか１つに記載の炭化珪素半導体装置の製造方法。 The method according to any one of claims 9 to 11, wherein the ion-implanted layer is formed by ion-implanting a second conductive type impurity and the ion-implanted layer is used as the second conductive layer. The method for manufacturing a silicon carbide semiconductor device according to one of the above.
- 前記イオン注入層を形成することでは、前記セル部の外周を囲む外周部（ＲＯ）にも前記イオン注入層を形成し、
前記層間絶縁膜を形成することでは、前記イオン注入層の上にも前記層間絶縁膜を形成しつつ、前記イオン注入層に繋がるコンタクトホールを形成し、
前記層間絶縁膜を形成することの後に、前記層間絶縁膜の上に、前記コンタクトホールを通じて前記イオン注入層に電気的に接続される引抜パッド（３３）を形成することを含む、請求項１２に記載の炭化珪素半導体装置の製造方法。 By forming the ion-implanted layer, the ion-implanted layer is also formed on the outer peripheral portion (RO) surrounding the outer periphery of the cell portion.
By forming the interlayer insulating film, a contact hole connected to the ion-implanted layer is formed while forming the interlayer insulating film on the ion-implanted layer.
The twelfth aspect of claim 12, wherein after forming the interlayer insulating film, a drawing pad (33) electrically connected to the ion implantation layer through the contact hole is formed on the interlayer insulating film. The method for manufacturing a silicon carbide semiconductor device according to the description. - 前記外周部に、前記セル部の外周を囲むガードリング部（ＲＧ）を形成すると共に、前記セル部と前記ガードリング部との間に位置する繋ぎ部（ＲＪ）を形成することを含み、
前記ガードリング部を形成すると共に、前記繋ぎ部を形成することは、前記イオン注入層を形成することの後に、前記ガードリング部と対応する位置に、前記セル部よりも前記ドリフト層が凹んだ凹部（２０）を形成することで、前記ガードリング部を形成すると共に、前記基板の厚み方向において、前記ガードリング部よりも内側の部分が該ガードリング部よりも突き出した島状のメサ部（ＲＭ）を構成し、該メサ部における前記セル部の外周に前記繋ぎ部を形成することであり、
前記イオン注入層を形成することでは、前記繋ぎ部の外縁部にも前記イオン注入層を形成することで、前記メサ部と前記凹部との境界位置を、前記イオン注入層と前記ベース領域および前記ドリフト層が順に形成された構造とする、請求項１３に記載の炭化珪素半導体装置の製造方法。 The outer peripheral portion includes forming a guard ring portion (RG) that surrounds the outer periphery of the cell portion and forming a connecting portion (RJ) located between the cell portion and the guard ring portion.
Forming the guard ring portion and forming the connecting portion means that the drift layer is recessed from the cell portion at a position corresponding to the guard ring portion after the ion implantation layer is formed. By forming the concave portion (20), the guard ring portion is formed, and an island-shaped mesa portion (a portion inside the guard ring portion protruding from the guard ring portion in the thickness direction of the substrate) ( RM) is formed, and the connecting portion is formed on the outer periphery of the cell portion in the mesa portion.
By forming the ion-implanted layer, the ion-implanted layer is also formed on the outer edge of the connecting portion, so that the boundary position between the mesa portion and the recess is set to the ion-implanted layer, the base region, and the above. The method for manufacturing a silicon carbide semiconductor device according to claim 13, wherein the drift layers are formed in order.
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