WO2020228456A1 - On-chip variable gain temperature compensation amplifier - Google Patents

Abstract

An on-chip variable gain temperature compensation amplifier, which adjusts the proportion of positive gain and negative gain by altering a bias voltage of a gain control transistor at different temperatures, so as to implement gain control by means of positive and negative offsetting, and thus compensate for the influence of on-chip temperature changes on device gain. The temperature compensation amplifier covers temperature changes from -55°C to 125°C, and has advantages such as a large gain range, high compensation accuracy, low power consumption and a simple structure.

Description

An on-chip variable gain temperature compensation amplifier Technical field

The invention relates to the technical field of integrated circuits, in particular to an on-chip variable gain temperature compensation amplifier.

Background technique

With the continuous development of integrated circuit production technology, the microwave radio frequency system using complementary metal oxide semiconductor technology has achieved high integration and low cost. It has obtained advantages in the fields of automotive radar, satellite communications, millimeter wave imaging, and short-distance high-speed wireless communications. widely used. In the radio frequency integrated circuit system, the device gain is often affected by temperature and process angle and changes drastically. The temperature coefficient of the gain of the transmitting component and the receiving component will cause the general applicability of the system to be greatly reduced. Therefore, it is necessary to compensate for the severe environmental conditions. Gain to stabilize device performance. Radio frequency circuits usually exhibit a gain with a negative temperature coefficient, and the temperature coefficient (in dB/℃) is approximately constant within the overall operating temperature range. Therefore, it is necessary to integrate a variable gain temperature compensation amplifier with a positive temperature coefficient to compensate for the increase in temperature. Gain damage. The traditional analog temperature compensation circuit adopts a common source structure or a common emitter structure, and the transconductance of the common source or common emitter is changed by controlling the bias voltage, thereby changing the device gain, but the disadvantage of this type of structure is that the input impedance matching will It changes with the gain, and the linearity is obviously deteriorated in the case of low gain. The digital temperature compensation circuit introduces complex control logic, and gain control instability may occur near the critical temperature.

Summary of the invention

In view of the shortcomings of the prior art, the present invention proposes an on-chip variable gain temperature compensation amplifier, which realizes gain control by means of differential common gate current cancellation, and modulates the gate bias of the common gate transistor of the amplifier as the temperature changes. Set the voltage to adjust the ratio of the amplifier's forward gain and reverse gain to produce a gain response with a positive temperature coefficient.

An on-chip variable gain temperature compensation amplifier, characterized in that it comprises a bias voltage generating circuit and an amplifier main circuit; the bias voltage generating circuit generates a transistor bias voltage that changes with temperature, and the amplifier main circuit According to the change of the bias voltage, different gains are generated to realize the temperature compensation effect.

Further, the amplifier main circuit includes transistors M1, M2, M3, M4, M5, M6, resistors R1, R2, an on-chip transformer X1, and seven ports INP, INN, OUTP, OUTN, VB, VSP, VSN, where Differential radio frequency signals flow in from INP and INN ports, and flow out from OUTP and OUTN ports. VB, VSP, and VSN are bias voltage input ports; INP port is connected to one end of resistor R1 and the gate of transistor M1, and the other end of resistor R1 is connected to Port VB is connected, the source of transistor M1 is grounded, the drain is connected to the sources of transistors M3 and M4, the gate of transistor M3 is connected to port VSP, the gate of transistor M4 is connected to port VSN, and the INN port is connected to one end of resistor R2 Connected to the gate of the transistor M2, the other end of the resistor R2 is connected to the port VB, the source of the transistor M2 is grounded, the drain is connected to the sources of the transistors M5 and M6, the gate of the transistor M5 is connected to the port VSN, and the transistor M6 The gate is connected to the port VSP, the drains of the transistors M3 and M5 are connected together, which is marked as port VOP, and the drains of the transistors M4 and M6 are connected together, which is marked as the port VON. The ports VOP and VON are respectively connected to the primary coil of the transformer X1 At both ends, the center tap of the transformer X1 primary coil is connected to the power supply VDD, and the two ends of the transformer X1 secondary coil are respectively connected to the OUTP port and the OUTN port;

The main circuit of the amplifier is a differential structure, the transistors M1 and M2 are the same, the transistors M3 and M6 are the same, and the transistors M4 and M5 are the same;

The transistors M1, M2, M3, M4, M5, and M6 are NPN transistors or NMOS transistors.

Further, the sources of the transistors M1 and M2 are replaced by grounding and connected to the output port of the tail current source composed of transistors.

Further, the bias voltage generating circuit includes an exponential current generating circuit, transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, resistors R3, R4, R5, R6, operational amplifiers OP1, OP2 , OP3, current source Ib, bias voltage output ports VB, VSP, VSN;

The output terminal of the exponential current generating circuit is connected to the source of the transistor M7 and the drain of the transistor M12, the gate of the transistor M12 is connected to the drain, the source is connected to the drain of the transistor M13, and the gate of the transistor M13 is connected to The drain is connected, the source is grounded, the source of the transistor M15 is grounded, the gate is connected to the gate of the transistor M13, the drain of the transistor M15 is connected to the source of the transistor M14, and the gate of the transistor M14 is connected to the gate of the transistor M12 ; The gate of the transistor M7 is connected to the output terminal of the operational amplifier OP1, the drain of the transistor M7 is connected to one end of the resistor R3 and the non-inverting input terminal of the operational amplifier, and the other end of the resistor R3 is connected to the power supply VDD, the inverting of the operational amplifier OP1 The input terminal is connected to one end of the resistor R4 and the drain of the transistor M8, the other end of the resistor R4 is connected to the power supply VDD, and the gate of the transistor M8 is connected to the output terminal of the operational amplifier OP3, and is connected to the bias voltage output port VSP at the same time. The non-inverting input terminal of the amplifier OP3 is connected to the sources of the transistors M8 and M9 and the drain of the transistor M10, and the inverting input terminal of the operational amplifier OP3 is connected to the gates of the transistors M10 and M11, and is connected to the bias voltage output port VB at the same time, The sources of the transistors M10 and M11 are grounded, the gate and drain of the transistor M11 are connected, and at the same time connected to one end of the resistor R7, the other end of the resistor R7 is connected to the output end of the current source Ib, and the input end of the current source Ib is connected to the power supply VDD The gate of the transistor M9 is connected to the output terminal of the operational amplifier OP2, and is connected to the bias voltage output port VSN. The drain of the transistor M9 is connected to one end of the resistor R5 and the non-inverting input terminal of the operational amplifier OP2, and the other of the resistor R5 One end is connected to the power supply VDD, the inverting input end of the operational amplifier OP2 is connected to one end of the resistor R6 and the drain of the transistor M14, and the other end of the resistor R6 is connected to the power supply VDD;

The resistors R3, R4, R5, and R6 are the same, the transistors M12, M13, M14, and M15 form a mirror current source circuit, the transistors M12 and M14 are the same, and the transistors M13 and M15 are the same;

Transistor M7 is a PNP type transistor or PMOS tube, and the transistors M8, M9, M10, M11, M12, M13, M14, M15 are all NPN type transistors or NMOS tubes;

When the transistors M8, M9, M10 and the transistors M3, M4, M1 are all NPN transistors, M8, M9, M10 and the emitter area of the transistors M3, M4, M1 are proportional; when the transistors M8, When M9, M10 and transistors M3, M4, and M1 are all NMOS tubes, M8, M9, M10 and transistors M3, M4, and M1 are proportional to the tube width.

Further, the exponential current generating circuit includes a positive temperature coefficient current generating circuit, a resistor R8, NPN transistors Q1, Q2, and a current output port Iexp; the output port of the positive temperature coefficient current generating circuit and one end of the resistor R8 and a transistor Q2 The base of the transistor Q1 is connected, the other end of the resistor R8 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector, and the emitter is grounded; the emitter of the transistor Q2 is grounded, and the collector is connected to the current output port Iexp.

Compared with the prior art, the beneficial effects of the present invention are as follows:

The present invention is based on the current cancellation structure, which compensates for the damage to the device gain caused by the ambient temperature by changing the bias voltage of the gain control transistor. Since the gain is not controlled by changing the bias state of the common source or common emitter input transistor, the amplifier is different It can maintain good linearity at temperature. The variable gain temperature compensation amplifier provided by the present invention can cover a temperature change range of -55°C to 125°C, and has the advantages of large gain range, high compensation accuracy, low power consumption, simple structure and the like.

Description of the drawings

Figure 1 is a circuit diagram of the on-chip variable gain temperature compensation amplifier of the present invention;

Fig. 2 is a schematic circuit diagram of the bias voltage control circuit in Fig. 1 of the present invention;

Fig. 3 is a schematic circuit diagram of the exponential current generating circuit in Fig. 2 of the present invention;

Fig. 4 is a graph showing the change of gain with temperature of the on-chip variable gain temperature compensation amplifier of the present invention.

Detailed ways

The following describes the present invention in detail based on the accompanying drawings and preferred embodiments. The purpose and effects of the present invention will become clearer. It should be understood that the specific embodiments described here are only used to explain the present invention, and not to limit the present invention. The present invention will be further described in detail below in conjunction with the drawings and embodiments.

As shown in Figure 1, it is an on-chip variable gain temperature compensation amplifier of the present invention, including a bias voltage generating circuit and an amplifier main circuit; wherein the bias voltage generating circuit generates a transistor bias voltage that changes with temperature; the amplifier main circuit According to the change of the bias voltage, different gains can be generated to realize the temperature compensation effect.

Specifically, the amplifier main circuit includes transistors M1, M2, M3, M4, M5, M6, resistors R1, R2, on-chip transformer X1, and seven ports INP, INN, OUTP, OUTN, VB, VSP, VSN , Where the differential radio frequency signal flows in from the INP and INN ports and flows out from the OUTP and OUTN ports. VB, VSP, and VSN are the bias voltage input ports; the INP port is connected to one end of the resistor R1 and the gate of the transistor M1, and the other end of the resistor R1 One end is connected to port VB, the source of transistor M1 is grounded, the drain is connected to the sources of transistors M3 and M4, the gate of transistor M3 is connected to port VSP, the gate of transistor M4 is connected to port VSN, and the INN port is connected to resistor R2 One end of the resistor R2 is connected to the gate of the transistor M2, the other end of the resistor R2 is connected to the port VB, the source of the transistor M2 is grounded, the drain is connected to the sources of the transistors M5 and M6, and the gate of the transistor M5 is connected to the port VSN. The gate of M6 is connected to the port VSP, the drains of the transistors M3 and M5 are connected together, denoted as port VOP, the drains of the transistors M4 and M6 are connected together, denoted as port VON, and the ports VOP and VON are respectively connected to the primary of transformer X1 At both ends of the coil, the center tap of the transformer X1 primary coil is connected to the power supply VDD, and the two ends of the transformer X1 secondary coil are respectively connected to the OUTP port and the OUTN port.

The main circuit of the amplifier is a differential structure, the transistors M1 and M2 are the same, the transistors M3 and M6 are the same, and the transistors M4 and M5 are the same. The transistors M1, M2, M3, M4, M5, and M6 are NPN transistors or NMOS transistors.

In addition to grounding, the sources of the transistors M1 and M2 can also be connected to the output port of a tail current source composed of transistors.

As shown in Figure 2, the bias voltage control circuit includes an exponential current generating circuit, transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, resistors R3, R4, R5, R6, operational amplifiers OP1, OP2 , OP3, current source Ib, bias voltage output ports VB, VSP, VSN; the output terminal of the exponential current generating circuit is connected to the source of transistor M7 and the drain of transistor M12, the gate and drain of transistor M12 are connected, the source The electrode is connected to the drain of the transistor M13, the gate of the transistor M13 is connected to the drain, the source is grounded, the source of the transistor M15 is grounded, the gate is connected to the gate of the transistor M13, and the drain of the transistor M15 is connected to the source of the transistor M14 The gate of the transistor M14 is connected to the gate of the transistor M12; the gate of the transistor M7 is connected to the output terminal of the operational amplifier OP1, and the drain of the transistor M7 is connected to one end of the resistor R3 and the non-inverting input terminal of the operational amplifier OP1. The other end of the resistor R3 is connected to the power supply VDD, the inverting input end of the operational amplifier OP1 is connected to one end of the resistor R4 and the drain of the transistor M8, the other end of the resistor R4 is connected to the power supply VDD, and the gate of the transistor M8 is connected to the operational amplifier OP3 The output terminal of the operational amplifier OP3 is connected to the bias voltage output port VSP at the same time. The non-inverting input terminal of the operational amplifier OP3 is connected to the source of the transistor M8 and M9 and the drain of the transistor M10. The inverting input terminal of the operational amplifier OP3 is connected to the transistor M10, The gate of M11 is connected and connected to the bias voltage output port VB at the same time. The sources of transistors M10 and M11 are both grounded. The gate and drain of transistor M11 are connected and connected to one end of resistor R7. The other end of resistor R7 is connected to the current The output terminal of the source Ib is connected, and the input terminal of the current source Ib is connected to the power supply VDD; the gate of the transistor M9 is connected to the output terminal of the operational amplifier OP2, and is connected to the bias voltage output port VSN, and the drain of the transistor M9 is connected to the resistor R5 One end of the OP is connected to the non-inverting input terminal of the operational amplifier OP2, the other end of the resistor R5 is connected to the power supply VDD, the inverting input terminal of the operational amplifier OP2 is connected to one end of the resistor R6 and the drain of the transistor M14, and the other end of the resistor R6 is connected to the power supply VDD is connected.

The resistors R3, R4, R5, and R6 are the same; the transistors M12, M13, M14, and M15 form a mirror current source circuit, and the transistors M12 and M14 are required to be the same, and the transistors M13 and M15 are the same. The transistor M7 is a PNP type transistor or a PMOS tube, and the transistors M8, M9, M10, M11, M12, M13, M14, and M15 are all NPN type transistors or NMOS tubes.

When the transistors M8, M9, M10 and the transistors M3, M4, M1 are all NPN transistors, M8, M9, M10 and the emitter area of the transistors M3, M4, M1 are proportional; when the transistors M8, M9, M10 When the transistors M3, M4, and M1 are all NMOS tubes, the tube widths of M8, M9, M10 and the transistors M3, M4, and M1 are proportional.

As shown in Figure 3, the exponential current generating circuit includes a positive temperature coefficient current generating circuit, resistor R8, NPN transistors Q1, Q2, and current output port Iexp; the output port of the positive temperature coefficient current generating circuit and one end of resistor R8 and transistor Q2 The base of the transistor Q1 is connected, the other end of the resistor R8 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector, and the emitter is grounded; the emitter of the transistor Q2 is grounded, and the collector is connected to the current output port Iexp.

The working principle and process of the present invention are as follows:

As the temperature rises, the output current of the positive temperature coefficient current generating circuit adjusts the ratio of the forward gain and the reverse gain in the main circuit of the amplifier through the exponential current generating circuit, thereby generating a gain response with a positive temperature coefficient. Further, by adjusting the temperature coefficient of the output current of the positive temperature coefficient current generating circuit, the gain temperature coefficient of the main circuit of the amplifier can be adjusted.

Specifically, the positive temperature coefficient generating circuit generates a current that is positively related to temperature. This current passes through the resistor R8 and the transistor Q1, and a voltage that is positively related to the temperature can be obtained at the base of the transistor Q2. Using the volt-ampere characteristics of the transistor Q2, a current Iexp that rises exponentially with temperature can be obtained at its collector. In the bias voltage control circuit, the current Iexp controls the difference between the currents I7 and I12 in Figure 2. According to the principle of "virtual short" and "virtual disconnection" of the operational amplifier, V1=V2 and V3=V4 can be obtained. Since the resistance R3=R4, R5=R6, I7=I8, I9=I14. The transistors M12, M13, M14, and M15 form a current mirror, which copies the current I12 to I14, that is, I14=I12. In summary, Iexp=I7-I12=I8-I9. The transistors M10 and M11 form a current mirror, which copies the fixed current Ib to I10, that is, I10=a×Ib. According to the circuit connection relationship, we can get I10=I8+I9. Therefore, the values of currents I8 and I9 can be determined by the values of Ib and Iexp, so that the circuit is in a stable working state at any temperature, and then We can get an input transistor bias voltage VB and a set of gain control transistor bias voltages VSP, VSN that change with temperature. Because in the bias voltage control circuit, VB, VSP, and VSN correspond to the bias voltages of M10, M8, and M9, respectively. By adjusting the size of the transistor in Figure 1, I1=I2=k×I10, I3=I6=k ×I8, I4=I5=k×I9, so I1=a×k×Ib, I3–I5=k×Iexp. According to the amplifying properties of the differential amplifier, the gain proportional to Iexp can be obtained. Converted to dB form, the gain curve that increases linearly with temperature can be obtained as shown in Figure 4. Using the gain response of the positive temperature coefficient in the dB domain, the variable gain temperature compensation amplifier can compensate for the damage to the overall gain of the radio frequency chip due to temperature rise.

Those of ordinary skill in the art can understand that the above descriptions are only preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art can still The technical solutions recorded in the foregoing examples are modified, or some of the technical features are equivalently replaced. All modifications and equivalent substitutions made within the spirit and principle of the invention shall be included in the protection scope of the invention.

Claims (5)

1. An on-chip variable gain temperature compensation amplifier, characterized in that it comprises a bias voltage generating circuit and an amplifier main circuit; the bias voltage generating circuit generates a transistor bias voltage that changes with temperature, and the amplifier main circuit According to the change of the bias voltage, different gains are generated to realize the temperature compensation effect.
2. The on-chip variable gain temperature compensation amplifier according to claim 1, wherein the main circuit of the amplifier includes transistors M1, M2, M3, M4, M5, M6, resistors R1, R2, on-chip transformer X1 and seven Ports INP, INN, OUTP, OUTN, VB, VSP, VSN, where the differential radio frequency signal flows in from INP, INN ports, and flows out from OUTP, OUTN ports, VB, VSP, VSN are bias voltage input ports; INP port and resistor R1 One end of the transistor M1 is connected to the gate of the transistor M1, the other end of the resistor R1 is connected to the port VB, the source of the transistor M1 is grounded, the drain is connected to the sources of the transistors M3 and M4, and the gate of the transistor M3 is connected to the port VSP. The gate of M4 is connected to the port VSN, the INN port is connected to one end of the resistor R2 and the gate of the transistor M2, the other end of the resistor R2 is connected to the port VB, the source of the transistor M2 is grounded, and the drain is connected to the source of the transistors M5 and M6 The gate of the transistor M5 is connected to the port VSN, the gate of the transistor M6 is connected to the port VSP, the drains of the transistors M3 and M5 are connected together, denoted as port VOP, and the drains of the transistors M4 and M6 are connected together. Denoted as port VON, ports VOP and VON are respectively connected to both ends of the transformer X1 primary coil, the center tap of the transformer X1 primary coil is connected to the power supply VDD, and both ends of the transformer X1 secondary coil are respectively connected to the OUTP port and OUTN port;

   The main circuit of the amplifier is a differential structure, the transistors M1 and M2 are the same, the transistors M3 and M6 are the same, and the transistors M4 and M5 are the same.

   The transistors M1, M2, M3, M4, M5, and M6 are NPN transistors or NMOS transistors.
3. The on-chip variable gain temperature compensation amplifier according to claim 2, wherein the sources of the transistors M1 and M2 are replaced by grounding and connected to the output port of the tail current source composed of transistors.
4. The on-chip variable gain temperature compensation amplifier according to claim 2, wherein the bias voltage generating circuit includes an exponential current generating circuit, transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, resistors R3, R4, R5, R6, operational amplifiers OP1, OP2, OP3, current source Ib, bias voltage output ports VB, VSP, VSN;

   The output terminal of the exponential current generating circuit is connected to the source of the transistor M7 and the drain of the transistor M12, the gate of the transistor M12 is connected to the drain, the source is connected to the drain of the transistor M13, and the gate of the transistor M13 is connected to The drain is connected, the source is grounded, the source of the transistor M15 is grounded, the gate is connected to the gate of the transistor M13, the drain of the transistor M15 is connected to the source of the transistor M14, and the gate of the transistor M14 is connected to the gate of the transistor M12 ; The gate of the transistor M7 is connected to the output terminal of the operational amplifier OP1, the drain of the transistor M7 is connected to one end of the resistor R3 and the non-inverting input terminal of the operational amplifier, and the other end of the resistor R3 is connected to the power supply VDD, the inverting of the operational amplifier OP1 The input terminal is connected to one end of the resistor R4 and the drain of the transistor M8, the other end of the resistor R4 is connected to the power supply VDD, and the gate of the transistor M8 is connected to the output terminal of the operational amplifier OP3, and is connected to the bias voltage output port VSP at the same time. The non-inverting input terminal of the amplifier OP3 is connected to the sources of the transistors M8 and M9 and the drain of the transistor M10, and the inverting input terminal of the operational amplifier OP3 is connected to the gates of the transistors M10 and M11, and is connected to the bias voltage output port VB at the same time, The sources of the transistors M10 and M11 are grounded, the gate and drain of the transistor M11 are connected, and at the same time connected to one end of the resistor R7, the other end of the resistor R7 is connected to the output end of the current source Ib, and the input end of the current source Ib is connected to the power supply VDD The gate of the transistor M9 is connected to the output terminal of the operational amplifier OP2, and is connected to the bias voltage output port VSN. The drain of the transistor M9 is connected to one end of the resistor R5 and the non-inverting input terminal of the operational amplifier OP2, and the other of the resistor R5 One end is connected to the power supply VDD, the inverting input end of the operational amplifier OP2 is connected to one end of the resistor R6 and the drain of the transistor M14, and the other end of the resistor R6 is connected to the power supply VDD;

   The resistors R3, R4, R5, and R6 are the same, the transistors M12, M13, M14, and M15 form a mirror current source circuit, the transistors M12 and M14 are the same, and the transistors M13 and M15 are the same;

   Transistor M7 is a PNP type transistor or PMOS tube, and the transistors M8, M9, M10, M11, M12, M13, M14, M15 are all NPN type transistors or NMOS tubes;

   When the transistors M8, M9, M10 and the transistors M3, M4, M1 are all NPN transistors, M8, M9, M10 and the emitter area of the transistors M3, M4, M1 are proportional; when the transistors M8, When M9, M10 and transistors M3, M4, and M1 are all NMOS tubes, M8, M9, M10 and transistors M3, M4, and M1 are proportional to the tube width.
5. The on-chip variable gain temperature compensation amplifier according to claim 4, wherein the exponential current generating circuit comprises a positive temperature coefficient current generating circuit, resistor R8, NPN transistors Q1, Q2, and current output port Iexp; positive The output port of the temperature coefficient current generating circuit is connected to one end of the resistor R8 and the base of the transistor Q2, the other end of the resistor R8 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector, and the emitter is grounded; the transistor Q2 The emitter of is grounded, and the collector is connected to the current output port Iexp.

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