WO2020228150A1 - 过电流保护电路及其驱动方法 - Google Patents

过电流保护电路及其驱动方法 Download PDF

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Publication number
WO2020228150A1
WO2020228150A1 PCT/CN2019/099473 CN2019099473W WO2020228150A1 WO 2020228150 A1 WO2020228150 A1 WO 2020228150A1 CN 2019099473 W CN2019099473 W CN 2019099473W WO 2020228150 A1 WO2020228150 A1 WO 2020228150A1
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Prior art keywords
comparator
adder
overcurrent protection
currents
pmos
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French (fr)
Inventor
张先明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement

Definitions

  • the invention relates to the field of display technology, in particular to an overcurrent protection circuit and a driving method thereof.
  • GOA Gate On Array
  • the use of GOA technology can effectively save the use of flexible circuit boards.
  • the signals required in the GOA drive circuit are provided by the outputs of the level conversion circuit.
  • GOA technology is currently a commonly used driving technology for TFT-LCD, which can save GateCOF and achieve the effect of reducing costs.
  • the signals required by GOA are all high-voltage signals, and due to the existence of fine dust particles, short circuits may occur between GOA signals, forming large currents, and even burn out the polarizer in severe cases, causing safety regulations.
  • the current overcurrent circuit mainly detects the current of each CK, LC, STV, and VSS, where CK is a high-frequency switching voltage signal.
  • the current of low-frequency signals such as LC/STV/VSS can be detected very well, but for high-frequency signals, if two-by-two short-circuits are short-circuited, it can be detected very well, but when there are multiple short-circuits, it is very difficult. It is difficult to detect, because the current is scattered on each CK, which makes it difficult to detect, but there is still the risk of triggering the melting screen.
  • the over-current protection circuit of the prior art can detect high-frequency signals well if they are short-circuited in pairs, but it is difficult to detect when there are multiple short-circuits because the current is scattered on each CK. It is difficult to detect, but there is still the risk of triggering the melting screen.
  • the present invention provides an overcurrent protection circuit and a driving method.
  • An overcurrent protection circuit including:
  • the overcurrent protection module includes: a controller, a mirror circuit, PMOS and NMOS;
  • the controller is connected to the mirror circuit, the PMOS and the NMOS; the PMOS is connected to the high-level voltage VGH and the output clock signal voltage V-clkout, and the NMOS is connected to the output clock signal voltage V-clkout and Low level voltage VGL;
  • the overcurrent detection module includes: a first adder, a first comparator, a second adder, a second comparator, and an AND circuit connected to each other;
  • the first adder, the first comparator and the first input terminal of the AND circuit are connected.
  • the input terminal of the first adder is connected to all CK currents of the PMOS, and the first adder calculates the all CK currents of the PMOS
  • the output terminal of the first adder is the total value of all the CK currents of the PMOS and is connected to the first input terminal of the first comparator.
  • a first preset current value is set at the second input terminal of the first comparator, and the first comparator compares all the CK currents of the PMOS The sum value and the first preset current value are combined, and the first comparator inputs the result to the first input terminal of the AND circuit.
  • the second adder, the second comparator and the second input terminal of the AND circuit are connected.
  • the input terminal of the second adder is connected to all CK currents of the NMOS, and the sum of all the CK currents of the NMOS is calculated by the second adder
  • the output terminal of the second adder is the total value of all the CK currents of the NMOS and is connected to the first input terminal of the second comparator.
  • a second preset current value is set at the second input terminal of the second comparator, and the second comparator compares all CK currents of the NMOS The total value and the second preset current value are combined, and the second comparator inputs the result to the second input terminal of the AND circuit.
  • the AND circuit detects whether the PMOS and the NMOS generate overcurrent, and outputs the result to the overcurrent protection module.
  • the embodiment of the present invention also provides an overcurrent protection circuit, including:
  • the overcurrent protection module includes: a controller, a mirror circuit, PMOS and NMOS;
  • the controller is connected to the mirror circuit, the PMOS and the NMOS; the PMOS is connected to the high-level voltage VGH and the output clock signal voltage V-clkout, and the NMOS is connected to the output clock signal voltage V-clkout and Low level voltage VGL; and
  • the overcurrent detection module includes: a first adder, a first comparator, a second adder, a second comparator, and an AND circuit connected to each other.
  • the mirror circuit protects the PMOS from overcurrent.
  • the first adder, the first comparator and the first input terminal of the AND circuit are connected.
  • the input terminal of the first adder is connected to all CK currents of the PMOS, and the first adder calculates the all CK currents of the PMOS
  • the output terminal of the first adder is the total value of all the CK currents of the PMOS and is connected to the first input terminal of the first comparator.
  • a first preset current value is set at the second input terminal of the first comparator, and the first comparator compares all the CK currents of the PMOS The sum value and the first preset current value are combined, and the first comparator inputs the result to the first input terminal of the AND circuit.
  • the second adder, the second comparator and the second input terminal of the AND circuit are connected.
  • the input terminal of the second adder is connected to all CK currents of the NMOS, and the sum of all the CK currents of the NMOS is calculated by the second adder
  • the output terminal of the second adder is the total value of all the CK currents of the NMOS and is connected to the first input terminal of the second comparator.
  • a second preset current value is set at the second input terminal of the second comparator, and the second comparator compares all CK currents of the NMOS The total value and the second preset current value are combined, and the second comparator inputs the result to the second input terminal of the AND circuit.
  • the AND circuit detects whether the PMOS and the NMOS generate overcurrent, and outputs the result to the overcurrent protection module.
  • the embodiment of the present invention also provides an overcurrent protection circuit driving method, which includes the following steps:
  • the first comparator is provided with a first preset current value, and the first comparator compares the first preset current value with the total value of all the CK currents of the PMOS, and outputs the result Give the gate circuit;
  • the second comparator is provided with a second preset current value, and the second comparator compares the second preset current value with the total value of all CK currents of the NMOS, and outputs the result to the Gate circuit;
  • the AND circuit detects whether the PMOS and the NMOS generate overcurrent, and outputs the result to the overcurrent protection module
  • the over-current protection circuit and driving method provided by the present invention increase the detection of the over-current circuit as a whole on the basis of the original over-current protection circuit. By superimposing the positive currents together, the negative polarity The currents are superimposed together. If the total current value exceeds the set value, it indicates that the circuit has a short circuit problem; if the total current value is lower than the set value, there is no short circuit problem.
  • FIG. 1 is a schematic diagram of an overcurrent protection circuit provided by an embodiment of the present invention.
  • FIG. 2 is a schematic circuit diagram of an overcurrent detection module in an overcurrent protection circuit provided by an embodiment of the present invention.
  • An embodiment of the present invention provides an overcurrent protection circuit, which includes an overcurrent protection module and an overcurrent detection module, wherein the overcurrent protection module is used to protect the circuit when the circuit is short-circuited and the current is too large.
  • the overcurrent detection module is used to detect the current value on the CK signal.
  • the overcurrent protection circuit provided by the embodiment of the present invention controls the output of the level conversion circuit by setting the overcurrent protection module, which can easily and effectively detect the current in real time, and quickly protect after the occurrence of a short circuit. It prevents the short circuit point of the panel from heating and burning, melting screen and fire caused by the short circuit, effectively preventing the occurrence of safety hazards.
  • the overcurrent protection circuit includes an overcurrent protection module and an overcurrent detection module.
  • the overcurrent protection module includes: controller 1, mirror circuit 2, PMOS3, and NMOS4.
  • the controller 1 is connected to the mirror circuit 2, the PMOS3, and the NMOS4;
  • the PMOS3 is connected to VGH and V-clkout, and
  • the NMOS4 is connected to the V-clkout and VGL.
  • the overcurrent detection module includes: a first adder 5, a first comparator 7, a second adder 6, a second comparator 8 and an AND circuit 9.
  • the mirror circuit 2 in the overcurrent protection module is used to protect the PMOS3.
  • FIG. 2 it is a schematic diagram of the overcurrent detection module in this embodiment.
  • the first adder 5, the first comparator 7 and the first input terminal of the AND circuit 9 are connected.
  • the input terminal of the first adder 5 is connected to all CK currents of the PMOS3, the total value of all CK currents is calculated by the first adder 5, and the output terminal is the total value of all CK currents of the PMOS3 And connected to the first input terminal of the first comparator 7. Ignore the first 4us of the rising or falling edge of CK, and only detect the current in normal operation.
  • a preset current value is set at the second input terminal of the first comparator 7, and the total value of all CK currents of the PMOS 3 is compared with the preset current value through the first comparator 7, And input the result to the first input terminal of the AND circuit 9.
  • the second adder 6, the second comparator 8 and the second input terminal of the AND circuit 9 are connected.
  • the input terminal of the second adder 6 is connected to all CK currents of the NMOS4, the total value of all CK currents is calculated by the second adder 6, and the output terminal is the total value of all CK currents of the NMOS4 And connected to the first input terminal of the second comparator 8. Ignore the first 4us of the rising or falling edge of CK, and only detect the current in normal operation.
  • the second input terminal of the second comparator 8 is connected to a preset current value, and the sum of all CK currents of the NMOS is compared with the preset current value through the second comparator 8, and the result is input To the second input terminal of the AND circuit 9.
  • the AND circuit 9 detects whether the PMOS3 and the NMOS4 generate overcurrent, that is, as long as the PMOS3 and the NMOS4 generate overcurrent, the AND gate The circuit 9 outputs the result of the overcurrent generated in the circuit to the overcurrent protection module, and the protection circuit takes effect at this time.
  • the embodiment of the present invention also provides an overcurrent protection circuit driving method, which includes the following steps:
  • the first comparator has a preset current value, and the first comparator compares the preset current value with the total value of all CK currents of the PMOS, and outputs the result to an AND circuit;
  • the second comparator has a preset current value, and the second comparator compares the preset current value with the total value of all CK currents of the NMOS, and outputs the result to the AND circuit;
  • the AND circuit detects whether the PMOS and the NMOS generate overcurrent, and outputs the result to the overcurrent protection module.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

本发明提供一种过电流保护电路及其驱动方法。所述过电流保护电路包括：过电流保护模块与过电流检测模块；所述过流保护模块包括：控制器，镜像电路，PMOS，NMOS；所述过电流检测模块包括：第一加法器，第一比较器，第二加法器，第二比较器以及一个与门电路，所述过电流保护电路增加了对过电流电路整体的侦测。

Description

过电流保护电路及其驱动方法 技术领域
本发明涉及显示技术领域，尤其涉及一种过电流保护电路及其驱动方法。
 背景技术
GOA(Gate On Array，栅极集成驱动)技术为目前液晶显示面板发展的趋势，使用GOA技术可以有效的节省柔性线路板的使用，其中，GOA驱动线路中需要的信号由电平转换电路的各输出提供。
GOA技术为目前TFT-LCD常用的驱动技术，其可以节省GateCOF，达到降低成本的效果。但是由于GOA所需要的信号都为高压信号，且由于微尘粒子的存在，导致GOA的信号之间可能会发生短路，形成大电流，严重时甚至烧坏偏光片，引起安全规范风险。
现在的过电流电路主要侦测每一个CK、LC、STV、VSS的电流，其中CK为高频切换的电压信号。
这种情况下可以很好的侦测LC/STV/VSS等低频信号的电流，但是对于高频信号，若两两短路的话，可以很好侦测，但是遇到多个之间短路时则很难侦测，因为电流分散在每个CK上，导致很难侦测，但是仍有触发熔屏的风险。
 技术问题
现有技术的过电流保护电路，对于高频信号，若两两短路的话，可以很好侦测，但是遇到多个之间短路时则很难侦测，因为电流分散在每个CK上，导致很难侦测，但是仍有触发熔屏的风险。
 技术解决方案
为解决上述技术问题，本发明提供一种过电流保护电路及驱动方法。
一种过电流保护电路，包括：
过电流保护模块与过电流检测模块；其中，
所述过流保护模块包括：控制器，镜像电路，PMOS和NMOS；
所述控制器连接所述镜像电路，所述PMOS和所述NMOS；所述PMOS连接高电平电压VGH和输出时钟信号电压V-clkout，所述NMOS连接所述输出时钟信号电压V-clkout和低电平电压VGL；
所述过电流检测模块包括：互相连接的第一加法器，第一比较器，第二加法器，第二比较器以及一个与门电路；
所述镜像电路过电流保护所述PMOS；
所述第一加法器，所述第一比较器和所述与门电路的第一输入端相连接。
根据本发明实施例所提供的过电流保护电路，所述第一加法器的所述输入端连接所述PMOS的所有CK电流，通过所述第一加法器计算所述PMOS的所述所有CK电流的合计值，所述第一加法器的输出端为所述PMOS的所述所有CK电流的合计值并连接到所述第一比较器的第一输入端。
根据本发明实施例所提供的过电流保护电路，所述第一比较器的第二输入端设置第一预设电流值，通过所述第一比较器比较所述PMOS的所述所有CK电流的合计值与所述第一预设电流值的大小，所述第一比较器将结果输入到所述与门电路的第一输入端。
根据本发明实施例所提供的过电流保护电路，所述第二加法器，所述第二比较器和所述与门电路的第二输入端相连接。
根据本发明实施例所提供的过电流保护电路，所述第二加法器的输入端连接所述NMOS的所有CK电流，通过所述第二加法器计算所述NMOS的所述所有CK电流的合计值，所述第二加法器的输出端为所述NMOS的所述所有CK电流的合计值并连接到所述第二比较器的第一输入端。
根据本发明实施例所提供的过电流保护电路，所述第二比较器的第二输入端设置第二预设电流值，通过所述第二比较器比较所述NMOS的所述所有CK电流的合计值与所述第二预设电流值的大小，所述第二比较器将结果输入到所述与门电路的第二输入端。
根据本发明实施例所提供的过电流保护电路，所述与门电路检测所述PMOS和所述NMOS是否产生过电流，并将结果输出给所述过流保护模块。
本发明实施例还提供了一种过电流保护电路，包括：
过电流保护模块与过电流检测模块；其中，
所述过流保护模块包括：控制器，镜像电路，PMOS和NMOS；
所述控制器连接所述镜像电路，所述PMOS和所述NMOS；所述PMOS连接高电平电压VGH和输出时钟信号电压V-clkout，所述NMOS连接所述输出时钟信号电压V-clkout和低电平电压VGL；以及
所述过电流检测模块包括：互相连接的第一加法器，第一比较器，第二加法器，第二比较器以及一个与门电路。
根据本发明实施例所提供的过电流保护电路，所述镜像电路过电流保护所述PMOS。
根据本发明实施例所提供的过电流保护电路，所述第一加法器，所述第一比较器和所述与门电路的第一输入端相连接。
根据本发明实施例所提供的过电流保护电路，所述第一加法器的所述输入端连接所述PMOS的所有CK电流，通过所述第一加法器计算所述PMOS的所述所有CK电流的合计值，所述第一加法器的输出端为所述PMOS的所述所有CK电流的合计值并连接到所述第一比较器的第一输入端。
根据本发明实施例所提供的过电流保护电路，所述第一比较器的第二输入端设置第一预设电流值，通过所述第一比较器比较所述PMOS的所述所有CK电流的合计值与所述第一预设电流值的大小，所述第一比较器将结果输入到所述与门电路的第一输入端。
根据本发明实施例所提供的过电流保护电路，所述第二加法器，所述第二比较器和所述与门电路的第二输入端相连接。
根据本发明实施例所提供的过电流保护电路，所述第二加法器的输入端连接所述NMOS的所有CK电流，通过所述第二加法器计算所述NMOS的所述所有CK电流的合计值，所述第二加法器的输出端为所述NMOS的所述所有CK电流的合计值并连接到所述第二比较器的第一输入端。
根据本发明实施例所提供的过电流保护电路，所述第二比较器的第二输入端设置第二预设电流值，通过所述第二比较器比较所述NMOS的所述所有CK电流的合计值与所述第二预设电流值的大小，所述第二比较器将结果输入到所述与门电路的第二输入端。
根据本发明实施例所提供的过电流保护电路，所述与门电路检测所述PMOS和所述NMOS是否产生过电流，并将结果输出给所述过流保护模块。
本发明实施例还提供了一种过电流保护电路驱动方法，包括以下步骤：
通过第一加法器计算PMOS的所有CK电流的合计值，并将结果输出给第一比较器；
通过第二加法器计算NMOS的所有CK电流的合计值，并将结果输出给第二比较器；
所述第一比较器设置有第一预设电流值，所述第一比较器将所述第一预设电流值与所述PMOS的所述所有CK电流的合计值作比较，并将结果输出给与门电路；
所述第二比较器设置有第二预设电流值，所述第二比较器将所述第二预设电流值与所述NMOS的所有CK电流的合计值作比较，并将结果输出给与门电路；以及
所述与门电路检测所述PMOS和所述NMOS是否产生过电流，并将结果输出给过流保护模块
 有益效果
本发明提供的一种过电流保护电路及驱动方法，在原有过电流保护电路的基础之上，增加了对过电流电路整体的侦测，通过将正极性的电流叠加在一起，将负极性的电流叠加在一起，若电流合计值超过设定值，则表示电路出现了短路问题；若电流合计值低于设定值，则无短路问题。
 附图说明
图1为本发明实施例所提供的过电流保护电路的示意图。
图2为本发明实施例所提供的过电流保护电路中的过电流检测模块的电路示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
本发明实施例提供一种过电流保护电路，其包括过电流保护模块和过电流检测模块，其中，所述过电流保护模块用于当电路短路，电流过大时，对电路起到保护作用。而所述过电流检测模块用于检测CK信号上的电流值。本发明实施例所提供的过电流保护电路通过设置过流保护模块对电平转换电路进行输出控制，可以简单有效的对电流进行实时的侦测，并在短路发生后快速的进行保护，有效的防止了因短路而引起的面板的短路点发热烧坏、熔屏以及起火现象发生，有效的阻止了安全隐患的产生。
如图1所示，为本实施例所提供的过电流保护电路，所述过电流保护电路包括过电流保护模块与过电流检测模块。其中，所述过流保护模块包括：控制器1，镜像电路2，PMOS3，NMOS4。所述控制器1连接所述镜像电路2，所述PMOS3，所述NMOS4；所述PMOS3连接VGH和V-clkout，所述NMOS4连接所述V-clkout和VGL。所述过电流检测模块包括：第一加法器5，第一比较器7，第二加法器6，第二比较器8以及一个与门电路9。
在所述过电流保护模块中的所述镜像电路2用于保护所述PMOS3。
如图2所示，为本实施例中过电流检测模块的示意图。
在所述过电流检测模块中，所述第一加法器5，所述第一比较器7和所述与门电路9的第一输入端相连接。其中，所述第一加法器5的输入端连接所述PMOS3的所有CK电流，通过所述第一加法器5计算所有CK电流的合计值，输出端为所述PMOS3的所有CK电流的合计值并连接到所述第一比较器7的第一输入端。忽略CK上升沿或下降沿的前4us，只侦测正常工作中电流。在所述第一比较器7的第二输入端设置有预设的电流值，通过所述第一比较器7比较所述PMOS3的所有CK电流的合计值与所述预设电流值的大小，并将结果输入到所述与门电路9的第一输入端。
在所述过电流检测模块中，所述第二加法器6，所述第二比较器8和所述与门电路9的第二输入端相连接。其中，所述第二加法器6的输入端连接所述NMOS4的所有CK电流，通过所述第二加法器6计算所有CK电流的合计值，输出端为所述NMOS4的所有CK电流的合计值并连接到所述第二比较器8的第一输入端。忽略CK上升沿或下降沿的前4us，只侦测正常工作中电流。所述第二比较器8的第二输入端连接预设电流值，通过所述第二比较器8比较所述NMOS的所有CK电流的合计值与所述预设电流值的大小，将结果输入到所述与门电路9的第二输入端。
在所述与门电路9中，所述与门电路9检测所述PMOS3和所述NMOS4是否产生过电流，即只要所述PMOS3和所述NMOS4中任一处产生过电流，则所述与门电路9就将电路中产生了过电流的结果输出给过流保护模块，此时保护电路生效。
本发明实施例还提供了一种过电流保护电路驱动方法，包括以下步骤：
通过第一加法器计算PMOS的所有CK电流的合计值，并将结果输出给第一比较器；
通过第二加法器计算NMOS的所有CK电流的合计值，并将结果输出给第二比较器；
所述第一比较器有一预设的电流值，所述第一比较器将所述预设电流值与所述PMOS的所有CK电流的合计值作比较，并将结果输出给与门电路；
所述第二比较器有一预设的电流值，所述第二比较器将所述预设电流值与所述NMOS的所有CK电流的合计值作比较，并将结果输出给与门电路；
所述与门电路检测所述PMOS和所述NMOS是否产生过电流，并将结果输出给过流保护模块。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (17)

  1. 一种过电流保护电路，包括：
    过电流保护模块与过电流检测模块；其中，
    所述过流保护模块包括：控制器，镜像电路，PMOS和NMOS；
    所述控制器连接所述镜像电路，所述PMOS和所述NMOS；所述PMOS连接高电平电压VGH和输出时钟信号电压V-clkout，所述NMOS连接所述输出时钟信号电压V-clkout和低电平电压VGL；
    所述过电流检测模块包括：互相连接的第一加法器，第一比较器，第二加法器，第二比较器以及一个与门电路；
    所述镜像电路过电流保护所述PMOS；
    所述第一加法器，所述第一比较器和所述与门电路的第一输入端相连接。
  2. 根据权利要求1所述的过电流保护电路，其中所述第一加法器的所述输入端连接所述PMOS的所有CK电流，通过所述第一加法器计算所述PMOS的所述所有CK电流的合计值，所述第一加法器的输出端为所述PMOS的所述所有CK电流的合计值并连接到所述第一比较器的第一输入端。
  3. 根据权利要求2所述的过电流保护电路，其中所述第一比较器的第二输入端设置第一预设电流值，通过所述第一比较器比较所述PMOS的所述所有CK电流的合计值与所述第一预设电流值的大小，所述第一比较器将结果输入到所述与门电路的第一输入端。
  4. 根据权利要求1所述的过电流保护电路，其中所述第二加法器，所述第二比较器和所述与门电路的第二输入端相连接。
  5. 根据权利要求4所述的过电流保护电路，其中所述第二加法器的输入端连接所述NMOS的所有CK电流，通过所述第二加法器计算所述NMOS的所述所有CK电流的合计值，所述第二加法器的输出端为所述NMOS的所述所有CK电流的合计值并连接到所述第二比较器的第一输入端。
  6. 根据权利要求5所述的过电流保护电路，其中所述第二比较器的第二输入端设置第二预设电流值，通过所述第二比较器比较所述NMOS的所述所有CK电流的合计值与所述第二预设电流值的大小，所述第二比较器将结果输入到所述与门电路的第二输入端。
  7. 根据权利要求1所述的过电流保护电路，其中所述与门电路检测所述PMOS和所述NMOS是否产生过电流，并将结果输出给所述过流保护模块。
  8. 一种过电流保护电路，包括：
    过电流保护模块与过电流检测模块；其中，
    所述过流保护模块包括：控制器，镜像电路，PMOS和NMOS；
    所述控制器连接所述镜像电路，所述PMOS和所述NMOS；所述PMOS连接高电平电压VGH和输出时钟信号电压V-clkout，所述NMOS连接所述输出时钟信号电压V-clkout和低电平电压VGL；以及
    所述过电流检测模块包括：互相连接的第一加法器，第一比较器，第二加法器，第二比较器以及一个与门电路。
  9. 根据权利要求8所述的过电流保护电路，其中所述镜像电路过电流保护所述PMOS。
  10. 根据权利要求8所述的过电流保护电路，其中所述第一加法器，所述第一比较器和所述与门电路的第一输入端相连接。
  11. 根据权利要求10所述的过电流保护电路，其中所述第一加法器的所述输入端连接所述PMOS的所有CK电流，通过所述第一加法器计算所述PMOS的所述所有CK电流的合计值，所述第一加法器的输出端为所述PMOS的所述所有CK电流的合计值并连接到所述第一比较器的第一输入端。
  12. 根据权利要求11所述的过电流保护电路，其中所述第一比较器的第二输入端设置第一预设电流值，通过所述第一比较器比较所述PMOS的所述所有CK电流的合计值与所述第一预设电流值的大小，所述第一比较器将结果输入到所述与门电路的第一输入端。
  13. 根据权利要求8所述的过电流保护电路，其中所述第二加法器，所述第二比较器和所述与门电路的第二输入端相连接。
  14. 根据权利要求13所述的过电流保护电路，其中所述第二加法器的输入端连接所述NMOS的所有CK电流，通过所述第二加法器计算所述NMOS的所述所有CK电流的合计值，所述第二加法器的输出端为所述NMOS的所述所有CK电流的合计值并连接到所述第二比较器的第一输入端。
  15. 根据权利要求14所述的过电流保护电路，其中所述第二比较器的第二输入端设置第二预设电流值，通过所述第二比较器比较所述NMOS的所述所有CK电流的合计值与所述第二预设电流值的大小，所述第二比较器将结果输入到所述与门电路的第二输入端。
  16. 根据权利要求8所述的过电流保护电路，其中所述与门电路检测所述PMOS和所述NMOS是否产生过电流，并将结果输出给所述过流保护模块。
  17. 一种过电流保护电路驱动方法，包括以下步骤：
    通过第一加法器计算PMOS的所有CK电流的合计值，并将结果输出给第一比较器；
    通过第二加法器计算NMOS的所有CK电流的合计值，并将结果输出给第二比较器；
    所述第一比较器设置有第一预设电流值，所述第一比较器将所述第一预设电流值与所述PMOS的所述所有CK电流的合计值作比较，并将结果输出给与门电路；
    所述第二比较器设置有第二预设电流值，所述第二比较器将所述第二预设电流值与所述NMOS的所有CK电流的合计值作比较，并将结果输出给与门电路；以及
    所述与门电路检测所述PMOS和所述NMOS是否产生过电流，并将结果输出给过流保护模块。
PCT/CN2019/099473 2019-05-16 2019-08-06 过电流保护电路及其驱动方法 Ceased WO2020228150A1 (zh)

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