WO2020207136A1

WO2020207136A1 - Gate driving unit, gate driving method, gate driving circuit, and display apparatus

Info

Publication number: WO2020207136A1
Application number: PCT/CN2020/076720
Authority: WO
Inventors: 秦文文; 王珍; 孙建
Original assignee: 京东方科技集团股份有限公司; 鄂尔多斯市源盛光电有限责任公司
Priority date: 2019-04-09
Filing date: 2020-02-26
Publication date: 2020-10-15
Also published as: CN109903715A; CN109903715B

Abstract

A gate driving unit, a gate driving method, a gate driving circuit, and a display apparatus. The gate driving unit comprises a pull-up control node control circuit (11), a connection and disconnection control circuit (12), and an output circuit (13), wherein the pull-up control node control circuit (11) is connected to a pull-up control node for controlling the potential of the pull-up control node; the connection and disconnection control circuit (12) is respectively connected to a pull-up node and a gate driving signal output end for connecting or disconnecting the pull-up control node and the pull-up node under the control of a connection and disconnection control signal input from a connection and disconnection control end; and the output circuit (13) is respectively connected to the pull-up node and the gate driving signal output end for controlling, under the control of the potential of the pull-up node, a gate driving signal to be output from the gate driving signal output end.

Description

Gate driving unit, gate driving method, gate driving circuit and display device

Cross references to related applications

This application claims the priority of Chinese Patent Application No. 201910280690.3 filed in China on April 9, 2019, the entire content of which is incorporated herein by reference.

Technical field

The present disclosure relates to the field of display driving technology, and in particular to a gate driving unit, a gate driving method, a gate driving circuit and a display device.

Background technique

Display panels with touch function often show poor horizontal stripes after the reliability test. The main reason is that they are affected by leakage current or threshold voltage shift. The first-level gate drive scan after the touch time period The voltage of the pull-up node of the unit is greatly reduced after the touch time period has elapsed, so that the output transistor included in the gate drive unit is not completely turned on or even cannot be turned on, resulting in the gate drive output by the first-stage gate drive unit The voltage amplitude of the signal is reduced or there is no output, resulting in poor horizontal stripes and screen splitting.

Summary of the invention

The present disclosure provides a gate driving unit including a pull-up control node control circuit, an on-off control circuit, and an output circuit, wherein,

The pull-up control node control circuit is connected to the pull-up control node, and is used to control the potential of the pull-up control node;

The on-off control circuit is respectively connected to the pull-up node and the gate drive signal output terminal, and is used for turning on or disconnecting the pull-up control node and the gate drive signal under the control of the on-off control signal input from the on-off control terminal. The connection between the pull-up nodes;

The output circuit is respectively connected to the pull-up node and the gate drive signal output terminal for controlling the output of the gate drive signal through the gate drive signal output terminal under the control of the potential of the pull-up node.

In implementation, the on-off control terminal includes a pull-down node and a first clock signal input terminal;

The on-off control circuit includes a first on-off control transistor and a second on-off control transistor;

The control electrode of the first on-off control transistor is connected to the pull-down node, the first electrode of the first on-off control transistor is connected to the pull-up node, and the second electrode of the first on-off control transistor Connected to the pull-up control node;

The control electrode of the second on-off control transistor is connected to the first clock signal input terminal, the first electrode of the second on-off control transistor is connected to the pull-up control node, and the second on-off control transistor The second pole of the transistor is connected to the pull-up node.

In implementation, the pull-up control node control circuit includes a first pull-up control sub-circuit and a second pull-up control sub-circuit;

The first pull-up control sub-circuit is respectively connected to the input terminal, the pull-up control node, and the first scan voltage terminal, and is used to control the pull-up control node under the control of the input signal input from the input terminal Connected to the first scanning voltage terminal;

The second pull-up control sub-circuit is respectively connected to the reset terminal, the pull-up control node, and the second scan voltage terminal, and is used to control the pull-up control node under the control of the reset signal input from the reset terminal Connect with the second scanning voltage terminal.

During implementation, the first pull-up control sub-circuit includes a first pull-up control transistor, and the second pull-up control sub-circuit includes a second pull-up control transistor;

The control electrode of the first pull-up control transistor is connected to the input terminal, the first electrode of the first pull-up control transistor is connected to the first scan voltage terminal, and the first electrode of the first pull-up control transistor is connected to the first scan voltage terminal. The two poles are connected to the pull-up control node;

The control electrode of the second pull-up control transistor is connected to the reset terminal, the first electrode of the second pull-up control transistor is connected to the pull-up control node, and the second electrode of the second pull-up control transistor The pole is connected to the second scanning voltage terminal.

In implementation, the gate driving unit described in the present disclosure further includes a pull-down node control circuit;

The pull-down node control circuit is respectively connected to a pull-down node, a pull-down control clock signal input terminal, the pull-up node, and the gate drive signal output terminal, and is used to control the clock signal, the potential of the pull-up node, and Under the control of the gate drive signal, the potential of the pull-down node is controlled.

In implementation, the pull-down node control circuit includes:

The first pull-down control transistor, the control electrode and the first electrode are both connected to the pull-down control clock signal input terminal, and the second electrode is connected to the pull-down node;

A second pull-down control transistor, a control electrode is connected to the pull-up node, a first electrode is connected to the pull-down node, and a second electrode is connected to the first voltage terminal;

A third pull-down control transistor, a control electrode is connected to the gate drive signal output terminal, a first electrode is connected to the pull-down node, and a second electrode is connected to the first voltage terminal; and,

The storage capacitor is pulled down, the first terminal is connected to the pull-down node, and the second terminal is connected to the first voltage terminal.

In implementation, the gate driving unit described in the present disclosure further includes a pull-up node control circuit, wherein:

The pull-up node control circuit is respectively connected to the pull-up node and the pull-down node, and is configured to control the potential of the pull-up node under the control of the potential of the pull-down node;

The output circuit is respectively connected to the pull-up node, the gate drive signal output terminal and the second clock signal input terminal, and is used to control the gate drive signal under the control of the potential of the pull-up node The output terminal is connected to the second clock signal input terminal.

In implementation, the pull-up node control circuit includes a pull-up node control transistor and a pull-up storage capacitor, and the output circuit includes an output transistor;

The control electrode of the pull-up node control transistor is connected to the pull-down node, the first electrode of the pull-up node control transistor is connected to the pull-up node, and the second electrode of the pull-up node control transistor is connected to the first Voltage terminal connection;

A first end of the pull-up storage capacitor is connected to the pull-up node, and a second end of the pull-up storage capacitor is connected to the gate drive signal output end;

The control electrode of the output transistor is connected to the pull-up node, the first electrode of the output transistor is connected to the second clock signal input terminal, and the second electrode of the output transistor is connected to the gate drive signal output terminal .

In implementation, the gate driving unit described in the present disclosure further includes an output reset circuit, wherein:

The output reset circuit is respectively connected to the pull-down node, the gate drive signal output terminal and the first voltage terminal, and is used to control the gate drive signal output terminal and the first voltage terminal under the control of the potential of the pull-down node. The first voltage terminals are connected.

The present disclosure also provides a gate driving method for driving the above-mentioned gate driving unit, and the gate driving method includes:

During the touch time period, the on-off control circuit disconnects the connection between the pull-up control node and the pull-up node under the control of the on-off control signal input from the on-off control terminal.

During implementation, the gate driving unit further includes a pull-down node control circuit for controlling the potential of the pull-down node under the control of the pull-down control clock signal, the potential of the pull-up node, and the gate drive signal;

The gate driving method further includes:

In the display period, when the potential of the pull-up node is an effective voltage, under the control of the pull-down control clock signal, the pull-down node control circuit controls the pull-down node to disconnect from the pull-down control clock signal input terminal.

The present disclosure also provides a gate driving circuit, including multiple stages of the above-mentioned gate driving units;

Except for the gate driving unit of the first stage, the input terminal of the gate driving unit of each stage is connected to the gate driving signal output terminal of the adjacent previous stage gate driving unit;

Except for the gate drive unit of the last stage, the input terminal of the gate drive unit of each stage is connected to the gate drive signal output terminal of the adjacent next stage gate drive unit.

In implementation, in the 3n-2 stage gate drive unit, the first clock signal input terminal is connected to the first clock signal terminal, the second clock signal input terminal is connected to the second clock signal terminal, and the third clock signal input terminal is connected to the first clock signal terminal. Three clock signal terminals are connected; n is a positive integer;

In the 3n-1 stage gate driving unit, the first clock signal input terminal is connected to the second clock signal terminal, the second clock signal input terminal is connected to the third clock signal terminal, and the third clock signal input terminal is connected to the first clock signal End connection

In the 3n-th stage gate drive unit, the first clock signal input terminal is connected to the third clock signal terminal, the second clock signal input terminal is connected to the first clock signal terminal, and the third clock signal input terminal is connected to the second clock signal terminal. .

The present disclosure also provides a display device including the above-mentioned gate drive circuit.

Description of the drawings

FIG. 1 is a structural diagram of a gate driving unit according to an embodiment of the present disclosure;

2 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure;

3 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure;

4 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure;

5 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure;

6 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure;

FIG. 7 is a structural diagram of a gate driving unit according to still another embodiment of the present disclosure;

FIG. 8 is a circuit diagram of a specific embodiment of the gate driving unit according to the present disclosure; and

FIG. 9 is a working timing diagram of the specific embodiment of the gate driving unit described in the present disclosure.

detailed description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present disclosure.

The transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the control pole, one of the poles is called the first pole and the other pole is called the second pole.

In actual operation, when the transistor is a triode, the control electrode can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base. The first electrode may be an emitter electrode, and the second electrode may be a collector electrode.

In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.

As shown in FIG. 1, the gate driving unit according to the embodiment of the present disclosure includes a pull-up control node control circuit 11, an on-off control circuit 12, and an output circuit 13, wherein,

The pull-up control node control circuit 11 is connected to the pull-up control node PUCN, and is used to control the potential of the pull-up control node PUCN;

The on-off control circuit 12 is respectively connected to the on-off control terminal Cs, the pull-up control node PUCN, and the pull-up node PU, and is used to turn on or off under the control of the on-off control signal input from the on-off control terminal Cs. Disconnect the connection between the pull-up control node PUCN and the pull-up node PU;

The output circuit 13 is respectively connected to the pull-up node PU and the gate drive signal output terminal OUTPUT, and is used to control the output of the gate drive signal through the gate drive signal output terminal OUTPUT under the control of the potential of the pull-up node PU .

When the gate driving unit according to the embodiment of the present disclosure is working, in the touch time period, under the control of the on-off control signal input by Cs, the connection between the pull-up control node PUCN and the pull-up node PU is controlled to be disconnected In order to prevent the potential of the pull-up node PU from being lowered due to the large leakage current during the touch time period, the potential of the pull-up node PU is maintained at a higher potential, so as to effectively improve the horizontal display of the display panel after the reliability test. Defective pattern of split screen.

In specific implementation, the on-off control terminal may include a pull-down node and a first clock signal input terminal; the first clock signal input terminal is used to input a first clock signal;

As shown in FIG. 2, based on the embodiment of the gate driving unit shown in FIG. 1, the on-off control terminal includes a pull-down node PD and a first clock signal input terminal; the first clock signal input terminal is used for To input the first clock signal CK1;

The on-off control circuit 12 includes a first on-off control transistor T9 and a second on-off control transistor T10;

The gate of the first on-off control transistor T9 is connected to the pull-down node PD, the drain of the first on-off control transistor T9 is connected to the pull-up node PU, and the first on-off control transistor T9 The source of is connected to the pull-up control node PUCN;

The gate of the second on-off control transistor T10 is connected to the first clock signal input terminal, the drain of the second on-off control transistor T10 is connected to the pull-up control node PUCN, and the second on-off control transistor T10 is connected to the pull-up control node PUCN. The source of the off control transistor T10 is connected to the pull-up node PU;

In the embodiment shown in FIG. 2, T9 and T10 are both n-type thin film transistors, but not limited to this.

When the embodiment of the gate driving unit shown in FIG. 2 of the present disclosure works,

During the touch time period, CK1 is low, and the potential of PD is low, T9 and T10 are both turned off to disconnect the connection between PU and PUCN, cut off the leakage path of PU, and ensure that the potential of PU is Higher potential.

Specifically, the pull-up control node control circuit may include a first pull-up control sub-circuit and a second pull-up control sub-circuit;

The first pull-up control sub-circuit is used to control the pull-up control node to be connected to the first scan voltage terminal under the control of the input signal input from the input terminal;

The second pull-up control sub-circuit is used for controlling the pull-up control node to be connected to the second scan voltage terminal under the control of the reset signal input from the reset terminal.

In specific implementation, the pull-up control node control circuit can control the potential of the pull-up control node under the control of the input signal and the reset signal.

The embodiments of the present disclosure can control forward scanning or reverse scanning by setting the first scanning voltage input from the first scanning voltage terminal and the second scanning voltage input from the second scanning voltage terminal.

As shown in FIG. 3, based on the embodiment of the gate driving unit shown in FIG. 1, the pull-up control node control circuit 11 includes a first pull-up control sub-circuit 111 and a second pull-up control sub-circuit 112 ；

The first pull-up control sub-circuit 111 is respectively connected to the input terminal Input, the pull-up control node PUCN, and the first scan voltage terminal CN, and is used to control the pull-up under the control of the input signal input from the input terminal Input. The pull control node PUCN is connected to the first scan voltage terminal CN;

The second pull-up control sub-circuit 112 is respectively connected to the reset terminal Reset, the pull-up control node PUCN, and the second scan voltage terminal CNB, and is used to control the reset terminal under the control of the reset signal input from the reset terminal. The pull control node PUCN is connected to the second scan voltage terminal CNB.

In specific implementation, Input is connected to the gate driving signal output terminal of the adjacent upper-level gate driving unit, and Reset is connected to the gate driving signal output terminal of the adjacent lower-level gate driving unit.

When the embodiment of the gate driving unit shown in FIG. 3 of the present disclosure is working, in forward scanning, CN inputs an effective voltage and CNB inputs an invalid voltage; in reverse scanning, CN inputs an invalid voltage, and CNB inputs an effective voltage .

Specifically, the effective voltage is a voltage capable of turning on a transistor whose gate is connected to it. For example, when the transistor is an n-type transistor, the effective voltage may be a high voltage; when the transistor is a p-type transistor, The effective voltage can be a low voltage;

The invalid voltage is a voltage capable of turning off the transistor whose gate is connected. For example, when the transistor is an n-type transistor, the invalid voltage may be a low voltage; when the transistor is a p-type transistor, the invalid voltage Can be high voltage.

Specifically, the first pull-up control sub-circuit may include a first pull-up control transistor, and the second pull-up control sub-circuit may include a second pull-up control transistor;

As shown in FIG. 4, on the basis of the embodiment of the gate driving unit shown in FIG. 3, the first pull-up control sub-circuit 111 includes a first pull-up control transistor T1, and the second pull-up control sub-circuit The circuit 112 includes a second pull-up control transistor T2;

The gate of T1 is connected to the input terminal Input, the drain of T1 is connected to the first scan voltage terminal CN, and the source of T1 is connected to the pull-up control node PUCN;

The gate of T2 is connected to the reset terminal Reset, the drain of T2 is connected to the pull-up control node PUCN, and the source of T2 is connected to the second scan voltage terminal CNB.

In the embodiment shown in FIG. 4, Input is connected to the gate driving signal output end of the adjacent upper-level gate driving unit, and Reset is connected to the gate driving signal output end of the adjacent lower-level gate driving unit.

In the embodiment shown in FIG. 4, both T1 and T2 are n-type thin film transistors, but not limited to this.

When the embodiment of the gate driving unit shown in FIG. 4 of the present disclosure is working, during forward scanning, CN inputs a high level and CNB inputs a low level. In the input phase, Input inputs a high level, and Reset inputs a low level. Level, T1 is turned on, T2 is turned off, to control the PU's potential to be high. In the reset phase, Input is low, Reset is high, T1 is turned off, and T2 is turned on to control the PU's potential to be low Level

In the reverse scan, CN inputs low level, CNB inputs high level, in the input stage, Reset inputs high level, Input inputs low level, T2 is turned on, and T1 is turned off to control the potential of PU to be high , In the reset phase, Input inputs high level, Reset inputs low level, T1 is turned on, and T2 is turned off to control the potential of PU to be low.

In the gate driving unit in the related art, the on-off control circuit 12 is not provided. During forward scanning, since the drain of T2 is connected to the pull-up node PU, the source of T2 is connected to the input low-level For CNB connection, during the touch time period, the potential of PU will be affected by the leakage current of T2 and decrease, especially after the reliability test, the characteristic curve of TFT (Thin Film Transistor) drifts and the leakage current increases under zero bias. Because the potential of PU decreases more. Based on this, the embodiment of the present disclosure adds an on-off control circuit 12. During the touch time period, the on-off control circuit 12 disconnects the connection between the pull-up node PU and the pull-up control node PUCN, so that the potential of the PU is not affected. The leakage current of T2 effectively reduces the voltage drop of PU, so that at the end of the touch time period and entering the next display period, the output transistor can be turned on normally, so that the corresponding row gate drive unit outputs a high level and returns to normal Display the screen.

In specific implementation, the gate driving unit described in the present disclosure may further include a pull-down node control circuit;

The pull-down node control circuit is used to control the potential of the pull-down node under the control of a pull-down control clock signal, the potential of the pull-up node, and the gate drive signal.

As shown in FIG. 5, based on the embodiment of the gate driving unit shown in FIG. 1, the gate driving unit according to the embodiment of the present disclosure further includes a pull-down node control circuit 14;

The pull-down node control circuit 14 is respectively connected to the pull-down node PD, the pull-down control clock signal input terminal (or called the third clock signal input terminal), the pull-up node PU and the gate drive signal output terminal OUTPUT, and Under the control of the pull-down control clock signal CK3 input at the pull-down control clock signal input terminal, the potential of the pull-up node PU, and the gate drive signal output from the gate drive signal output terminal OUTPUT, the pull-down is controlled Potential of node PD.

The pull-down node control circuit 14 in the gate driving unit described in the embodiment of the present disclosure controls the potential of the PD under the control of the potentials of CK3, PU and OUTPUT; when the gate driving unit described in the embodiment of the present disclosure works, When the potential of PU rises, CK3 becomes an invalid voltage, so that the transistor whose gate is connected to CK3 included in the pull-down node control circuit 14 is turned off, and under the control of the potential of PU, the potential of PD becomes an invalid voltage. , So that the potential of the PU can be maintained at a higher potential, while no direct current path is formed in the circuit, which can effectively reduce the power consumption of the gate drive unit.

Specifically, the pull-down node control circuit may include:

In specific implementation, the first voltage terminal may be a low voltage terminal, but is not limited to this.

As shown in FIG. 6, based on the embodiment of the gate driving unit shown in FIG. 5, the pull-down node control circuit 14 includes a first pull-down control transistor T7, a second pull-down control transistor T6, and a third pull-down control transistor. Transistor T8 and pull-down storage capacitor C2, among them,

The gate of T7 and the drain of T7 are both connected to the pull-down control clock signal CK3, and the source of T7 is connected to the pull-down node PD;

The gate of T6 is connected to the pull-up node PU, the drain of T6 is connected to the pull-down node PD, and the source of T6 is connected to the low voltage VSS;

The gate of T8 is connected to the gate drive signal output terminal OUTPUT, the drain of T8 is connected to the pull-down node PD, and the source of T8 is connected to the low voltage VSS;

The first terminal of C2 is connected to the pull-down node PD, and the second terminal of C2 is connected to the low voltage VSS.

In the embodiment shown in FIG. 6, each transistor is an n-type thin film transistor, but it is not limited thereto.

When the embodiment of the gate driving unit of the present disclosure shown in FIG. 6 is working, when the potential of PU rises, CK3 is low, T7 is turned off, and PU pulls down the potential of PD through T6, so that the The electric potential is maintained at a higher potential, and no DC path is formed in the circuit. The power consumption simulation result of the simulation software is obtained. The power consumption of the gate drive unit described in the embodiment of the present disclosure is about that of the 8T2C gate drive unit in the related art. 1/4 of the power consumption, effectively reducing the power consumption of the gate drive unit.

In specific implementation, the gate driving unit described in the present disclosure may further include a pull-up node control circuit and an output reset circuit, where:

The pull-up node control circuit is used to control the potential of the pull-up node under the control of the potential of the pull-down node;

The output circuit is used to control the gate drive signal output terminal to be connected to the second clock signal input terminal under the control of the potential of the pull-up node;

The output reset circuit is used to control the communication between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the pull-down node.

As shown in FIG. 7, on the basis of the embodiment of the gate driving unit shown in FIG. 5, the gate driving unit described in the embodiment of the present disclosure may further include a pull-up node control circuit 15 and an output reset circuit 16, wherein ,

The pull-up node control circuit 15 is respectively connected to the pull-up node PU and the pull-down node PD, and is configured to control the potential of the pull-up node PU under the control of the potential of the pull-down node PD;

The output circuit 13 is respectively connected to the pull-up node PU, the gate drive signal output terminal OUTPUT, and the second clock signal input terminal, and is used to control the pull-up node PU under the control of the potential of the The gate drive signal output terminal OUTPUT is connected to the second clock signal input terminal; the second clock signal input terminal is used to input the second clock signal CK2;

The output reset circuit 16 is respectively connected to the pull-down node PD, the gate drive signal output terminal and to the first voltage terminal, and is used to control the gate drive under the control of the potential of the pull-down node PD. The signal output terminal OUTPUT is connected with the first voltage terminal.

In this embodiment, the first voltage terminal is used to input a low voltage VSS.

When the embodiment of the gate driving unit of the present disclosure shown in FIG. 7 is working, the output circuit 13 is used to control the OUTPUT to output an effective voltage, the output reset circuit 16 is used to control the OUTPUT to output an invalid voltage, and the pull-up node control circuit 15 is used to When the potential of PD is a valid voltage, the potential of the PU is controlled to be an invalid voltage.

In specific implementation, the pull-up node control circuit 15 may include a pull-up node control transistor and a pull-up storage capacitor, the output circuit 13 may include an output transistor, and the output reset circuit 16 may include an output reset transistor;

The control electrode of the pull-up node control transistor is connected to the pull-down node PD, the first electrode of the pull-up node control transistor is connected to the pull-up node PU, and the second electrode of the pull-up node control transistor is connected to The first voltage terminal is connected to access the low voltage VSS;

The first end of the pull-up storage capacitor is connected to the pull-up node PU, and the second end of the pull-up storage capacitor is connected to the gate drive signal output terminal OUTPUT;

The control electrode of the output transistor is connected to the pull-up node PU, the first electrode of the output transistor is connected to the second clock signal CK2, and the second electrode of the output transistor is connected to the gate drive signal output Terminal OUTPUT connection;

The control electrode of the output reset transistor is connected to the pull-down node PD, the first electrode of the output reset transistor is connected to the gate drive signal output terminal, and the second electrode of the output reset transistor is connected to the first voltage terminal. Connect to access low voltage VSS.

In the following, a specific embodiment is used to illustrate the gate driving unit described in the present disclosure.

As shown in FIG. 8, a specific embodiment of the gate driving unit described in the present disclosure includes a pull-up control node control circuit 11, an on-off control circuit 12, an output circuit 13, a pull-down node control circuit 14, and a pull-up node control circuit 15 and output reset circuit 16, in which,

The pull-up control node control circuit includes a first pull-up control sub-circuit 111 and a second pull-up control sub-circuit 112;

The first pull-up control sub-circuit 111 includes a first pull-up control transistor T1, and the second pull-up control sub-circuit 112 includes a second pull-up control transistor T2;

The gate of T1 is connected to the input terminal Input, the drain of T1 is connected to the first scan voltage terminal CN, and the source of T1 is connected to the pull-up node PU;

The gate of T2 is connected to the reset terminal Reset, the drain of T2 is connected to the pull-up node PU, and the source of T2 is connected to the second scan voltage terminal CNB;

Input is connected to the gate drive signal output terminal of the adjacent upper stage gate drive unit, and Reset is connected to the gate drive signal output terminal of the adjacent next stage gate drive unit;

The pull-down node control circuit 14 includes a first pull-down control transistor T7, a second pull-down control transistor T6, a third pull-down control transistor T8 and a pull-down storage capacitor C2, wherein,

The first terminal of C2 is connected to the pull-down node PD, and the second terminal of C2 is connected to the low voltage VSS;

The pull-up node control circuit 15 includes a pull-up node control transistor T5 and a pull-up storage capacitor C1, the output circuit 13 includes an output transistor T3, and the output reset circuit 16 includes an output reset transistor T4;

The gate of the pull-up node control transistor T5 is connected to the pull-down node PD, the drain of the pull-up node control transistor T5 is connected to the pull-up node PU, and the pull-up node controls the source of the transistor T5 Connect to low voltage VSS;

A first end of the pull-up storage capacitor C1 is connected to the pull-up node PU, and a second end of the pull-up storage capacitor C1 is connected to the gate drive signal output terminal OUTPUT;

The gate of the output transistor T3 is connected to the pull-up node PU, the drain of the output transistor T3 is connected to the second clock signal CK2, and the source of the output transistor T3 is connected to the gate drive signal Output terminal OUTPUT connection;

The gate of the output reset transistor T4 is connected to the pull-down node PD, the drain of the output reset transistor T4 is connected to the gate drive signal output terminal, and the source of the output reset transistor T4 is connected to a low voltage VSS.

In the specific embodiment of the gate driving unit shown in FIG. 8, all the transistors are n-type thin film transistors, but not limited to this.

In the specific embodiment of the gate driving unit shown in FIG. 8, C1 is used to bootstrap the potential of the PU, and C2 is used to stabilize the voltage of the PD and reduce the noise of the PD.

As shown in FIG. 9, the specific embodiment of the gate driving unit shown in FIG. 8 of the present disclosure is in operation, and after a reliability test is performed, during forward scanning, CN inputs a high level, and CNB inputs a low level. level;

In the input phase t1, Input inputs high level, Reset inputs low level, CK1 is high level, T10 is on, T1 is on, T2 is off, the potential of PU is high, CK2 and CK3 are both low, OUTPUT outputs low level, and the potential of PD is low level;

Enter the touch time period TB after the input stage t1;

In the touch time period TB, CK1, CK2, and CK3 are all low, and T9 and T10 are all turned off to avoid that the potential of the pull-up node PU decreases due to the large leakage current of T2 during the touch time period. Keep the potential of the pull-up node PU at a higher potential to effectively improve the horizontal stripes and split screen defects of the display panel after the reliability test;

After the touch time period TB ends, enter the output stage t2;

In the output stage t2, CK2 is high, CK1 and CK3 are both low, the potential of PU is boosted by C1 bootstrap, T3 is turned on, OUTPUT outputs high, and T8 and T6 are turned on to make the potential of PD Because CK3 is low and the potential of PD is also low, both T5 and T7 are turned off, so that the potential of PU remains high. At the same time, no DC path is formed in the circuit to reduce power Consumption

In the reset phase t3, Reset inputs high level, Input inputs low level, T1 is turned off, T2 is turned on, CK3 is high, CK1 and CK2 are both low, T9 is turned on, and the potential of PU is low. T7 is turned on, T6 is turned off, so that the potential of PD is high, T3 is turned off, and T4 is turned on to control OUTPUT to output a low level.

In FIG. 9, PU0 is the pull-up node of the adjacent upper-level gate drive unit. Before the touch time period TB starts, the potential of PU0 is pulled up. During the touch time period TB, The potential of PU0 is also maintained at a high level.

In some embodiments, using the gate driving unit described in the embodiments of the present disclosure, after the reliability test is performed on the gate driving unit, the potential of PU can be maintained at about 4.4V during the touch time period TB If the reliability test of the gate driving unit is not done, the potential of PU can be maintained at about 6.4V during the touch time period TB. It can be seen from the above that the gate driving unit according to the embodiments of the present disclosure can maintain the potential of the pull-up node PU during the touch time period TB even after the reliability test of the gate driving circuit, so that After the touch time period TB has elapsed, the potential of the PU can still be maintained at a high level without affecting the output of the gate driving signal by the gate driving unit.

The gate driving method according to the embodiment of the present disclosure is used to drive the above-mentioned gate driving unit, and the gate driving method includes:

In the gate driving method according to the embodiment of the present disclosure, during the touch time period, the on-off control circuit controls to disconnect the connection between the pull-up control node and the pull-up node under the control of the on-off control signal, so as to avoid touching During the control period, the potential of the pull-up node is reduced due to the large leakage current, so that the potential of the pull-up node is maintained at a higher potential, so as to effectively improve the horizontal stripe splitting phenomenon of the display panel after the reliability test.

In specific implementation, the gate driving unit further includes a pull-down node control circuit, configured to control the potential of the pull-down node under the control of the pull-down control clock signal, the potential of the pull-up node, and the gate drive signal;

The gate driving method further includes:

When the gate driving unit according to the embodiment of the present disclosure is working, when the potential of the pull-up node rises, the pull-down control clock signal is an invalid voltage, so that the gate included in the pull-down node control circuit is connected to the pull-down control clock The signal transistor is turned off, and under the control of the potential of the pull-up node, the potential of the pull-down node is made an invalid voltage, so that the potential of the pull-up node can be maintained at a higher potential. At the same time, no DC path is formed in the circuit, which can effectively reduce Power consumption of the gate drive unit.

The gate driving circuit according to the embodiment of the present disclosure includes multiple stages of the above-mentioned gate driving unit;

In some embodiments, the pull-up control node control circuit includes a first pull-up control sub-circuit and a second pull-up control sub-circuit; the first pull-up control sub-circuit is connected to the input terminal and the pull-up control sub-circuit respectively The node is connected to the first scan voltage terminal, and is used to control the pull-up control node to be connected to the first scan voltage terminal under the control of the input signal input from the input terminal; the second pull-up control sub-circuit Respectively connected to the reset terminal, the pull-up control node and the second scan voltage terminal, and are used to control the pull-up control node to be connected to the second scan voltage terminal under the control of the reset signal input from the reset terminal In the above-mentioned multi-stage gate drive unit, in addition to the first-stage gate drive unit, the input terminal of each stage of the gate drive unit and the gate drive of the adjacent previous-stage gate drive unit The signal output terminal is connected; except for the gate drive unit of the last stage, the reset terminal of the gate drive unit of each stage is connected to the gate drive signal output terminal of the adjacent next stage gate drive unit.

In specific implementation, in the 3n-2th stage gate drive unit in the gate drive circuit of the embodiment of the present disclosure, the first clock signal input terminal is connected to the first clock signal terminal, and the second clock signal input terminal Connected to the second clock signal terminal, and the third clock signal input terminal is connected to the third clock signal terminal; n is a positive integer;

In the 3n-1 stage gate drive unit in the gate drive circuit according to the embodiment of the present disclosure, the first clock signal input terminal is connected to the second clock signal terminal, and the second clock signal input terminal is connected to the third clock signal Terminal connected, the third clock signal input terminal is connected with the first clock signal terminal;

In the 3n-th stage gate drive unit in the gate drive circuit according to the embodiment of the present disclosure, the first clock signal input terminal is connected to the third clock signal terminal, and the second clock signal input terminal is connected to the first clock signal terminal , The third clock signal input terminal is connected to the second clock signal terminal.

The display device according to the embodiment of the present disclosure includes the above-mentioned gate driving circuit.

The display device provided by the embodiment of the present disclosure may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

The above are the preferred embodiments of the present disclosure. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present disclosure, several improvements and modifications can be made, and these improvements and modifications are also It should be regarded as the protection scope of this disclosure.

Claims

A gate drive unit includes a pull-up control node control circuit, an on-off control circuit and an output circuit, wherein

The pull-up control node control circuit is connected to the pull-up control node, and is used to control the potential of the pull-up control node;

The on-off control circuit is respectively connected to the pull-up node and the gate drive signal output terminal, and is used for turning on or disconnecting the pull-up control node and the gate drive signal under the control of the on-off control signal input from the on-off control terminal. The connection between the pull-up nodes;

The output circuit is respectively connected to the pull-up node and the gate drive signal output terminal for controlling the output of the gate drive signal through the gate drive signal output terminal under the control of the potential of the pull-up node.
3. The gate driving unit of claim 1, wherein the on-off control terminal comprises a pull-down node and a first clock signal input terminal;

The on-off control circuit includes a first on-off control transistor and a second on-off control transistor;

The control electrode of the first on-off control transistor is connected to the pull-down node, the first electrode of the first on-off control transistor is connected to the pull-up node, and the second electrode of the first on-off control transistor Connected to the pull-up control node;

The control electrode of the second on-off control transistor is connected to the first clock signal input terminal, the first electrode of the second on-off control transistor is connected to the pull-up control node, and the second on-off control transistor The second pole of the transistor is connected to the pull-up node.
3. The gate driving unit of claim 1, wherein the pull-up control node control circuit comprises a first pull-up control sub-circuit and a second pull-up control sub-circuit;

The first pull-up control sub-circuit is respectively connected to the input terminal, the pull-up control node, and the first scan voltage terminal, and is used to control the pull-up control node under the control of the input signal input from the input terminal Connected to the first scanning voltage terminal;

The second pull-up control sub-circuit is respectively connected to the reset terminal, the pull-up control node, and the second scan voltage terminal, and is used to control the pull-up control node under the control of the reset signal input from the reset terminal Connected to the second scanning voltage terminal.
5. The gate driving unit of claim 3, wherein the first pull-up control sub-circuit includes a first pull-up control transistor, and the second pull-up control sub-circuit includes a second pull-up control transistor;

The control electrode of the first pull-up control transistor is connected to the input terminal, the first electrode of the first pull-up control transistor is connected to the first scan voltage terminal, and the first electrode of the first pull-up control transistor is connected to the first scan voltage terminal. The two poles are connected to the pull-up control node;

The control electrode of the second pull-up control transistor is connected to the reset terminal, the first electrode of the second pull-up control transistor is connected to the pull-up control node, and the second electrode of the second pull-up control transistor The pole is connected to the second scanning voltage terminal.
4. The gate driving unit of claim 1, further comprising a pull-down node control circuit;

The pull-down node control circuit is respectively connected to a pull-down node, a pull-down control clock signal input terminal, the pull-up node, and the gate drive signal output terminal, and is used to control the clock signal, the potential of the pull-up node, and Under the control of the gate drive signal, the potential of the pull-down node is controlled.
7. The gate driving unit of claim 5, wherein the pull-down node control circuit comprises:

The first pull-down control transistor, the control electrode and the first electrode are both connected to the pull-down control clock signal input terminal, and the second electrode is connected to the pull-down node;

A second pull-down control transistor, a control electrode is connected to the pull-up node, a first electrode is connected to the pull-down node, and a second electrode is connected to the first voltage terminal;

A third pull-down control transistor, a control electrode is connected to the gate drive signal output terminal, a first electrode is connected to the pull-down node, and a second electrode is connected to the first voltage terminal; and,

The storage capacitor is pulled down, the first terminal is connected to the pull-down node, and the second terminal is connected to the first voltage terminal.
The gate driving unit according to any one of claims 1 to 6, further comprising a pull-up node control circuit, wherein:

The pull-up node control circuit is respectively connected to the pull-up node and the pull-down node, and is configured to control the potential of the pull-up node under the control of the potential of the pull-down node;

The output circuit is respectively connected to the pull-up node, the gate drive signal output terminal and the second clock signal input terminal, and is used to control the gate drive signal under the control of the potential of the pull-up node The output terminal is connected to the second clock signal input terminal.
7. The gate driving unit according to claim 7, wherein the pull-up node control circuit includes a pull-up node control transistor and a pull-up storage capacitor, and the output circuit includes an output transistor;

The control electrode of the pull-up node control transistor is connected to the pull-down node, the first electrode of the pull-up node control transistor is connected to the pull-up node, and the second electrode of the pull-up node control transistor is connected to the first Voltage terminal connection;

A first end of the pull-up storage capacitor is connected to the pull-up node, and a second end of the pull-up storage capacitor is connected to the gate drive signal output end;

The control electrode of the output transistor is connected to the pull-up node, the first electrode of the output transistor is connected to the second clock signal input terminal, and the second electrode of the output transistor is connected to the gate drive signal output terminal .
The gate driving unit according to any one of claims 1 to 8, further comprising an output reset circuit, wherein:

The output reset circuit is respectively connected to the pull-down node, the gate drive signal output terminal and the first voltage terminal, and is used to control the gate drive signal output terminal and the first voltage terminal under the control of the potential of the pull-down node. The first voltage terminals are connected.
9. The gate driving unit of claim 9, wherein the output reset circuit comprises an output reset transistor,

The control electrode of the output reset transistor is connected to the pull-down node, the first electrode of the output reset transistor is connected to the gate drive signal output terminal, and the second electrode of the output reset transistor is connected to the first voltage端连接。 End connection.
A gate driving method for driving the gate driving unit according to any one of claims 1 to 10, the gate driving method comprising:

During the touch time period, the on-off control circuit disconnects the connection between the pull-up control node and the pull-up node under the control of the on-off control signal input from the on-off control terminal.
The gate driving method of claim 11, wherein the gate driving unit further comprises a pull-down node control circuit for controlling the clock signal, the potential of the pull-up node, and the gate driving signal in the pull-down mode. Down, control the potential of the pull-down node;

The gate driving method further includes:

In the display period, when the potential of the pull-up node is an effective voltage, under the control of the pull-down control clock signal, the pull-down node control circuit controls the pull-down node to disconnect from the pull-down control clock signal input terminal.
A gate driving circuit, comprising multiple stages of the gate driving unit according to any one of claims 1 to 10;

Except for the gate driving unit of the first stage, the input terminal of the gate driving unit of each stage is connected to the gate driving signal output terminal of the adjacent previous stage gate driving unit;

Except for the gate drive unit of the last stage, the input terminal of the gate drive unit of each stage is connected to the gate drive signal output terminal of the adjacent next stage gate drive unit.
The gate drive circuit of claim 13, wherein:

In the 3n-2 stage gate driving unit, the first clock signal input terminal is connected to the first clock signal terminal, the second clock signal input terminal is connected to the second clock signal terminal, and the third clock signal input terminal is connected to the third clock signal terminal. End connection; n is a positive integer;

In the 3n-1 stage gate driving unit, the first clock signal input terminal is connected to the second clock signal terminal, the second clock signal input terminal is connected to the third clock signal terminal, and the third clock signal input terminal is connected to the first clock signal End connection

In the 3n-th stage gate drive unit, the first clock signal input terminal is connected to the third clock signal terminal, the second clock signal input terminal is connected to the first clock signal terminal, and the third clock signal input terminal is connected to the second clock signal terminal. .
A display device comprising the gate driving circuit according to claim 13 or 14.