WO2020203798A1 - Image pickup element and image pickup device - Google Patents

Abstract

This image pickup element comprises: a plurality of photoelectric conversion units which are provided in each of a first region, a second region, and a third region between the first region and the second region, and photoelectrically convert light to generate charges; a first output unit which outputs at least one among a signal based on the charges generated by the plurality of photoelectric conversion units provided in the first region and a signal based on the charges generated by the plurality of photoelectric conversion units provided in the second region; and a second output unit which outputs a signal based on the charges generated by the plurality of photoelectric conversion units provided in the third region.

Description

Image sensor and image sensor

The present invention relates to an image pickup device and an image pickup device.

There is known an image sensor that collects a plurality of pixels into blocks and reads signals in parallel in block units (see Patent Document 1). With such an image sensor, it is difficult to perform interpolation processing when a defect occurs in the block.

Japanese Patent Application Laid-Open No. 2016-171455

The image pickup device according to the first aspect of the present invention is provided in each of a first region, a second region, and a third region between the first region and the second region, and charges light by photoelectric conversion. A signal based on the electric charge generated by the plurality of photoelectric conversion units provided in the first region, and the plurality of photoelectric conversion units provided in the second region. It includes a first output unit that outputs at least one of a charge-based signal, and a second output unit that outputs a charge-based signal generated by a plurality of the photoelectric conversion units provided in the third region.
The image pickup apparatus according to the second aspect of the present invention is a generation unit that generates image data based on the image pickup device according to the first aspect and signals output from at least one of the first output unit and the second output unit. And.

It is a figure which shows the configuration example of a digital camera. It is a figure explaining the outline of the image sensor. It is a figure explaining the cross section of an image sensor. It is a figure which illustrates the Bayer arrangement. It is a circuit diagram explaining the structure of a block. It is a schematic diagram which illustrates the relationship between the arrangement of a color filter and a block. 7 (a) to 7 (d) are diagrams for explaining the first block to the fourth block, respectively. It is a figure explaining the interpolation processing. 9 (a) and 9 (b) are diagrams for explaining a wiring example of the output signal line. 10 (a) and 10 (b) are diagrams for explaining other wiring examples of the output signal line. 11 (a) and 11 (b) are diagrams for explaining another wiring example of the output signal line. 12 (a) and 12 (b) are diagrams for explaining the relationship between the arrangement of the color filter and the block according to the first modification. It is a figure which illustrates the relationship between the arrangement of a color filter and a block by modification 2. It is a figure exemplifying the relationship between the arrangement of the color filter and the block according to the modification 3. It is a figure which illustrates the relationship between the arrangement of the color filter and the block by the modification 4. It is a figure which illustrates the relationship between the arrangement of the color filter and the block by the modification 5. 17 (a) to 17 (i) are diagrams for explaining the first to ninth blocks according to the modified example 6, respectively. It is a figure explaining an example of wiring of an output signal line. It is a figure explaining an example of wiring of a control signal line. It is a figure explaining an example of wiring of a control signal line.

In the image pickup device according to the present embodiment, a plurality of regions provided with a plurality of photoelectric conversion units for photoelectric conversion of light are arranged. Hereinafter, a detailed description will be given with reference to the drawings.
FIG. 1 is a diagram schematically showing a configuration example of a digital camera including an image sensor 101 according to an embodiment. The digital camera is composed of an interchangeable lens 110 and a camera body 100, and the interchangeable lens 110 is attached to the camera body 100 via a lens mounting portion 105.
The digital camera may be configured as a camera with an integrated lens instead of an interchangeable lens type.

In FIG. 1, the xyz axes constituting the coordinate systems orthogonal to each other are defined. It is assumed that the light from the subject is incident in the positive direction of the z-axis of FIG. Further, as shown in the coordinate axes, the front direction of the paper surface orthogonal to the z-axis is defined as the x-axis plus direction, and the upward direction orthogonal to the z-axis and the x-axis is defined as the y-axis plus direction. In some subsequent figures, the coordinate axes are displayed so that the orientation of each figure can be understood with reference to the coordinate axes of FIG.

The interchangeable lens 110 includes, for example, a lens control unit 111, a zoom lens 112, a focus lens 113, an anti-vibration lens 114, an aperture member 115, a lens operation unit 116, and the like. The lens control unit 111 includes a CPU and peripheral components such as a memory. The lens control unit 111 controls the drive of the focus lens 113, the anti-vibration lens 114, and the aperture member 115, detects the positions of the zoom lens 112 and the focus lens 113, transmits information on the interchangeable lens 110 to the camera body 100, and the camera body 100. Receives camera information from.

The camera body 100 includes, for example, an image sensor 101, a body control unit 102, a body operation unit 103, a display unit 104, and the like. The image sensor 101 is arranged on the planned image plane (planned focal plane) of the interchangeable lens 110, and photoelectrically converts the subject image imaged by the interchangeable lens 110. The body operation unit 103 includes a shutter button, an operation member for various settings, and the like. The display unit 104 is composed of, for example, a liquid crystal monitor (also referred to as a rear monitor) mounted on the back surface of the camera body 100.

The body control unit 102 includes a CPU and peripheral parts such as a memory. The body control unit 102 controls the operation of the digital camera, such as drive control of the image sensor 101, reading of a signal from the image sensor 101, focus detection calculation and focus adjustment of the interchangeable lens 110, processing and recording of an image signal. Further, the body control unit 102 communicates with the lens control unit 111 via an electric contact 106 provided in the lens mounting unit 105 to receive information on the interchangeable lens 110 and camera information (defocus amount, aperture value, etc.). To send.

A subject image is formed on the light receiving surface of the image sensor 101 by the light flux passing through the interchangeable lens 110. This subject image is photoelectrically converted by the image pickup element 101, and the signal after the photoelectric conversion is sent to the body control unit 102.

The body control unit 102 detects the defocus amount of the interchangeable lens 110 by performing a known focus detection calculation based on the signal from the image sensor 101. The defocus amount is the amount of deviation between the position of the subject image (imaging surface) formed by the interchangeable lens 110 and the position of the light receiving surface of the image sensor 101.
The defocus amount detected by the body control unit 102 is sent to the lens control unit 111. The lens control unit 111 calculates the drive amount of the focus lens 113 based on the received defocus amount. Then, the focus lens 113 is moved to the in-focus position by driving a motor or the like (not shown) based on the calculated drive amount.

Further, the body control unit 102 processes a signal from the image sensor 101 to generate image data. The image data is recorded on a memory card (not shown) or used when displaying an image on the display unit 104. The image processing for the signal from the image sensor 101 includes a correction process described in detail later, a color interpolation process, and the like. The body control unit 102 further causes the display unit 104 to display a monitor image (also referred to as a through image) based on the signal from the image sensor 101.

<Structure of image sensor>
FIG. 2 is a schematic diagram illustrating an outline of the image sensor 101. The image sensor 101 is composed of a CMOS image sensor. The image sensor 101 includes a pixel area 201, a vertical control unit 202, a horizontal control unit 203, a sensor output unit 204, and a sensor control unit 205. In FIG. 2, the power supply unit and the detailed circuit are omitted.

The pixel area 201 has, for example, a plurality of pixels arranged two-dimensionally in the x-axis direction (first direction) and the y-axis direction (second direction). Each pixel has a photodiode as a photoelectric conversion unit that generates an electric charge according to the amount of incident light. Each of the plurality of pixels is controlled by the vertical control unit 202 and the horizontal control unit 203, and a signal based on the charge generated by the photodiode of each pixel is read out (output) via the signal line 210.

The sensor output unit 204 performs correlation double sampling (CDS) on the signal output from each pixel, and applies gain as necessary. The signal processed by the sensor output unit 204 is output to a signal processing unit (not shown) in the subsequent stage.

In the above description, an example in which the sensor output unit 204 outputs an analog signal to the signal processing unit in the subsequent stage has been described, but the sensor output unit 204 is provided with an A / D converter and the signal after the A / D conversion is digitally output. It may be configured to output.

In the present embodiment, the pixel area 201 is divided into a plurality of areas. Each region has a plurality (eg, 4) photodiodes. A predetermined number (for example, four) of the plurality of regions are connected by signal lines between the regions described later. A predetermined number of regions connected by signal lines between regions are called blocks. The signal generated by the photodiode in any region of the block is output via the signal line 210 of the block. Therefore, the number of signal lines 210 is equal to the number of blocks. With this configuration, the sensor output unit 204 inputs signals from a plurality of blocks in parallel, processes the signals from the input multiple blocks in parallel, and performs signal processing units in the subsequent stage (not shown). ) Can be output in parallel.
A plurality of signal lines 210 may be provided in one block.

The sensor control unit 205 controls each unit of the image sensor 101 described above. That is, the operation of the image sensor 101 described below is performed based on the control of the sensor control unit 205 that receives the command of the body control unit 102.
In the present embodiment, the photodiode and the output unit that outputs a signal based on the electric charge generated by the photodiode are referred to as "pixels". An example will be described in which the output unit includes each transfer transistor, a floating diffusion (FD) region, an amplification transistor, and a selection transistor described later, and a signal line for outputting a signal, but the range of the output unit is not necessarily the same as in this example. It does not have to be.

FIG. 3 is a diagram illustrating a cross section of the image sensor 101. Note that FIG. 3 shows only a part of the cross section of the entire image sensor 101. The image sensor 101 is configured as a so-called back-illuminated image sensor, and photoelectrically converts incident light in the plus direction of the z-axis. The image sensor 101 is configured by, for example, laminating a first semiconductor substrate 70 and a second semiconductor substrate 80.

The first semiconductor substrate 70 includes at least a PD layer 71 and a wiring layer 72. The PD layer 71 is arranged on the back surface side (z-axis minus side) of the wiring layer 72. A plurality of photodiode PDs are arranged two-dimensionally on the PD layer 71. The wiring 61, the wiring 62, the wiring 63, and the wiring 64 form the wiring of the signal line 210, the signal line in the area described later, the signal line between the areas described later, and the control line described later in the wiring layer 72. .. The wiring 61 to 64 are formed in different layers of the wiring layer 72, respectively. The above wiring may be formed by using only the wiring of the same layer in the wiring layer 72, or may be formed by using the wiring of different layers of the wiring layer 72.
Although the wiring of four layers is illustrated in FIG. 3, the number of layers may be changed as appropriate. The layers of the wiring layer 72 can be connected by, for example, vias (not shown). Various circuits such as the sensor output unit 204 are arranged on the second semiconductor substrate 80, for example. The second semiconductor substrate 80 may also be configured in multiple layers.

A plurality of color filters 73 corresponding to each of the plurality of photodiode PDs are provided on the incident side (z-axis minus side) of the incident light in the PD layer 71. The color filter 73 is provided with any one of three color filters (color filters) having different spectral characteristics of, for example, red (R), green (G), and blue (B). The color filter 73 includes a color filter having a spectral characteristic for dispersing light in the first wavelength region (red (R) light) of the incident light, and light in the second wavelength region of the incident light (light of the incident light). It includes a color filter having a spectral characteristic for dispersing green (G) light) and a color filter having a spectral characteristic for separating light in a third wavelength region (blue (B) light) among incident light. Is done. Three types of color filters 73, for example, corresponding to red (R), green (G), and blue (B), are arranged so as to form the Bayer arrangement illustrated in FIG.
Although the Bayer array will be described as an example in this embodiment, the color filter 73 may have an array other than the Bayer array.

A plurality of microlenses 74 corresponding to each of the plurality of color filters 73 are provided on the incident side (z-axis minus side) of the incident light in the color filter 73. The microlens 74 collects incident light toward the corresponding photodiode PD. The incident light that has passed through the microlens 74 is transmitted by the color filter 73 only in a part of the wavelength region and is incident on the photodiode PD. The photodiode PD photoelectrically converts the incident light to generate an electric charge.

A plurality of joining pads 75 are arranged on the surface (z-axis plus side) of the wiring layer 72. A plurality of bonding pads 76 facing the plurality of bonding pads 75 are arranged on the surface (z-axis minus side) of the second semiconductor substrate 80 facing the wiring layer 72. When the plurality of bonding pads 75 and the plurality of bonding pads 76 are joined to each other, the first semiconductor substrate 70 and the second semiconductor substrate 80 are electrically connected to each other via the plurality of bonding pads 75 and the plurality of bonding pads 76. Connected to.
The number of the joining pads 75 and the plurality of joining pads 76 can be equal to the number of blocks described above, respectively. That is, a set of joining pads 75 and 76 is provided corresponding to one block.

In the present embodiment, one pixel of the image sensor 101 is composed of a first pixel portion 30x provided on the first semiconductor substrate 70 and a second pixel portion 30y provided on the second semiconductor substrate 80. .. In addition to the microlens 74, the color filter 73, and the photodiode PD, the first pixel portion 30x can include a transistor described in detail later, wiring 61 to wiring 64 connecting the pixel portions 30P, and the like. The second pixel unit 30y can include a circuit such as the sensor output unit 204.

<Explanation of blocks>
FIG. 5 is a circuit diagram illustrating a block configuration of the image sensor 101. In the example shown in FIG. 5, each block has four regions A to D. Four first pixel units 30x-1 to 30x-4 are arranged in the area A. Four first pixel units 30x-5 to 30x-8 are arranged in the area B. Four first pixel units 30x-9 to 30x-12 are arranged in the area C. Four first pixel units 30x-13 to 30x-16 are arranged in the area D.

The first pixel unit 30x includes a photodiode PD as a photoelectric conversion unit, four transistors (transfer transistor Tx functioning as a transfer unit, a reset transistor RST functioning as a reset unit, and an amplification transistor SF functioning as an amplification unit, respectively. It has a selection transistor SEL) that functions as a switch and an FD region.
Each part of the first pixel part 30x is connected as shown in FIG. In FIG. 5, reference numeral VDD indicates a power supply voltage.
The transfer transistor Tx transfers the electric charge generated by the photodiode PD to the FD region. The transfer transistor Tx is turned on when the corresponding control signal φTx reaches the High level to transfer charges, and turns off when the corresponding control signal φTx reaches the Low level.

The FD region accumulates the transferred charge and converts the transferred charge into a voltage. The amplification transistor SF forms a source follower circuit and outputs a signal corresponding to the potential in the FD region. The reset transistor RST resets (discharges) the electric charge of the FD region and the photodiode PD. The reset transistor RST turns on when the corresponding control signal φRST reaches the High level, and turns off when the corresponding control signal φRST reaches the Low level.

The selection transistor SEL outputs the signal output from the amplification transistor SF to the signal line 60 in the region. The selection transistor SEL is turned on when the corresponding control signal φSEL reaches the High level to output a signal, and turns off when the corresponding control signal φSEL reaches the Low level.

The signal line 60 in the region connects the output units (drains) of a plurality of (four in this example) selection transistors SEL in the region in each of the regions A to D. The signal lines 90 between the regions are the output units of a plurality of (four in this example) regions A to D in the block, that is, the signal lines 60 in the region A, the signal lines 60 in the region B, and the regions C. The signal line 60 of the above and the signal line 60 in the area D are connected.
Since the signal lines in the block are connected in this way, the signal generated by the photodiode PD in any region in the block includes the signal line 60 in the region, the signal line 90 between the regions, and the signal line 210. It is output via.

The sensor control unit 205 can supply independent control signals φSEL-1 to φSEL-16 to the selection transistors SEL of the 16 first pixel units 30x in the block. For example, when the sensor control unit 205 sequentially supplies the high level control signals φSEL-1 to φSEL-16, the 16 selection transistors SEL are turned on in order and a signal is output to the signal line 210. In this way, the signals generated by the 16 first pixel units 30x in the block can be output individually.

Note that the sensor control unit 205 may output a signal to the signal line 210 by combining a plurality of the 16 selection transistors SEL. For example, the sensor control unit 205 supplies a high level control signal φSEL to a plurality of first pixel units 30x among the first pixel units 30x-1 to 30x-16. In this way, the signals output from the plurality of first pixel units 30x to which the high level control signal φSEL is supplied are added to the signal line 60 in the region, the signal line 90 between the regions, and the signal line 210, and binning. It is also possible to do.

Further, the sensor control unit 205 can supply independent control signals φTx-1 to φTx-16 to the transfer transistors Tx of the 16 first pixel units 30x in the block. For example, by supplying the high level control signals φTx-1 to φTx-16 in order by the sensor control unit 205, the 16 transfer transistors Tx are turned on in order, and the electric charge generated by the photodiode PD is in the FD region. Transferred to. In this way, the charges generated by the 16 first pixel units 30x in the block can be individually transferred.

Note that the sensor control unit 205 may turn on a plurality of the 16 transfer transistors Tx at the same timing. For example, the sensor control unit 205 supplies a high level control signal φTx to a plurality of first pixel units 30x among the first pixel units 30x-1 to 30x-16. In this way, the charges generated in the plurality of first pixel units 30x to which the high level control signal φTx is supplied are transferred to the respective FD regions.

FIG. 6 is a schematic diagram illustrating the relationship between the arrangement of the color filters and the blocks, and shows a partial configuration 301 of the pixel area 201 (FIG. 2). In the pixel area 201, the configuration 301 is repeatedly arranged, for example, in the x-axis direction and the y-axis direction.

<Arrangement>
In the present embodiment, four pixels are arranged in each of the plurality of regions. In the example of FIG. 6, the 64 pixels included in the configuration 301 are divided into 16 regions. One area is composed of four pixels in a Bayer array.
That is, a pixel (referred to as an R pixel) having a color filter 73 that transmits light in the wavelength region corresponding to red (R) and a pixel having a color filter 73 that transmits light in the wavelength region corresponding to blue (B). (Referred to as B pixel), a pixel (referred to as G pixel) having a color filter 73 located on the GR row and transmitting light in the wavelength region corresponding to green (G), and a pixel (referred to as G pixel) located on the GB row. One region is composed of pixels (referred to as G pixels) having a color filter 73 that transmits light in a wavelength region corresponding to green (G).
And one block is composed of four regions arranged apart from each other. As a result, the configuration 301 has four blocks.

FIG. 7A is a diagram illustrating the first block. The first block has four regions 11 to 14 arranged apart from each other. Regions 11 to 14 correspond to regions A to D in FIG. FIG. 7B is a diagram illustrating the second block. The second block has four regions 21 to 24 that are spaced apart from each other. Regions 21 to 24 correspond to regions A to D in FIG. FIG. 7C is a diagram illustrating the third block. The third block has four regions 31 to 34 that are spaced apart from each other. Regions 31 to 34 correspond to regions A to D in FIG. FIG. 7D is a diagram illustrating the fourth block. The fourth block has four regions 41 to 44 that are spaced apart from each other. Regions 41 to 44 correspond to regions A to D in FIG.

In FIGS. 6 and 7, the 16 pixels of the first block are shaded. Further, the 16 pixels of the second block are indicated by dots. Further, the 16 pixels of the third block are indicated by vertical stripes. Furthermore, the 16 pixels of the fourth block are indicated by horizontal stripes.

Explain the reason why one block has an area separated from each other instead of an area arranged adjacent to each other. Generally, when a signal from a certain pixel cannot be output due to a defect generated in the image sensor 101, the image sensor 101 performs interpolation processing using signals from other pixels arranged around a pixel that cannot output the signal. Generates a signal at a pixel position where the signal cannot be output. Further, when the image data based on the signal from a certain pixel cannot be generated due to the defect generated in the image pickup element 101, the image pickup element 101 is based on the signal from another pixel arranged around the pixel position where the image data cannot be generated. The image data at the pixel position where the image data could not be generated is generated by the correction process for correcting the image data.

In the present embodiment, for example, when a defect generated in the first block makes it impossible to output a signal from a pixel (referred to as a pixel of interest) in the first block, for example, the body control unit 102 or the sensor control unit 205 Interpolation processing is performed using signals from other pixels arranged around the pixel of interest. The defects of the first block include a failure of the signal line 210 of the first block, a failure of the signal line 90 between the regions of the first block, and a defect of the signal line 60 in the region of the first block. When a failure occurs, the case where the failure occurs in the attention pixel itself is included.

FIG. 8 is a diagram illustrating the interpolation process. In FIG. 8, the R pixel surrounded by a solid line circle and included in the region 14 constituting the first block of FIG. 7A is set as the pixel of interest. The body control unit 102 or the sensor control unit 205 is, for example, four R pixels surrounded by a broken line circle, and the R pixels included in the regions 23 and 24 constituting the second block of FIG. 7B, respectively. , The signal from the R pixel included in the regions 32 and 34 constituting the third block in FIG. 7C is used to interpolate the signal at the position of the pixel of interest.

When performing such interpolation processing, it is better to use a signal from a pixel arranged at a position close to the position of the pixel of interest than to use a signal from a pixel arranged at a position far from the position of the pixel of interest. , It is advantageous in that the accuracy of the interpolation processing is improved. If one block has regions adjacent to each other, it is highly possible that a region located around the region including the pixel of interest is also included in the same defect block as the pixel of interest. If the area around the area containing the pixel of interest is defective, the body control unit 102 or the sensor control unit 205 may use a signal from a pixel contained in another block located further away from the position of the pixel of interest. It is necessary to perform interpolation using, and the accuracy of the interpolation processing becomes low.

However, according to the present embodiment, since one block is configured to have regions separated from each other, the regions 32, 34, 23, and 24 located next to the region 14 of the first block including the pixel of interest are , Both are included in a third block or a second block different from the first block. That is, since the area around the area including the pixel of interest is included in a block different from the defect block, the body control unit 102 or the sensor control unit 205 receives a signal from a pixel arranged at a position close to the position of the pixel of interest. It can be used to perform the interpolation process with high accuracy.
For example, when the pixel in the region 24 of the second block is the pixel of interest, a signal from a pixel included in another configuration (not shown) located on the x-axis plus direction side of the configuration 301 may be used.

<Wiring>
9 (a) to 9 (b) are schematic views illustrating an example of wiring of the signal line 90 between the regions and wiring of the signal line 60 in the region among the output signal lines of the configuration 301. FIG. 9A illustrates the wiring of the signal line 90-1 between the regions of the first block, the signal line 90-2 between the regions of the second block, and the signal line 60 in the regions of the third and fourth blocks. It is a figure to do. The signal lines 90-1 between the regions of the first block are shaded. The signal lines 90-2 between the regions of the second block are indicated by dots. The double circle indicates that the wiring and the output unit (drain) output unit of the selection transistor SEL in the first pixel unit 30x are connected.

Further, FIG. 9B shows the wiring of the signal line 90-3 between the regions of the third block, the signal line 90-4 between the regions of the fourth block, and the signal line 60 in the regions of the first and second blocks. It is a figure exemplifying. The signal lines 90-3 between the regions of the third block are indicated by vertical stripes. The signal lines 90-4 between the regions of the fourth block are indicated by horizontal stripes. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.

As described above, the wiring of the signal line 60 in the region connects the output portions (drains) of the selection transistors SEL of the four first pixel portions 30x constituting each region to each other.
Further, the wiring of the signal line 90 between the regions connects the signal lines 60 in the regions of the four regions of each block to each other.
According to the wiring examples of FIGS. 9A and 9B, the wiring can be housed in two of the wiring layers 72. In other words, the number of layers occupied by the signal line 60 in the region and the signal line 90 between the regions can be reduced. By reducing the number of wiring layers, the effect of cost reduction can be obtained.

<Example of other wiring (1)>
10 (a) to 10 (b) are schematic views illustrating another wiring example of the output signal line in the configuration 301. FIG. 10A is a diagram illustrating the wiring of the signal line 90-1 between the regions of the first block, the signal line between the regions of the fourth block, and the signal line 60 in the regions of the third and fourth blocks. is there. The signal lines 90-1 between the regions of the first block are shaded. The signal lines between the regions of the fourth block are indicated by horizontal stripes. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.

Further, FIG. 10B shows the wiring of the signal line 90-2 between the regions of the second block, the signal line 90-3 between the regions of the third block, and the signal line 60 in the regions of the first and second blocks. It is a figure exemplifying. The signal lines 90-2 between the regions of the second block are indicated by dots. The signal lines between the regions of the third block are indicated by vertical stripes. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.

The wiring of the signal line 60 in the region connects the output units (drains) of the selection transistors SEL of the four first pixel units 30x constituting each region to each other, and the wiring of the signal line 90 between the regions is each. The point of connecting the signal lines 60 in the regions of the four regions of the block to each other is the same as the wiring illustrated in FIGS. 9 (a) and 9 (b). In the wiring examples of FIGS. 10 (a) and 10 (b), the wiring can be stored in two of the wiring layers 72 in the same manner as the wiring illustrated in FIGS. 9 (a) and 9 (b). it can. In other words, the number of layers occupied by the signal line 60 in the region and the signal line 90 between the regions can be reduced.

<Example of other wiring (2)>
11 (a) to 11 (b) are schematic views illustrating another wiring example of the output signal line in the configuration 301. FIG. 11A shows a signal line 90-1 between the regions of the first block, a signal line 90-2 between the regions of the second block, a signal line 90-3 between the regions of the third block, and a fourth. Of the wiring of the signal line 90-4 between the block regions, the first wiring and the third wiring in the x-axis direction and a part of the wiring of the signal line 60 in the region of the first block to the fourth block are illustrated. It is a figure. The signal lines 90-1 between the regions of the first block are shaded. The signal lines 90-2 between the regions of the second block are indicated by dots. The signal lines 90-3 between the regions of the third block are indicated by vertical stripes. The signal lines 90-4 between the regions of the fourth block are indicated by horizontal stripes. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.

Further, FIG. 11B shows signal lines 90-1 between the regions of the first block, signal lines 90-2 between the regions of the second block, signal lines 90-3 between the regions of the third block, and Of the wiring of the signal line 90-4 between the regions of the fourth block, the second wiring and the fourth wiring in the y-axis direction, and the remaining portion of the wiring of the signal line 60 in the region of the first block to the fourth block. It is a figure which exemplifies. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.

The wiring of the signal line 60 in the region connects the output units (drains) of the selection transistors SEL of the four first pixel units 30x constituting each region to each other, and the wiring of the signal line 90 between the regions is each. The points connecting the wirings of the signal lines 60 in the regions of the four regions of the block to each other are the wirings exemplified in FIGS. 9A, 9B, 10A, and 10B. The same is true. The wiring examples illustrated in FIGS. 11 (a) and 11 (b) are also described above, similarly to the wiring illustrated in FIGS. 9 (a), 9 (b), 10 (a), and 10 (b). The wiring can be housed in two of the wiring layers 72. In other words, the number of layers occupied by the signal line 60 in the region and the signal line 90 between the regions can be reduced.

According to the embodiment described above, the following effects can be obtained.
(1) The image sensor 101 is provided in a region 11 as a first region, a region 12 as a second region, and a region 21 as a third region between the region 11 and the region 12, respectively, and transmits light. A plurality of first pixel units 30x that are converted to generate charges, a signal based on the charges generated by the plurality of first pixel units 30x provided in the region 11, and a plurality of first pixel units 30x provided in the region 12. A first output unit (signal line 60 in the region of the first block, signal line 90-1 between regions, signal line 210) that outputs at least one of the signals based on the charge generated in the above and the region 21 are provided. A second output unit (signal line 60 in the region of the second block, signal line 90-2 between regions, signal line 210) that outputs a signal based on the charge generated by the plurality of first pixel units 30x. Be prepared. Since the region 21 is arranged between the region 11 and the region 12 in this way, if the region 11 or the region 12 becomes defective, the signal to be obtained from the first pixel portion 30x in the region 11 and the region 12 The interpolation process and the correction process for generating the signal obtained from the first pixel unit 30x in the region 21 located between the regions 11 and 12 can be performed with high accuracy.

(2) The plurality of first pixel units 30x are provided in the first direction and the second direction in the area 11, the area 12, and the area 21, respectively. With this configuration, the interpolation processing and correction processing can be performed with high accuracy by using the signals obtained from the first pixel unit 30x whose positions in the first direction and the second direction correspond to each other in each region.

(3) The first output unit of the above (1) is wired in at least one of the first direction and the second direction, and serves as a first signal line that outputs a signal based on the electric charge generated by the first pixel unit 30x. It has a signal line 90-1 between regions, and the second output unit of the above (1) is wired in at least one of the first direction and the second direction, and is a signal based on the charge generated by the first pixel unit 30x. It has a signal line 90-2 between regions as a second signal line to output. With this configuration, even if the region 11 or region 12 becomes defective and no signal is output from the signal line 90-1 between the regions, the signal obtained from the first pixel unit 30x in the region 21 can be output between the regions. It can be output from the signal line 90-2 of.

(4) Since the signal line 90-1 between the regions and the signal line 90-2 between the regions are provided in different layers of the wiring layer 72, the wirings in the first direction and the second direction are crossed in one layer. Can be wired properly without. Further, the number of layers occupied by the signal lines 90 between the regions in the wiring layer 72 can be reduced. By reducing the number of wiring layers, the effect of cost reduction can be obtained.

(5) Since the signal line 90-1 between the regions and the signal line 90-2 between the regions are provided in the same layer of the wiring layer 72 and are wired so as not to intersect each other, the first direction and the first layer in one layer. Wiring can be performed appropriately without crossing the wiring in two directions. Further, the number of layers occupied by the signal lines 90 between the regions in the wiring layer 72 can be reduced. By reducing the number of wiring layers, the effect of cost reduction can be obtained.

(6) The signal line 90-1 between the regions has a first wiring wired in the first direction of FIG. 11A and a second wiring wired in the second direction of FIG. 11B. However, the first wiring and the second wiring are provided in different layers of the wiring layer 72. With this configuration, the wiring in the first direction and the wiring in the second direction can be appropriately wired in one layer without intersecting each other. Further, the number of layers occupied by the signal lines 90 between the regions in the wiring layer 72 can be reduced. By reducing the number of wiring layers, the effect of cost reduction can be obtained.

(7) The signal line 90-2 between the regions has a third wiring wired in the first direction of FIG. 11A and a fourth wiring wired in the second direction of FIG. 11B. The first wiring and the third wiring are provided in the same layer of the wiring layer 72 (FIG. 11A), and the second wiring and the fourth wiring are in the same layer of the wiring layer 72 (the same layer of the wiring layer 72. It is provided in FIG. 11 (b)). With this configuration, the wiring in the first direction and the wiring in the second direction can be appropriately wired in one layer without intersecting each other. Further, the number of layers occupied by the signal lines 90 between the regions in the wiring layer 72 can be reduced. By reducing the number of wiring layers, the effect of cost reduction can be obtained.

(8) A plurality of first pixel units 30x provided in the region 22 as a fourth region, which is different from the region 11, the region 12, and the region 21, are provided, and the second output portion of the above (1) is provided in the region 21. At least one of a signal based on the charge generated by the plurality of first pixel units 30x and a signal based on the charge generated by the plurality of first pixel units 30x provided in the region 22 is output. With this configuration, even if the region 12 becomes defective and no signal is output from the signal lines 90-1 between the regions, the signal obtained by the first pixel unit 30x in the region 21 or the region 22 can be second. It can be output from the signal line 90-2 between the regions as the signal line.

(9) The plurality of first pixel units 30x include a photoelectric conversion unit that photoelectrically converts light of the first wavelength and a photoelectric conversion unit that photoelectrically converts light of a second wavelength different from the first wavelength. With this configuration, light of different wavelengths can be photoelectrically converted.

(10) A body control unit 102 as a generation unit that generates image data based on a signal output from at least one of the first output unit and the second output unit of the above (1) is provided. With this configuration, it is possible to generate an image for recording and an image for a monitor.

(11) The body control unit 102 corrects the signal output from the first output unit of the above (1) based on the signal output from the second output unit of the above (1) to generate image data. To do. With this configuration, it is possible to appropriately generate an image for recording and an image for a monitor.

(12) When the signal is not output from the first output unit of (1), the body control unit 102 corrects the image data based on the signal output from the second output unit of (1) to obtain an image. Generate data. With this configuration, it is possible to appropriately generate an image for recording and an image for a monitor.

(13) When the signal is not output from the first output unit of the above (1), the body control unit 102 outputs the data corresponding to the signal output from the first output unit in the image data from the second output unit. Generated based on the output signal. With this configuration, it is possible to appropriately generate an image for recording and an image for a monitor.

The following modifications are also within the scope of the present invention, and one or more of the modifications can be combined with the above-described embodiment.
(Modification example 1)
In the above-described embodiment, an example in which one block has four regions (16 pixels) has been described. Instead, one block may have nine regions (36 pixels).
12 (a) and 12 (b) are schematic views illustrating the relationship between the arrangement of the color filter and the block according to the first modification and the wiring of the output signal line, and are the schematic views of the pixel area 201 (FIG. 2). A partial configuration 302 is shown. In the pixel area 201, the configurations 302 are repeatedly arranged, for example, in the x-axis direction (first direction) and the y-axis direction (second direction).

<Arrangement>
Also in the case of the modification 1, the pixel area 201 is divided into a plurality of areas by dividing the pixel area 201 into four pixels. In the examples of FIGS. 12A and 12B, 144 pixels included in the configuration 302 are divided into 36 regions. One area is composed of four pixels in a Bayer array. Then, one block is composed of nine regions arranged apart from each other. As a result, the configuration 302 has four blocks.

In FIGS. 12 (a) and 12 (b), the 36 pixels of the first block are shaded. Further, the 36 pixels of the second block are indicated by dots. Further, the 36 pixels of the third block are indicated by vertical stripes. Furthermore, the 36 pixels of the fourth block are indicated by horizontal stripes.

Also in the modified example 1, one block has a region separated from each other, not a region arranged adjacent to each other. Since it is configured in this way, for example, the area located next to the area of the first block including the pixel of interest is included in another block (any of the second block to the fourth block) different from the first block. Is done. That is, since the area around the area including the pixel of interest is included in a block different from the defect block, the body control unit 102 or the sensor control unit 205 receives a signal from a pixel arranged at a position close to the position of the pixel of interest. It can be used to perform interpolation processing and correction processing with high accuracy.

<Wiring>
FIG. 12A illustrates the wiring of the signal lines between the regions of the first block, the signal lines between the regions of the second block, and the signal lines in the regions of the third and fourth blocks. The signal lines between the regions of the first block are shaded. The signal lines between the regions of the second block are indicated by dots. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.

Further, FIG. 12B illustrates the wiring of the signal lines between the regions of the third block, the signal lines between the regions of the fourth block, and the signal lines in the regions of the first and second blocks. The signal lines between the regions of the third block are indicated by vertical stripes. The signal lines between the regions of the second block are indicated by horizontal stripes. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.

The wiring of the signal line in the region connects the output portions (drains) of the selection transistors SEL of the four first pixel portions 30x constituting each region to each other.
Further, the wiring of the signal lines between the regions connects the signal lines in the regions of the nine regions of each block to each other.
As illustrated in FIGS. 12 (a) and 12 (b), the wiring can be housed in two layers even in the case of the first modification. Therefore, the number of wiring layers in the wiring layer 72 can be reduced from 4 to 2 to reduce the cost as compared with the case where the wiring of the first block to the fourth block is formed in four different layers of the wiring layer 72. ..

(Modification 2)
One block may have 64 pixels. FIG. 13 is a schematic view illustrating the relationship between the arrangement of the color filter and the block according to the modified example 2, and shows a partial configuration 303 of the pixel area 201 (FIG. 2). In the pixel area 201, the configuration 303 is repeatedly arranged, for example, in the x-axis direction (first direction) and the y-axis direction (second direction).

<Arrangement>
Also in the case of the modification 2, the pixel area 201 is divided into a plurality of areas by dividing the pixel area 201 into four pixels. In the example of FIG. 13, 256 pixels included in the configuration 303 are divided into 64 regions. One area is composed of four pixels in a Bayer array. And one block is composed of 16 regions arranged apart from each other. As a result, the configuration 303 has four blocks.

In FIG. 13, the 64 pixels of the first block are shaded. Further, the 64 pixels of the second block are indicated by dots. Further, the 64 pixels of the third block are indicated by vertical stripes. Furthermore, the 64 pixels of the fourth block are indicated by horizontal stripes.

Also in the second modification, one block has a region separated from each other, not a region arranged adjacent to each other. Since it is configured in this way, for example, the area located next to the area of the first block including the pixel of interest is included in another block (any of the second block to the fourth block) different from the first block. Is done. That is, since the area around the area including the pixel of interest is included in a block different from the defect block, the body control unit 102 or the sensor control unit 205 receives a signal from a pixel arranged at a position close to the position of the pixel of interest. It can be used to perform interpolation processing and correction processing with high accuracy.

<Wiring>
Although not shown, the wiring of the signal line in the modified example 2 is shown in FIGS. 9 (a) and 9 (b) referred to in the description of the above embodiment, and FIG. 12 (a) referred to in the description of the modified example 1. , Wiring can be performed according to FIG. 12 (b). That is, in one layer of the wiring layer 72, the signal line between the regions of the first block, the signal line between the regions of the second block, and the signal line in the regions of the third and fourth blocks are 1 of the wiring layer 72. In the other layers of the wiring layer 72, the signal lines between the regions of the third block, the signal lines between the regions of the fourth block, and the signal lines in the regions of the first and second blocks are wired. Wired to another layer of layer 72.

By wiring in this way, the above wiring can be stored in two layers even in the case of the modified example 2. Therefore, the number of wiring layers in the wiring layer 72 can be reduced from 4 to 2 to reduce the cost as compared with the case where the wiring of the first block to the fourth block is formed in four different layers of the wiring layer 72. ..

(Modification 3)
The signal lines between the regions connecting the signal lines in the regions of the plurality of regions of the block may be wired in the direction sandwiched between the x-axis and the y-axis. FIG. 14 is a schematic diagram illustrating the relationship between the arrangement of the color filter and the block according to the modification 3 and the wiring of the output signal line, and shows a partial configuration 304 of the pixel area 201 (FIG. 2). In the pixel area 201, the configurations 304 are repeatedly arranged, for example, in the x-axis direction and the y-axis direction.

<Arrangement>
Also in the case of the modification 3, the pixel area 201 is divided into a plurality of areas by dividing the pixel area 201 into four pixels. In the example of FIG. 14, the 32 pixels included in the configuration 304 are divided into eight regions. One area is composed of four pixels in a Bayer array. And one block is composed of four regions arranged apart from each other. As a result, configuration 304 has two blocks.
In FIG. 14, 16 pixels included in the first block are shaded. Further, the 16 pixels of the second block are indicated by dots.

Also in the modified example 3, one block is not composed of regions arranged adjacent to each other, but is composed of regions separated from each other. With this configuration, for example, the regions located next to the region of the first block including the pixel of interest are all included in the second block different from the first block. That is, since the area around the area including the pixel of interest is included in a block different from the defect block, the body control unit 102 or the sensor control unit 205 receives a signal from a pixel arranged at a position close to the position of the pixel of interest. It can be used to perform interpolation processing and correction processing with high accuracy.

<Wiring>
FIG. 14 illustrates the wiring of the signal lines between the regions of the first block, the signal lines between the regions of the second block, and the signal lines within the regions of the first and second blocks. The wiring direction is the direction sandwiched between the x-axis and the y-axis. For example, if the direction sandwiched between the x-axis plus direction and the y-axis plus direction is the first direction, the direction sandwiched between the x-axis plus direction and the y-axis minus direction is the second direction. The wiring of the signal lines between the regions of the first block and the signal lines within the regions is shown in shading. The wiring of the signal lines between the regions of the second block and the signal lines within the regions is indicated by dots. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.
The wiring of the signal line in the region connects the output portions (drains) of the selection transistors SEL of the four first pixel portions 30x constituting each region to each other.
Further, the wiring of the signal lines between the regions connects the signal lines in the regions of the four regions constituting each block to each other.

As shown in FIG. 14, the wiring of the output signal line in the case of the modification 3 can be housed in one layer of the wiring layer 72. Therefore, the number of wiring layers in the wiring layer 72 is increased as compared with the case where the wiring of the signal line between the regions of the first block to the second block and the signal line in the region are formed in two different layers of the wiring layer 72. The cost can be reduced by reducing from 2 to 1.

(Modification example 4)
In the above-mentioned modification 3, an example in which one block has 16 pixels has been described. Instead, one block may have 36 pixels. FIG. 15 is a schematic diagram illustrating the relationship between the arrangement of the color filter and the block according to the modified example 4 and the wiring of the output signal line, and shows a partial configuration 305 of the pixel area 201 (FIG. 2). In the pixel area 201, the configuration 305 is repeatedly arranged, for example, in the x-axis direction and the y-axis direction.

<Arrangement>
Also in the case of the modification 4, the pixel area 201 is divided into a plurality of areas by dividing the pixel area 201 into four pixels. In the example of FIG. 15, 72 pixels included in the configuration 305 are divided into 18 regions. One area is composed of four pixels in a Bayer array. And one block is composed of nine regions arranged apart from each other. As a result, configuration 305 has two blocks.
In FIG. 15, the 36 pixels of the first block are shaded. Further, the 36 pixels of the second block are indicated by dots.

Also in the modified example 4, one block is composed of regions separated from each other, not regions arranged adjacent to each other. With this configuration, for example, the regions located next to the region of the first block including the pixel of interest are all included in the second block different from the first block. That is, since the area around the area including the pixel of interest is included in a block different from the defect block, the body control unit 102 or the sensor control unit 205 receives a signal from a pixel arranged at a position close to the position of the pixel of interest. It can be used to perform interpolation processing and correction processing with high accuracy.

<Wiring>
FIG. 15 illustrates the wiring of the signal lines between the regions of the first block, the signal lines between the regions of the second block, and the signal lines within the regions of the first and second blocks. The wiring direction is the direction sandwiched between the x-axis and the y-axis. For example, if the direction sandwiched between the x-axis plus direction and the y-axis plus direction is the first direction, the direction sandwiched between the x-axis plus direction and the y-axis minus direction is the second direction. The wiring of the signal lines between the regions of the first block and the signal lines within the regions is shown in shading. The wiring of the signal lines between the regions of the second block and the signal lines within the regions is indicated by dots. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.
The area wiring connects the output units (drains) of the selection transistors SEL of the four first pixel units 30x constituting each region to each other.
Further, the wiring of the signal lines between the regions connects the signal lines in the regions of the nine regions constituting each block to each other.

As shown in FIG. 15, even in the case of the modified example 4, the wiring of the output signal line can be housed in one layer of the wiring layer 72. Therefore, the number of wiring layers in the wiring layer 72 is increased as compared with the case where the wiring of the signal line between the regions of the first block to the second block and the signal line in the region are formed in two different layers of the wiring layer 72. The cost can be reduced by reducing from 2 to 1.

(Modification 5)
Another example will be described in which the wiring of the output signal line is housed in one layer of the wiring layer 72. FIG. 16 is a schematic diagram illustrating the relationship between the arrangement of the color filter and the block according to the modified example 5 and the wiring of the output signal line, and shows a partial configuration 306 of the pixel area 201 (FIG. 2). In the pixel area 201, the configuration 306 is repeatedly arranged, for example, in the x-axis direction (first direction) and the y-axis direction (second direction).

<Arrangement>
Also in the case of the modification 5, the pixel area 201 is divided into a plurality of areas by dividing the pixel area 201 into four pixels. In the example of FIG. 16, 256 pixels included in the configuration 306 are divided into 64 regions. One area is composed of four pixels in a Bayer array. Then, one block is composed of nine regions arranged apart from each other.

In FIG. 16, the 36 pixels of the first block are shaded. Further, the 36 pixels of the second block are indicated by dots. Further, the 36 pixels of the third block are indicated by vertical stripes. Furthermore, the 36 pixels of the fourth block are indicated by horizontal stripes.
In the fifth modification, the first block and the second block partially overlap each other in the x-axis direction of the blocks. Further, the first block and the third block partially overlap each other in the y-axis direction of the blocks. Further, the second block and the fourth block partially overlap each other in the y-axis direction of the blocks. Furthermore, the third block and the fourth block partially overlap each other in the x-axis direction of the blocks.
As described above, in the case of the modified example 5, the four blocks are not accommodated in the configuration 306, but the four blocks are arranged so as to partially overlap in the x-axis or y-axis direction.

Also in the modified example 5, one block is composed of regions separated from each other, not regions arranged adjacent to each other. Since it is configured in this way, for example, the area located next to the area of the first block including the pixel of interest is included in another block (any of the second block to the fourth block) different from the first block. Is done. That is, since the area around the area including the pixel of interest is included in a block different from the defect block, the body control unit 102 or the sensor control unit 205 receives a signal from a pixel arranged at a position close to the position of the pixel of interest. It can be used to perform interpolation processing and correction processing with high accuracy.

<Wiring>
FIG. 16 shows a signal line between the regions of the first block, a signal line between the regions of the second block, a signal line between the regions of the third block, a signal line between the regions of the fourth block, and first to fourth. Illustrate the wiring of signal lines in the area of the block. The signal lines between the regions of the first block are shaded. The signal lines between the regions of the second block are indicated by dots. The signal lines between the regions of the third block are indicated by vertical stripes. The signal lines between the regions of the fourth block are indicated by horizontal stripes. The double circle indicates that the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x are connected.

The wiring of the signal line in the region connects the output portions (drains) of the selection transistors SEL of the four first pixel portions 30x constituting each region to each other.
Further, the wiring of the signal lines between the regions connects the signal lines in the regions of the nine regions constituting each block to each other.

In FIG. 16, for example, taking the first block surrounded by a broken line as an example, the regions of the first block are connected in a spiral shape starting from the first pixel portion 30x of the region located at the center of the first block shown by shading. Wire. For example, from the R pixel in the area located in the center of the first block to the R pixel in the area one area away in the y-axis plus direction are connected by a signal line between the shaded areas, and one area in the x-axis plus direction. The distant G pixels are connected by signal lines between the shaded areas. Subsequently, the G pixel (RG column) in the region located at the center of the first block is connected to the G pixel in the region separated by one region in the plus direction of the x-axis by a signal line between the shaded areas, and further y. The R pixels in a region separated by one region in the minus direction of the axis are connected by a signal line between the shaded regions.

Similarly, the B pixel in the region located in the center of the first block is connected to the B pixel in the region one region away in the minus direction of the y-axis by a signal line between the shaded areas, and further 1 in the minus direction of the x-axis. The G pixels that are separated from each other are connected by signal lines between the shaded areas. Subsequently, the G pixel (GB row) in the region located at the center of the first block is connected to the G pixel in the region one region away in the minus direction of the x-axis by a signal line between the shaded areas, and further y. The B pixels in the region separated by one region in the plus direction of the axis are connected by signal lines between the shaded regions.

Similarly, for the second block indicated by dots, the third block indicated by vertical stripes, and the fourth block indicated by horizontal stripes, each block spirally starts from the first pixel portion 30x of the region located at the center of each block. The first pixel portion 30x of the region constituting the above is connected and wired.

As shown in FIG. 16, the wiring of the output signal line in the case of the modification 5 can be housed in one layer of the wiring layer 72. Therefore, the number of wiring layers in the wiring layer 72 is increased as compared with the case where the wiring of the signal line between the regions of the first block to the fourth block and the signal line in the region are formed in four different layers of the wiring layer 72. The cost can be reduced by reducing from 4 to 1.

(Modification 6)
In the above-described embodiment and modification, the case where the regions of the blocks are arranged one region apart is illustrated. Instead, the regions of the block may be arranged at a distance of two or more regions.

<Arrangement>
FIG. 17A is a diagram illustrating the first block in the modified example 6, and the first block has four regions 11, 14, 29, and 32 arranged two regions apart from each other. The frame indicated by reference numeral 307 is a configuration 307 including, for example, 144 pixels (12 in the x-axis direction × 12 in the y-axis direction) as a part of the pixel area 201 (FIG. 2).
FIG. 17B is a diagram illustrating a second block in the modified example 6, and the second block has four regions 12, 15, 30, and 33 arranged two regions apart from each other.

FIG. 17C is a diagram for explaining the third block in the modified example 6, and the third block has four regions 13, 16, 31, and 34 arranged two regions apart from each other. FIG. 17D is a diagram for explaining the fourth block in the modified example 6, and the fourth block has four regions 17, 20, 35, and 38 which are arranged two regions apart from each other.

FIG. 17E is a diagram for explaining the fifth block in the modified example 6, and the fifth block has four regions 18, 21, 36, and 39 which are arranged two regions apart from each other. FIG. 17F is a diagram illustrating the sixth block in the modified example 6, and the sixth block has four regions 19, 22, 37, and 40 arranged two regions apart from each other.

FIG. 17 (g) is a diagram illustrating the seventh block in the modified example 6, and the seventh block has four regions 23, 26, 41, and 44 which are arranged two regions apart from each other. FIG. 17 (h) is a diagram illustrating the eighth block in the modified example 6, and the eighth block has four regions 24, 27, 42, and 45 arranged two regions apart from each other.

FIG. 17 (i) is a diagram illustrating the ninth block in the modified example 6, and the ninth block has four regions 25, 28, 43, and 46 arranged two regions apart from each other.
As shown in FIGS. 17 (a) to 17 (i), the regions constituting each block are arranged two regions apart. Also in the case of the modification 6, the pixel area 201 is divided into a plurality of areas by dividing the pixel area 201 into four pixels. In the example of FIG. 17, 144 pixels included in the configuration 307 are divided into 36 regions. One area is composed of four pixels in a Bayer array. Then, one block is composed of four regions arranged so as to be separated from each other by two regions. As a result, the configuration 307 has nine blocks shown in FIGS. 17 (a) to 17 (i).

<Wiring>
FIG. 18 is a schematic diagram illustrating an example of wiring of the output signal line in the configuration 307. The wiring shown by shading is the wiring in the x-axis direction (first direction) of the wiring of the signal lines between the regions from the first block to the ninth block, and the signal lines in the regions 1-7 and 9. It is a figure which illustrates a part of the wiring of.
The wiring indicated by dots is a diagram illustrating wiring in the y-axis direction (second direction) of the signal lines between the regions from the first block to the ninth block and wiring of signal lines in regions other than the above. is there. For example, one layer of the wiring layer 72 is shaded with wiring, and the other layer of the wiring layer 72 is dotted. The double circle indicates that the wiring between different layers is connected between the wiring and the output unit (drain) of the selection transistor SEL in the first pixel unit 30x.

The wiring of the signal line in the region connects the output portions (drains) of the selection transistors SEL of the four first pixel portions 30x constituting each region to each other.
Further, in the wiring of the signal lines between the regions, the signal lines in the regions of the four regions constituting each block are indicated by the output unit (drain) of the selection transistor SEL in the first pixel unit 30x or the connection point indicated by a double circle. Connect to each other via.

By wiring in this way, the wiring of the output signal line can be stored in two layers even in the case of the modification example 6. Therefore, the number of wiring layers in the wiring layer 72 is reduced from 9 to 2, as compared with the case where the wiring of the signal line between the regions of the first block to the ninth block is formed in nine different layers of the wiring layer 72. The cost can be suppressed.

(Modification 7)
In the above-described embodiment and modification, the case where the number of regions constituting the block is arranged N in the x-axis direction and N in the y-axis direction is illustrated. Instead, the number of regions constituting the block may be arranged N in the x-axis direction and M in the y-axis direction. The magnitude relationship between M and N may be N <M or N> M.

<Wiring for supplying control signals φSEL-1 to φSEL-N>
In the above-described embodiment and modification, the wiring of the output signal line has been mainly described, but the control signals φSEL-1 to φSEL are applied to each of the selection transistors SEL of the plurality of first pixel units 30x constituting each block. The control line for supplying −N may also be wired to the wiring layer 72. The layer on which the control line is wired may be separated from the layer on which the output signal line is wired, or a part of the control line may be wired on the same layer as the output signal line.

Further, the control line may be common between blocks. For example, in the case of the configuration 301 described with reference to FIGS. 6 and 7, the control line can be wired as illustrated in FIG.
In the case of FIG. 19, wirings 1-1 to 1-16 are provided as wiring for the control lines to the first and second blocks of the configuration 301, and wiring 2-1 is provided as wiring for the control lines to the third and fourth blocks of the configuration 301. ~ 2-16 is provided. The double circle indicates that the wiring and the control unit (gate) of the selection transistor SEL of the first pixel units 30x-1 to 30x-16 are connected.

The sensor control unit 205 connects the G pixel on the GB row included in the area 11 and the G pixel on the GB row included in the area 21 to the control signal φSEL-1 (No. 1) at the same timing via the wiring 1-1. 1 block), φSEL-1 (second block) is supplied. That is, the control lines of the control signals φSEL-1 of the first and second blocks are shared.
The sensor control unit 205 also sends control signals φSEL-2 (first block) and φSEL-2 to the R pixel included in the area 11 and the R pixel included in the area 21 at the same timing via the wiring 1-2. (Second block) is supplied. That is, the control lines of the control signals φSEL-2 of the first and second blocks are shared.

Further, the sensor control unit 205 sends a control signal φSEL-3 (to the G pixel on the GB row included in the area 12 and the G pixel on the GB row included in the area 22 at the same timing via the wiring 1-3. 1st block), φSEL-3 (2nd block) is supplied. That is, the control lines of the control signals φSEL-3 of the first and second blocks are shared.
The sensor control unit 205 also sends control signals φSEL-4 (first block) and φSEL-4 to the R pixel included in the area 12 and the R pixel included in the area 22 at the same timing via the wiring 1-4. (Second block) is supplied. That is, the control lines of the control signals φSEL-4 of the first and second blocks are shared.

Then, the sensor control unit 205 sends the control signals φSEL-5 (first block) and φSEL- to the B pixel included in the area 11 and the B pixel included in the area 21 at the same timing via the wiring 1-5. 5 (second block) is supplied. That is, the control lines of the control signals φSEL-5 of the first and second blocks are shared.
The sensor control unit 205 also sends a control signal φSEL-6 (to the G pixel on the RG row included in the area 11 and the G pixel on the RG row included in the area 21 at the same timing via the wiring 1-6. 1st block), φSEL-6 (2nd block) is supplied. That is, the control lines of the control signals φSEL-6 of the first and second blocks are shared.

Further, the sensor control unit 205 sends control signals φSEL-7 (first block) and φSEL-7 to the B pixel included in the area 12 and the B pixel included in the area 22 at the same timing via the wiring 1-7. (Second block) is supplied. That is, the control lines of the control signals φSEL-7 of the first and second blocks are shared.
The sensor control unit 205 also sends a control signal φSEL-8 (to the G pixel on the RG row included in the area 12 and the G pixel on the RG row included in the area 22 at the same timing via the wiring 1-8). 1st block), φSEL-8 (2nd block) is supplied. That is, the control lines of the control signals φSEL-8 of the first and second blocks are shared.

Then, the sensor control unit 205 connects the G pixel on the GB row included in the area 13 and the G pixel on the GB row included in the area 23 to the control signal φSEL-9 at the same timing via the wiring 1-9. (1st block), φSEL-9 (2nd block) is supplied. That is, the control lines of the control signals φSEL-9 of the first and second blocks are shared.
The sensor control unit 205 also sends control signals φSEL-10 (first block) and φSEL-10 to the R pixel included in the area 13 and the R pixel included in the area 23 at the same timing via the wiring 1-10. (Second block) is supplied. That is, the control lines of the control signals φSEL-10 of the first and second blocks are shared.

Further, the sensor control unit 205 connects the G pixel on the GB row included in the area 14 and the G pixel on the GB row included in the area 24 to the control signal φSEL-11 (at the same timing via wiring 1-11). The first block) and φSEL-11 (second block) are supplied. That is, the control lines of the control signals φSEL-11 of the first and second blocks are shared.
The sensor control unit 205 also sends control signals φSEL-12 (first block) and φSEL-12 to the R pixel included in the area 14 and the R pixel included in the area 24 at the same timing via the wiring 1-12. (Second block) is supplied. That is, the control lines of the control signals φSEL-12 of the first and second blocks are shared.

Then, the sensor control unit 205 sends the control signals φSEL-13 (first block) and φSEL- to the B pixel included in the area 13 and the B pixel included in the area 23 at the same timing via the wiring 1-13. 13 (second block) is supplied. That is, the control lines of the control signals φSEL-13 of the first and second blocks are shared.
The sensor control unit 205 also sends a control signal φSEL-14 (to the G pixel on the RG row included in the area 13 and the G pixel on the RG row included in the area 23 at the same timing via the wiring 1-14. 1st block), φSEL-14 (2nd block) is supplied. That is, the control lines of the control signals φSEL-14 of the first and second blocks are shared.

Further, the sensor control unit 205 sends control signals φSEL-15 (first block) and φSEL-15 to the B pixel included in the area 14 and the B pixel included in the area 24 at the same timing via the wiring 1-15. (Second block) is supplied. That is, the control lines of the control signals φSEL-15 of the first and second blocks are shared.
The sensor control unit 205 also sends a control signal φSEL-16 (to the G pixel on the RG row included in the area 14 and the G pixel on the RG row included in the area 24 at the same timing via wiring 1-16. 1st block), φSEL-16 (2nd block) is supplied. That is, the control lines of the control signals φSEL-16 of the first and second blocks are shared.

As described above, the plurality of first pixel portions 30x provided in the region 11 or region 12 of the first block are the first pixel portion 30x-1 and the first pixel portion 30x provided in the first direction or the second direction. The plurality of first pixel portions 30x having -2 and provided in the region 21 of the second block are the first pixel portion 30x-1 and the first pixel portion 30x-2 provided in the first direction or the second direction. The first output unit is selected as a first switch for outputting a signal based on the charge generated by the first pixel unit 30x-1 of the first block to the signal line 90-1 between regions. Selection as a second switch for outputting a signal based on the charge generated by the transistor SEL-1 (first block) and the first pixel unit 30x-2 of the first block to the signal line 90-1 between regions. It has a transistor SEL-2 (first block), and the second output unit outputs a signal based on the charge generated by the first pixel unit 30x-1 of the second block to the signal line 90-2 between regions. A signal based on the charge generated by the selection transistor SEL-1 (second block) as the third switch and the first pixel portion 30x-2 of the second block is output to the signal line 90-2 between the regions. It has a selection transistor SEL-2 (second block) as a fourth switch, and is wired in the first direction row or the second direction, and has a selection transistor SEL-1 (first block) as a first switch. ) And the selection transistor SEL-1 (second block) as the third switch, and the first control line (wiring 1-1), which is wired in the first or second direction, as the second switch. It has a second control line (wiring 1-2) for controlling the selection transistor SEL-2 (first block) and the selection transistor SEL-2 (second block) as the fourth switch. With this configuration, by sharing the control lines between the blocks, it is possible to simplify the wiring of the control lines as compared with the case where the control lines are not shared.

In the above description, the control line wirings 1-1 to 1-16 for the first and second blocks have been described, but the same applies to the control line wirings 2-1 to 2-16 for the third and fourth blocks. is there.
In addition, when increasing the number of regions possessed by a block, that is, the number of pixels, the number of control lines may be increased according to the number of pixels.

<Wiring for supplying control signals φTx-1 to φTx-N>
The control lines for supplying the control signals φTx-1 to φTx-N to each of the transfer transistors Tx of the plurality of first pixel units 30x constituting each block are also the control signals φSEL described with reference to FIG. Similar to the control line for supplying -1 to φSEL-N, the wiring layer 72 may be wired.
Further, the control line for supplying the control signals φTx-1 to φTx−N may also be common between the blocks. By sharing the control lines between the blocks, it is possible to simplify the wiring of the control lines as compared with the case where the control lines are not shared.

<Matrix wiring>
In the case of the configuration 301 described with reference to FIGS. 6 and 7, the control lines may be wired in a matrix as illustrated in FIG. In the case of FIG. 20, as the wiring of the control signals φSEL-1 to φSEL-N for the first to fourth blocks of the configuration 301, wirings a1 to a8 in the x-axis direction and wirings b1 to b8 in the y-axis direction are provided. It is assumed that each first pixel portion 30x is provided with two selection transistors SEL. In each first pixel unit 30x, any of the wirings a1 to a8 is connected to the control unit (gate) of one of the selection transistors SEL, and any of the wirings b1 to b8 is connected to the control unit (gate) of the other selection transistor SEL. Is connected.

The sensor control unit 205 supplies the control signal φSEL to the first pixel unit 30x, which is the target of signal reading (the target of outputting the signal), via the intersecting wirings a1 to a8 and b1 to b8. With this configuration, the signal generated by the first pixel unit 30x in which the two selection transistors SEL are turned on by the control signals φSEL supplied by the wirings a1 to a8 and the wirings b1 to b8 is transmitted to the signal line 210. It is output.

In the above description, an example of mounting the image sensor 101 on a digital camera has been described, but the image sensor 101 may be mounted on an electronic device such as a smartphone, a tablet terminal, or a wearable terminal in addition to the digital camera.

Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other aspects conceivable within the scope of the technical idea of the present invention are also included within the scope of the present invention.

The disclosure content of the next priority basic application is incorporated here as a quotation.
Japanese Patent Application No. 2019-069144 (filed on March 29, 2019)

11-46 ... region, 30P ... pixel portion, 30x-1 to 30x-N ... first pixel portion, 60 ... signal line in the region, 61 to 64 ... wiring, 71 ... PD layer, 72 ... wiring layer, 73 ... Color filter, 90, 90-1 to 4-... signal lines between regions, 100 ... camera body, 101 ... image sensor, 102 ... body control unit, 201 ... pixel area, 204 ... output unit, 205 ... control unit, 210 ... signal line, PD ... photodiode, SEL ... selection transistor, SF ... amplification transistor, Tx ... transfer transistor

Claims (15)

1. A plurality of photoelectric conversion units provided in the first region, the second region, and the third region between the first region and the second region, respectively, to generate electric charges by photoelectric conversion of light.
   Outputs at least one of a signal based on the electric charge generated by the plurality of photoelectric conversion units provided in the first region and a signal based on the electric charge generated by the plurality of photoelectric conversion units provided in the second region. 1st output unit and
   A second output unit that outputs a signal based on the electric charge generated by the plurality of photoelectric conversion units provided in the third region, and a second output unit.
   An image sensor comprising.
2. In the image pickup device according to claim 1,
   The plurality of photoelectric conversion units are image pickup devices provided in the first region, the second region, and the third region, respectively, in the first direction and the second direction intersecting the first direction.
3. In the image pickup device according to claim 2,
   The first output unit has a first signal line that is wired in at least one of the first direction and the second direction and outputs a signal based on the electric charge generated by the photoelectric conversion unit.
   The second output unit is an image pickup device having a second signal line that is wired in at least one of the first direction and the second direction and outputs a signal based on the electric charge generated by the photoelectric conversion unit.
4. In the image pickup device according to claim 3,
   An image pickup device in which the first signal line and the second signal line are provided in different wiring layers.
5. In the image pickup device according to claim 3,
   An image pickup device in which the first signal line and the second signal line are provided in the same wiring layer and are wired so as not to intersect with each other.
6. In the image pickup device according to claim 3,
   The first signal line has a first wiring wired in the first direction and a second wiring wired in the second direction.
   The first wiring and the second wiring are image pickup devices provided in different wiring layers.
7. In the image pickup device according to claim 6,
   The second signal line has a third wiring wired in the first direction and a fourth wiring wired in the second direction.
   The first wiring and the third wiring are provided in the same wiring layer.
   The second wiring and the fourth wiring are image pickup devices provided in the same wiring layer.
8. In the image pickup device according to any one of claims 3 to 7.
   The plurality of photoelectric conversion units provided in the first region or the second region have a first photoelectric conversion unit and a second photoelectric conversion unit provided in the first direction or the second direction.
   The plurality of photoelectric conversion units provided in the third region include a third photoelectric conversion unit and a fourth photoelectric conversion unit provided in the first direction or the second direction.
   The first output unit transfers the electric charge generated by the first photoelectric conversion unit to the first storage unit and the electric charge generated by the second photoelectric conversion unit to the second storage unit. It has a second transfer unit and
   The second output unit transfers the electric charge generated by the third photoelectric conversion unit to the third storage unit and the electric charge generated by the fourth photoelectric conversion unit to the fourth storage unit. It has a fourth transfer unit and
   A first control line that is wired in the first direction or the second direction and controls the first transfer unit and the third transfer unit.
   A second control line that is wired in the first direction or the second direction and controls the second transfer unit and the fourth transfer unit.
   An image sensor comprising.
9. In the image pickup device according to any one of claims 3 to 7.
   The plurality of photoelectric conversion units provided in the first region or the second region have a first photoelectric conversion unit and a second photoelectric conversion unit provided in the first direction or the second direction.
   The plurality of photoelectric conversion units provided in the third region include a third photoelectric conversion unit and a fourth photoelectric conversion unit provided in the first direction or the second direction.
   The first output unit is based on a first switch for outputting a signal based on the charge generated by the first photoelectric conversion unit to the first signal line and a charge generated by the second photoelectric conversion unit. It has a second switch for outputting a signal to the first signal line, and has.
   The second output unit is based on a third switch for outputting a signal based on the charge generated by the third photoelectric conversion unit to the second signal line and a charge generated by the fourth photoelectric conversion unit. It has a fourth switch for outputting a signal to the second signal line, and has.
   A first control line that is wired in the first direction or the second direction and controls the first switch and the third switch.
   A second control line, which is wired in the first direction or the second direction and for controlling the second switch and the fourth switch,
   An image sensor comprising.
10. In the image pickup device according to any one of claims 1 to 9.
    A plurality of the photoelectric conversion units provided in the fourth region, which are different from the first region, the second region, and the third region, are provided.
    The second output unit is based on a signal based on the charges generated by the plurality of photoelectric conversion units provided in the third region and the charges generated by the plurality of photoelectric conversion units provided in the fourth region. An image sensor that outputs at least one of the signals.
11. In the image pickup device according to any one of claims 1 to 10.
    The plurality of photoelectric conversion units are imaging elements having a photoelectric conversion unit that photoelectrically converts light of the first wavelength and a photoelectric conversion unit that photoelectrically converts light of a second wavelength different from the first wavelength.
12. The image sensor according to any one of claims 1 to 11.
    An imaging device including a generation unit that generates image data based on a signal output from at least one of the first output unit and the second output unit.
13. In the imaging apparatus according to claim 12,
    The generation unit is an imaging device that generates the image data by correcting the signal output from the first output unit based on the signal output from the second output unit.
14. In the imaging apparatus according to claim 12 or 13,
    The generation unit is an imaging device that generates the image data by correcting the image data based on the signal output from the second output unit when the signal is not output from the first output unit.
15. In the imaging apparatus according to claim 14,
    When the signal is not output from the first output unit, the generation unit obtains data corresponding to the signal output from the first output unit in the image data based on the signal output from the second output unit. An imaging device to generate.

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